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From: vijay.kilari@gmail.com
To: marc.zyngier@arm.com, christoffer.dall@linaro.org,
	peter.maydell@linaro.org
Cc: kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org,
	Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Subject: [PATCH v9 04/11] irqchip/gic-v3: Add missing system register definitions
Date: Wed, 23 Nov 2016 18:31:51 +0530	[thread overview]
Message-ID: <1479906118-15832-5-git-send-email-vijay.kilari@gmail.com> (raw)
In-Reply-To: <1479906118-15832-1-git-send-email-vijay.kilari@gmail.com>

From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>

Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
---
 include/linux/irqchip/arm-gic-v3.h | 43 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 0deea34..b4f8287 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -352,8 +352,30 @@
 /*
  * CPU interface registers
  */
-#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << 1)
-#define ICC_CTLR_EL1_EOImode_drop	(1U << 1)
+#define ICC_CTLR_EL1_EOImode_SHIFT	(1)
+#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_drop	(1U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_MASK	(1 << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_CBPR_SHIFT		0
+#define ICC_CTLR_EL1_CBPR_MASK		(1 << ICC_CTLR_EL1_CBPR_SHIFT)
+#define ICC_CTLR_EL1_PRI_BITS_SHIFT	8
+#define ICC_CTLR_EL1_PRI_BITS_MASK	(0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
+#define ICC_CTLR_EL1_ID_BITS_SHIFT	11
+#define ICC_CTLR_EL1_ID_BITS_MASK	(0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
+#define ICC_CTLR_EL1_SEIS_SHIFT		14
+#define ICC_CTLR_EL1_SEIS_MASK		(0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
+#define ICC_CTLR_EL1_A3V_SHIFT		15
+#define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
+#define ICC_PMR_EL1_SHIFT		0
+#define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
+#define ICC_BPR0_EL1_SHIFT		0
+#define ICC_BPR0_EL1_MASK		(0x7 << ICC_BPR0_EL1_SHIFT)
+#define ICC_BPR1_EL1_SHIFT		0
+#define ICC_BPR1_EL1_MASK		(0x7 << ICC_BPR1_EL1_SHIFT)
+#define ICC_IGRPEN0_EL1_SHIFT		0
+#define ICC_IGRPEN0_EL1_MASK		(1 << ICC_IGRPEN0_EL1_SHIFT)
+#define ICC_IGRPEN1_EL1_SHIFT		0
+#define ICC_IGRPEN1_EL1_MASK		(1 << ICC_IGRPEN1_EL1_SHIFT)
 #define ICC_SRE_EL1_SRE			(1U << 0)
 
 /*
@@ -384,12 +406,29 @@
 
 #define ICH_VMCR_CTLR_SHIFT		0
 #define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
+#define ICH_VMCR_CBPR_SHIFT		4
+#define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_EOIM_SHIFT		9
+#define ICH_VMCR_EOIM_MASK		(1 << ICH_VMCR_EOIM_SHIFT)
 #define ICH_VMCR_BPR1_SHIFT		18
 #define ICH_VMCR_BPR1_MASK		(7 << ICH_VMCR_BPR1_SHIFT)
 #define ICH_VMCR_BPR0_SHIFT		21
 #define ICH_VMCR_BPR0_MASK		(7 << ICH_VMCR_BPR0_SHIFT)
 #define ICH_VMCR_PMR_SHIFT		24
 #define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)
+#define ICH_VMCR_ENG0_SHIFT		0
+#define ICH_VMCR_ENG0_MASK		(1 << ICH_VMCR_ENG0_SHIFT)
+#define ICH_VMCR_ENG1_SHIFT		1
+#define ICH_VMCR_ENG1_MASK		(1 << ICH_VMCR_ENG1_SHIFT)
+
+#define ICH_VTR_PRI_BITS_SHIFT		29
+#define ICH_VTR_PRI_BITS_MASK		(7 << ICH_VTR_PRI_BITS_SHIFT)
+#define ICH_VTR_ID_BITS_SHIFT		23
+#define ICH_VTR_ID_BITS_MASK		(7 << ICH_VTR_ID_BITS_SHIFT)
+#define ICH_VTR_SEIS_SHIFT		22
+#define ICH_VTR_SEIS_MASK		(1 << ICH_VTR_SEIS_SHIFT)
+#define ICH_VTR_A3V_SHIFT		21
+#define ICH_VTR_A3V_MASK		(1 << ICH_VTR_A3V_SHIFT)
 
 #define ICC_IAR1_EL1_SPURIOUS		0x3ff
 
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: vijay.kilari@gmail.com (vijay.kilari at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 04/11] irqchip/gic-v3: Add missing system register definitions
Date: Wed, 23 Nov 2016 18:31:51 +0530	[thread overview]
Message-ID: <1479906118-15832-5-git-send-email-vijay.kilari@gmail.com> (raw)
In-Reply-To: <1479906118-15832-1-git-send-email-vijay.kilari@gmail.com>

From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>

Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
---
 include/linux/irqchip/arm-gic-v3.h | 43 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 41 insertions(+), 2 deletions(-)

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 0deea34..b4f8287 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -352,8 +352,30 @@
 /*
  * CPU interface registers
  */
-#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << 1)
-#define ICC_CTLR_EL1_EOImode_drop	(1U << 1)
+#define ICC_CTLR_EL1_EOImode_SHIFT	(1)
+#define ICC_CTLR_EL1_EOImode_drop_dir	(0U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_drop	(1U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_MASK	(1 << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_CBPR_SHIFT		0
+#define ICC_CTLR_EL1_CBPR_MASK		(1 << ICC_CTLR_EL1_CBPR_SHIFT)
+#define ICC_CTLR_EL1_PRI_BITS_SHIFT	8
+#define ICC_CTLR_EL1_PRI_BITS_MASK	(0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
+#define ICC_CTLR_EL1_ID_BITS_SHIFT	11
+#define ICC_CTLR_EL1_ID_BITS_MASK	(0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
+#define ICC_CTLR_EL1_SEIS_SHIFT		14
+#define ICC_CTLR_EL1_SEIS_MASK		(0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
+#define ICC_CTLR_EL1_A3V_SHIFT		15
+#define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
+#define ICC_PMR_EL1_SHIFT		0
+#define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
+#define ICC_BPR0_EL1_SHIFT		0
+#define ICC_BPR0_EL1_MASK		(0x7 << ICC_BPR0_EL1_SHIFT)
+#define ICC_BPR1_EL1_SHIFT		0
+#define ICC_BPR1_EL1_MASK		(0x7 << ICC_BPR1_EL1_SHIFT)
+#define ICC_IGRPEN0_EL1_SHIFT		0
+#define ICC_IGRPEN0_EL1_MASK		(1 << ICC_IGRPEN0_EL1_SHIFT)
+#define ICC_IGRPEN1_EL1_SHIFT		0
+#define ICC_IGRPEN1_EL1_MASK		(1 << ICC_IGRPEN1_EL1_SHIFT)
 #define ICC_SRE_EL1_SRE			(1U << 0)
 
 /*
@@ -384,12 +406,29 @@
 
 #define ICH_VMCR_CTLR_SHIFT		0
 #define ICH_VMCR_CTLR_MASK		(0x21f << ICH_VMCR_CTLR_SHIFT)
+#define ICH_VMCR_CBPR_SHIFT		4
+#define ICH_VMCR_CBPR_MASK		(1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_EOIM_SHIFT		9
+#define ICH_VMCR_EOIM_MASK		(1 << ICH_VMCR_EOIM_SHIFT)
 #define ICH_VMCR_BPR1_SHIFT		18
 #define ICH_VMCR_BPR1_MASK		(7 << ICH_VMCR_BPR1_SHIFT)
 #define ICH_VMCR_BPR0_SHIFT		21
 #define ICH_VMCR_BPR0_MASK		(7 << ICH_VMCR_BPR0_SHIFT)
 #define ICH_VMCR_PMR_SHIFT		24
 #define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)
+#define ICH_VMCR_ENG0_SHIFT		0
+#define ICH_VMCR_ENG0_MASK		(1 << ICH_VMCR_ENG0_SHIFT)
+#define ICH_VMCR_ENG1_SHIFT		1
+#define ICH_VMCR_ENG1_MASK		(1 << ICH_VMCR_ENG1_SHIFT)
+
+#define ICH_VTR_PRI_BITS_SHIFT		29
+#define ICH_VTR_PRI_BITS_MASK		(7 << ICH_VTR_PRI_BITS_SHIFT)
+#define ICH_VTR_ID_BITS_SHIFT		23
+#define ICH_VTR_ID_BITS_MASK		(7 << ICH_VTR_ID_BITS_SHIFT)
+#define ICH_VTR_SEIS_SHIFT		22
+#define ICH_VTR_SEIS_MASK		(1 << ICH_VTR_SEIS_SHIFT)
+#define ICH_VTR_A3V_SHIFT		21
+#define ICH_VTR_A3V_MASK		(1 << ICH_VTR_A3V_SHIFT)
 
 #define ICC_IAR1_EL1_SPURIOUS		0x3ff
 
-- 
1.9.1

  parent reply	other threads:[~2016-11-23 13:01 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 13:01 [PATCH v9 0/11] arm/arm64: vgic: Implement API for vGICv3 live migration vijay.kilari
2016-11-23 13:01 ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 01/11] arm/arm64: vgic: Implement support for userspace access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 13:05   ` Christoffer Dall
2016-11-28 13:05     ` Christoffer Dall
2016-12-06 11:42     ` Auger Eric
2016-12-06 11:42       ` Auger Eric
2016-12-06 14:30       ` Christoffer Dall
2016-12-06 14:30         ` Christoffer Dall
2016-12-15  7:36       ` Vijay Kilari
2016-12-15  7:36         ` Vijay Kilari
2016-12-16 12:40         ` Auger Eric
2016-12-16 12:40           ` Auger Eric
2016-11-23 13:01 ` [PATCH v9 02/11] arm/arm64: vgic: Add distributor and redistributor access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 13:08   ` Christoffer Dall
2016-11-28 13:08     ` Christoffer Dall
2016-12-06 13:18     ` Auger Eric
2016-12-06 13:18       ` Auger Eric
2016-11-23 13:01 ` [PATCH v9 03/11] arm/arm64: vgic: Introduce find_reg_by_id() vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-12-06 13:27   ` Auger Eric
2016-12-06 13:27     ` Auger Eric
2016-11-23 13:01 ` vijay.kilari [this message]
2016-11-23 13:01   ` [PATCH v9 04/11] irqchip/gic-v3: Add missing system register definitions vijay.kilari at gmail.com
2016-12-06 13:53   ` Auger Eric
2016-12-06 13:53     ` Auger Eric
2017-01-23 10:55     ` Vijay Kilari
2017-01-23 10:55       ` Vijay Kilari
2016-11-23 13:01 ` [PATCH v9 05/11] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 14:28   ` Christoffer Dall
2016-11-28 14:28     ` Christoffer Dall
2016-12-08 11:52     ` Auger Eric
2016-12-08 11:52       ` Auger Eric
2016-12-08 12:21       ` Christoffer Dall
2016-12-08 12:21         ` Christoffer Dall
2016-12-08 12:50         ` Auger Eric
2016-12-08 12:50           ` Auger Eric
2016-12-11 16:38           ` Christoffer Dall
2016-12-11 16:38             ` Christoffer Dall
2016-11-23 13:01 ` [PATCH v9 06/11] arm/arm64: vgic: Implement VGICv3 CPU interface access vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:39   ` Christoffer Dall
2016-11-28 19:39     ` Christoffer Dall
2016-11-29  7:38     ` Vijay Kilari
2016-11-29  7:38       ` Vijay Kilari
2016-11-29  8:37       ` Christoffer Dall
2016-11-29  8:37         ` Christoffer Dall
2016-11-29 10:01         ` Vijay Kilari
2016-11-29 10:01           ` Vijay Kilari
2016-11-29 10:51           ` Christoffer Dall
2016-11-29 10:51             ` Christoffer Dall
2016-11-23 13:01 ` [PATCH v9 07/11] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:50   ` Christoffer Dall
2016-11-28 19:50     ` Christoffer Dall
2016-11-29 16:36     ` Vijay Kilari
2016-11-29 16:36       ` Vijay Kilari
2016-11-29 21:09       ` Christoffer Dall
2016-11-29 21:09         ` Christoffer Dall
2016-11-30  7:10         ` Peter Maydell
2016-11-30  7:10           ` Peter Maydell
2016-11-30  8:24           ` Christoffer Dall
2016-11-30  8:24             ` Christoffer Dall
2016-11-30  8:29             ` Peter Maydell
2016-11-30  8:29               ` Peter Maydell
2016-11-23 13:01 ` [PATCH v9 08/11] arm/arm64: Documentation: Update arm-vgic-v3.txt vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 09/11] arm: coproc: Drop const from coproc reg access function vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 10/11] arm: coproc: Introduce find_coproc_reg_by_id() vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-23 13:01 ` [PATCH v9 11/11] arm: vgic: Save and restore GICv3 CPU interface regs for AArch32 vijay.kilari
2016-11-23 13:01   ` vijay.kilari at gmail.com
2016-11-28 19:51 ` [PATCH v9 0/11] arm/arm64: vgic: Implement API for vGICv3 live migration Christoffer Dall
2016-11-28 19:51   ` Christoffer Dall

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