* [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support
@ 2016-11-24 6:47 Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 01/19] imx: add i.MX 6SLL CPU type Peng Fan
` (18 more replies)
0 siblings, 19 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
This patch set is to add i.MX6SLL support.
1. There are also a few patches to fix bugs in this patchset.
2. Default add device tree support.
3. Add two defconfigs, one for DCD, the other for plugin.
Peng Fan (19):
imx: add i.MX 6SLL CPU type
imx: mx6sll: add pinmux header files
imx: mx6sll: update register address
imx-common: timer: add i.MX6SLL support
imx: mx6sll: add iomux settings
imx: mx6: fix mmdc ch0 clk for 6SL
imx: mx6: lcdif: gate clock before changing mux
imx: mx6sl: add lcdif clock support
imx: clock: gate clk before changing pix clk mux
imx: mx6sll: add clock support
imx-common: cache: configure L2 Cache for i.MX6SLL
imx: mx6sll: add Kconfig entry for i.MX6SLL
mx6_common: correct loadaddr and text base for i.MX6SLL
OCOTP: Update OCOTP driver to support i.MX6SLL
imx-common: lcdif: update lcdif regs for i.MX6SL/SLL
pinctrl: imx6: support i.MX6SLL
arm: dts: add i.MX6SLL device tree
arm: imx: add i.MX6SLL EVK board support
imx: mx6sllevk: add plugin support
arch/arm/cpu/armv7/mx6/Kconfig | 11 +
arch/arm/cpu/armv7/mx6/clock.c | 143 ++-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6sll-evk.dts | 801 ++++++++++++++++
arch/arm/dts/imx6sll-pinfunc.h | 882 ++++++++++++++++++
arch/arm/dts/imx6sll.dtsi | 859 +++++++++++++++++
arch/arm/imx-common/cache.c | 17 +-
arch/arm/imx-common/cpu.c | 2 +
arch/arm/imx-common/iomux-v3.c | 10 +-
arch/arm/imx-common/timer.c | 10 +-
arch/arm/include/asm/arch-imx/cpu.h | 3 +-
arch/arm/include/asm/arch-mx6/clock.h | 2 +-
arch/arm/include/asm/arch-mx6/crm_regs.h | 21 +
arch/arm/include/asm/arch-mx6/imx-regs.h | 76 +-
arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 +
arch/arm/include/asm/arch-mx6/mx6sll_pins.h | 1019 +++++++++++++++++++++
arch/arm/include/asm/imx-common/iomux-v3.h | 6 +-
arch/arm/include/asm/imx-common/regs-lcdif.h | 7 +-
arch/arm/include/asm/imx-common/sys_proto.h | 1 +
board/freescale/mx6sllevk/Kconfig | 12 +
board/freescale/mx6sllevk/Makefile | 6 +
board/freescale/mx6sllevk/imximage.cfg | 127 +++
board/freescale/mx6sllevk/mx6sllevk.c | 131 +++
board/freescale/mx6sllevk/plugin.S | 155 ++++
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +-
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +-
configs/mx6sllevk_defconfig | 36 +
configs/mx6sllevk_plugin_defconfig | 37 +
drivers/misc/mxc_ocotp.c | 16 +-
drivers/pinctrl/nxp/pinctrl-imx6.c | 2 +
include/configs/mx6_common.h | 3 +-
include/configs/mx6sllevk.h | 152 +++
include/dt-bindings/clock/imx6sll-clock.h | 204 +++++
33 files changed, 4667 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/dts/imx6sll-evk.dts
create mode 100644 arch/arm/dts/imx6sll-pinfunc.h
create mode 100644 arch/arm/dts/imx6sll.dtsi
create mode 100644 arch/arm/include/asm/arch-mx6/mx6sll_pins.h
create mode 100644 board/freescale/mx6sllevk/Kconfig
create mode 100644 board/freescale/mx6sllevk/Makefile
create mode 100644 board/freescale/mx6sllevk/imximage.cfg
create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
create mode 100644 board/freescale/mx6sllevk/plugin.S
create mode 100644 configs/mx6sllevk_defconfig
create mode 100644 configs/mx6sllevk_plugin_defconfig
create mode 100644 include/configs/mx6sllevk.h
create mode 100644 include/dt-bindings/clock/imx6sll-clock.h
--
2.6.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 01/19] imx: add i.MX 6SLL CPU type
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 02/19] imx: mx6sll: add pinmux header files Peng Fan
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add i.MX6SLL cpu type.
MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/imx-common/cpu.c | 2 ++
arch/arm/include/asm/arch-imx/cpu.h | 3 ++-
arch/arm/include/asm/imx-common/sys_proto.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 632faca..40fe813 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -155,6 +155,8 @@ const char *get_imx_type(u32 imxtype)
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
+ case MXC_CPU_MX6SLL:
+ return "6SLL"; /* SLL version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
case MXC_CPU_MX6UL:
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 667115b0..8bd1421 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -19,7 +19,8 @@
#define MXC_CPU_MX6UL 0x64
#define MXC_CPU_MX6ULL 0x65
#define MXC_CPU_MX6SOLO 0x66 /* dummy */
-#define MXC_CPU_MX6D 0x67
+#define MXC_CPU_MX6SLL 0x67
+#define MXC_CPU_MX6D 0x6A
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 005435a..539d34b 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -36,6 +36,7 @@
#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 02/19] imx: mx6sll: add pinmux header files
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 01/19] imx: add i.MX 6SLL CPU type Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 03/19] imx: mx6sll: update register address Peng Fan
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add i.MX6SLL pinmux header files
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 +
arch/arm/include/asm/arch-mx6/mx6sll_pins.h | 1019 +++++++++++++++++++++++++++
2 files changed, 1021 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mx6/mx6sll_pins.h
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index b9cd670..2934b12 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -33,6 +33,8 @@ enum {
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
+#elif defined(CONFIG_MX6SLL)
+#include "mx6sll_pins.h"
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
new file mode 100644
index 0000000..1ecb7ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
@@ -0,0 +1,1019 @@
+/*
+ * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
+#define __ASM_ARCH_IMX6SLL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX6_PAD_WDOG_B__WDOG1_B = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__UART5_RI_B = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0),
+ MX6_PAD_WDOG_B__GPIO3_IO18 = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0),
+
+ MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__I2C3_SCL = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0),
+ MX6_PAD_REF_CLK_24M__PWM3_OUT = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__USB_OTG2_ID = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0),
+ MX6_PAD_REF_CLK_24M__CCM_PMIC_READY = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0),
+ MX6_PAD_REF_CLK_24M__GPIO3_IO21 = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_24M__SD3_WP = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0),
+
+ MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__I2C3_SDA = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0),
+ MX6_PAD_REF_CLK_32K__PWM4_OUT = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__USB_OTG1_ID = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0),
+ MX6_PAD_REF_CLK_32K__SD1_LCTL = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO3_IO22 = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__SD3_CD_B = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0),
+
+ MX6_PAD_PWM1__PWM1_OUT = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0),
+ MX6_PAD_PWM1__CCM_CLKO = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0),
+ MX6_PAD_PWM1__AUDIO_CLK_OUT = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0),
+ MX6_PAD_PWM1__CSI_MCLK = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0),
+ MX6_PAD_PWM1__GPIO3_IO23 = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0),
+ MX6_PAD_PWM1__EPIT1_OUT = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL0__KEY_COL0 = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0),
+ MX6_PAD_KEY_COL0__I2C2_SCL = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0),
+ MX6_PAD_KEY_COL0__LCD_DATA00 = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0),
+ MX6_PAD_KEY_COL0__SD1_CD_B = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0),
+ MX6_PAD_KEY_COL0__GPIO3_IO24 = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW0__KEY_ROW0 = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0),
+ MX6_PAD_KEY_ROW0__I2C2_SDA = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0),
+ MX6_PAD_KEY_ROW0__LCD_DATA01 = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0),
+ MX6_PAD_KEY_ROW0__SD1_WP = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0),
+ MX6_PAD_KEY_ROW0__GPIO3_IO25 = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL1__KEY_COL1 = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0),
+ MX6_PAD_KEY_COL1__ECSPI4_MOSI = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0),
+ MX6_PAD_KEY_COL1__LCD_DATA02 = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0),
+ MX6_PAD_KEY_COL1__SD3_DATA4 = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0),
+ MX6_PAD_KEY_COL1__GPIO3_IO26 = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW1__KEY_ROW1 = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0),
+ MX6_PAD_KEY_ROW1__ECSPI4_MISO = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0),
+ MX6_PAD_KEY_ROW1__LCD_DATA03 = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0),
+ MX6_PAD_KEY_ROW1__CSI_FIELD = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__SD3_DATA5 = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0),
+ MX6_PAD_KEY_ROW1__GPIO3_IO27 = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL2__KEY_COL2 = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0),
+ MX6_PAD_KEY_COL2__ECSPI4_SS0 = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0),
+ MX6_PAD_KEY_COL2__LCD_DATA04 = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0),
+ MX6_PAD_KEY_COL2__CSI_DATA12 = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0),
+ MX6_PAD_KEY_COL2__SD3_DATA6 = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0),
+ MX6_PAD_KEY_COL2__GPIO3_IO28 = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW2__KEY_ROW2 = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0),
+ MX6_PAD_KEY_ROW2__ECSPI4_SCLK = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0),
+ MX6_PAD_KEY_ROW2__LCD_DATA05 = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0),
+ MX6_PAD_KEY_ROW2__CSI_DATA13 = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0),
+ MX6_PAD_KEY_ROW2__SD3_DATA7 = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0),
+ MX6_PAD_KEY_ROW2__GPIO3_IO29 = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL3__KEY_COL3 = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0),
+ MX6_PAD_KEY_COL3__AUD6_RXFS = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0),
+ MX6_PAD_KEY_COL3__LCD_DATA06 = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0),
+ MX6_PAD_KEY_COL3__CSI_DATA14 = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0),
+ MX6_PAD_KEY_COL3__GPIO3_IO30 = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__SD1_RESET = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW3__KEY_ROW3 = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0),
+ MX6_PAD_KEY_ROW3__AUD6_RXC = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0),
+ MX6_PAD_KEY_ROW3__LCD_DATA07 = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0),
+ MX6_PAD_KEY_ROW3__CSI_DATA15 = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0),
+ MX6_PAD_KEY_ROW3__GPIO3_IO31 = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__SD1_VSELECT = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL4__KEY_COL4 = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0),
+ MX6_PAD_KEY_COL4__AUD6_RXD = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0),
+ MX6_PAD_KEY_COL4__LCD_DATA08 = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0),
+ MX6_PAD_KEY_COL4__CSI_DATA16 = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__GPIO4_IO00 = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__USB_OTG1_PWR = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW4__KEY_ROW4 = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0),
+ MX6_PAD_KEY_ROW4__AUD6_TXC = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0),
+ MX6_PAD_KEY_ROW4__LCD_DATA09 = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0),
+ MX6_PAD_KEY_ROW4__CSI_DATA17 = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__GPIO4_IO01 = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__USB_OTG1_OC = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0),
+
+ MX6_PAD_KEY_COL5__KEY_COL5 = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0),
+ MX6_PAD_KEY_COL5__AUD6_TXFS = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0),
+ MX6_PAD_KEY_COL5__LCD_DATA10 = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0),
+ MX6_PAD_KEY_COL5__CSI_DATA18 = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL5__GPIO4_IO02 = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL5__USB_OTG2_PWR = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW5__KEY_ROW5 = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0),
+ MX6_PAD_KEY_ROW5__AUD6_TXD = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0),
+ MX6_PAD_KEY_ROW5__LCD_DATA11 = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0),
+ MX6_PAD_KEY_ROW5__CSI_DATA19 = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW5__GPIO4_IO03 = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW5__USB_OTG2_OC = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0),
+
+ MX6_PAD_KEY_COL6__KEY_COL6 = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0),
+ MX6_PAD_KEY_COL6__UART4_DCE_RX = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0),
+ MX6_PAD_KEY_COL6__UART4_DTE_TX = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__LCD_DATA12 = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0),
+ MX6_PAD_KEY_COL6__CSI_DATA20 = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__GPIO4_IO04 = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL6__SD3_RESET = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_ROW6__KEY_ROW6 = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0),
+ MX6_PAD_KEY_ROW6__UART4_DCE_TX = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__UART4_DTE_RX = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0),
+ MX6_PAD_KEY_ROW6__LCD_DATA13 = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0),
+ MX6_PAD_KEY_ROW6__CSI_DATA21 = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__GPIO4_IO05 = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW6__SD3_VSELECT = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0),
+
+ MX6_PAD_KEY_COL7__KEY_COL7 = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0),
+ MX6_PAD_KEY_COL7__UART4_DCE_RTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0),
+ MX6_PAD_KEY_COL7__UART4_DTE_CTS = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__LCD_DATA14 = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0),
+ MX6_PAD_KEY_COL7__CSI_DATA22 = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__GPIO4_IO06 = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL7__SD1_WP = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0),
+
+ MX6_PAD_KEY_ROW7__KEY_ROW7 = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0),
+ MX6_PAD_KEY_ROW7__UART4_DCE_CTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__UART4_DTE_RTS = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0),
+ MX6_PAD_KEY_ROW7__LCD_DATA15 = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0),
+ MX6_PAD_KEY_ROW7__CSI_DATA23 = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO4_IO07 = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__SD1_CD_B = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0),
+
+ MX6_PAD_EPDC_DATA00__EPDC_DATA00 = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA00__ECSPI4_MOSI = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0),
+ MX6_PAD_EPDC_DATA00__LCD_DATA24 = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA00__CSI_DATA00 = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0),
+ MX6_PAD_EPDC_DATA00__GPIO1_IO07 = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA01__EPDC_DATA01 = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA01__ECSPI4_MISO = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0),
+ MX6_PAD_EPDC_DATA01__LCD_DATA25 = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA01__CSI_DATA01 = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0),
+ MX6_PAD_EPDC_DATA01__GPIO1_IO08 = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA02__EPDC_DATA02 = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA02__ECSPI4_SS0 = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0),
+ MX6_PAD_EPDC_DATA02__LCD_DATA26 = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA02__CSI_DATA02 = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0),
+ MX6_PAD_EPDC_DATA02__GPIO1_IO09 = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA03__EPDC_DATA03 = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA03__ECSPI4_SCLK = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0),
+ MX6_PAD_EPDC_DATA03__LCD_DATA27 = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA03__CSI_DATA03 = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0),
+ MX6_PAD_EPDC_DATA03__GPIO1_IO10 = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA04__EPDC_DATA04 = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA04__ECSPI4_SS1 = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0),
+ MX6_PAD_EPDC_DATA04__LCD_DATA28 = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA04__CSI_DATA04 = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0),
+ MX6_PAD_EPDC_DATA04__GPIO1_IO11 = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA05__EPDC_DATA05 = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA05__ECSPI4_SS2 = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0),
+ MX6_PAD_EPDC_DATA05__LCD_DATA29 = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA05__CSI_DATA05 = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0),
+ MX6_PAD_EPDC_DATA05__GPIO1_IO12 = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA06__EPDC_DATA06 = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__ECSPI4_SS3 = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__LCD_DATA30 = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA06__CSI_DATA06 = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0),
+ MX6_PAD_EPDC_DATA06__GPIO1_IO13 = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA07__EPDC_DATA07 = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__ECSPI4_RDY = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__LCD_DATA31 = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA07__CSI_DATA07 = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0),
+ MX6_PAD_EPDC_DATA07__GPIO1_IO14 = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA08__EPDC_DATA08 = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA08__ECSPI3_MOSI = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0),
+ MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA08__GPIO1_IO15 = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA09__EPDC_DATA09 = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA09__ECSPI3_MISO = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0),
+ MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA09__GPIO1_IO16 = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA10__ECSPI3_SS0 = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0),
+ MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA10__GPIO1_IO17 = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA11__ECSPI3_SCLK = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0),
+ MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA11__GPIO1_IO18 = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__UART2_DCE_RX = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0),
+ MX6_PAD_EPDC_DATA12__UART2_DTE_TX = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__EPDC_PWR_COM = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__GPIO1_IO19 = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA12__ECSPI3_SS1 = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0),
+
+ MX6_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__UART2_DCE_TX = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__UART2_DTE_RX = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0),
+ MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0),
+ MX6_PAD_EPDC_DATA13__GPIO1_IO20 = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA13__ECSPI3_SS2 = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0),
+
+ MX6_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__UART2_DCE_RTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0),
+ MX6_PAD_EPDC_DATA14__UART2_DTE_CTS = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0),
+ MX6_PAD_EPDC_DATA14__GPIO1_IO21 = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA14__ECSPI3_SS3 = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0),
+
+ MX6_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__UART2_DCE_CTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__UART2_DTE_RTS = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0),
+ MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__GPIO1_IO22 = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_DATA15__ECSPI3_RDY = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0),
+
+ MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0),
+ MX6_PAD_EPDC_SDCLK__I2C2_SCL = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0),
+ MX6_PAD_EPDC_SDCLK__CSI_DATA08 = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0),
+ MX6_PAD_EPDC_SDCLK__GPIO1_IO23 = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDLE__ECSPI2_MISO = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0),
+ MX6_PAD_EPDC_SDLE__I2C2_SDA = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0),
+ MX6_PAD_EPDC_SDLE__CSI_DATA09 = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0),
+ MX6_PAD_EPDC_SDLE__GPIO1_IO24 = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDOE__ECSPI2_SS0 = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0),
+ MX6_PAD_EPDC_SDOE__CSI_DATA10 = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0),
+ MX6_PAD_EPDC_SDOE__GPIO1_IO25 = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0),
+ MX6_PAD_EPDC_SDSHR__EPDC_SDCE4 = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDSHR__CSI_DATA11 = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0),
+ MX6_PAD_EPDC_SDSHR__GPIO1_IO26 = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE0__ECSPI2_SS1 = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0),
+ MX6_PAD_EPDC_SDCE0__PWM3_OUT = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE0__GPIO1_IO27 = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__WDOG2_B = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__PWM4_OUT = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE1__GPIO1_IO28 = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE2__I2C3_SCL = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0),
+ MX6_PAD_EPDC_SDCE2__PWM1_OUT = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE2__GPIO1_IO29 = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE3__I2C3_SDA = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0),
+ MX6_PAD_EPDC_SDCE3__PWM2_OUT = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_SDCE3__GPIO1_IO30 = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__ECSPI2_SS2 = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__CSI_PIXCLK = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0),
+ MX6_PAD_EPDC_GDCLK__GPIO1_IO31 = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDCLK__SD2_RESET = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__ECSPI2_SS3 = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__CSI_HSYNC = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0),
+ MX6_PAD_EPDC_GDOE__GPIO2_IO00 = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDOE__SD2_VSELECT = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__CSI_MCLK = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__GPIO2_IO01 = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDRL__SD2_WP = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0),
+
+ MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__PWM4_OUT = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__CSI_VSYNC = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0),
+ MX6_PAD_EPDC_GDSP__GPIO2_IO02 = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_GDSP__SD2_CD_B = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0),
+
+ MX6_PAD_EPDC_VCOM0__EPDC_VCOM0 = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__AUD5_RXFS = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0),
+ MX6_PAD_EPDC_VCOM0__UART3_DCE_RX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0),
+ MX6_PAD_EPDC_VCOM0__UART3_DTE_TX = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__GPIO2_IO03 = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM0__EPDC_SDCE5 = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_VCOM1__EPDC_VCOM1 = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__AUD5_RXD = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0),
+ MX6_PAD_EPDC_VCOM1__UART3_DCE_TX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__UART3_DTE_RX = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0),
+ MX6_PAD_EPDC_VCOM1__GPIO2_IO04 = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_VCOM1__EPDC_SDCE6 = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__UART3_DCE_RTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0),
+ MX6_PAD_EPDC_BDR0__UART3_DTE_CTS = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__GPIO2_IO05 = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR0__EPDC_SDCE7 = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__UART3_DCE_CTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__UART3_DTE_RTS = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0),
+ MX6_PAD_EPDC_BDR1__GPIO2_IO06 = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_BDR1__EPDC_SDCE8 = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16 = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17 = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18 = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19 = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0),
+ MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_COM__LCD_DATA20 = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0),
+ MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0),
+ MX6_PAD_EPDC_PWR_COM__GPIO2_IO11 = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_COM__SD3_RESET = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0),
+ MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21 = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0),
+ MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0),
+ MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12 = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0),
+ MX6_PAD_EPDC_PWR_STAT__LCD_DATA22 = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0),
+ MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_STAT__SD3_WP = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0),
+
+ MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23 = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0),
+ MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0),
+ MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0),
+
+ MX6_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__LCD_WR_RWN = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__PWM4_OUT = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_CLK__GPIO2_IO15 = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__LCD_RD_E = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART2_DCE_RX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__UART2_DTE_TX = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_ENABLE__GPIO2_IO16 = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0),
+ MX6_PAD_LCD_HSYNC__LCD_CS = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART2_DCE_TX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__UART2_DTE_RX = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0),
+ MX6_PAD_LCD_HSYNC__GPIO2_IO17 = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__LCD_RS = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__UART2_DCE_RTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0),
+ MX6_PAD_LCD_VSYNC__UART2_DTE_CTS = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__GPIO2_IO18 = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__LCD_BUSY = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0),
+ MX6_PAD_LCD_RESET__UART2_DCE_CTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__UART2_DTE_RTS = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0),
+ MX6_PAD_LCD_RESET__GPIO2_IO19 = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_RESET__CCM_PMIC_READY = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0),
+
+ MX6_PAD_LCD_DATA00__LCD_DATA00 = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0),
+ MX6_PAD_LCD_DATA00__ECSPI1_MOSI = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0),
+ MX6_PAD_LCD_DATA00__USB_OTG2_ID = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0),
+ MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__UART5_DTR_B = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__GPIO2_IO20 = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__ARM_TRACE00 = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00 = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA01__LCD_DATA01 = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0),
+ MX6_PAD_LCD_DATA01__ECSPI1_MISO = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0),
+ MX6_PAD_LCD_DATA01__USB_OTG1_ID = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0),
+ MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__AUD4_RXFS = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0),
+ MX6_PAD_LCD_DATA01__GPIO2_IO21 = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__ARM_TRACE01 = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01 = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA02__LCD_DATA02 = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0),
+ MX6_PAD_LCD_DATA02__ECSPI1_SS0 = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0),
+ MX6_PAD_LCD_DATA02__EPIT2_OUT = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__AUD4_RXC = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0),
+ MX6_PAD_LCD_DATA02__GPIO2_IO22 = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__ARM_TRACE02 = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02 = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA03__LCD_DATA03 = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0),
+ MX6_PAD_LCD_DATA03__ECSPI1_SCLK = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0),
+ MX6_PAD_LCD_DATA03__UART5_DSR_B = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__AUD4_RXD = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0),
+ MX6_PAD_LCD_DATA03__GPIO2_IO23 = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__ARM_TRACE03 = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03 = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA04__LCD_DATA04 = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0),
+ MX6_PAD_LCD_DATA04__ECSPI1_SS1 = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0),
+ MX6_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0),
+ MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__AUD4_TXC = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0),
+ MX6_PAD_LCD_DATA04__GPIO2_IO24 = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__ARM_TRACE04 = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04 = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA05__LCD_DATA05 = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0),
+ MX6_PAD_LCD_DATA05__ECSPI1_SS2 = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0),
+ MX6_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0),
+ MX6_PAD_LCD_DATA05__AUD4_TXFS = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0),
+ MX6_PAD_LCD_DATA05__GPIO2_IO25 = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__ARM_TRACE05 = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05 = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA06__LCD_DATA06 = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0),
+ MX6_PAD_LCD_DATA06__ECSPI1_SS3 = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0),
+ MX6_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0),
+ MX6_PAD_LCD_DATA06__AUD4_TXD = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0),
+ MX6_PAD_LCD_DATA06__GPIO2_IO26 = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__ARM_TRACE06 = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06 = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA07__LCD_DATA07 = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0),
+ MX6_PAD_LCD_DATA07__ECSPI1_RDY = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0),
+ MX6_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__GPIO2_IO27 = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__ARM_TRACE07 = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07 = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA08__LCD_DATA08 = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0),
+ MX6_PAD_LCD_DATA08__KEY_COL0 = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0),
+ MX6_PAD_LCD_DATA08__CSI_DATA09 = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0),
+ MX6_PAD_LCD_DATA08__ECSPI2_SCLK = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0),
+ MX6_PAD_LCD_DATA08__GPIO2_IO28 = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__ARM_TRACE08 = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08 = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA09__LCD_DATA09 = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0),
+ MX6_PAD_LCD_DATA09__KEY_ROW0 = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0),
+ MX6_PAD_LCD_DATA09__CSI_DATA08 = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0),
+ MX6_PAD_LCD_DATA09__ECSPI2_MOSI = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0),
+ MX6_PAD_LCD_DATA09__GPIO2_IO29 = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__ARM_TRACE09 = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09 = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0),
+ MX6_PAD_LCD_DATA10__KEY_COL1 = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0),
+ MX6_PAD_LCD_DATA10__CSI_DATA07 = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0),
+ MX6_PAD_LCD_DATA10__ECSPI2_MISO = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0),
+ MX6_PAD_LCD_DATA10__GPIO2_IO30 = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__ARM_TRACE10 = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0),
+ MX6_PAD_LCD_DATA11__KEY_ROW1 = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0),
+ MX6_PAD_LCD_DATA11__CSI_DATA06 = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0),
+ MX6_PAD_LCD_DATA11__ECSPI2_SS1 = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0),
+ MX6_PAD_LCD_DATA11__GPIO2_IO31 = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__ARM_TRACE11 = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0),
+ MX6_PAD_LCD_DATA12__KEY_COL2 = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0),
+ MX6_PAD_LCD_DATA12__CSI_DATA05 = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0),
+ MX6_PAD_LCD_DATA12__UART5_DCE_RTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0),
+ MX6_PAD_LCD_DATA12__UART5_DTE_CTS = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__GPIO3_IO00 = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__ARM_TRACE12 = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0),
+ MX6_PAD_LCD_DATA13__KEY_ROW2 = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0),
+ MX6_PAD_LCD_DATA13__CSI_DATA04 = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0),
+ MX6_PAD_LCD_DATA13__UART5_DCE_CTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__UART5_DTE_RTS = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0),
+ MX6_PAD_LCD_DATA13__GPIO3_IO01 = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__ARM_TRACE13 = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0),
+ MX6_PAD_LCD_DATA14__KEY_COL3 = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0),
+ MX6_PAD_LCD_DATA14__CSI_DATA03 = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0),
+ MX6_PAD_LCD_DATA14__UART5_DCE_RX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0),
+ MX6_PAD_LCD_DATA14__UART5_DTE_TX = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__GPIO3_IO02 = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__ARM_TRACE14 = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0),
+ MX6_PAD_LCD_DATA15__KEY_ROW3 = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0),
+ MX6_PAD_LCD_DATA15__CSI_DATA02 = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0),
+ MX6_PAD_LCD_DATA15__UART5_DCE_TX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__UART5_DTE_RX = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0),
+ MX6_PAD_LCD_DATA15__GPIO3_IO03 = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__ARM_TRACE15 = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0),
+ MX6_PAD_LCD_DATA16__KEY_COL4 = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0),
+ MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0),
+ MX6_PAD_LCD_DATA16__I2C2_SCL = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0),
+ MX6_PAD_LCD_DATA16__GPIO3_IO04 = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24 = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0),
+ MX6_PAD_LCD_DATA17__KEY_ROW4 = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0),
+ MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0),
+ MX6_PAD_LCD_DATA17__I2C2_SDA = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0),
+ MX6_PAD_LCD_DATA17__GPIO3_IO05 = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25 = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0),
+ MX6_PAD_LCD_DATA18__KEY_COL5 = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0),
+ MX6_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0),
+ MX6_PAD_LCD_DATA18__GPT_CAPTURE1 = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0),
+ MX6_PAD_LCD_DATA18__GPIO3_IO06 = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26 = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0),
+ MX6_PAD_LCD_DATA19__KEY_ROW5 = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0),
+ MX6_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0),
+ MX6_PAD_LCD_DATA19__GPT_CAPTURE2 = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0),
+ MX6_PAD_LCD_DATA19__GPIO3_IO07 = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27 = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0),
+ MX6_PAD_LCD_DATA20__KEY_COL6 = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0),
+ MX6_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0),
+ MX6_PAD_LCD_DATA20__GPT_COMPARE1 = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__GPIO3_IO08 = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28 = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0),
+ MX6_PAD_LCD_DATA21__KEY_ROW6 = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0),
+ MX6_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0),
+ MX6_PAD_LCD_DATA21__GPT_COMPARE2 = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__GPIO3_IO09 = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29 = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0),
+ MX6_PAD_LCD_DATA22__KEY_COL7 = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0),
+ MX6_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0),
+ MX6_PAD_LCD_DATA22__GPT_COMPARE3 = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__GPIO3_IO10 = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30 = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0),
+
+ MX6_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0),
+ MX6_PAD_LCD_DATA23__KEY_ROW7 = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0),
+ MX6_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0),
+ MX6_PAD_LCD_DATA23__GPT_CLKIN = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0),
+ MX6_PAD_LCD_DATA23__GPIO3_IO11 = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0),
+ MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31 = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_RXFS__AUD3_RXFS = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__I2C1_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0),
+ MX6_PAD_AUD_RXFS__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0),
+ MX6_PAD_AUD_RXFS__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__I2C3_SCL = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0),
+ MX6_PAD_AUD_RXFS__GPIO1_IO00 = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXFS__ECSPI3_SS0 = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0),
+ MX6_PAD_AUD_RXFS__MBIST_BEND = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_RXC__AUD3_RXC = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__I2C1_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0),
+ MX6_PAD_AUD_RXC__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0),
+ MX6_PAD_AUD_RXC__I2C3_SDA = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0),
+ MX6_PAD_AUD_RXC__GPIO1_IO01 = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXC__ECSPI3_SS1 = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0),
+
+ MX6_PAD_AUD_RXD__AUD3_RXD = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__ECSPI3_MOSI = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0),
+ MX6_PAD_AUD_RXD__UART4_DCE_RX = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0),
+ MX6_PAD_AUD_RXD__UART4_DTE_TX = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__SD1_LCTL = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_RXD__GPIO1_IO02 = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXC__AUD3_TXC = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__ECSPI3_MISO = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0),
+ MX6_PAD_AUD_TXC__UART4_DCE_TX = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__UART4_DTE_RX = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0),
+ MX6_PAD_AUD_TXC__SD2_LCTL = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXC__GPIO1_IO03 = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXFS__AUD3_TXFS = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__PWM3_OUT = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__UART4_DCE_RTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0),
+ MX6_PAD_AUD_TXFS__UART4_DTE_CTS = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__SD3_LCTL = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXFS__GPIO1_IO04 = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_TXD__AUD3_TXD = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXD__ECSPI3_SCLK = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0),
+ MX6_PAD_AUD_TXD__UART4_DCE_CTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0),
+ MX6_PAD_AUD_TXD__UART4_DTE_RTS = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0),
+ MX6_PAD_AUD_TXD__GPIO1_IO05 = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__PWM4_OUT = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__ECSPI3_RDY = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0),
+ MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__GPIO1_IO06 = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0),
+ MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0),
+
+ MX6_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0),
+
+ MX6_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__PWM1_OUT = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART4_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0),
+ MX6_PAD_UART1_RXD__UART4_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART5_DCE_RX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0),
+ MX6_PAD_UART1_RXD__UART5_DTE_TX = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__GPIO3_IO16 = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0),
+
+ MX6_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0),
+ MX6_PAD_UART1_TXD__PWM2_OUT = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART4_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART4_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0),
+ MX6_PAD_UART1_TXD__UART5_DCE_TX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART5_DTE_RX = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0),
+ MX6_PAD_UART1_TXD__GPIO3_IO17 = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0),
+ MX6_PAD_UART1_TXD__UART5_DCD_B = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0),
+
+ MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0),
+ MX6_PAD_I2C1_SCL__UART1_DCE_RTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0),
+ MX6_PAD_I2C1_SCL__UART1_DTE_CTS = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__ECSPI3_SS2 = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0),
+ MX6_PAD_I2C1_SCL__SD3_RESET = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__GPIO3_IO12 = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SCL__ECSPI1_SS1 = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0),
+
+ MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0),
+ MX6_PAD_I2C1_SDA__UART1_DCE_CTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__UART1_DTE_RTS = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0),
+ MX6_PAD_I2C1_SDA__ECSPI3_SS3 = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0),
+ MX6_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__GPIO3_IO13 = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C1_SDA__ECSPI1_SS2 = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0),
+
+ MX6_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0),
+ MX6_PAD_I2C2_SCL__AUD4_RXFS = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0),
+ MX6_PAD_I2C2_SCL__SPDIF_IN = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0),
+ MX6_PAD_I2C2_SCL__SD3_WP = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0),
+ MX6_PAD_I2C2_SCL__GPIO3_IO14 = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0),
+ MX6_PAD_I2C2_SCL__ECSPI1_RDY = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0),
+
+ MX6_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0),
+ MX6_PAD_I2C2_SDA__AUD4_RXC = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0),
+ MX6_PAD_I2C2_SDA__SPDIF_OUT = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0),
+ MX6_PAD_I2C2_SDA__SD3_CD_B = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0),
+ MX6_PAD_I2C2_SDA__GPIO3_IO15 = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0),
+ MX6_PAD_ECSPI1_SCLK__AUD4_TXD = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0),
+ MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0),
+ MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0 = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__SD2_RESET = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0),
+
+ MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0),
+ MX6_PAD_ECSPI1_MOSI__AUD4_TXC = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0),
+ MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0),
+ MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1 = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__SD2_VSELECT = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MOSI__GPIO4_IO09 = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0),
+ MX6_PAD_ECSPI1_MISO__AUD4_TXFS = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0),
+ MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0),
+ MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MISO__EPDC_BDR0 = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_MISO__SD2_WP = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0),
+ MX6_PAD_ECSPI1_MISO__GPIO4_IO10 = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0),
+ MX6_PAD_ECSPI1_SS0__AUD4_RXD = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0),
+ MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0),
+ MX6_PAD_ECSPI1_SS0__EPDC_BDR1 = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__SD2_CD_B = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0),
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0),
+ MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0),
+ MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0),
+ MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0),
+ MX6_PAD_ECSPI2_SCLK__SD1_RESET = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__GPIO4_IO12 = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0),
+
+ MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0),
+ MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0),
+ MX6_PAD_ECSPI2_MOSI__CSI_HSYNC = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0),
+ MX6_PAD_ECSPI2_MOSI__SD1_VSELECT = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MOSI__GPIO4_IO13 = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0),
+ MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0),
+ MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__CSI_MCLK = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__SD1_WP = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0),
+ MX6_PAD_ECSPI2_MISO__GPIO4_IO14 = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_MISO__USB_OTG1_OC = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0),
+
+ MX6_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0),
+ MX6_PAD_ECSPI2_SS0__ECSPI1_SS3 = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0),
+ MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0),
+ MX6_PAD_ECSPI2_SS0__CSI_VSYNC = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0),
+ MX6_PAD_ECSPI2_SS0__SD1_CD_B = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0),
+ MX6_PAD_ECSPI2_SS0__GPIO4_IO15 = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0),
+ MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__KEY_COL0 = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0),
+ MX6_PAD_SD1_CLK__EPDC_SDCE4 = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__GPIO5_IO15 = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__KEY_ROW0 = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0),
+ MX6_PAD_SD1_CMD__EPDC_SDCE5 = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__GPIO5_IO14 = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__KEY_COL1 = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0),
+ MX6_PAD_SD1_DATA0__EPDC_SDCE6 = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA0__GPIO5_IO11 = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__KEY_ROW1 = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0),
+ MX6_PAD_SD1_DATA1__EPDC_SDCE7 = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA1__GPIO5_IO08 = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__KEY_COL2 = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0),
+ MX6_PAD_SD1_DATA2__EPDC_SDCE8 = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA2__GPIO5_IO13 = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__KEY_ROW2 = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0),
+ MX6_PAD_SD1_DATA3__EPDC_SDCE9 = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA3__GPIO5_IO06 = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA4__SD1_DATA4 = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__KEY_COL3 = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0),
+ MX6_PAD_SD1_DATA4__EPDC_SDCLK_N = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__UART4_DCE_RX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0),
+ MX6_PAD_SD1_DATA4__UART4_DTE_TX = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA4__GPIO5_IO12 = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA5__SD1_DATA5 = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__KEY_ROW3 = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0),
+ MX6_PAD_SD1_DATA5__EPDC_SDOED = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__UART4_DCE_TX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA5__UART4_DTE_RX = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0),
+ MX6_PAD_SD1_DATA5__GPIO5_IO09 = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA6__SD1_DATA6 = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__KEY_COL4 = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0),
+ MX6_PAD_SD1_DATA6__EPDC_SDOEZ = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__UART4_DCE_RTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0),
+ MX6_PAD_SD1_DATA6__UART4_DTE_CTS = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA6__GPIO5_IO07 = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD1_DATA7__SD1_DATA7 = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA7__KEY_ROW4 = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0),
+ MX6_PAD_SD1_DATA7__CCM_PMIC_READY = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0),
+ MX6_PAD_SD1_DATA7__UART4_DCE_CTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0),
+ MX6_PAD_SD1_DATA7__UART4_DTE_RTS = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0),
+ MX6_PAD_SD1_DATA7__GPIO5_IO10 = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_RESET__SD2_RESET = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__WDOG2_B = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__SPDIF_OUT = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__CSI_MCLK = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_RESET__GPIO4_IO27 = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CLK__AUD4_RXFS = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0),
+ MX6_PAD_SD2_CLK__ECSPI3_SCLK = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0),
+ MX6_PAD_SD2_CLK__CSI_DATA00 = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0),
+ MX6_PAD_SD2_CLK__GPIO5_IO05 = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__AUD4_RXC = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0),
+ MX6_PAD_SD2_CMD__ECSPI3_SS0 = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0),
+ MX6_PAD_SD2_CMD__CSI_DATA01 = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0),
+ MX6_PAD_SD2_CMD__EPIT1_OUT = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__GPIO5_IO04 = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA0__AUD4_RXD = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0),
+ MX6_PAD_SD2_DATA0__ECSPI3_MOSI = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0),
+ MX6_PAD_SD2_DATA0__CSI_DATA02 = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0),
+ MX6_PAD_SD2_DATA0__UART5_DCE_RTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0),
+ MX6_PAD_SD2_DATA0__UART5_DTE_CTS = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA0__GPIO5_IO01 = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA1__AUD4_TXC = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0),
+ MX6_PAD_SD2_DATA1__ECSPI3_MISO = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0),
+ MX6_PAD_SD2_DATA1__CSI_DATA03 = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0),
+ MX6_PAD_SD2_DATA1__UART5_DCE_CTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA1__UART5_DTE_RTS = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0),
+ MX6_PAD_SD2_DATA1__GPIO4_IO30 = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA2__AUD4_TXFS = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0),
+ MX6_PAD_SD2_DATA2__CSI_DATA04 = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0),
+ MX6_PAD_SD2_DATA2__UART5_DCE_RX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0),
+ MX6_PAD_SD2_DATA2__UART5_DTE_TX = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA2__GPIO5_IO03 = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA3__AUD4_TXD = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0),
+ MX6_PAD_SD2_DATA3__CSI_DATA05 = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0),
+ MX6_PAD_SD2_DATA3__UART5_DCE_TX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA3__UART5_DTE_RX = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0),
+ MX6_PAD_SD2_DATA3__GPIO4_IO28 = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA4__SD2_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__SD3_DATA4 = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0),
+ MX6_PAD_SD2_DATA4__UART2_DCE_RX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0),
+ MX6_PAD_SD2_DATA4__UART2_DTE_TX = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__CSI_DATA06 = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0),
+ MX6_PAD_SD2_DATA4__SPDIF_OUT = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA4__GPIO5_IO02 = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA5__SD2_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA5__SD3_DATA5 = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0),
+ MX6_PAD_SD2_DATA5__UART2_DCE_TX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA5__UART2_DTE_RX = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0),
+ MX6_PAD_SD2_DATA5__CSI_DATA07 = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0),
+ MX6_PAD_SD2_DATA5__SPDIF_IN = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0),
+ MX6_PAD_SD2_DATA5__GPIO4_IO31 = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA6__SD2_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA6__SD3_DATA6 = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0),
+ MX6_PAD_SD2_DATA6__UART2_DCE_RTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0),
+ MX6_PAD_SD2_DATA6__UART2_DTE_CTS = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA6__CSI_DATA08 = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0),
+ MX6_PAD_SD2_DATA6__SD2_WP = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0),
+ MX6_PAD_SD2_DATA6__GPIO4_IO29 = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD2_DATA7__SD2_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA7__SD3_DATA7 = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0),
+ MX6_PAD_SD2_DATA7__UART2_DCE_CTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0),
+ MX6_PAD_SD2_DATA7__UART2_DTE_RTS = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0),
+ MX6_PAD_SD2_DATA7__CSI_DATA09 = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0),
+ MX6_PAD_SD2_DATA7__SD2_CD_B = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0),
+ MX6_PAD_SD2_DATA7__GPIO5_IO00 = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__AUD5_RXFS = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0),
+ MX6_PAD_SD3_CLK__KEY_COL5 = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0),
+ MX6_PAD_SD3_CLK__CSI_DATA10 = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0),
+ MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__GPIO5_IO18 = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USB_OTG1_PWR = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__AUD5_RXC = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0),
+ MX6_PAD_SD3_CMD__KEY_ROW5 = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0),
+ MX6_PAD_SD3_CMD__CSI_DATA11 = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0),
+ MX6_PAD_SD3_CMD__USB_OTG2_ID = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0),
+ MX6_PAD_SD3_CMD__GPIO5_IO21 = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USB_OTG2_PWR = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA0__AUD5_RXD = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0),
+ MX6_PAD_SD3_DATA0__KEY_COL6 = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0),
+ MX6_PAD_SD3_DATA0__CSI_DATA12 = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0),
+ MX6_PAD_SD3_DATA0__USB_OTG1_ID = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0),
+ MX6_PAD_SD3_DATA0__GPIO5_IO19 = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__AUD5_TXC = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0),
+ MX6_PAD_SD3_DATA1__KEY_ROW6 = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0),
+ MX6_PAD_SD3_DATA1__CSI_DATA13 = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0),
+ MX6_PAD_SD3_DATA1__SD1_VSELECT = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__GPIO5_IO20 = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA1__JTAG_DE_B = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0),
+
+ MX6_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__AUD5_TXFS = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0),
+ MX6_PAD_SD3_DATA2__KEY_COL7 = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0),
+ MX6_PAD_SD3_DATA2__CSI_DATA14 = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0),
+ MX6_PAD_SD3_DATA2__EPIT1_OUT = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__GPIO5_IO16 = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA2__USB_OTG2_OC = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0),
+
+ MX6_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__AUD5_TXD = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0),
+ MX6_PAD_SD3_DATA3__KEY_ROW7 = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0),
+ MX6_PAD_SD3_DATA3__CSI_DATA15 = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0),
+ MX6_PAD_SD3_DATA3__EPIT2_OUT = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__GPIO5_IO17 = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_DATA3__USB_OTG1_OC = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0),
+
+ MX6_PAD_GPIO4_IO20__SD1_STROBE = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO20__AUD6_RXFS = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0),
+ MX6_PAD_GPIO4_IO20__ECSPI4_SS0 = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0),
+ MX6_PAD_GPIO4_IO20__GPT_CAPTURE1 = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0),
+ MX6_PAD_GPIO4_IO20__GPIO4_IO20 = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO4_IO21__SD2_STROBE = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO21__AUD6_RXC = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0),
+ MX6_PAD_GPIO4_IO21__ECSPI4_SCLK = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0),
+ MX6_PAD_GPIO4_IO21__GPT_CAPTURE2 = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0),
+ MX6_PAD_GPIO4_IO21__GPIO4_IO21 = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0),
+
+ MX6_PAD_GPIO4_IO19__SD3_STROBE = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO19__AUD6_RXD = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0),
+ MX6_PAD_GPIO4_IO19__ECSPI4_MOSI = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0),
+ MX6_PAD_GPIO4_IO19__GPT_COMPARE1 = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO19__GPIO4_IO19 = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO25__AUD6_TXC = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0),
+ MX6_PAD_GPIO4_IO25__ECSPI4_MISO = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0),
+ MX6_PAD_GPIO4_IO25__GPT_COMPARE2 = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO25__GPIO4_IO25 = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO18__AUD6_TXFS = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0),
+ MX6_PAD_GPIO4_IO18__ECSPI4_SS1 = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0),
+ MX6_PAD_GPIO4_IO18__GPT_COMPARE3 = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO18__GPIO4_IO18 = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO24__AUD6_TXD = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0),
+ MX6_PAD_GPIO4_IO24__ECSPI4_SS2 = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0),
+ MX6_PAD_GPIO4_IO24__GPT_CLKIN = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0),
+ MX6_PAD_GPIO4_IO24__GPIO4_IO24 = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__SD1_RESET = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__SD3_RESET = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO23__GPIO4_IO23 = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__USB_OTG1_ID = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0),
+ MX6_PAD_GPIO4_IO17__SD1_VSELECT = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__SD3_VSELECT = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO17__GPIO4_IO17 = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO22__SPDIF_IN = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0),
+ MX6_PAD_GPIO4_IO22__SD1_WP = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0),
+ MX6_PAD_GPIO4_IO22__SD3_WP = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0),
+ MX6_PAD_GPIO4_IO22__GPIO4_IO22 = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO16__SPDIF_OUT = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO16__SD1_CD_B = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0),
+ MX6_PAD_GPIO4_IO16__SD3_CD_B = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0),
+ MX6_PAD_GPIO4_IO16__GPIO4_IO16 = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__WDOG1_B = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__PWM4_OUT = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__CCM_PMIC_READY = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0),
+ MX6_PAD_GPIO4_IO26__GPIO4_IO26 = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX6SLL_PINS_H__ */
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 03/19] imx: mx6sll: update register address
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 01/19] imx: add i.MX 6SLL CPU type Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 02/19] imx: mx6sll: add pinmux header files Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 04/19] imx-common: timer: add i.MX6SLL support Peng Fan
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Update register address for i.MX6 SLL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx6/imx-regs.h | 76 ++++++++++++++++++++------------
1 file changed, 49 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8bb36eb..53e499c 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -26,7 +26,7 @@
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
-#else
+#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
@@ -46,13 +46,9 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
#define GPV2_BASE_ADDR 0x00D00000
-#else
-#define GPV2_BASE_ADDR 0x00200000
-#endif
-
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
@@ -61,6 +57,7 @@
#define PCIE_ARB_END_ADDR 0x08FFFFFF
#else
+#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000
@@ -96,7 +93,7 @@
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
-#else
+#elif !defined(CONFIG_MX6SLL)
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
@@ -111,7 +108,8 @@
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
@@ -141,19 +139,21 @@
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
-#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
-#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
-#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
-#else
+
+#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+
#ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
@@ -161,7 +161,6 @@
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#endif
#ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
@@ -176,6 +175,8 @@
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
@@ -198,11 +199,18 @@
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
-#ifdef CONFIG_MX6SL
+#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#ifdef CONFIG_MX6SLL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SL)
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#elif CONFIG_MX6SX
+#elif defined(CONFIG_MX6SX)
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
@@ -215,6 +223,9 @@
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif
+#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
@@ -249,7 +260,7 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
-/* i.MX6SL */
+/* i.MX6SL/SLL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#ifdef CONFIG_MX6UL
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
@@ -263,6 +274,10 @@
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SLL
+#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
@@ -296,6 +311,8 @@
#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
@@ -334,7 +351,8 @@
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
@@ -348,10 +366,14 @@
/* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
-#define LCDIF1_BASE_ADDR ((is_mx6ul()) ? \
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
+ MX6SLL_LCDIF_BASE_ADDR : \
+ (is_cpu_type(MXC_CPU_MX6SL)) ? \
+ MX6SL_LCDIF_BASE_ADDR : \
+ ((is_cpu_type(MXC_CPU_MX6UL)) ? \
MX6UL_LCDIF1_BASE_ADDR : \
((is_mx6ull()) ? \
- MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))
+ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -672,7 +694,7 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
+#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 04/19] imx-common: timer: add i.MX6SLL support
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (2 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 03/19] imx: mx6sll: update register address Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 05/19] imx: mx6sll: add iomux settings Peng Fan
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add i.MX6 SLL GPT timer support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/imx-common/timer.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1f7c671..ee6eff2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -45,7 +45,7 @@ static inline int gpt_has_clk_source_osc(void)
#if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull())
+ is_mx6ull() || is_mx6sll())
return 1;
return 0;
@@ -84,8 +84,12 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
- /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */
- if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) {
+ /*
+ * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+ * Enable bit and prescaler
+ */
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+ is_mx6sll()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 05/19] imx: mx6sll: add iomux settings
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (3 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 04/19] imx-common: timer: add i.MX6SLL support Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 06/19] imx: mx6: fix mmdc ch0 clk for 6SL Peng Fan
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add iomux settings for i.MX6 SLL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/imx-common/iomux-v3.c | 10 +++++++---
arch/arm/include/asm/imx-common/iomux-v3.h | 6 ++++--
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 392f4bc..c9a3bf2 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-#if defined CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
@@ -51,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
#else
- if (is_mx6ull()) {
+ if (is_mx6ull() || is_mx6sll()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
@@ -60,7 +60,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#endif
#endif
- if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs)
+ if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
@@ -73,6 +73,10 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+ else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
+#endif
#endif
#ifdef CONFIG_IOMUX_LPSR
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index b3af696..7587cbb 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -144,10 +144,12 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
-#if defined CONFIG_MX6SL
+/* i.MX6SL/SLL */
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
-#endif
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT (1 << 27)
#elif defined(CONFIG_VF610)
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 06/19] imx: mx6: fix mmdc ch0 clk for 6SL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (4 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 05/19] imx: mx6sll: add iomux settings Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 07/19] imx: mx6: lcdif: gate clock before changing mux Peng Fan
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ae3143c..8ab07b6 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
+ if (is_mx6sl()) {
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+ break;
+ }
+
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0:
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 07/19] imx: mx6: lcdif: gate clock before changing mux
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (5 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 06/19] imx: mx6: fix mmdc ch0 clk for 6SL Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 08/19] imx: mx6sl: add lcdif clock support Peng Fan
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
The mux for the lcd clock is not glitchless,
so need to first gate the clock before changing the mux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 8ab07b6..644b9d7 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -771,6 +771,16 @@ int enable_lcdif_clock(u32 base_addr)
return 0;
}
+ /* Gate LCDIF clock first */
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg &= ~MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+
+ /* Select pre-mux */
reg = readl(&imx_ccm->cscdr2);
reg &= ~lcdif_clk_sel_mask;
writel(reg, &imx_ccm->cscdr2);
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 08/19] imx: mx6sl: add lcdif clock support
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (6 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 07/19] imx: mx6: lcdif: gate clock before changing mux Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 09/19] imx: clock: gate clk before changing pix clk mux Peng Fan
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add lcdif clock support for i.MX6SL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/cpu/armv7/mx6/clock.c | 78 ++++++++++++++++++++++++--------
arch/arm/include/asm/arch-mx6/crm_regs.h | 21 +++++++++
2 files changed, 80 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 644b9d7..e307b28 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -625,16 +625,18 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
debug("This chip not support lcd!\n");
return;
}
- if (base_addr == LCDIF1_BASE_ADDR) {
- reg = readl(&imx_ccm->cscdr2);
- /* Can't change clocks when clock not from pre-mux */
- if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
- return;
+ if (!is_mx6sl()) {
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+ return;
+ }
}
if (is_mx6sx()) {
@@ -705,19 +707,35 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
- /* Select pre-lcd clock to PLL5 and set pre divider */
- clrsetbits_le32(&imx_ccm->cscdr2,
- MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
- (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
- ((pred - 1) <<
- MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
-
- /* Set the post divider */
- clrsetbits_le32(&imx_ccm->cbcmr,
- MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
- ((postd - 1) <<
- MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ if (!is_mx6sl()) {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cbcmr,
+ MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ } else {
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK,
+ (((postd - 1)^0x6) <<
+ MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
+ }
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -767,6 +785,28 @@ int enable_lcdif_clock(u32 base_addr)
/* Set to pre-mux clock@default */
lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+ } else if (is_mx6sl()) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg &= ~(MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK);
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->cscdr3);
+ reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscdr3);
+
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+
+ return 0;
} else {
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index f74737a..7eade7b 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -307,6 +307,9 @@ struct mxc_ccm_reg {
/* LCFIF2_PODF on i.MX6SX */
#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20
+/* LCDIF_PIX_PODF on i.MX6SL */
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK (0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET 20
/* ACLK_EMI on i.MX6DQ/SDL/DQP */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
@@ -529,6 +532,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0)
#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0
+/*LCD on i.MX6SL */
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET 6
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET 3
+
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
@@ -554,6 +563,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
+/* For i.MX6SL */
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14
+
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
@@ -783,6 +798,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
+/* i.MX6SL */
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 09/19] imx: clock: gate clk before changing pix clk mux
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (7 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 08/19] imx: mx6sl: add lcdif clock support Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 10/19] imx: mx6sll: add clock support Peng Fan
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 50 ++++++++++++++---------
arch/arm/include/asm/arch-mx6/clock.h | 2 +-
board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +-
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +-
4 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e307b28..0f68218 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -707,6 +707,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
+ enable_lcdif_clock(base_addr, 0);
if (!is_mx6sl()) {
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(&imx_ccm->cscdr2,
@@ -736,11 +737,14 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
(((postd - 1)^0x6) <<
MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET));
}
+
+ enable_lcdif_clock(base_addr, 1);
} else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
+ enable_lcdif_clock(base_addr, 0);
/* Select pre-lcd clock to PLL5 and set pre divider */
clrsetbits_le32(&imx_ccm->cscdr2,
MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
@@ -754,10 +758,12 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
((postd - 1) <<
MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+
+ enable_lcdif_clock(base_addr, 1);
}
}
-int enable_lcdif_clock(u32 base_addr)
+int enable_lcdif_clock(u32 base_addr, bool enable)
{
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
@@ -796,15 +802,17 @@ int enable_lcdif_clock(u32 base_addr)
MXC_CCM_CCGR3_LCDIF_PIX_MASK);
writel(reg, &imx_ccm->CCGR3);
- reg = readl(&imx_ccm->cscdr3);
- reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
- reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
- writel(reg, &imx_ccm->cscdr3);
+ if (enable) {
+ reg = readl(&imx_ccm->cscdr3);
+ reg &= ~MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET;
+ writel(reg, &imx_ccm->cscdr3);
- reg = readl(&imx_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
- MXC_CCM_CCGR3_LCDIF_PIX_MASK;
- writel(reg, &imx_ccm->CCGR3);
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LCDIF_AXI_MASK |
+ MXC_CCM_CCGR3_LCDIF_PIX_MASK;
+ writel(reg, &imx_ccm->CCGR3);
+ }
return 0;
} else {
@@ -820,19 +828,21 @@ int enable_lcdif_clock(u32 base_addr)
reg &= ~MXC_CCM_CCGR2_LCD_MASK;
writel(reg, &imx_ccm->CCGR2);
- /* Select pre-mux */
- reg = readl(&imx_ccm->cscdr2);
- reg &= ~lcdif_clk_sel_mask;
- writel(reg, &imx_ccm->cscdr2);
+ if (enable) {
+ /* Select pre-mux */
+ reg = readl(&imx_ccm->cscdr2);
+ reg &= ~lcdif_clk_sel_mask;
+ writel(reg, &imx_ccm->cscdr2);
- /* Enable the LCDIF pix clock */
- reg = readl(&imx_ccm->CCGR3);
- reg |= lcdif_ccgr3_mask;
- writel(reg, &imx_ccm->CCGR3);
+ /* Enable the LCDIF pix clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
- reg = readl(&imx_ccm->CCGR2);
- reg |= MXC_CCM_CCGR2_LCD_MASK;
- writel(reg, &imx_ccm->CCGR2);
+ reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+ }
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 82f9f92..0cbf699 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -74,7 +74,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
-int enable_lcdif_clock(u32 base_addr);
+int enable_lcdif_clock(u32 base_addr, bool enable);
void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
void mxs_set_lcdclk(u32 base_addr, u32 freq);
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 965e511..0460cd9 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -504,7 +504,7 @@ static iomux_v3_cfg_t const lcd_pads[] = {
static int setup_lcd(void)
{
- enable_lcdif_clock(LCDIF1_BASE_ADDR);
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 399bad2..b28ce10 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -600,7 +600,7 @@ static iomux_v3_cfg_t const lcd_pads[] = {
static int setup_lcd(void)
{
- enable_lcdif_clock(LCDIF1_BASE_ADDR);
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 10/19] imx: mx6sll: add clock support
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (8 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 09/19] imx: clock: gate clk before changing pix clk mux Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL Peng Fan
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add clock support for i.MX6SLL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 28 +++++++++++++++++++++-------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 0f68218..fe5c349 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -171,6 +171,8 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
+ if (is_mx6sll())
+ return -EINVAL;
if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
@@ -382,7 +384,7 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_mx6sl() || is_mx6sx() ||
+ if (is_mx6sll() || is_mx6sl() || is_mx6sx() ||
is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
@@ -400,7 +402,7 @@ static u32 get_uart_clk(void)
reg = __raw_readl(&imx_ccm->cscdr1);
if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
- is_mx6ull()) {
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
@@ -420,7 +422,7 @@ static u32 get_cspi_clk(void)
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull()) {
+ is_mx6sll() || is_mx6ull()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
@@ -482,7 +484,8 @@ static u32 get_mmdc_ch0_clk(void)
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
- if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() ||
+ is_mx6sll()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -625,7 +628,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) {
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+ !is_mx6sll()) {
debug("This chip not support lcd!\n");
return;
}
@@ -783,7 +787,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_mx6ul() || is_mx6ull()) {
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
@@ -976,6 +980,16 @@ static u32 get_usdhc_clk(u32 port)
u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
+ if (is_mx6ul() || is_mx6ull()) {
+ if (port > 1)
+ return 0;
+ }
+
+ if (is_mx6sll()) {
+ if (port > 2)
+ return 0;
+ }
+
switch (port) {
case 0:
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
@@ -1139,7 +1153,7 @@ void hab_caam_clock_enable(unsigned char enable)
{
u32 reg;
- if (is_mx6ull()) {
+ if (is_mx6ull() || is_mx6sll()) {
/* CG5, DCP clock */
reg = __raw_readl(&imx_ccm->CCGR0);
if (enable)
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (9 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 10/19] imx: mx6sll: add clock support Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 12/19] imx: mx6sll: add Kconfig entry " Peng Fan
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
If L2 cache configured as OCRAM, reset it.
Switch to use runtime check.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/imx-common/cache.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index b775488..1c4a9a2 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/io.h>
+#include <asm/imx-common/sys_proto.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
@@ -39,6 +40,7 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val;
@@ -55,15 +57,14 @@ void v7_outer_cache_enable(void)
*/
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
+ if (is_mx6sl() || is_mx6sll()) {
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
}
-#endif
writel(0x132, &pl310->pl310_tag_latency_ctrl);
writel(0x132, &pl310->pl310_data_latency_ctrl);
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 12/19] imx: mx6sll: add Kconfig entry for i.MX6SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (10 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 13/19] mx6_common: correct loadaddr and text base " Peng Fan
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
add Kconfig entry for i.MX6SLL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..72bc083 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -26,6 +26,10 @@ config MX6SX
select ROM_UNIFIED_SECTIONS
bool
+config MX6SLL
+ select ROM_UNIFIED_SECTIONS
+ bool
+
config MX6UL
select SYS_L2CACHE_OFF
select ROM_UNIFIED_SECTIONS
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 13/19] mx6_common: correct loadaddr and text base for i.MX6SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (11 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 12/19] imx: mx6sll: add Kconfig entry " Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL Peng Fan
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Correct loadaddr and text base for i.MX6SLL
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
include/configs/mx6_common.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index d28654b..c3a1257 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -44,7 +44,8 @@
#define CONFIG_REVISION_TAG
/* Boot options */
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6UL))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
#define CONFIG_LOADADDR 0x82000000
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x87800000
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (12 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 13/19] mx6_common: correct loadaddr and text base " Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL Peng Fan
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add the i.MX6SLL support to OCOTP driver.
The i.MX6SLL reuses the i.MX6ULL fuse, bank 7 and bank8 have 4 words
each, and there is a hole between bank 5 and bank 6.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/misc/mxc_ocotp.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 8a100c1..0b1c050 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -62,7 +62,7 @@
#define FUSE_BANK_SIZE 0x80
#ifdef CONFIG_MX6SL
#define FUSE_BANKS 8
-#elif defined(CONFIG_MX6ULL)
+#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
#define FUSE_BANKS 9
#else
#define FUSE_BANKS 16
@@ -79,7 +79,7 @@
/*
* There is a hole in shadow registers address map of size 0x100
* between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX,
- * iMX6UL and i.MX6ULL.
+ * iMX6UL, i.MX6ULL and i.MX6SLL.
* Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
* we should account for this hole in address space.
*
@@ -100,8 +100,8 @@ u32 fuse_bank_physical(int index)
if (is_mx6sl()) {
phy_index = index;
- } else if (is_mx6ul() || is_mx6ull()) {
- if (is_mx6ull() && index == 8)
+ } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
+ if ((is_mx6ull() || is_mx6sll()) && index == 8)
index = 7;
if (index >= 6)
@@ -121,7 +121,7 @@ u32 fuse_bank_physical(int index)
u32 fuse_word_physical(u32 bank, u32 word_index)
{
- if (is_mx6ull()) {
+ if (is_mx6ull() || is_mx6sll()) {
if (bank == 8)
word_index = word_index + 4;
}
@@ -164,10 +164,10 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
return -EINVAL;
}
- if (is_mx6ull()) {
+ if (is_mx6ull() || is_mx6sll()) {
if ((bank == 7 || bank == 8) &&
word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) {
- printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", caller);
+ printf("mxc_ocotp %s(): Invalid argument\n", caller);
return -EINVAL;
}
}
@@ -271,7 +271,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
#else
u32 addr;
/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
- if ((is_mx6ull()) && (bank > 7)) {
+ if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) {
bank = bank - 1;
word += 4;
}
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (13 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL Peng Fan
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Update lcdif regs for i.MX6SL/SLL
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/imx-common/regs-lcdif.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h
index 5a4f61f..ab147b5 100644
--- a/arch/arm/include/asm/imx-common/regs-lcdif.h
+++ b/arch/arm/include/asm/imx-common/regs-lcdif.h
@@ -20,7 +20,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
#endif
mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
@@ -56,7 +56,7 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
- defined(CONFIG_MX7)
+ defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
#endif
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
@@ -64,7 +64,8 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7)
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
mxs_reg_32(hw_lcdif_thres)
mxs_reg_32(hw_lcdif_as_ctrl)
mxs_reg_32(hw_lcdif_as_buf)
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (14 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-27 17:02 ` Simon Glass
2016-11-24 6:47 ` [U-Boot] [PATCH 17/19] arm: dts: add i.MX6SLL device tree Peng Fan
` (2 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
is for IOMUXC_SNVS.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
---
drivers/pinctrl/nxp/pinctrl-imx6.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c
index 32b4754..4488b16 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -28,6 +28,8 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sll-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sll-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
{ .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info },
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 17/19] arm: dts: add i.MX6SLL device tree
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (15 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL Peng Fan
@ 2016-11-24 6:47 ` Peng Fan
2016-11-24 6:48 ` [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support Peng Fan
2016-11-24 6:48 ` [U-Boot] [PATCH 19/19] imx: mx6sllevk: add plugin support Peng Fan
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:47 UTC (permalink / raw)
To: u-boot
Add i.MX6SLL device tree.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/dts/imx6sll-pinfunc.h | 882 ++++++++++++++++++++++++++++++
arch/arm/dts/imx6sll.dtsi | 859 +++++++++++++++++++++++++++++
include/dt-bindings/clock/imx6sll-clock.h | 204 +++++++
3 files changed, 1945 insertions(+)
create mode 100644 arch/arm/dts/imx6sll-pinfunc.h
create mode 100644 arch/arm/dts/imx6sll.dtsi
create mode 100644 include/dt-bindings/clock/imx6sll-clock.h
diff --git a/arch/arm/dts/imx6sll-pinfunc.h b/arch/arm/dts/imx6sll-pinfunc.h
new file mode 100644
index 0000000..5a3700b
--- /dev/null
+++ b/arch/arm/dts/imx6sll-pinfunc.h
@@ -0,0 +1,882 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SLL_PINFUNC_H
+#define __DTS_IMX6SLL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
+#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0
+#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0
+#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0
+#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0
+#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0
+#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
+#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
+#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0
+#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1
+#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0
+#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0
+#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1
+#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1
+#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0
+#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1
+#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0
+#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1
+#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1
+#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2
+#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1
+#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1
+#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1
+#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2
+#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1
+#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1
+#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0
+#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3
+#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1
+#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1
+#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3
+#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3
+#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1
+#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0
+#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2
+#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5
+#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3
+#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4
+#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3
+#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2
+#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2
+#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1
+#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1
+#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1
+#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2
+#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3
+#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2
+#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1
+#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1
+#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0
+#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1
+#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1
+#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1
+#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0
+#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1
+#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1
+#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0
+#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1
+#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4
+#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6
+#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1
+#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5
+#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7
+#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0
+#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0
+#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0
+#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1
+#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0
+#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0
+#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3
+#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2
+#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2
+#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3
+#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1
+#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3
+#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2
+#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0
+#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3
+#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2
+#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3
+#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2
+#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2
+#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6
+#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7
+#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4
+#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3
+#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5
+#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1
+#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1
+#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1
+#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1
+#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1
+#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1
+#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0
+#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0
+#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0
+#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0
+#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0
+#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1
+#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1
+#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0
+#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2
+#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0
+
+#endif /* __DTS_IMX6SLL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
new file mode 100644
index 0000000..349c47a
--- /dev/null
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -0,0 +1,859 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/imx6sll-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx6sll-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi3 = &ecspi3;
+ spi4 = &ecspi4;
+ usbphy0 = &usbphy1;
+ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 996000 1225000
+ 792000 1175000
+ 396000 1075000
+ 198000 975000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 996000 1225000
+ 792000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ fsl,low-power-run;
+ clocks = <&clks IMX6SLL_CLK_ARM>,
+ <&clks IMX6SLL_CLK_PLL2_PFD2>,
+ <&clks IMX6SLL_CLK_STEP>,
+ <&clks IMX6SLL_CLK_PLL1_SW>,
+ <&clks IMX6SLL_CLK_PLL1_SYS>,
+ <&clks IMX6SLL_CLK_PLL1>,
+ <&clks IMX6SLL_PLL1_BYPASS>,
+ <&clks IMX6SLL_PLL1_BYPASS_SRC>;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+ "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
+ "pll1_bypass_src";
+ };
+ };
+
+ intc: interrupt-controller at 00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock at 1 {
+ compatible = "fixed-clock";
+ reg = <1>;
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ ipp_di0: clock at 2 {
+ compatible = "fixed-clock";
+ reg = <2>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di0";
+ };
+
+ ipp_di1: clock at 3 {
+ compatible = "fixed-clock";
+ reg = <3>;
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "ipp_di1";
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gpc>;
+ ranges;
+
+ busfreq {
+ compatible = "fsl,imx_busfreq";
+ clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
+ <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
+ <&clks IMX6SLL_CLK_PLL3_USB_OTG>, <&clks IMX6SLL_CLK_PERIPH>,
+ <&clks IMX6SLL_CLK_PERIPH_PRE>, <&clks IMX6SLL_CLK_PERIPH_CLK2>,
+ <&clks IMX6SLL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SLL_CLK_OSC>,
+ <&clks IMX6SLL_CLK_AHB>, <&clks IMX6SLL_CLK_AXI_PODF>,
+ <&clks IMX6SLL_CLK_PERIPH2>, <&clks IMX6SLL_CLK_PERIPH2_PRE>,
+ <&clks IMX6SLL_CLK_PERIPH2_CLK2>, <&clks IMX6SLL_CLK_PERIPH2_CLK2_SEL>,
+ <&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_MMDC_P0_FAST>, <&clks IMX6SLL_PLL1_BYPASS_SRC>,
+ <&clks IMX6SLL_PLL1_BYPASS>, <&clks IMX6SLL_CLK_PLL1_SYS>, <&clks IMX6SLL_CLK_PLL1_SW>,
+ <&clks IMX6SLL_CLK_PLL1>;
+ clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
+ "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
+ "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
+ "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1";
+ fsl,max_ddr_freq = <400000000>;
+ };
+
+ ocrams: sram at 00900000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x00900000 0x4000>;
+ };
+
+ ocrams_ddr: sram at 00904000 {
+ compatible = "fsl,ddr-lpm-sram";
+ reg = <0x00904000 0x1000>;
+ };
+
+ ocram: sram at 00905000 {
+ compatible = "mmio-sram";
+ reg = <0x00905000 0x1B000>;
+ };
+
+ L2: l2-cache at 00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ };
+
+ aips1: aips-bus at 02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba: spba-bus at 02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ spdif: spdif at 02004000 {
+ compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
+ <&clks IMX6SLL_CLK_OSC>,
+ <&clks IMX6SLL_CLK_SPDIF>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_IPG>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "dma";
+ status = "disabled";
+ };
+
+ ecspi1: ecspi at 02008000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI1>,
+ <&clks IMX6SLL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi at 0200c000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI2>,
+ <&clks IMX6SLL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi at 02010000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI3>,
+ <&clks IMX6SLL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi at 02014000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_ECSPI4>,
+ <&clks IMX6SLL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart4: serial at 02018000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02018000 0x4000>;
+ interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
+ <&clks IMX6SLL_CLK_UART4_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial at 02020000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
+ <&clks IMX6SLL_CLK_UART1_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial at 02024000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02024000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
+ <&clks IMX6SLL_CLK_UART2_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ssi1: ssi at 02028000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
+ <&clks IMX6SLL_CLK_SSI1>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ ssi2: ssi2 at 0202c000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
+ <&clks IMX6SLL_CLK_SSI2>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ ssi3: ssi at 02030000 {
+ compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
+ <&clks IMX6SLL_CLK_SSI3>;
+ clock-names = "ipg", "baud";
+ status = "disabled";
+ };
+
+ uart3: serial at 02034000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02034000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-name = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
+ <&clks IMX6SLL_CLK_UART3_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+
+ pwm1: pwm at 02080000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM1>,
+ <&clks IMX6SLL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm2: pwm at 02084000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM2>,
+ <&clks IMX6SLL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm3: pwm at 02088000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM3>,
+ <&clks IMX6SLL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ pwm4: pwm at 0208c000 {
+ compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PWM4>,
+ <&clks IMX6SLL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ };
+
+ gpt1: gpt at 02098000 {
+ compatible = "fsl,imx6sll-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
+ <&clks IMX6SLL_CLK_GPT_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio at 0209c000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 020a0000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 020a4000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 020a8000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 020ac000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio at 020b0000 {
+ compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ kpp: kpp at 020b8000 {
+ compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_KPP>;
+ status = "disabled";
+ };
+
+ wdog1: wdog at 020bc000 {
+ compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_WDOG1>;
+ };
+
+ wdog2: wdog at 020c0000 {
+ compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_WDOG2>;
+ status = "disabled";
+ };
+
+ clks: ccm at 020c4000 {
+ compatible = "fsl,imx6sll-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
+ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+ };
+
+ anatop: anatop at 020c8000 {
+ compatible = "fsl,imx6sll-anatop",
+ "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x4000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_3p0: regulator-3p0 at 120 {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd3p0";
+ regulator-min-microvolt = <2625000>;
+ regulator-max-microvolt = <3400000>;
+ anatop-reg-offset = <0x120>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <0>;
+ anatop-min-voltage = <2625000>;
+ anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+ status = "disabled";
+ };
+
+ usbphy1: usbphy at 020c9000 {
+ compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
+ "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBPHY1>;
+ phy-3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy at 020ca000 {
+ compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
+ "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBPHY2>;
+ phy-reg_3p0-supply = <®_3p0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ snvs: snvs at 020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x61>;
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup;
+ };
+ };
+
+ epit1: epit at 020d0000 {
+ reg = <0x020d0000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit at 020d4000 {
+ reg = <0x020d4000 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src at 020d8000 {
+ compatible = "fsl,imx6sll-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc at 020dc000 {
+ compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
+ };
+
+ iomuxc: iomuxc at 020e0000 {
+ compatible = "fsl,imx6sll-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr at 020e4000 {
+ compatible = "fsl,imx6sll-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ csi: csi at 020e8000 {
+ compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
+ reg = <0x020e8000 0x4000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_CSI>,
+ <&clks IMX6SLL_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+ status = "disabled";
+ };
+
+ sdma: sdma at 020ec000 {
+ compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_SDMA>,
+ <&clks IMX6SLL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ iram = <&ocram>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pxp: pxp at 020f0000 {
+ compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>,
+ <&clks IMX6SLL_CLK_PXP>;
+ clock-names = "pxp_ipg", "pxp_axi";
+ status = "disabled";
+ };
+
+ epdc: epdc at 020f4000 {
+ compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_EPDC_AXI>, <&clks IMX6SLL_CLK_EPDC_PIX>;
+ clock-names = "epdc_axi", "epdc_pix";
+ status = "disabled";
+ };
+
+ lcdif: lcdif at 020f8000 {
+ compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
+ reg = <0x020f8000 0x4000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
+ <&clks IMX6SLL_CLK_LCDIF_APB>,
+ <&clks IMX6SLL_CLK_DUMMY>;
+ clock-names = "pix", "axi", "disp_axi";
+ status = "disabled";
+ };
+
+ dcp: dcp at 020fc000 {
+ compatible = "fsl,imx6sl-dcp";
+ reg = <0x020fc000 0x4000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DCP>;
+ clock-names = "dcp";
+ };
+ };
+
+ aips2: aips-bus at 02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ usbotg1: usb at 02184000 {
+ compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
+ "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,anatop = <&anatop>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbotg2: usb at 02184200 {
+ compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
+ "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc at 02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
+ "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ };
+
+ usdhc1: usdhc at 02190000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02190000 0x4000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC1>,
+ <&clks IMX6SLL_CLK_USDHC1>,
+ <&clks IMX6SLL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc at 02194000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02194000 0x4000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC2>,
+ <&clks IMX6SLL_CLK_USDHC2>,
+ <&clks IMX6SLL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc at 02198000 {
+ compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_USDHC3>,
+ <&clks IMX6SLL_CLK_USDHC3>,
+ <&clks IMX6SLL_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-step = <2>;
+ fsl,tuning-start-tap = <20>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp at 021ac000 {
+ compatible = "fsl,imx6sll-romcp", "syscon";
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc: mmdc at 021b0000 {
+ compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ rngb: rngb at 021b4000 {
+ compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>;
+ };
+
+ ocotp: ocotp-ctrl at 021bc000 {
+ compatible = "fsl,imx6sll-ocotp", "syscon";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6SLL_CLK_OCOTP>;
+ };
+
+ csu: csu at 021c0000 {
+ compatible = "fsl,imx6sll-csu";
+ reg = <0x021c0000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ snvs_gpr: snvs-gpr at 0x021c4000 {
+ compatible = "fsl, imx6sll-snvs-gpr";
+ reg = <0x021c4000 0x10000>;
+ };
+
+ iomuxc_snvs: iomuxc-snvs at 021c8000 {
+ compatible = "fsl,imx6sll-iomuxc-snvs";
+ reg = <0x021c80000 0x10000>;
+ };
+
+ audmux: audmux at 021d8000 {
+ compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
+
+ uart5: serial at 021f4000 {
+ compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+ interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+ clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
+ <&clks IMX6SLL_CLK_UART5_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 0000000..39c2567
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY 0
+#define IMX6SLL_CLK_CKIL 1
+#define IMX6SLL_CLK_OSC 2
+#define IMX6SLL_PLL1_BYPASS_SRC 3
+#define IMX6SLL_PLL2_BYPASS_SRC 4
+#define IMX6SLL_PLL3_BYPASS_SRC 5
+#define IMX6SLL_PLL4_BYPASS_SRC 6
+#define IMX6SLL_PLL5_BYPASS_SRC 7
+#define IMX6SLL_PLL6_BYPASS_SRC 8
+#define IMX6SLL_PLL7_BYPASS_SRC 9
+#define IMX6SLL_CLK_PLL1 10
+#define IMX6SLL_CLK_PLL2 11
+#define IMX6SLL_CLK_PLL3 12
+#define IMX6SLL_CLK_PLL4 13
+#define IMX6SLL_CLK_PLL5 14
+#define IMX6SLL_CLK_PLL6 15
+#define IMX6SLL_CLK_PLL7 16
+#define IMX6SLL_PLL1_BYPASS 17
+#define IMX6SLL_PLL2_BYPASS 18
+#define IMX6SLL_PLL3_BYPASS 19
+#define IMX6SLL_PLL4_BYPASS 20
+#define IMX6SLL_PLL5_BYPASS 21
+#define IMX6SLL_PLL6_BYPASS 22
+#define IMX6SLL_PLL7_BYPASS 23
+#define IMX6SLL_CLK_PLL1_SYS 24
+#define IMX6SLL_CLK_PLL2_BUS 25
+#define IMX6SLL_CLK_PLL3_USB_OTG 26
+#define IMX6SLL_CLK_PLL4_AUDIO 27
+#define IMX6SLL_CLK_PLL5_VIDEO 28
+#define IMX6SLL_CLK_PLL6_ENET 29
+#define IMX6SLL_CLK_PLL7_USB_HOST 30
+#define IMX6SLL_CLK_USBPHY1 31
+#define IMX6SLL_CLK_USBPHY2 32
+#define IMX6SLL_CLK_USBPHY1_GATE 33
+#define IMX6SLL_CLK_USBPHY2_GATE 34
+#define IMX6SLL_CLK_PLL2_PFD0 35
+#define IMX6SLL_CLK_PLL2_PFD1 36
+#define IMX6SLL_CLK_PLL2_PFD2 37
+#define IMX6SLL_CLK_PLL2_PFD3 38
+#define IMX6SLL_CLK_PLL3_PFD0 39
+#define IMX6SLL_CLK_PLL3_PFD1 40
+#define IMX6SLL_CLK_PLL3_PFD2 41
+#define IMX6SLL_CLK_PLL3_PFD3 42
+#define IMX6SLL_CLK_PLL4_POST_DIV 43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44
+#define IMX6SLL_CLK_PLL5_POST_DIV 45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46
+#define IMX6SLL_CLK_PLL2_198M 47
+#define IMX6SLL_CLK_PLL3_120M 48
+#define IMX6SLL_CLK_PLL3_80M 49
+#define IMX6SLL_CLK_PLL3_60M 50
+#define IMX6SLL_CLK_STEP 51
+#define IMX6SLL_CLK_PLL1_SW 52
+#define IMX6SLL_CLK_AXI_ALT_SEL 53
+#define IMX6SLL_CLK_AXI_SEL 54
+#define IMX6SLL_CLK_PERIPH_PRE 55
+#define IMX6SLL_CLK_PERIPH2_PRE 56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58
+#define IMX6SLL_CLK_PERCLK_SEL 59
+#define IMX6SLL_CLK_USDHC1_SEL 60
+#define IMX6SLL_CLK_USDHC2_SEL 61
+#define IMX6SLL_CLK_USDHC3_SEL 62
+#define IMX6SLL_CLK_SSI1_SEL 63
+#define IMX6SLL_CLK_SSI2_SEL 64
+#define IMX6SLL_CLK_SSI3_SEL 65
+#define IMX6SLL_CLK_PXP_SEL 66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL 67
+#define IMX6SLL_CLK_LCDIF_SEL 68
+#define IMX6SLL_CLK_EPDC_PRE_SEL 69
+#define IMX6SLL_CLK_SPDIF_SEL 70
+#define IMX6SLL_CLK_ECSPI_SEL 71
+#define IMX6SLL_CLK_UART_SEL 72
+#define IMX6SLL_CLK_ARM 73
+#define IMX6SLL_CLK_PERIPH 74
+#define IMX6SLL_CLK_PERIPH2 75
+#define IMX6SLL_CLK_PERIPH2_CLK2 76
+#define IMX6SLL_CLK_PERIPH_CLK2 77
+#define IMX6SLL_CLK_MMDC_PODF 78
+#define IMX6SLL_CLK_AXI_PODF 79
+#define IMX6SLL_CLK_AHB 80
+#define IMX6SLL_CLK_IPG 81
+#define IMX6SLL_CLK_PERCLK 82
+#define IMX6SLL_CLK_USDHC1_PODF 83
+#define IMX6SLL_CLK_USDHC2_PODF 84
+#define IMX6SLL_CLK_USDHC3_PODF 85
+#define IMX6SLL_CLK_SSI1_PRED 86
+#define IMX6SLL_CLK_SSI2_PRED 87
+#define IMX6SLL_CLK_SSI3_PRED 88
+#define IMX6SLL_CLK_SSI1_PODF 89
+#define IMX6SLL_CLK_SSI2_PODF 90
+#define IMX6SLL_CLK_SSI3_PODF 91
+#define IMX6SLL_CLK_PXP_PODF 92
+#define IMX6SLL_CLK_LCDIF_PRED 93
+#define IMX6SLL_CLK_LCDIF_PODF 94
+#define IMX6SLL_CLK_EPDC_SEL 95
+#define IMX6SLL_CLK_EPDC_PODF 96
+#define IMX6SLL_CLK_SPDIF_PRED 97
+#define IMX6SLL_CLK_SPDIF_PODF 98
+#define IMX6SLL_CLK_ECSPI_PODF 99
+#define IMX6SLL_CLK_UART_PODF 100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1 101
+#define IMX6SLL_CLK_AIPSTZ2 102
+#define IMX6SLL_CLK_DCP 103
+#define IMX6SLL_CLK_UART2_IPG 104
+#define IMX6SLL_CLK_UART2_SERIAL 105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1 106
+#define IMX6SLL_CLK_ECSPI2 107
+#define IMX6SLL_CLK_ECSPI3 108
+#define IMX6SLL_CLK_ECSPI4 109
+#define IMX6SLL_CLK_UART3_IPG 110
+#define IMX6SLL_CLK_UART3_SERIAL 111
+#define IMX6SLL_CLK_UART4_IPG 112
+#define IMX6SLL_CLK_UART4_SERIAL 113
+#define IMX6SLL_CLK_EPIT1 114
+#define IMX6SLL_CLK_EPIT2 115
+#define IMX6SLL_CLK_GPT_BUS 116
+#define IMX6SLL_CLK_GPT_SERIAL 117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI 118
+#define IMX6SLL_CLK_I2C1 119
+#define IMX6SLL_CLK_I2C2 120
+#define IMX6SLL_CLK_I2C3 121
+#define IMX6SLL_CLK_OCOTP 122
+#define IMX6SLL_CLK_LCDIF_APB 123
+#define IMX6SLL_CLK_PXP 124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG 125
+#define IMX6SLL_CLK_UART5_SERIAL 126
+#define IMX6SLL_CLK_EPDC_AXI 127
+#define IMX6SLL_CLK_EPDC_PIX 128
+#define IMX6SLL_CLK_LCDIF_PIX 129
+#define IMX6SLL_CLK_WDOG1 130
+#define IMX6SLL_CLK_MMDC_P0_FAST 131
+#define IMX6SLL_CLK_MMDC_P0_IPG 132
+#define IMX6SLL_CLK_OCRAM 133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1 134
+#define IMX6SLL_CLK_PWM2 135
+#define IMX6SLL_CLK_PWM3 136
+#define IMX6SLL_CLK_PWM4 137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM 138
+#define IMX6SLL_CLK_SDMA 139
+#define IMX6SLL_CLK_KPP 140
+#define IMX6SLL_CLK_WDOG2 141
+#define IMX6SLL_CLK_SPBA 142
+#define IMX6SLL_CLK_SPDIF 143
+#define IMX6SLL_CLK_SPDIF_GCLK 144
+#define IMX6SLL_CLK_SSI1 145
+#define IMX6SLL_CLK_SSI1_IPG 146
+#define IMX6SLL_CLK_SSI2 147
+#define IMX6SLL_CLK_SSI2_IPG 148
+#define IMX6SLL_CLK_SSI3 149
+#define IMX6SLL_CLK_SSI3_IPG 150
+#define IMX6SLL_CLK_UART1_IPG 151
+#define IMX6SLL_CLK_UART1_SERIAL 152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3 153
+#define IMX6SLL_CLK_USDHC1 154
+#define IMX6SLL_CLK_USDHC2 155
+#define IMX6SLL_CLK_USDHC3 156
+
+#define IMX6SLL_CLK_IPP_DI0 157
+#define IMX6SLL_CLK_IPP_DI1 158
+#define IMX6SLL_CLK_LDB_DI0_SEL 159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7 161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162
+#define IMX6SLL_CLK_LDB_DI0 163
+#define IMX6SLL_CLK_LDB_DI1_SEL 164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7 166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167
+#define IMX6SLL_CLK_LDB_DI1 168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
+#define IMX6SLL_CLK_EXTERN_AUDIO 172
+
+#define IMX6SLL_CLK_END 173
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (16 preceding siblings ...)
2016-11-24 6:47 ` [U-Boot] [PATCH 17/19] arm: dts: add i.MX6SLL device tree Peng Fan
@ 2016-11-24 6:48 ` Peng Fan
2016-11-24 22:42 ` Fabio Estevam
2016-11-24 6:48 ` [U-Boot] [PATCH 19/19] imx: mx6sllevk: add plugin support Peng Fan
18 siblings, 1 reply; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:48 UTC (permalink / raw)
To: u-boot
Add i.MX6SLL EVK board support.
1. Add imx6sll-evk device tree.
2. Enable SDHC/I2C/UART.
3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver.
Boot Log:
U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800)
CPU: Freescale i.MX6SLL rev1.0 at 792MHz
CPU: Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM: 2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/armv7/mx6/Kconfig | 7 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6sll-evk.dts | 801 +++++++++++++++++++++++++++++++++
board/freescale/mx6sllevk/Kconfig | 12 +
board/freescale/mx6sllevk/Makefile | 6 +
board/freescale/mx6sllevk/imximage.cfg | 121 +++++
board/freescale/mx6sllevk/mx6sllevk.c | 131 ++++++
configs/mx6sllevk_defconfig | 36 ++
include/configs/mx6sllevk.h | 152 +++++++
9 files changed, 1267 insertions(+)
create mode 100644 arch/arm/dts/imx6sll-evk.dts
create mode 100644 board/freescale/mx6sllevk/Kconfig
create mode 100644 board/freescale/mx6sllevk/Makefile
create mode 100644 board/freescale/mx6sllevk/imximage.cfg
create mode 100644 board/freescale/mx6sllevk/mx6sllevk.c
create mode 100644 configs/mx6sllevk_defconfig
create mode 100644 include/configs/mx6sllevk.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 72bc083..c5674c5 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -124,6 +124,12 @@ config TARGET_MX6SLEVK
bool "mx6slevk"
select SUPPORT_SPL
+config TARGET_MX6SLLEVK
+ bool "mx6sll evk"
+ select MX6SLL
+ select DM
+ select DM_THERMAL
+
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
select MX6SX
@@ -244,6 +250,7 @@ source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sllevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c5b2f2..4b4356b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -285,6 +285,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
bk4r1.dtb
dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+ imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6q-icore.dtb
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
new file mode 100644
index 0000000..b4af007
--- /dev/null
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -0,0 +1,801 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+ model = "Freescale i.MX6SLL EVK Board";
+ compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
+
+ memory {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ battery: max8903 at 0 {
+ compatible = "fsl,max8903-charger";
+ pinctrl-names = "default";
+ dok_input = <&gpio4 13 1>;
+ uok_input = <&gpio4 13 1>;
+ chg_input = <&gpio4 15 1>;
+ flt_input = <&gpio4 14 1>;
+ fsl,dcm_always_high;
+ fsl,dc_valid;
+ fsl,adc_disable;
+ status = "okay";
+ };
+
+ pxp_v4l2_out {
+ compatible = "fsl,imx6sl-pxp-v4l2";
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator at 1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_aud3v: regulator at 2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "wm8962-supply-3v15";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-boot-on;
+ };
+
+ reg_aud4v: regulator at 3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "wm8962-supply-4v2";
+ regulator-min-microvolt = <4325000>;
+ regulator-max-microvolt = <4325000>;
+ regulator-boot-on;
+ };
+
+ reg_lcd: regulator at 4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "lcd-pwr";
+ gpio = <&gpio4 8 0>;
+ enable-active-high;
+ };
+
+ reg_sd1_vmmc: sd1_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_sd2_vmmc: sd2_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "eMMC-VCCQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ reg_sd3_vmmc: sd3_vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD3_WIFI";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+
+ sound {
+ compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ cpu-dai = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ codec-master;
+ hp-det-gpios = <&gpio4 24 1>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux3>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+ soc-supply = <&sw1c_reg>;
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pfuze100 at 08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ max17135: max17135 at 48 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max17135>;
+ compatible = "maxim,max17135";
+ reg = <0x48>;
+ status = "okay";
+
+ vneg_pwrup = <1>;
+ gvee_pwrup = <2>;
+ vpos_pwrup = <10>;
+ gvdd_pwrup = <12>;
+ gvdd_pwrdn = <1>;
+ vpos_pwrdn = <2>;
+ gvee_pwrdn = <8>;
+ vneg_pwrdn = <10>;
+ gpio_pmic_pwrgood = <&gpio2 13 0>;
+ gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+ gpio_pmic_wakeup = <&gpio2 14 0>;
+ gpio_pmic_v3p3 = <&gpio2 7 0>;
+ gpio_pmic_intr = <&gpio2 12 0>;
+
+ regulators {
+ DISPLAY_reg: DISPLAY {
+ regulator-name = "DISPLAY";
+ };
+
+ GVDD_reg: GVDD {
+ /* 20v */
+ regulator-name = "GVDD";
+ };
+
+ GVEE_reg: GVEE {
+ /* -22v */
+ regulator-name = "GVEE";
+ };
+
+ HVINN_reg: HVINN {
+ /* -22v */
+ regulator-name = "HVINN";
+ };
+
+ HVINP_reg: HVINP {
+ /* 20v */
+ regulator-name = "HVINP";
+ };
+
+ VCOM_reg: VCOM {
+ regulator-name = "VCOM";
+ /* 2's-compliment, -4325000 */
+ regulator-min-microvolt = <0xffbe0178>;
+ /* 2's-compliment, -500000 */
+ regulator-max-microvolt = <0xfff85ee0>;
+ };
+
+ VNEG_reg: VNEG {
+ /* -15v */
+ regulator-name = "VNEG";
+ };
+
+ VPOS_reg: VPOS {
+ /* 15v */
+ regulator-name = "VPOS";
+ };
+
+ V3P3_reg: V3P3 {
+ regulator-name = "V3P3";
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ codec: wm8962 at 1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
+ DCVDD-supply = <&vgen3_reg>;
+ DBVDD-supply = <®_aud3v>;
+ AVDD-supply = <&vgen3_reg>;
+ CPVDD-supply = <&vgen3_reg>;
+ MICVDD-supply = <®_aud3v>;
+ PLLVDD-supply = <&vgen3_reg>;
+ SPKVDD1-supply = <®_aud4v>;
+ SPKVDD2-supply = <®_aud4v>;
+ amic-mono;
+ };
+};
+
+&gpc {
+ fsl,ldo-bypass = <1>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6sll-evk {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
+ MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
+ /*
+ * Must set the LVE of pad SD2_RESET, otherwise current
+ * leakage through eMMC chip will pull high the VCCQ to
+ * 2.6v, which will impact SD1 and SD3 SD3.0 voltage switch.
+ */
+ MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
+ MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+ MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
+ MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+ MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+ /* CHG_FLT, CHG_UOK/DOK, CHG_STATUS */
+ MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
+ MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
+ MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
+ >;
+ };
+
+ pinctrl_audmux3: audmux3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
+ MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
+ MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
+ MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
+ MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088
+ MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088
+ MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088
+ MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088
+ MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088
+ MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088
+ MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088
+ MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088
+ MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088
+ MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088
+ MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088
+ MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088
+ MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
+ MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
+ >;
+ };
+
+ pinctrl_epdc0: epdcgrp0 {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1
+ MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1
+ MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1
+ MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1
+ MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1
+ MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1
+ MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1
+ MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1
+ MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1
+ MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1
+ MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1
+ MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1
+ MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1
+ MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1
+ MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1
+ MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1
+ MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1
+ MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1
+ MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1
+ MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1
+ MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1
+ MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1
+ MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1
+ MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1
+ MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1
+ >;
+ };
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
+ MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79
+ MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79
+ MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79
+ MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79
+ MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79
+ MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79
+ MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79
+ MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79
+ MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79
+ MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79
+ MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+ MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79
+ MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79
+ MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79
+ MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79
+ >;
+ };
+
+ pinctrl_max17135: max17135grp-1 {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */
+ MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */
+ MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */
+ MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */
+ MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x1b0b1 /* bt reg on */
+ MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x1b0b1
+ MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5dte: uart5dtegrp {
+ fsl,pins = <
+ MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x1b0b1
+ MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x1b0b1
+ MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
+ MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9
+ MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9
+ MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9
+ MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
+ MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9
+ MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9
+ MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9
+ MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9
+ MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
+ MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
+ >;
+ };
+
+ pinctrl_pwm1: pmw1grp {
+ fsl,pins = <
+ MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0
+ >;
+ };
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ lcd-supply = <®_lcd>;
+ display = <&display>;
+ status = "okay";
+
+ display: display {
+ bits-per-pixel = <16>;
+ bus-width = <24>;
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ clock-frequency = <33500000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <89>;
+ hfront-porch = <164>;
+ vback-porch = <23>;
+ vfront-porch = <10>;
+ hsync-len = <10>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pxp {
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ fsl,uart-has-rtscts;
+ /* for DTE mode, add below change */
+ /* fsl,dte-mode; */
+ /* pinctrl-0 = <&pinctrl_uart5dte>; */
+ status = "disabled";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_sd1_vmmc>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vqmmc-supply = <®_sd2_vmmc>;
+ bus-width = <8>;
+ no-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_sd3_vmmc>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&epdc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_epdc0>;
+ V3P3-supply = <&V3P3_reg>;
+ VCOM-supply = <&VCOM_reg>;
+ DISPLAY-supply = <&DISPLAY_reg>;
+ status = "okay";
+};
+
+&ssi2 {
+ status = "okay";
+};
diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig
new file mode 100644
index 0000000..4ba9bbf
--- /dev/null
+++ b/board/freescale/mx6sllevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLLEVK
+
+config SYS_BOARD
+ default "mx6sllevk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mx6sllevk"
+
+endif
diff --git a/board/freescale/mx6sllevk/Makefile b/board/freescale/mx6sllevk/Makefile
new file mode 100644
index 0000000..667fcb0
--- /dev/null
+++ b/board/freescale/mx6sllevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sllevk.o
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
new file mode 100644
index 0000000..53fb74f
--- /dev/null
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3F393B3C
+DATA 4 0x021B0850 0x262C3826
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
new file mode 100644
index 0000000..7630957
--- /dev/null
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ u32 dev_id, rev_id, i;
+ u32 switch_num = 6;
+ u32 offset = PFUZE100_SW1CMODE;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV)
+ return 0;
+
+ if (ret != 0)
+ return ret;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+ /* Init mode to APS_PFM */
+ pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+ for (i = 0; i < switch_num - 1; i++)
+ pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+ /* set SW1AB staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+ /* set SW1C staby volatage 0.975V */
+ pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+ pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SLL EVK\n");
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+ return devno;
+}
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
new file mode 100644
index 0000000..8ae049e
--- /dev/null
+++ b/configs/mx6sllevk_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
new file mode 100644
index 0000000..b9f25cf
--- /dev/null
+++ b/include/configs/mx6sllevk.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* I2C Configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "epdc_waveform=epdc_splash.bin\0" \
+ "script=boot.scr\0" \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_file=imx6sll-evk.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=1\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "usb start; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_STACKSIZE SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE SZ_8K
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
+#define CONFIG_ENV_IS_IN_MMC
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#endif /* __CONFIG_H */
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 19/19] imx: mx6sllevk: add plugin support
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
` (17 preceding siblings ...)
2016-11-24 6:48 ` [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support Peng Fan
@ 2016-11-24 6:48 ` Peng Fan
18 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-24 6:48 UTC (permalink / raw)
To: u-boot
Add plugin support for mx6sllevk board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
board/freescale/mx6sllevk/imximage.cfg | 6 ++
board/freescale/mx6sllevk/plugin.S | 155 +++++++++++++++++++++++++++++++++
configs/mx6sllevk_plugin_defconfig | 37 ++++++++
3 files changed, 198 insertions(+)
create mode 100644 board/freescale/mx6sllevk/plugin.S
create mode 100644 configs/mx6sllevk_plugin_defconfig
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
index 53fb74f..7d8b323 100644
--- a/board/freescale/mx6sllevk/imximage.cfg
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -23,6 +23,11 @@ IMAGE_VERSION 2
BOOT_FROM sd
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
@@ -119,3 +124,4 @@ DATA 4 0x021B0800 0xA1390003
DATA 4 0x021B0004 0x00020052
DATA 4 0x021B0404 0x00011006
DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sllevk/plugin.S b/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 0000000..f9ef35a
--- /dev/null
+++ b/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x00080000
+ str r1, [r0, #0x550]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x534]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x2AC]
+ str r1, [r0, #0x548]
+ str r1, [r0, #0x52C]
+ ldr r1, =0x00020000
+ str r1, [r0, #0x530]
+ ldr r1, =0x00003030
+ str r1, [r0, #0x2B0]
+ str r1, [r0, #0x2B4]
+ str r1, [r0, #0x2B8]
+ str r1, [r0, #0x2BC]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x540]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x544]
+ str r1, [r0, #0x54C]
+ str r1, [r0, #0x554]
+ str r1, [r0, #0x558]
+ str r1, [r0, #0x294]
+ str r1, [r0, #0x298]
+ str r1, [r0, #0x29C]
+ str r1, [r0, #0x2A0]
+
+ ldr r1, =0x00082030
+ str r1, [r0, #0x2C0]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r1, =0x00008000
+ str r1, [r0, #0x1C]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x084700C7
+ str r1, [r0, #0x85C]
+ ldr r1, =0x00400000
+ str r1, [r0, #0x890]
+
+ ldr r1, =0x3F393B3C
+ str r1, [r0, #0x848]
+ ldr r1, =0x262C3826
+ str r1, [r0, #0x850]
+
+ ldr r1, =0x33333333
+ str r1, [r0, #0x81C]
+ str r1, [r0, #0x820]
+ str r1, [r0, #0x824]
+ str r1, [r0, #0x828]
+
+ ldr r1, =0xf3333333
+ str r1, [r0, #0x82C]
+ str r1, [r0, #0x830]
+ str r1, [r0, #0x834]
+ str r1, [r0, #0x838]
+
+ ldr r1, =0x24922492
+ str r1, [r0, #0x8C0]
+ ldr r1, =0x00000800
+ str r1, [r0, #0x8B8]
+
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x53574333
+ str r1, [r0, #0x00C]
+ ldr r1, =0x00100B22
+ str r1, [r0, #0x010]
+ ldr r1, =0x00170778
+ str r1, [r0, #0x038]
+ ldr r1, =0x00C700DB
+ str r1, [r0, #0x014]
+ ldr r1, =0x00201718
+ str r1, [r0, #0x018]
+ ldr r1, =0x0F9F26D2
+ str r1, [r0, #0x02C]
+ ldr r1, =0x009F0E10
+ str r1, [r0, #0x030]
+ ldr r1, =0x0000005F
+ str r1, [r0, #0x040]
+ ldr r1, =0xC4190000
+ str r1, [r0, #0x000]
+ ldr r1, =0x20000000
+ str r1, [r0, #0x83C]
+
+ ldr r1, =0x00008050
+ str r1, [r0, #0x01C]
+ ldr r1, =0x00008058
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x003F8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8030
+ str r1, [r0, #0x01C]
+ ldr r1, =0xFF0A8038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x04028038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x83018038
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038030
+ str r1, [r0, #0x01C]
+ ldr r1, =0x01038038
+ str r1, [r0, #0x01C]
+
+ ldr r1, =0x00001800
+ str r1, [r0, #0x020]
+ ldr r1, =0xA1390003
+ str r1, [r0, #0x800]
+ ldr r1, =0x00020052
+ str r1, [r0, #0x004]
+ ldr r1, =0x00011006
+ str r1, [r0, #0x404]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x068]
+ str r1, [r0, #0x06c]
+ str r1, [r0, #0x070]
+ str r1, [r0, #0x074]
+ str r1, [r0, #0x078]
+ str r1, [r0, #0x07c]
+ str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+ imx6sll_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
new file mode 100644
index 0000000..e6be979
--- /dev/null
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
--
2.6.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support
2016-11-24 6:48 ` [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support Peng Fan
@ 2016-11-24 22:42 ` Fabio Estevam
2016-11-25 1:21 ` Peng Fan
0 siblings, 1 reply; 23+ messages in thread
From: Fabio Estevam @ 2016-11-24 22:42 UTC (permalink / raw)
To: u-boot
Hi Peng,
On Thu, Nov 24, 2016 at 4:48 AM, Peng Fan <peng.fan@nxp.com> wrote:
> +int dram_init(void)
> +{
> + gd->ram_size = PHYS_SDRAM_SIZE;
Couldn't imx_ddr_size() be used instead?
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support
2016-11-24 22:42 ` Fabio Estevam
@ 2016-11-25 1:21 ` Peng Fan
0 siblings, 0 replies; 23+ messages in thread
From: Peng Fan @ 2016-11-25 1:21 UTC (permalink / raw)
To: u-boot
Hi Fabio,
On Thu, Nov 24, 2016 at 08:42:00PM -0200, Fabio Estevam wrote:
>Hi Peng,
>
>On Thu, Nov 24, 2016 at 4:48 AM, Peng Fan <peng.fan@nxp.com> wrote:
>
>> +int dram_init(void)
>> +{
>> + gd->ram_size = PHYS_SDRAM_SIZE;
>
>Couldn't imx_ddr_size() be used instead?
Will fix this in V2.
Thanks,
Peng.
>_______________________________________________
>U-Boot mailing list
>U-Boot at lists.denx.de
>http://lists.denx.de/mailman/listinfo/u-boot
--
^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL
2016-11-24 6:47 ` [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL Peng Fan
@ 2016-11-27 17:02 ` Simon Glass
0 siblings, 0 replies; 23+ messages in thread
From: Simon Glass @ 2016-11-27 17:02 UTC (permalink / raw)
To: u-boot
On 23 November 2016 at 23:47, Peng Fan <peng.fan@nxp.com> wrote:
> There two iomuxc for i.MX6SLL. One is normal IOMUXC, the other
> is for IOMUXC_SNVS.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> ---
> drivers/pinctrl/nxp/pinctrl-imx6.c | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2016-11-27 17:02 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-24 6:47 [U-Boot] [PATCH 00/19] imx: add i.MX6SLL support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 01/19] imx: add i.MX 6SLL CPU type Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 02/19] imx: mx6sll: add pinmux header files Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 03/19] imx: mx6sll: update register address Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 04/19] imx-common: timer: add i.MX6SLL support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 05/19] imx: mx6sll: add iomux settings Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 06/19] imx: mx6: fix mmdc ch0 clk for 6SL Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 07/19] imx: mx6: lcdif: gate clock before changing mux Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 08/19] imx: mx6sl: add lcdif clock support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 09/19] imx: clock: gate clk before changing pix clk mux Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 10/19] imx: mx6sll: add clock support Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 11/19] imx-common: cache: configure L2 Cache for i.MX6SLL Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 12/19] imx: mx6sll: add Kconfig entry " Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 13/19] mx6_common: correct loadaddr and text base " Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 14/19] OCOTP: Update OCOTP driver to support i.MX6SLL Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 15/19] imx-common: lcdif: update lcdif regs for i.MX6SL/SLL Peng Fan
2016-11-24 6:47 ` [U-Boot] [PATCH 16/19] pinctrl: imx6: support i.MX6SLL Peng Fan
2016-11-27 17:02 ` Simon Glass
2016-11-24 6:47 ` [U-Boot] [PATCH 17/19] arm: dts: add i.MX6SLL device tree Peng Fan
2016-11-24 6:48 ` [U-Boot] [PATCH 18/19] arm: imx: add i.MX6SLL EVK board support Peng Fan
2016-11-24 22:42 ` Fabio Estevam
2016-11-25 1:21 ` Peng Fan
2016-11-24 6:48 ` [U-Boot] [PATCH 19/19] imx: mx6sllevk: add plugin support Peng Fan
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