* [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly
@ 2016-11-28 7:57 Zumeng Chen
2016-11-28 9:22 ` Nicolas Ferre
0 siblings, 1 reply; 3+ messages in thread
From: Zumeng Chen @ 2016-11-28 7:57 UTC (permalink / raw)
To: nicolas.ferre; +Cc: davem, netdev, linux-kernel
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:
<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>
There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
---
drivers/net/ethernet/cadence/macb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..2f9c5b2 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
if (status & MACB_BIT(RXUBR)) {
ctrl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+ wmb();
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
--
2.4.11
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly
2016-11-28 7:57 [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen
@ 2016-11-28 9:22 ` Nicolas Ferre
2016-11-28 13:47 ` Zumeng Chen
0 siblings, 1 reply; 3+ messages in thread
From: Nicolas Ferre @ 2016-11-28 9:22 UTC (permalink / raw)
To: Zumeng Chen; +Cc: davem, netdev, linux-kernel, Cyrille Pitchen
Le 28/11/2016 à 08:57, Zumeng Chen a écrit :
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> ---
> drivers/net/ethernet/cadence/macb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 533653b..2f9c5b2 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> if (status & MACB_BIT(RXUBR)) {
> ctrl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
It seems that there is exactly the same pattern in function
at91ether_interrupt() can you fix both locations in your patch please?
Thanks, best regards,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly
2016-11-28 9:22 ` Nicolas Ferre
@ 2016-11-28 13:47 ` Zumeng Chen
0 siblings, 0 replies; 3+ messages in thread
From: Zumeng Chen @ 2016-11-28 13:47 UTC (permalink / raw)
To: Nicolas Ferre; +Cc: davem, netdev, linux-kernel, Cyrille Pitchen
On 2016年11月28日 17:22, Nicolas Ferre wrote:
> Le 28/11/2016 à 08:57, Zumeng Chen a écrit :
>> When a hardware issue happened as described by inline comments, the register
>> write pattern looks like the following:
>>
>> <write ~MACB_BIT(RE)>
>> + wmb();
>> <write MACB_BIT(RE)>
>>
>> There might be a memory barrier between these two write operations, so add wmb
>> to ensure an flip from 0 to 1 for NCR.
>>
>> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
>> ---
>> drivers/net/ethernet/cadence/macb.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
>> index 533653b..2f9c5b2 100644
>> --- a/drivers/net/ethernet/cadence/macb.c
>> +++ b/drivers/net/ethernet/cadence/macb.c
>> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
>> if (status & MACB_BIT(RXUBR)) {
>> ctrl = macb_readl(bp, NCR);
>> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
>> + wmb();
>> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>>
>> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> It seems that there is exactly the same pattern in function
> at91ether_interrupt() can you fix both locations in your patch please?
Indeed, I'll send v2 soon, thanks Nicolas.
Although I only have the environment to re-produce the error report
as follows: "not whole frame pointed by descriptor" for macb_interrupt.
Cheers,
Zumeng
>
> Thanks, best regards,
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2016-11-28 13:47 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-28 7:57 [PATCH 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen
2016-11-28 9:22 ` Nicolas Ferre
2016-11-28 13:47 ` Zumeng Chen
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.