[Qemu-devel] [PATCH] target-m68k: fix CAS

[Qemu-devel] [PATCH] target-m68k: fix CAS

[Laurent Vivier]

- update flags before setting the result to cmp, because
  after that cmp == load and flags are always Z,
- comparison is signed, so use signed values,
- move "cas" after arith_im in the table,
  otherwise casw can be decoded as an arith_im.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
NOTE: this patch applies to my branch m68k-for-2.9,
once reviewed I will merge it with the patch already in
the branch, "target-m68k: add cas/cas2 ops"
I've checked CAS2, but I didn't find any problem.

 target-m68k/translate.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index ffa987d..c7c881c 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2216,15 +2216,15 @@ DISAS_INSN(cas)
     switch ((insn >> 9) & 3) {
     case 1:
         opsize = OS_BYTE;
-        opc = MO_UB;
+        opc = MO_SB;
         break;
     case 2:
         opsize = OS_WORD;
-        opc = MO_TEUW;
+        opc = MO_TESW;
         break;
     case 3:
         opsize = OS_LONG;
-        opc = MO_TEUL;
+        opc = MO_TESL;
         break;
     default:
         g_assert_not_reached();
@@ -2241,7 +2241,7 @@ DISAS_INSN(cas)
         return;
     }
 
-    cmp = gen_extend(DREG(ext, 0), opsize, 0);
+    cmp = gen_extend(DREG(ext, 0), opsize, 1);
 
     /* if  <EA> == Dc then
      *     <EA> = Du
@@ -2253,9 +2253,10 @@ DISAS_INSN(cas)
     load = tcg_temp_new();
     tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
                                IS_USER(s), opc);
+    /* update flags before setting cmp to load */
+    gen_update_cc_cmp(s, load, cmp, opsize);
     gen_partset_reg(opsize, DREG(ext, 0), load);
 
-    gen_update_cc_cmp(s, load, cmp, opsize);
     tcg_temp_free(load);
 }
 
@@ -5337,17 +5338,17 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(arith_im,  0680, fff8, CF_ISA_A);
     INSN(arith_im,  0c00, ff38, CF_ISA_A);
     INSN(arith_im,  0c00, ff00, M68000);
-    INSN(cas,       0ac0, ffc0, CAS);
-    INSN(cas,       0cc0, ffc0, CAS);
-    INSN(cas,       0ec0, ffc0, CAS);
-    INSN(cas2w,     0cfc, ffff, CAS);
-    INSN(cas2l,     0efc, ffff, CAS);
     BASE(bitop_im,  0800, ffc0);
     BASE(bitop_im,  0840, ffc0);
     BASE(bitop_im,  0880, ffc0);
     BASE(bitop_im,  08c0, ffc0);
     INSN(arith_im,  0a80, fff8, CF_ISA_A);
     INSN(arith_im,  0a00, ff00, M68000);
+    INSN(cas,       0ac0, ffc0, CAS);
+    INSN(cas,       0cc0, ffc0, CAS);
+    INSN(cas,       0ec0, ffc0, CAS);
+    INSN(cas2w,     0cfc, ffff, CAS);
+    INSN(cas2l,     0efc, ffff, CAS);
     BASE(move,      1000, f000);
     BASE(move,      2000, f000);
     BASE(move,      3000, f000);
-- 
2.7.4