From: Boris Brezillon <boris.brezillon@free-electrons.com> To: Mike Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Ray Jui <rjui@broadcom.com>, Scott Branden <sbranden@broadcom.com>, bcm-kernel-feedback-list@broadcom.com, Stephen Warren <swarren@wwwdotorg.org>, Lee Jones <lee@kernel.org>, Eric Anholt <eric@anholt.net>, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Boris Brezillon <boris.brezillon@free-electrons.com> Subject: [PATCH 2/2] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock Date: Thu, 1 Dec 2016 22:00:20 +0100 [thread overview] Message-ID: <1480626020-20031-3-git-send-email-boris.brezillon@free-electrons.com> (raw) In-Reply-To: <1480626020-20031-1-git-send-email-boris.brezillon@free-electrons.com> The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6dadab..eaf82f49dede 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: boris.brezillon@free-electrons.com (Boris Brezillon) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock Date: Thu, 1 Dec 2016 22:00:20 +0100 [thread overview] Message-ID: <1480626020-20031-3-git-send-email-boris.brezillon@free-electrons.com> (raw) In-Reply-To: <1480626020-20031-1-git-send-email-boris.brezillon@free-electrons.com> The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6dadab..eaf82f49dede 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( -- 2.7.4
next prev parent reply other threads:[~2016-12-01 21:00 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-12-01 21:00 [PATCH 0/2] clk: bcm2835: Propage rate change to PLLH Boris Brezillon 2016-12-01 21:00 ` Boris Brezillon 2016-12-01 21:00 ` [PATCH 1/2] clk: bcm: Support rate change propagation on bcm2835 clocks Boris Brezillon 2016-12-01 21:00 ` Boris Brezillon 2016-12-02 19:01 ` Eric Anholt 2016-12-02 19:01 ` Eric Anholt 2016-12-02 19:50 ` Boris Brezillon 2016-12-02 19:50 ` Boris Brezillon 2016-12-02 21:13 ` Eric Anholt 2016-12-02 21:13 ` Eric Anholt 2016-12-08 23:06 ` Stephen Boyd 2016-12-08 23:06 ` Stephen Boyd 2016-12-01 21:00 ` Boris Brezillon [this message] 2016-12-01 21:00 ` [PATCH 2/2] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock Boris Brezillon 2016-12-08 23:06 ` Stephen Boyd 2016-12-08 23:06 ` Stephen Boyd
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