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From: Dario Faggioli <dario.faggioli@citrix.com>
To: George Dunlap <George.Dunlap@citrix.com>,
	Stefano Stabellini <sstabellini@kernel.org>
Cc: Andre Przywara <andre.przywara@arm.com>,
	Julien Grall <julien.grall@arm.com>,
	Steve Capper <Steve.Capper@arm.com>,
	Vijay Kilari <vijay.kilari@gmail.com>,
	xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [RFC PATCH 21/24] ARM: vITS: handle INVALL command
Date: Fri, 16 Dec 2016 02:30:18 +0100	[thread overview]
Message-ID: <1481851818.3445.390.camel@citrix.com> (raw)
In-Reply-To: <A5AE4178-19E0-44C7-B751-034EC37EF21F@citrix.com>


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On Wed, 2016-12-14 at 03:39 +0100, George Dunlap wrote:
> > On Dec 10, 2016, at 4:18 AM, Stefano Stabellini <sstabellini@kernel
> > .org> wrote:
> > > > The issue with spreading interrupts migrations over time is
> > > > that it makes
> > > > interrupt latency less deterministic. It is OK, in the uncommon
> > > > case of
> > > > vCPU migration with interrupts, to take a hit for a short time.
> > > > This
> > > > "hit" can be measured. It can be known. If your workload cannot
> > > > tolerate
> > > > it, vCPUs can be pinned. It should be a rare event anyway. On
> > > > the other
> > > > hand, by spreading interrupts migrations, we make it harder to
> > > > predict
> > > > latency. Aside from determinism, another problem with this
> > > > approach is
> > > > that it ensures that every interrupt assigned to a vCPU will
> > > > first hit
> > > > the wrong pCPU, then it will be moved. It guarantees the worst-
> > > > case
> > > > scenario for interrupt latency for the vCPU that has been
> > > > moved. If we
> > > > migrated all interrupts as soon as possible, we would minimize
> > > > the
> > > > amount of interrupts delivered to the wrong pCPU. Most
> > > > interrupts would
> > > > be delivered to the new pCPU right away, reducing interrupt
> > > > latency.
> 
> Another approach which one might take:
> 3. Eagerly migrate a subset of the interrupts and lazily migrate the
> others.  For instance, we could eagerly migrate all the interrupts
> which have fired since the last vcpu migration.  In a system where
> migrations happen frequently, this should only be a handful; in a
> system that migrates infrequently, this will be more, but it won’t
> matter, because it will happen less often.
> 
Yes, if doable (e.g., I don't know how easy and practical is to know
and keep track of fired interrupts) this looks a good solution to me
too.

> So at the moment, the scheduler already tries to avoid migrating
> things *a little bit* if it can (see migrate_resist).  It’s not clear
> to me at the moment whether this is enough or not.  
>
Well, true, but migration resistance, in Credit2, is just a fixed value
which:
 1. is set at boot time;
 2. is always the same for all vcpus;
 3. is always the same, no matter what a vcpu is doing.

And even if we make it tunable and changeable at runtime (which I
intend to do), it's still something pretty "static" because of 2 and 3.

And even if we make it tunable per-vcpu (which is doable), it would be
rather hard to decide to what value to set it, for each vcpu. And, of
course, 3 would still apply (i.e., it would change according to the
vcpu workload or characteristics).

So, it's guessing. More or less fine grained, but always guessing.

On the other hand, using something proportional to nr. of routed
interrupt as the migration resistance threshold would overcome all 1, 2
and 3. It would give us a migrate_resist value which is adaptive, and
is determined according to actual workload of properties of a specific
vcpu.
Feeding routed interrupt info to the load balancer comes from similar
reasoning (and we actually may want to do both).

FTR, Credit1 has a similar mechanism, i.e., it *even wilded guesses*
whether a vcpu could still have some of its data in cache, and tries
not to migrate it if it's likely (see __csched_vcpu_is_cache_hot()).
We can improve that too, although it is a lot more complex and less
predictable, as usual with Credit1.

> Or to put it a different way — how long should the scheduler try to
> wait before moving one of these vcpus?  
>
Yep, it's similar to the "anticipation" problem in I/O schedulers
(where "excessive seeks" ~= "too frequent migrations").

 https://en.wikipedia.org/wiki/Anticipatory_scheduling

> At the moment I haven’t seen a good way of calculating this.
> 
Exactly, and basing the calculation on the number of routed interrupt
--and, if possible, other metrics too-- could be that "good way" we're
looking for.

It would need experimenting, of course, but I like the idea.

> #3 to me has the feeling of being somewhat more satisfying, but also
> potentially fairly complicated.  Since the scheduler already does
> migration resistance somewhat, #1 would be a simpler to implement in
> the sort run.  If it turns out that #1 has other drawbacks, we can
> implement #3 as and when needed.
> 
> Thoughts?
> 
Yes, we can do things incrementally, which is always good. I like your
#1 proposal because it has the really positive side effect of bringing
us in the camp of adaptive migration resistance, which is something
pretty advanced and pretty cool, if we manage to do it right. :-)

Regards,
Dario
-- 
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)

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  reply	other threads:[~2016-12-16  1:30 UTC|newest]

Thread overview: 144+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-28 18:24 [RFC PATCH 00/24] [FOR 4.9] arm64: Dom0 ITS emulation Andre Przywara
2016-09-28 18:24 ` [RFC PATCH 01/24] ARM: GICv3 ITS: parse and store ITS subnodes from hardware DT Andre Przywara
2016-10-26  1:11   ` Stefano Stabellini
2016-11-01 15:13   ` Julien Grall
2016-11-14 17:35     ` Andre Przywara
2016-11-23 15:39       ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 02/24] ARM: GICv3: allocate LPI pending and property table Andre Przywara
2016-10-24 14:28   ` Vijay Kilari
2016-11-02 16:22     ` Andre Przywara
2016-10-26  1:10   ` Stefano Stabellini
2016-11-10 15:29     ` Andre Przywara
2016-11-10 21:00       ` Stefano Stabellini
2016-11-01 17:22   ` Julien Grall
2016-11-15 11:32     ` Andre Przywara
2016-11-23 15:58       ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 03/24] ARM: GICv3 ITS: allocate device and collection table Andre Przywara
2016-10-09 13:55   ` Vijay Kilari
2016-10-10  9:05     ` Andre Przywara
2016-10-24 14:30   ` Vijay Kilari
2016-11-02 17:51     ` Andre Przywara
2016-10-26 22:57   ` Stefano Stabellini
2016-11-01 17:34     ` Julien Grall
2016-11-10 15:32     ` Andre Przywara
2016-11-10 21:06       ` Stefano Stabellini
2016-11-01 18:19   ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 04/24] ARM: GICv3 ITS: map ITS command buffer Andre Przywara
2016-10-24 14:31   ` Vijay Kilari
2016-10-26 23:03   ` Stefano Stabellini
2016-11-10 16:04     ` Andre Przywara
2016-11-02 13:38   ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 05/24] ARM: GICv3 ITS: introduce ITS command handling Andre Przywara
2016-10-26 23:55   ` Stefano Stabellini
2016-10-27 21:52     ` Stefano Stabellini
2016-11-10 15:57     ` Andre Przywara
2016-11-02 15:05   ` Julien Grall
2017-01-31  9:10     ` Andre Przywara
2017-01-31 10:23       ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 06/24] ARM: GICv3 ITS: introduce host LPI array Andre Przywara
2016-10-27 22:59   ` Stefano Stabellini
2016-11-02 15:14     ` Julien Grall
2016-11-10 17:22     ` Andre Przywara
2016-11-10 21:48       ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 07/24] ARM: GICv3 ITS: introduce device mapping Andre Przywara
2016-10-24 15:31   ` Vijay Kilari
2016-11-03 19:33     ` Andre Przywara
2016-10-28  0:08   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 08/24] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2016-10-24 15:31   ` Vijay Kilari
2016-11-03 19:47     ` Andre Przywara
2016-10-28  1:04   ` Stefano Stabellini
2017-01-12 19:14     ` Andre Przywara
2017-01-13 19:37       ` Stefano Stabellini
2017-01-16  9:44         ` André Przywara
2017-01-16 19:16           ` Stefano Stabellini
2016-11-04 15:46   ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 09/24] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2016-10-28  1:51   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 10/24] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2016-10-28 23:07   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 11/24] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2016-10-24 15:32   ` Vijay Kilari
2016-11-03 20:21     ` Andre Przywara
2016-11-04 11:53       ` Julien Grall
2016-10-29  0:39   ` Stefano Stabellini
2017-03-29 15:47     ` Andre Przywara
2016-11-02 17:18   ` Julien Grall
2016-11-02 17:41     ` Stefano Stabellini
2016-11-02 18:03       ` Julien Grall
2016-11-02 18:09         ` Stefano Stabellini
2017-01-31  9:10     ` Andre Przywara
2017-01-31 10:38       ` Julien Grall
2017-01-31 12:04         ` Andre Przywara
2016-09-28 18:24 ` [RFC PATCH 12/24] ARM: vGICv3: introduce basic ITS emulation bits Andre Przywara
2016-10-09 14:20   ` Vijay Kilari
2016-10-10 10:38     ` Andre Przywara
2016-10-24 15:31   ` Vijay Kilari
2016-11-03 19:26     ` Andre Przywara
2016-11-04 12:07       ` Julien Grall
2016-11-03 17:50   ` Julien Grall
2016-11-08 23:54   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 13/24] ARM: vITS: handle CLEAR command Andre Przywara
2016-11-04 15:48   ` Julien Grall
2016-11-09  0:39   ` Stefano Stabellini
2016-11-09 13:32     ` Julien Grall
2016-09-28 18:24 ` [RFC PATCH 14/24] ARM: vITS: handle INT command Andre Przywara
2016-11-09  0:42   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 15/24] ARM: vITS: handle MAPC command Andre Przywara
2016-11-09  0:48   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 16/24] ARM: vITS: handle MAPD command Andre Przywara
2016-11-09  0:54   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 17/24] ARM: vITS: handle MAPTI command Andre Przywara
2016-11-09  1:07   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 18/24] ARM: vITS: handle MOVI command Andre Przywara
2016-11-09  1:13   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 19/24] ARM: vITS: handle DISCARD command Andre Przywara
2016-11-09  1:28   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 20/24] ARM: vITS: handle INV command Andre Przywara
2016-11-09  1:49   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 21/24] ARM: vITS: handle INVALL command Andre Przywara
2016-10-24 15:32   ` Vijay Kilari
2016-11-04  9:22     ` Andre Przywara
2016-11-10  0:21       ` Stefano Stabellini
2016-11-10 11:57         ` Julien Grall
2016-11-10 20:42           ` Stefano Stabellini
2016-11-11 15:53             ` Julien Grall
2016-11-11 20:31               ` Stefano Stabellini
2016-11-18 18:39                 ` Stefano Stabellini
2016-11-25 16:10                   ` Julien Grall
2016-12-01  1:19                     ` Stefano Stabellini
2016-12-02 16:18                       ` Andre Przywara
2016-12-03  0:46                         ` Stefano Stabellini
2016-12-05 13:36                           ` Julien Grall
2016-12-05 19:51                             ` Stefano Stabellini
2016-12-06 15:56                               ` Julien Grall
2016-12-06 19:36                                 ` Stefano Stabellini
2016-12-06 21:32                                   ` Dario Faggioli
2016-12-06 21:53                                     ` Stefano Stabellini
2016-12-06 22:01                                       ` Stefano Stabellini
2016-12-06 22:12                                         ` Dario Faggioli
2016-12-06 23:13                                         ` Julien Grall
2016-12-07 20:20                                           ` Stefano Stabellini
2016-12-09 18:01                                             ` Julien Grall
2016-12-09 20:13                                               ` Stefano Stabellini
2016-12-09 18:07                                             ` Andre Przywara
2016-12-09 20:18                                               ` Stefano Stabellini
2016-12-14  2:39                                                 ` George Dunlap
2016-12-16  1:30                                                   ` Dario Faggioli [this message]
2016-12-06 22:39                                       ` Dario Faggioli
2016-12-06 23:24                                         ` Julien Grall
2016-12-07  0:17                                           ` Dario Faggioli
2016-12-07 20:21                                         ` Stefano Stabellini
2016-12-09 10:14                                           ` Dario Faggioli
2016-12-06 21:36                               ` Dario Faggioli
2016-12-09 19:00                           ` Andre Przywara
2016-12-10  0:30                             ` Stefano Stabellini
2016-12-12 10:38                               ` Andre Przywara
2016-12-14  0:38                                 ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 22/24] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2016-11-10  0:38   ` Stefano Stabellini
2016-09-28 18:24 ` [RFC PATCH 23/24] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2016-09-28 18:24 ` [RFC PATCH 24/24] ARM: vGIC: advertising LPI support Andre Przywara
2016-11-10  0:49   ` Stefano Stabellini
2016-11-10 11:22     ` Julien Grall
2016-11-02 13:56 ` [RFC PATCH 00/24] [FOR 4.9] arm64: Dom0 ITS emulation Julien Grall

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