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* [PATCH V2] drm/i915: relax uncritical udelay_range()
@ 2016-12-16  1:59 ` Nicholas Mc Guire
  0 siblings, 0 replies; 5+ messages in thread
From: Nicholas Mc Guire @ 2016-12-16  1:59 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: Shashank Sharma, Jani Nikula, ymohanma, David Airlie, intel-gfx,
	dri-devel, linux-kernel, Nicholas Mc Guire

udelay_range(1, 2) is inefficient and as discussions with Jani Nikula
<jani.nikula@linux.intel.com> unnecessary here. This replaces this
tight setting with a relaxed delay of min=20 and max=50 which helps
the hrtimer subsystem optimize timer handling.

Fixes: commit be4fc046bed3 ("drm/i915: add VLV DSI PLL Calculations") 
Link: http://lkml.org/lkml/2016/12/15/147
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
---

V2: use relaxed uslee_range() rather than udelay
    fix documentation of changed timings

Problem found by coccinelle:

Patch was compile tested with: x86_64_defconfig (implies CONFIG_DRM_I915)

Patch is against 4.9.0 (localversion-next is next-20161215)

 drivers/gpu/drm/i915/intel_dsi_pll.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..d210bc4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -156,8 +156,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
 		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
 
-	/* wait at least 0.5 us after ungating before enabling VCO */
-	usleep_range(1, 10);
+	/* wait at least 0.5 us after ungating before enabling VCO,
+	 * allow hrtimer subsystem optimization by relaxing timing
+	 */
+	usleep_range(10, 50);
 
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
 
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH V2] drm/i915: relax uncritical udelay_range()
@ 2016-12-16  1:59 ` Nicholas Mc Guire
  0 siblings, 0 replies; 5+ messages in thread
From: Nicholas Mc Guire @ 2016-12-16  1:59 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: David Airlie, intel-gfx, linux-kernel, dri-devel, Nicholas Mc Guire

udelay_range(1, 2) is inefficient and as discussions with Jani Nikula
<jani.nikula@linux.intel.com> unnecessary here. This replaces this
tight setting with a relaxed delay of min=20 and max=50 which helps
the hrtimer subsystem optimize timer handling.

Fixes: commit be4fc046bed3 ("drm/i915: add VLV DSI PLL Calculations") 
Link: http://lkml.org/lkml/2016/12/15/147
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
---

V2: use relaxed uslee_range() rather than udelay
    fix documentation of changed timings

Problem found by coccinelle:

Patch was compile tested with: x86_64_defconfig (implies CONFIG_DRM_I915)

Patch is against 4.9.0 (localversion-next is next-20161215)

 drivers/gpu/drm/i915/intel_dsi_pll.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..d210bc4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -156,8 +156,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
 		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
 
-	/* wait at least 0.5 us after ungating before enabling VCO */
-	usleep_range(1, 10);
+	/* wait at least 0.5 us after ungating before enabling VCO,
+	 * allow hrtimer subsystem optimization by relaxing timing
+	 */
+	usleep_range(10, 50);
 
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
 
-- 
2.1.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: relax uncritical udelay_range()
  2016-12-16  1:59 ` Nicholas Mc Guire
  (?)
@ 2016-12-16  2:15 ` Patchwork
  -1 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2016-12-16  2:15 UTC (permalink / raw)
  To: Nicholas Mc Guire; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: relax uncritical udelay_range()
URL   : https://patchwork.freedesktop.org/series/16897/
State : success

== Summary ==

Series 16897v1 drm/i915: relax uncritical udelay_range()
https://patchwork.freedesktop.org/api/1.0/series/16897/revisions/1/mbox/


fi-bdw-5557u     total:247  pass:233  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:247  pass:208  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:247  pass:222  dwarn:0   dfail:0   fail:0   skip:25 
fi-bxt-t5700     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-j1900     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650       total:247  pass:195  dwarn:0   dfail:0   fail:0   skip:52 
fi-ivb-3520m     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:247  pass:227  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:247  pass:224  dwarn:3   dfail:0   fail:0   skip:20 
fi-skl-6770hq    total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:247  pass:215  dwarn:0   dfail:0   fail:0   skip:32 

639f10d1159e87cac2f85769dcd081520b904f56 drm-tip: 2016y-12m-15d-17h-57m-41s UTC integration manifest
83a9dc0 drm/i915: relax uncritical udelay_range()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3303/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH V2] drm/i915: relax uncritical udelay_range()
  2016-12-16  1:59 ` Nicholas Mc Guire
@ 2016-12-16  9:25   ` Jani Nikula
  -1 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-12-16  9:25 UTC (permalink / raw)
  To: Nicholas Mc Guire, Daniel Vetter
  Cc: Shashank Sharma, ymohanma, David Airlie, intel-gfx, dri-devel,
	linux-kernel, Nicholas Mc Guire

On Fri, 16 Dec 2016, Nicholas Mc Guire <hofrat@osadl.org> wrote:
> udelay_range(1, 2) is inefficient and as discussions with Jani Nikula
> <jani.nikula@linux.intel.com> unnecessary here. This replaces this
> tight setting with a relaxed delay of min=20 and max=50 which helps
> the hrtimer subsystem optimize timer handling.
>
> Fixes: commit be4fc046bed3 ("drm/i915: add VLV DSI PLL Calculations") 
> Link: http://lkml.org/lkml/2016/12/15/147
> Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

> ---
>
> V2: use relaxed uslee_range() rather than udelay
>     fix documentation of changed timings
>
> Problem found by coccinelle:
>
> Patch was compile tested with: x86_64_defconfig (implies CONFIG_DRM_I915)
>
> Patch is against 4.9.0 (localversion-next is next-20161215)
>
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..d210bc4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -156,8 +156,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
>  		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
>  
> -	/* wait at least 0.5 us after ungating before enabling VCO */
> -	usleep_range(1, 10);
> +	/* wait at least 0.5 us after ungating before enabling VCO,
> +	 * allow hrtimer subsystem optimization by relaxing timing
> +	 */
> +	usleep_range(10, 50);
>  
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

-- 
Jani Nikula, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH V2] drm/i915: relax uncritical udelay_range()
@ 2016-12-16  9:25   ` Jani Nikula
  0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-12-16  9:25 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: David Airlie, intel-gfx, linux-kernel, dri-devel, Nicholas Mc Guire

On Fri, 16 Dec 2016, Nicholas Mc Guire <hofrat@osadl.org> wrote:
> udelay_range(1, 2) is inefficient and as discussions with Jani Nikula
> <jani.nikula@linux.intel.com> unnecessary here. This replaces this
> tight setting with a relaxed delay of min=20 and max=50 which helps
> the hrtimer subsystem optimize timer handling.
>
> Fixes: commit be4fc046bed3 ("drm/i915: add VLV DSI PLL Calculations") 
> Link: http://lkml.org/lkml/2016/12/15/147
> Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

> ---
>
> V2: use relaxed uslee_range() rather than udelay
>     fix documentation of changed timings
>
> Problem found by coccinelle:
>
> Patch was compile tested with: x86_64_defconfig (implies CONFIG_DRM_I915)
>
> Patch is against 4.9.0 (localversion-next is next-20161215)
>
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..d210bc4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -156,8 +156,10 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
>  		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
>  
> -	/* wait at least 0.5 us after ungating before enabling VCO */
> -	usleep_range(1, 10);
> +	/* wait at least 0.5 us after ungating before enabling VCO,
> +	 * allow hrtimer subsystem optimization by relaxing timing
> +	 */
> +	usleep_range(10, 50);
>  
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-12-16  9:25 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-16  1:59 [PATCH V2] drm/i915: relax uncritical udelay_range() Nicholas Mc Guire
2016-12-16  1:59 ` Nicholas Mc Guire
2016-12-16  2:15 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-12-16  9:25 ` [PATCH V2] " Jani Nikula
2016-12-16  9:25   ` Jani Nikula

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