[PATCH v3 1/3] USB3/DWC3: Add definition for global soc bus configuration register

[PATCH v3 1/3] USB3/DWC3: Add definition for global soc bus configuration register

[Changming Huang]

Add the macro definition for global soc bus configuration register 0/1

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - no change
Changes in v2:
  - split the patch
  - add more macro definition for soc bus configuration register

 drivers/usb/dwc3/core.h |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index de5a857..065aa6f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,32 @@
 
 /* Bit fields */
 
+/* Global SoC Bus Configuration Register 0 */
+#define AXI3_CACHE_TYPE_AW		0x8 /* write allocate */
+#define AXI3_CACHE_TYPE_AR		0x4 /* read allocate */
+#define AXI3_CACHE_TYPE_SNP		0x2 /* cacheable */
+#define AXI3_CACHE_TYPE_BUF		0x1 /* bufferable */
+#define DWC3_GSBUSCFG0_DATARD_SHIFT	28
+#define DWC3_GSBUSCFG0_DESCRD_SHIFT	24
+#define DWC3_GSBUSCFG0_DATAWR_SHIFT	20
+#define DWC3_GSBUSCFG0_DESCWR_SHIFT	16
+#define DWC3_GSBUSCFG0_SNP_MASK		0xffff0000
+#define DWC3_GSBUSCFG0_DATABIGEND	(1 << 11)
+#define DWC3_GSBUSCFG0_DESCBIGEND	(1 << 10)
+#define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA	(1 << 6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA	(1 << 5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA	(1 << 4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA	(1 << 3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA	(1 << 2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA	(1 << 1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA	(1 << 0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK	0xff
+
+/* Global SoC Bus Configuration Register 1 */
+#define DWC3_GSBUSCFG1_1KPAGEENA	(1 << 12) /* 1K page boundary enable */
+#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK	0xf00
+
 /* Global Debug Queue/FIFO Space Available Register */
 #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
 #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
-- 
1.7.9.5

[PATCH v3 1/3] USB3/DWC3: Add definition for global soc bus configuration register

[Changming Huang]

Add the macro definition for global soc bus configuration register 0/1

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - no change
Changes in v2:
  - split the patch
  - add more macro definition for soc bus configuration register

 drivers/usb/dwc3/core.h |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index de5a857..065aa6f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,32 @@
 
 /* Bit fields */
 
+/* Global SoC Bus Configuration Register 0 */
+#define AXI3_CACHE_TYPE_AW		0x8 /* write allocate */
+#define AXI3_CACHE_TYPE_AR		0x4 /* read allocate */
+#define AXI3_CACHE_TYPE_SNP		0x2 /* cacheable */
+#define AXI3_CACHE_TYPE_BUF		0x1 /* bufferable */
+#define DWC3_GSBUSCFG0_DATARD_SHIFT	28
+#define DWC3_GSBUSCFG0_DESCRD_SHIFT	24
+#define DWC3_GSBUSCFG0_DATAWR_SHIFT	20
+#define DWC3_GSBUSCFG0_DESCWR_SHIFT	16
+#define DWC3_GSBUSCFG0_SNP_MASK		0xffff0000
+#define DWC3_GSBUSCFG0_DATABIGEND	(1 << 11)
+#define DWC3_GSBUSCFG0_DESCBIGEND	(1 << 10)
+#define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA	(1 << 6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA	(1 << 5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA	(1 << 4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA	(1 << 3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA	(1 << 2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA	(1 << 1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA	(1 << 0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK	0xff
+
+/* Global SoC Bus Configuration Register 1 */
+#define DWC3_GSBUSCFG1_1KPAGEENA	(1 << 12) /* 1K page boundary enable */
+#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK	0xf00
+
 /* Global Debug Queue/FIFO Space Available Register */
 #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
 #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
-- 
1.7.9.5

[PATCH v3 1/3] USB3/DWC3: Add definition for global soc bus configuration register

[Changming Huang]

Add the macro definition for global soc bus configuration register 0/1

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - no change
Changes in v2:
  - split the patch
  - add more macro definition for soc bus configuration register

 drivers/usb/dwc3/core.h |   26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index de5a857..065aa6f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -161,6 +161,32 @@
 
 /* Bit fields */
 
+/* Global SoC Bus Configuration Register 0 */
+#define AXI3_CACHE_TYPE_AW		0x8 /* write allocate */
+#define AXI3_CACHE_TYPE_AR		0x4 /* read allocate */
+#define AXI3_CACHE_TYPE_SNP		0x2 /* cacheable */
+#define AXI3_CACHE_TYPE_BUF		0x1 /* bufferable */
+#define DWC3_GSBUSCFG0_DATARD_SHIFT	28
+#define DWC3_GSBUSCFG0_DESCRD_SHIFT	24
+#define DWC3_GSBUSCFG0_DATAWR_SHIFT	20
+#define DWC3_GSBUSCFG0_DESCWR_SHIFT	16
+#define DWC3_GSBUSCFG0_SNP_MASK		0xffff0000
+#define DWC3_GSBUSCFG0_DATABIGEND	(1 << 11)
+#define DWC3_GSBUSCFG0_DESCBIGEND	(1 << 10)
+#define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
+#define DWC3_GSBUSCFG0_INCR128BRSTENA	(1 << 6) /* INCR128 burst */
+#define DWC3_GSBUSCFG0_INCR64BRSTENA	(1 << 5) /* INCR64 burst */
+#define DWC3_GSBUSCFG0_INCR32BRSTENA	(1 << 4) /* INCR32 burst */
+#define DWC3_GSBUSCFG0_INCR16BRSTENA	(1 << 3) /* INCR16 burst */
+#define DWC3_GSBUSCFG0_INCR8BRSTENA	(1 << 2) /* INCR8 burst */
+#define DWC3_GSBUSCFG0_INCR4BRSTENA	(1 << 1) /* INCR4 burst */
+#define DWC3_GSBUSCFG0_INCRBRSTENA	(1 << 0) /* undefined length enable */
+#define DWC3_GSBUSCFG0_INCRBRST_MASK	0xff
+
+/* Global SoC Bus Configuration Register 1 */
+#define DWC3_GSBUSCFG1_1KPAGEENA	(1 << 12) /* 1K page boundary enable */
+#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK	0xf00
+
 /* Global Debug Queue/FIFO Space Available Register */
 #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
 #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
-- 
1.7.9.5

[PATCH v3 2/3] USB3/DWC3: Add property "snps,incr-burst-type-adjustment" for INCR burst type

[Changming Huang]

New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
Field "x": 1/0 - undefined length INCR burst type enable or not;
Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.

While enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platform:
around 3% improvement (from 364MB/s to 375MB/s).

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node.

 Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
 arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
 4 files changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e3e6983..8c405a3 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -55,6 +55,10 @@ Optional properties:
 	fladj_30mhz_sdbnd signal is invalid or incorrect.
 
  - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
+	register, undefined length INCR burst type enable and INCRx type.
+	First field is for undefined length INCR burst type enable or not.
+	Second field is for largest INCRx type enabled.
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
@@ -63,4 +67,5 @@ dwc3@4a030000 {
 	reg = <0x4a030000 0xcfff>;
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
+	snps,incr-burst-type-adjustment = <0x1>, <16>;
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..2999edb 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		pcie@3400000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 97d331e..64828ce 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -482,6 +482,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3@3000000 {
@@ -491,6 +492,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb2: usb3@3100000 {
@@ -500,6 +502,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		sata: sata@3200000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index d058e56..414af27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -710,6 +710,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3@3110000 {
@@ -720,6 +721,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		ccn@4000000 {
-- 
1.7.9.5

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Changming Huang]

New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
Field "x": 1/0 - undefined length INCR burst type enable or not;
Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.

While enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platform:
around 3% improvement (from 364MB/s to 375MB/s).

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node.

 Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
 arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
 4 files changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e3e6983..8c405a3 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -55,6 +55,10 @@ Optional properties:
 	fladj_30mhz_sdbnd signal is invalid or incorrect.
 
  - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
+	register, undefined length INCR burst type enable and INCRx type.
+	First field is for undefined length INCR burst type enable or not.
+	Second field is for largest INCRx type enabled.
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
@@ -63,4 +67,5 @@ dwc3@4a030000 {
 	reg = <0x4a030000 0xcfff>;
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
+	snps,incr-burst-type-adjustment = <0x1>, <16>;
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..2999edb 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		pcie@3400000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 97d331e..64828ce 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -482,6 +482,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3@3000000 {
@@ -491,6 +492,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb2: usb3@3100000 {
@@ -500,6 +502,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		sata: sata@3200000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index d058e56..414af27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -710,6 +710,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3@3110000 {
@@ -720,6 +721,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		ccn@4000000 {
-- 
1.7.9.5

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Changming Huang]

New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
Field "x": 1/0 - undefined length INCR burst type enable or not;
Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.

While enabling undefined length INCR burst type and INCR16 burst type,
get better write performance on NXP Layerscape platform:
around 3% improvement (from 364MB/s to 375MB/s).

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node.

 Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
 arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
 4 files changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e3e6983..8c405a3 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -55,6 +55,10 @@ Optional properties:
 	fladj_30mhz_sdbnd signal is invalid or incorrect.
 
  - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
+	register, undefined length INCR burst type enable and INCRx type.
+	First field is for undefined length INCR burst type enable or not.
+	Second field is for largest INCRx type enabled.
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
@@ -63,4 +67,5 @@ dwc3 at 4a030000 {
 	reg = <0x4a030000 0xcfff>;
 	interrupts = <0 92 4>
 	usb-phy = <&usb2_phy>, <&usb3,phy>;
+	snps,incr-burst-type-adjustment = <0x1>, <16>;
 };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..2999edb 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		pcie at 3400000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 97d331e..64828ce 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -482,6 +482,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3 at 3000000 {
@@ -491,6 +492,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb2: usb3 at 3100000 {
@@ -500,6 +502,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		sata: sata at 3200000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index d058e56..414af27 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -710,6 +710,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		usb1: usb3 at 3110000 {
@@ -720,6 +721,7 @@
 			dr_mode = "host";
 			snps,quirk-frame-length-adjustment = <0x20>;
 			snps,dis_rxdet_inp3_quirk;
+			snps,incr-burst-type-adjustment = <0x1>, <16>;
 		};
 
 		ccn at 4000000 {
-- 
1.7.9.5

[PATCH v3 3/3] USB3/DWC3: Enable undefined length INCR burst type

[Changming Huang]

Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst size to
one special value, instead of the default value.

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node to reset GSBUSCFG0.
Changes in v2:
  - split patch
  - create one new function to handle soc bus configuration register.

 drivers/usb/dwc3/core.c |   51 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |    7 +++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 369bab1..404d7e9 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -650,6 +650,55 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 }
 
+/* set global soc bus configuration registers */
+static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
+{
+	struct device *dev = dwc->dev;
+	u32 cfg;
+	int ret;
+
+	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+	/* Get INCR burst type, if return !NULL, not to change this type */
+	ret = device_property_read_u32_array(dev,
+			"snps,incr-burst-type-adjustment",
+			dwc->incr_burst_type, 2);
+	if (!ret) {
+		/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+		cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+		if (*dwc->incr_burst_type)
+			cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+		switch (*(dwc->incr_burst_type + 1)) {
+		case 256:
+			cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+			break;
+		case 128:
+			cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+			break;
+		case 64:
+			cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+			break;
+		case 32:
+			cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+			break;
+		case 16:
+			cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+			break;
+		case 8:
+			cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+			break;
+		case 4:
+			cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+			break;
+		default:
+			dev_err(dev, "Invalid property\n");
+			break;
+		}
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -698,6 +747,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	/* Adjust Frame Length */
 	dwc3_frame_length_adjustment(dwc);
 
+	dwc3_set_soc_bus_cfg(dwc);
+
 	usb_phy_set_suspend(dwc->usb2_phy, 0);
 	usb_phy_set_suspend(dwc->usb3_phy, 0);
 	ret = phy_power_on(dwc->usb2_generic_phy);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 065aa6f..cfe389b 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -805,6 +805,7 @@ struct dwc3_scratchpad_array {
  * @regs: base address for our registers
  * @regs_size: address space size
  * @fladj: frame length adjustment
+ * @incr_burst_type: INCR burst type adjustment
  * @irq_gadget: peripheral controller's IRQ number
  * @nr_scratch: number of scratch buffers
  * @u1u2: only used on revisions <1.83a for workaround
@@ -928,6 +929,12 @@ struct dwc3 {
 	enum usb_phy_interface	hsphy_mode;
 
 	u32			fladj;
+	/*
+	 * For INCR burst type.
+	 * First field: for undefined length INCR burst type enable.
+	 * Second field: for INCRx burst type enable
+	 */
+	u32			incr_burst_type[2];
 	u32			irq_gadget;
 	u32			nr_scratch;
 	u32			u1u2;
-- 
1.7.9.5

[PATCH v3 3/3] USB3/DWC3: Enable undefined length INCR burst type

[Changming Huang]

Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst size to
one special value, instead of the default value.

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node to reset GSBUSCFG0.
Changes in v2:
  - split patch
  - create one new function to handle soc bus configuration register.

 drivers/usb/dwc3/core.c |   51 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |    7 +++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 369bab1..404d7e9 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -650,6 +650,55 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 }
 
+/* set global soc bus configuration registers */
+static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
+{
+	struct device *dev = dwc->dev;
+	u32 cfg;
+	int ret;
+
+	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+	/* Get INCR burst type, if return !NULL, not to change this type */
+	ret = device_property_read_u32_array(dev,
+			"snps,incr-burst-type-adjustment",
+			dwc->incr_burst_type, 2);
+	if (!ret) {
+		/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+		cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+		if (*dwc->incr_burst_type)
+			cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+		switch (*(dwc->incr_burst_type + 1)) {
+		case 256:
+			cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+			break;
+		case 128:
+			cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+			break;
+		case 64:
+			cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+			break;
+		case 32:
+			cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+			break;
+		case 16:
+			cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+			break;
+		case 8:
+			cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+			break;
+		case 4:
+			cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+			break;
+		default:
+			dev_err(dev, "Invalid property\n");
+			break;
+		}
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -698,6 +747,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	/* Adjust Frame Length */
 	dwc3_frame_length_adjustment(dwc);
 
+	dwc3_set_soc_bus_cfg(dwc);
+
 	usb_phy_set_suspend(dwc->usb2_phy, 0);
 	usb_phy_set_suspend(dwc->usb3_phy, 0);
 	ret = phy_power_on(dwc->usb2_generic_phy);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 065aa6f..cfe389b 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -805,6 +805,7 @@ struct dwc3_scratchpad_array {
  * @regs: base address for our registers
  * @regs_size: address space size
  * @fladj: frame length adjustment
+ * @incr_burst_type: INCR burst type adjustment
  * @irq_gadget: peripheral controller's IRQ number
  * @nr_scratch: number of scratch buffers
  * @u1u2: only used on revisions <1.83a for workaround
@@ -928,6 +929,12 @@ struct dwc3 {
 	enum usb_phy_interface	hsphy_mode;
 
 	u32			fladj;
+	/*
+	 * For INCR burst type.
+	 * First field: for undefined length INCR burst type enable.
+	 * Second field: for INCRx burst type enable
+	 */
+	u32			incr_burst_type[2];
 	u32			irq_gadget;
 	u32			nr_scratch;
 	u32			u1u2;
-- 
1.7.9.5

[PATCH v3 3/3] USB3/DWC3: Enable undefined length INCR burst type

[Changming Huang]

Enable the undefined length INCR burst type and set INCRx.
Different platform may has the different burst size type.
In order to get best performance, we need to tune the burst size to
one special value, instead of the default value.

Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
Changes in v3:
  - add new property for INCR burst in usb node to reset GSBUSCFG0.
Changes in v2:
  - split patch
  - create one new function to handle soc bus configuration register.

 drivers/usb/dwc3/core.c |   51 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/core.h |    7 +++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 369bab1..404d7e9 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -650,6 +650,55 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 }
 
+/* set global soc bus configuration registers */
+static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
+{
+	struct device *dev = dwc->dev;
+	u32 cfg;
+	int ret;
+
+	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
+
+	/* Get INCR burst type, if return !NULL, not to change this type */
+	ret = device_property_read_u32_array(dev,
+			"snps,incr-burst-type-adjustment",
+			dwc->incr_burst_type, 2);
+	if (!ret) {
+		/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
+		cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
+		if (*dwc->incr_burst_type)
+			cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
+		switch (*(dwc->incr_burst_type + 1)) {
+		case 256:
+			cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
+			break;
+		case 128:
+			cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
+			break;
+		case 64:
+			cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
+			break;
+		case 32:
+			cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
+			break;
+		case 16:
+			cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
+			break;
+		case 8:
+			cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
+			break;
+		case 4:
+			cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
+			break;
+		default:
+			dev_err(dev, "Invalid property\n");
+			break;
+		}
+	}
+
+	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -698,6 +747,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	/* Adjust Frame Length */
 	dwc3_frame_length_adjustment(dwc);
 
+	dwc3_set_soc_bus_cfg(dwc);
+
 	usb_phy_set_suspend(dwc->usb2_phy, 0);
 	usb_phy_set_suspend(dwc->usb3_phy, 0);
 	ret = phy_power_on(dwc->usb2_generic_phy);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 065aa6f..cfe389b 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -805,6 +805,7 @@ struct dwc3_scratchpad_array {
  * @regs: base address for our registers
  * @regs_size: address space size
  * @fladj: frame length adjustment
+ * @incr_burst_type: INCR burst type adjustment
  * @irq_gadget: peripheral controller's IRQ number
  * @nr_scratch: number of scratch buffers
  * @u1u2: only used on revisions <1.83a for workaround
@@ -928,6 +929,12 @@ struct dwc3 {
 	enum usb_phy_interface	hsphy_mode;
 
 	u32			fladj;
+	/*
+	 * For INCR burst type.
+	 * First field: for undefined length INCR burst type enable.
+	 * Second field: for INCRx burst type enable
+	 */
+	u32			incr_burst_type[2];
 	u32			irq_gadget;
 	u32			nr_scratch;
 	u32			u1u2;
-- 
1.7.9.5

Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
> Field "x": 1/0 - undefined length INCR burst type enable or not;
> Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> 
> While enabling undefined length INCR burst type and INCR16 burst type,
> get better write performance on NXP Layerscape platform:
> around 3% improvement (from 364MB/s to 375MB/s).
> 
> Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> ---
> Changes in v3:
>   - add new property for INCR burst in usb node.
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>  4 files changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index e3e6983..8c405a3 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -55,6 +55,10 @@ Optional properties:
>  	fladj_30mhz_sdbnd signal is invalid or incorrect.
>  
>   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> + - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
> +	register, undefined length INCR burst type enable and INCRx type.
> +	First field is for undefined length INCR burst type enable or not.
> +	Second field is for largest INCRx type enabled.

Why do you need the first field? Is the 2nd field used if the 1st is 0? 
If not, then just use the presence of the property to enable or not.

Rob

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
> Field "x": 1/0 - undefined length INCR burst type enable or not;
> Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> 
> While enabling undefined length INCR burst type and INCR16 burst type,
> get better write performance on NXP Layerscape platform:
> around 3% improvement (from 364MB/s to 375MB/s).
> 
> Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> ---
> Changes in v3:
>   - add new property for INCR burst in usb node.
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>  4 files changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index e3e6983..8c405a3 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -55,6 +55,10 @@ Optional properties:
>  	fladj_30mhz_sdbnd signal is invalid or incorrect.
>  
>   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> + - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
> +	register, undefined length INCR burst type enable and INCRx type.
> +	First field is for undefined length INCR burst type enable or not.
> +	Second field is for largest INCRx type enabled.

Why do you need the first field? Is the 2nd field used if the 1st is 0? 
If not, then just use the presence of the property to enable or not.

Rob

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Friday, December 23, 2016 2:45 AM
> To: Jerry Huang <jerry.huang@nxp.com>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
> DWC3.
> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >
> > While enabling undefined length INCR burst type and INCR16 burst type,
> > get better write performance on NXP Layerscape platform:
> > around 3% improvement (from 364MB/s to 375MB/s).
> >
> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > ---
> > Changes in v3:
> >   - add new property for INCR burst in usb node.
> >
> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >  4 files changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > index e3e6983..8c405a3 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -55,6 +55,10 @@ Optional properties:
> >  	fladj_30mhz_sdbnd signal is invalid or incorrect.
> >
> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> reallocated.
> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> GSBUSCFG0
> > +	register, undefined length INCR burst type enable and INCRx type.
> > +	First field is for undefined length INCR burst type enable or not.
> > +	Second field is for largest INCRx type enabled.
> 
> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> If not, then just use the presence of the property to enable or not.
The first field is one switch.
When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256. 
When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Friday, December 23, 2016 2:45 AM
> To: Jerry Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
> Cc: balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org;
> will.deacon-5wv7dgnIgG8@public.gmane.org; linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
> DWC3.
> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >
> > While enabling undefined length INCR burst type and INCR16 burst type,
> > get better write performance on NXP Layerscape platform:
> > around 3% improvement (from 364MB/s to 375MB/s).
> >
> > Signed-off-by: Changming Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
> > ---
> > Changes in v3:
> >   - add new property for INCR burst in usb node.
> >
> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >  4 files changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > index e3e6983..8c405a3 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -55,6 +55,10 @@ Optional properties:
> >  	fladj_30mhz_sdbnd signal is invalid or incorrect.
> >
> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> reallocated.
> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> GSBUSCFG0
> > +	register, undefined length INCR burst type enable and INCRx type.
> > +	First field is for undefined length INCR burst type enable or not.
> > +	Second field is for largest INCRx type enabled.
> 
> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> If not, then just use the presence of the property to enable or not.
The first field is one switch.
When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256. 
When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.
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[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Friday, December 23, 2016 2:45 AM
> To: Jerry Huang <jerry.huang@nxp.com>
> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
> DWC3.
> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >
> > While enabling undefined length INCR burst type and INCR16 burst type,
> > get better write performance on NXP Layerscape platform:
> > around 3% improvement (from 364MB/s to 375MB/s).
> >
> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > ---
> > Changes in v3:
> >   - add new property for INCR burst in usb node.
> >
> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >  4 files changed, 11 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > index e3e6983..8c405a3 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -55,6 +55,10 @@ Optional properties:
> >  	fladj_30mhz_sdbnd signal is invalid or incorrect.
> >
> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> reallocated.
> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> GSBUSCFG0
> > +	register, undefined length INCR burst type enable and INCRx type.
> > +	First field is for undefined length INCR burst type enable or not.
> > +	Second field is for largest INCRx type enabled.
> 
> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> If not, then just use the presence of the property to enable or not.
The first field is one switch.
When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256. 
When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.

Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> Hi, Rob,
>> -----Original Message-----
>> From: Rob Herring [mailto:robh@kernel.org]
>> Sent: Friday, December 23, 2016 2:45 AM
>> To: Jerry Huang <jerry.huang@nxp.com>
>> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
>> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
>> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
>> DWC3.
>> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
>> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >
>> > While enabling undefined length INCR burst type and INCR16 burst type,
>> > get better write performance on NXP Layerscape platform:
>> > around 3% improvement (from 364MB/s to 375MB/s).
>> >
>> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > ---
>> > Changes in v3:
>> >   - add new property for INCR burst in usb node.
>> >
>> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >  4 files changed, 11 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > index e3e6983..8c405a3 100644
>> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > @@ -55,6 +55,10 @@ Optional properties:
>> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >
>> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> reallocated.
>> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> GSBUSCFG0
>> > +   register, undefined length INCR burst type enable and INCRx type.
>> > +   First field is for undefined length INCR burst type enable or not.
>> > +   Second field is for largest INCRx type enabled.
>>
>> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> If not, then just use the presence of the property to enable or not.
> The first field is one switch.
> When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256.
> When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
> So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
> If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.

Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.

Rob

Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> Hi, Rob,
>> -----Original Message-----
>> From: Rob Herring [mailto:robh@kernel.org]
>> Sent: Friday, December 23, 2016 2:45 AM
>> To: Jerry Huang <jerry.huang@nxp.com>
>> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
>> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
>> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
>> DWC3.
>> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
>> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >
>> > While enabling undefined length INCR burst type and INCR16 burst type,
>> > get better write performance on NXP Layerscape platform:
>> > around 3% improvement (from 364MB/s to 375MB/s).
>> >
>> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > ---
>> > Changes in v3:
>> >   - add new property for INCR burst in usb node.
>> >
>> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >  4 files changed, 11 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > index e3e6983..8c405a3 100644
>> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > @@ -55,6 +55,10 @@ Optional properties:
>> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >
>> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> reallocated.
>> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> GSBUSCFG0
>> > +   register, undefined length INCR burst type enable and INCRx type.
>> > +   First field is for undefined length INCR burst type enable or not.
>> > +   Second field is for largest INCRx type enabled.
>>
>> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> If not, then just use the presence of the property to enable or not.
> The first field is one switch.
> When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256.
> When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
> So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
> If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.

Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.

Rob

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> Hi, Rob,
>> -----Original Message-----
>> From: Rob Herring [mailto:robh at kernel.org]
>> Sent: Friday, December 23, 2016 2:45 AM
>> To: Jerry Huang <jerry.huang@nxp.com>
>> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
>> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
>> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
>> kernel at lists.infradead.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0
>> DWC3.
>> > Field "x": 1/0 - undefined length INCR burst type enable or not; Field
>> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >
>> > While enabling undefined length INCR burst type and INCR16 burst type,
>> > get better write performance on NXP Layerscape platform:
>> > around 3% improvement (from 364MB/s to 375MB/s).
>> >
>> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > ---
>> > Changes in v3:
>> >   - add new property for INCR burst in usb node.
>> >
>> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >  4 files changed, 11 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > index e3e6983..8c405a3 100644
>> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > @@ -55,6 +55,10 @@ Optional properties:
>> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >
>> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> reallocated.
>> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> GSBUSCFG0
>> > +   register, undefined length INCR burst type enable and INCRx type.
>> > +   First field is for undefined length INCR burst type enable or not.
>> > +   Second field is for largest INCRx type enabled.
>>
>> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> If not, then just use the presence of the property to enable or not.
> The first field is one switch.
> When it is 1, means undefined length INCR burst type enabled, we can use any length less than or equal to the largest-enabled burst length of INCR4/8/16/32/64/128/256.
> When it is zero, means INCRx burst mode enabled, we can use one fixed burst length of 1/4/8/16/32/64/128/256 byte.
> So, the 2nd field is used if the 1st is 0, we need to select one largest burst length the USB controller can support.
> If we don't want to change the value of this register (use the default value), we don't need to add this property to usb node.

Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.

Rob

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Wednesday, January 04, 2017 5:24 AM
> To: Jerry Huang <jerry.huang@nxp.com>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> > Hi, Rob,
> >> -----Original Message-----
> >> From: Rob Herring [mailto:robh@kernel.org]
> >> Sent: Friday, December 23, 2016 2:45 AM
> >> To: Jerry Huang <jerry.huang@nxp.com>
> >> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> >> will.deacon@arm.com; linux@armlinux.org.uk;
> >> devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> >> linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> incr-burst- type-adjustment" for INCR burst type
> >>
> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > USB3.0
> >> DWC3.
> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> >> > Field
> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >> >
> >> > While enabling undefined length INCR burst type and INCR16 burst
> >> > type, get better write performance on NXP Layerscape platform:
> >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> >
> >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > ---
> >> > Changes in v3:
> >> >   - add new property for INCR burst in usb node.
> >> >
> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> >  4 files changed, 11 insertions(+)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > index e3e6983..8c405a3 100644
> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > @@ -55,6 +55,10 @@ Optional properties:
> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> >
> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> >> reallocated.
> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> >> GSBUSCFG0
> >> > +   register, undefined length INCR burst type enable and INCRx type.
> >> > +   First field is for undefined length INCR burst type enable or not.
> >> > +   Second field is for largest INCRx type enabled.
> >>
> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> If not, then just use the presence of the property to enable or not.
> > The first field is one switch.
> > When it is 1, means undefined length INCR burst type enabled, we can use
> any length less than or equal to the largest-enabled burst length of
> INCR4/8/16/32/64/128/256.
> > When it is zero, means INCRx burst mode enabled, we can use one fixed
> burst length of 1/4/8/16/32/64/128/256 byte.
> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
> length the USB controller can support.
> > If we don't want to change the value of this register (use the default value),
> we don't need to add this property to usb node.
> 
> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
Maybe, I didn't describe it clearly. 
According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
I understand totally that when it is none-zero, we can use it for INCR burst mode. 
Then, when it is 0, how to select the INCRx value?

So, I think we still need two vaue to specify INCRBrstEna and INCRx burst type.

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Wednesday, January 04, 2017 5:24 AM
> To: Jerry Huang <jerry.huang@nxp.com>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> > Hi, Rob,
> >> -----Original Message-----
> >> From: Rob Herring [mailto:robh@kernel.org]
> >> Sent: Friday, December 23, 2016 2:45 AM
> >> To: Jerry Huang <jerry.huang@nxp.com>
> >> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> >> will.deacon@arm.com; linux@armlinux.org.uk;
> >> devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> >> linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> incr-burst- type-adjustment" for INCR burst type
> >>
> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > USB3.0
> >> DWC3.
> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> >> > Field
> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >> >
> >> > While enabling undefined length INCR burst type and INCR16 burst
> >> > type, get better write performance on NXP Layerscape platform:
> >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> >
> >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > ---
> >> > Changes in v3:
> >> >   - add new property for INCR burst in usb node.
> >> >
> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> >  4 files changed, 11 insertions(+)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > index e3e6983..8c405a3 100644
> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > @@ -55,6 +55,10 @@ Optional properties:
> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> >
> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> >> reallocated.
> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> >> GSBUSCFG0
> >> > +   register, undefined length INCR burst type enable and INCRx type.
> >> > +   First field is for undefined length INCR burst type enable or not.
> >> > +   Second field is for largest INCRx type enabled.
> >>
> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> If not, then just use the presence of the property to enable or not.
> > The first field is one switch.
> > When it is 1, means undefined length INCR burst type enabled, we can use
> any length less than or equal to the largest-enabled burst length of
> INCR4/8/16/32/64/128/256.
> > When it is zero, means INCRx burst mode enabled, we can use one fixed
> burst length of 1/4/8/16/32/64/128/256 byte.
> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
> length the USB controller can support.
> > If we don't want to change the value of this register (use the default value),
> we don't need to add this property to usb node.
> 
> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
Maybe, I didn't describe it clearly. 
According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
I understand totally that when it is none-zero, we can use it for INCR burst mode. 
Then, when it is 0, how to select the INCRx value?

So, I think we still need two vaue to specify INCRBrstEna and INCRx burst type.

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

Hi, Rob,

> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Wednesday, January 04, 2017 5:24 AM
> To: Jerry Huang <jerry.huang@nxp.com>
> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> > Hi, Rob,
> >> -----Original Message-----
> >> From: Rob Herring [mailto:robh at kernel.org]
> >> Sent: Friday, December 23, 2016 2:45 AM
> >> To: Jerry Huang <jerry.huang@nxp.com>
> >> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
> >> will.deacon at arm.com; linux at armlinux.org.uk;
> >> devicetree at vger.kernel.org; linux-usb at vger.kernel.org;
> >> linux-kernel at vger.kernel.org; linux-arm- kernel at lists.infradead.org
> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> incr-burst- type-adjustment" for INCR burst type
> >>
> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > USB3.0
> >> DWC3.
> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> >> > Field
> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
> >> >
> >> > While enabling undefined length INCR burst type and INCR16 burst
> >> > type, get better write performance on NXP Layerscape platform:
> >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> >
> >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > ---
> >> > Changes in v3:
> >> >   - add new property for INCR burst in usb node.
> >> >
> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> >  4 files changed, 11 insertions(+)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > index e3e6983..8c405a3 100644
> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > @@ -55,6 +55,10 @@ Optional properties:
> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> >
> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
> >> reallocated.
> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> >> GSBUSCFG0
> >> > +   register, undefined length INCR burst type enable and INCRx type.
> >> > +   First field is for undefined length INCR burst type enable or not.
> >> > +   Second field is for largest INCRx type enabled.
> >>
> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> If not, then just use the presence of the property to enable or not.
> > The first field is one switch.
> > When it is 1, means undefined length INCR burst type enabled, we can use
> any length less than or equal to the largest-enabled burst length of
> INCR4/8/16/32/64/128/256.
> > When it is zero, means INCRx burst mode enabled, we can use one fixed
> burst length of 1/4/8/16/32/64/128/256 byte.
> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
> length the USB controller can support.
> > If we don't want to change the value of this register (use the default value),
> we don't need to add this property to usb node.
> 
> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
Maybe, I didn't describe it clearly. 
According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
I understand totally that when it is none-zero, we can use it for INCR burst mode. 
Then, when it is 0, how to select the INCRx value?

So, I think we still need two vaue to specify INCRBrstEna and INCRx burst type.

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Jerry Huang
> Sent: Wednesday, January 04, 2017 10:25 AM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> Hi, Rob,
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Wednesday, January 04, 2017 5:24 AM
> > To: Jerry Huang <jerry.huang@nxp.com>
> > Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> > will.deacon@arm.com; linux@armlinux.org.uk;
> > devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
> > Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> > type-adjustment" for INCR burst type
> >
> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> wrote:
> > > Hi, Rob,
> > >> -----Original Message-----
> > >> From: Rob Herring [mailto:robh@kernel.org]
> > >> Sent: Friday, December 23, 2016 2:45 AM
> > >> To: Jerry Huang <jerry.huang@nxp.com>
> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
> > >> catalin.marinas@arm.com; will.deacon@arm.com;
> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> > >> kernel@lists.infradead.org
> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> > >> incr-burst- type-adjustment" for INCR burst type
> > >>
> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> > >> > USB3.0
> > >> DWC3.
> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> > >> > Field
> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> type.
> > >> >
> > >> > While enabling undefined length INCR burst type and INCR16 burst
> > >> > type, get better write performance on NXP Layerscape platform:
> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> > >> >
> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > >> > ---
> > >> > Changes in v3:
> > >> >   - add new property for INCR burst in usb node.
> > >> >
> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> > >> >  4 files changed, 11 insertions(+)
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > index e3e6983..8c405a3 100644
> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > @@ -55,6 +55,10 @@ Optional properties:
> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> > >> >
> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
> > >> > be
> > >> reallocated.
> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> > >> GSBUSCFG0
> > >> > +   register, undefined length INCR burst type enable and INCRx type.
> > >> > +   First field is for undefined length INCR burst type enable or not.
> > >> > +   Second field is for largest INCRx type enabled.
> > >>
> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> > >> If not, then just use the presence of the property to enable or not.
> > > The first field is one switch.
> > > When it is 1, means undefined length INCR burst type enabled, we can
> > > use
> > any length less than or equal to the largest-enabled burst length of
> > INCR4/8/16/32/64/128/256.
> > > When it is zero, means INCRx burst mode enabled, we can use one
> > > fixed
> > burst length of 1/4/8/16/32/64/128/256 byte.
> > > So, the 2nd field is used if the 1st is 0, we need to select one
> > > largest burst
> > length the USB controller can support.
> > > If we don't want to change the value of this register (use the
> > > default value),
> > we don't need to add this property to usb node.
> >
> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> Then, when it is 0, how to select the INCRx value?
> 
> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
> type.
Hi, Balbi, 
It seems there is no feedback for my comment, so these patches can be accepted?

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Jerry Huang
> Sent: Wednesday, January 04, 2017 10:25 AM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> Hi, Rob,
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh@kernel.org]
> > Sent: Wednesday, January 04, 2017 5:24 AM
> > To: Jerry Huang <jerry.huang@nxp.com>
> > Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> > will.deacon@arm.com; linux@armlinux.org.uk;
> > devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
> > Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> > type-adjustment" for INCR burst type
> >
> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> wrote:
> > > Hi, Rob,
> > >> -----Original Message-----
> > >> From: Rob Herring [mailto:robh@kernel.org]
> > >> Sent: Friday, December 23, 2016 2:45 AM
> > >> To: Jerry Huang <jerry.huang@nxp.com>
> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
> > >> catalin.marinas@arm.com; will.deacon@arm.com;
> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> > >> kernel@lists.infradead.org
> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> > >> incr-burst- type-adjustment" for INCR burst type
> > >>
> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> > >> > USB3.0
> > >> DWC3.
> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> > >> > Field
> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> type.
> > >> >
> > >> > While enabling undefined length INCR burst type and INCR16 burst
> > >> > type, get better write performance on NXP Layerscape platform:
> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> > >> >
> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > >> > ---
> > >> > Changes in v3:
> > >> >   - add new property for INCR burst in usb node.
> > >> >
> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> > >> >  4 files changed, 11 insertions(+)
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > index e3e6983..8c405a3 100644
> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > @@ -55,6 +55,10 @@ Optional properties:
> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> > >> >
> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
> > >> > be
> > >> reallocated.
> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> > >> GSBUSCFG0
> > >> > +   register, undefined length INCR burst type enable and INCRx type.
> > >> > +   First field is for undefined length INCR burst type enable or not.
> > >> > +   Second field is for largest INCRx type enabled.
> > >>
> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> > >> If not, then just use the presence of the property to enable or not.
> > > The first field is one switch.
> > > When it is 1, means undefined length INCR burst type enabled, we can
> > > use
> > any length less than or equal to the largest-enabled burst length of
> > INCR4/8/16/32/64/128/256.
> > > When it is zero, means INCRx burst mode enabled, we can use one
> > > fixed
> > burst length of 1/4/8/16/32/64/128/256 byte.
> > > So, the 2nd field is used if the 1st is 0, we need to select one
> > > largest burst
> > length the USB controller can support.
> > > If we don't want to change the value of this register (use the
> > > default value),
> > we don't need to add this property to usb node.
> >
> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> Then, when it is 0, how to select the INCRx value?
> 
> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
> type.
Hi, Balbi, 
It seems there is no feedback for my comment, so these patches can be accepted?

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Jerry Huang
> Sent: Wednesday, January 04, 2017 10:25 AM
> To: 'Rob Herring' <robh@kernel.org>
> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> Hi, Rob,
> 
> > -----Original Message-----
> > From: Rob Herring [mailto:robh at kernel.org]
> > Sent: Wednesday, January 04, 2017 5:24 AM
> > To: Jerry Huang <jerry.huang@nxp.com>
> > Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
> > will.deacon at arm.com; linux at armlinux.org.uk;
> > devicetree at vger.kernel.org; linux-usb at vger.kernel.org;
> > linux-kernel at vger.kernel.org; linux-arm- kernel at lists.infradead.org
> > Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> > type-adjustment" for INCR burst type
> >
> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> wrote:
> > > Hi, Rob,
> > >> -----Original Message-----
> > >> From: Rob Herring [mailto:robh at kernel.org]
> > >> Sent: Friday, December 23, 2016 2:45 AM
> > >> To: Jerry Huang <jerry.huang@nxp.com>
> > >> Cc: balbi at kernel.org; mark.rutland at arm.com;
> > >> catalin.marinas at arm.com; will.deacon at arm.com;
> > >> linux at armlinux.org.uk; devicetree at vger.kernel.org;
> > >> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> > >> kernel at lists.infradead.org
> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> > >> incr-burst- type-adjustment" for INCR burst type
> > >>
> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> > >> > USB3.0
> > >> DWC3.
> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
> > >> > Field
> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> type.
> > >> >
> > >> > While enabling undefined length INCR burst type and INCR16 burst
> > >> > type, get better write performance on NXP Layerscape platform:
> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> > >> >
> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> > >> > ---
> > >> > Changes in v3:
> > >> >   - add new property for INCR burst in usb node.
> > >> >
> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> > >> >  4 files changed, 11 insertions(+)
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > index e3e6983..8c405a3 100644
> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > >> > @@ -55,6 +55,10 @@ Optional properties:
> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> > >> >
> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
> > >> > be
> > >> reallocated.
> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
> > >> GSBUSCFG0
> > >> > +   register, undefined length INCR burst type enable and INCRx type.
> > >> > +   First field is for undefined length INCR burst type enable or not.
> > >> > +   Second field is for largest INCRx type enabled.
> > >>
> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> > >> If not, then just use the presence of the property to enable or not.
> > > The first field is one switch.
> > > When it is 1, means undefined length INCR burst type enabled, we can
> > > use
> > any length less than or equal to the largest-enabled burst length of
> > INCR4/8/16/32/64/128/256.
> > > When it is zero, means INCRx burst mode enabled, we can use one
> > > fixed
> > burst length of 1/4/8/16/32/64/128/256 byte.
> > > So, the 2nd field is used if the 1st is 0, we need to select one
> > > largest burst
> > length the USB controller can support.
> > > If we don't want to change the value of this register (use the
> > > default value),
> > we don't need to add this property to usb node.
> >
> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> Then, when it is 0, how to select the INCRx value?
> 
> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
> type.
Hi, Balbi, 
It seems there is no feedback for my comment, so these patches can be accepted?

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 4776 bytes --]


Hi,

Jerry Huang <jerry.huang@nxp.com> writes:
>> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
>> wrote:
>> > > Hi, Rob,
>> > >> -----Original Message-----
>> > >> From: Rob Herring [mailto:robh@kernel.org]
>> > >> Sent: Friday, December 23, 2016 2:45 AM
>> > >> To: Jerry Huang <jerry.huang@nxp.com>
>> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
>> > >> catalin.marinas@arm.com; will.deacon@arm.com;
>> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
>> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>> > >> kernel@lists.infradead.org
>> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> > >> incr-burst- type-adjustment" for INCR burst type
>> > >>
>> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> > >> > USB3.0
>> > >> DWC3.
>> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> > >> > Field
>> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
>> type.
>> > >> >
>> > >> > While enabling undefined length INCR burst type and INCR16 burst
>> > >> > type, get better write performance on NXP Layerscape platform:
>> > >> > around 3% improvement (from 364MB/s to 375MB/s).
>> > >> >
>> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > >> > ---
>> > >> > Changes in v3:
>> > >> >   - add new property for INCR burst in usb node.
>> > >> >
>> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> > >> >  4 files changed, 11 insertions(+)
>> > >> >
>> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > index e3e6983..8c405a3 100644
>> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > @@ -55,6 +55,10 @@ Optional properties:
>> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> > >> >
>> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
>> > >> > be
>> > >> reallocated.
>> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> > >> GSBUSCFG0
>> > >> > +   register, undefined length INCR burst type enable and INCRx type.
>> > >> > +   First field is for undefined length INCR burst type enable or not.
>> > >> > +   Second field is for largest INCRx type enabled.
>> > >>
>> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> > >> If not, then just use the presence of the property to enable or not.
>> > > The first field is one switch.
>> > > When it is 1, means undefined length INCR burst type enabled, we can
>> > > use
>> > any length less than or equal to the largest-enabled burst length of
>> > INCR4/8/16/32/64/128/256.
>> > > When it is zero, means INCRx burst mode enabled, we can use one
>> > > fixed
>> > burst length of 1/4/8/16/32/64/128/256 byte.
>> > > So, the 2nd field is used if the 1st is 0, we need to select one
>> > > largest burst
>> > length the USB controller can support.
>> > > If we don't want to change the value of this register (use the
>> > > default value),
>> > we don't need to add this property to usb node.
>> >
>> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
>> INCRx.
>> Maybe, I didn't describe it clearly.
>> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
>> burst mode, 1 means INCR burst mode.
>> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
>> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
>> Ad you mentioned, if we just use a single value with 0 meaning INCR and
>> 4/8/16/etc being INCRx.
>> I understand totally that when it is none-zero, we can use it for INCR burst
>> mode.
>> Then, when it is 0, how to select the INCRx value?
>> 
>> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
>> type.
> Hi, Balbi, 
> It seems there is no feedback for my comment, so these patches can be accepted?

probably not, we need to really understand what information we need so
it can be described properly. The last thing we want is unnecessary DT
properties.

It seems to me that we can extrapolate INCRBrstEna based on which burst
modes are enabled. If only 0 is passed, then that bit should be 1, if 0
and any other size is passed, then that bit should be 0, no?

-- 
balbi

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RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

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Hi,

Jerry Huang <jerry.huang@nxp.com> writes:
>> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
>> wrote:
>> > > Hi, Rob,
>> > >> -----Original Message-----
>> > >> From: Rob Herring [mailto:robh@kernel.org]
>> > >> Sent: Friday, December 23, 2016 2:45 AM
>> > >> To: Jerry Huang <jerry.huang@nxp.com>
>> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
>> > >> catalin.marinas@arm.com; will.deacon@arm.com;
>> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
>> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>> > >> kernel@lists.infradead.org
>> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> > >> incr-burst- type-adjustment" for INCR burst type
>> > >>
>> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> > >> > USB3.0
>> > >> DWC3.
>> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> > >> > Field
>> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
>> type.
>> > >> >
>> > >> > While enabling undefined length INCR burst type and INCR16 burst
>> > >> > type, get better write performance on NXP Layerscape platform:
>> > >> > around 3% improvement (from 364MB/s to 375MB/s).
>> > >> >
>> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > >> > ---
>> > >> > Changes in v3:
>> > >> >   - add new property for INCR burst in usb node.
>> > >> >
>> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> > >> >  4 files changed, 11 insertions(+)
>> > >> >
>> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > index e3e6983..8c405a3 100644
>> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > @@ -55,6 +55,10 @@ Optional properties:
>> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> > >> >
>> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
>> > >> > be
>> > >> reallocated.
>> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> > >> GSBUSCFG0
>> > >> > +   register, undefined length INCR burst type enable and INCRx type.
>> > >> > +   First field is for undefined length INCR burst type enable or not.
>> > >> > +   Second field is for largest INCRx type enabled.
>> > >>
>> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> > >> If not, then just use the presence of the property to enable or not.
>> > > The first field is one switch.
>> > > When it is 1, means undefined length INCR burst type enabled, we can
>> > > use
>> > any length less than or equal to the largest-enabled burst length of
>> > INCR4/8/16/32/64/128/256.
>> > > When it is zero, means INCRx burst mode enabled, we can use one
>> > > fixed
>> > burst length of 1/4/8/16/32/64/128/256 byte.
>> > > So, the 2nd field is used if the 1st is 0, we need to select one
>> > > largest burst
>> > length the USB controller can support.
>> > > If we don't want to change the value of this register (use the
>> > > default value),
>> > we don't need to add this property to usb node.
>> >
>> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
>> INCRx.
>> Maybe, I didn't describe it clearly.
>> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
>> burst mode, 1 means INCR burst mode.
>> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
>> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
>> Ad you mentioned, if we just use a single value with 0 meaning INCR and
>> 4/8/16/etc being INCRx.
>> I understand totally that when it is none-zero, we can use it for INCR burst
>> mode.
>> Then, when it is 0, how to select the INCRx value?
>> 
>> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
>> type.
> Hi, Balbi, 
> It seems there is no feedback for my comment, so these patches can be accepted?

probably not, we need to really understand what information we need so
it can be described properly. The last thing we want is unnecessary DT
properties.

It seems to me that we can extrapolate INCRBrstEna based on which burst
modes are enabled. If only 0 is passed, then that bit should be 1, if 0
and any other size is passed, then that bit should be 0, no?

-- 
balbi

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[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

Hi,

Jerry Huang <jerry.huang@nxp.com> writes:
>> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
>> wrote:
>> > > Hi, Rob,
>> > >> -----Original Message-----
>> > >> From: Rob Herring [mailto:robh at kernel.org]
>> > >> Sent: Friday, December 23, 2016 2:45 AM
>> > >> To: Jerry Huang <jerry.huang@nxp.com>
>> > >> Cc: balbi at kernel.org; mark.rutland at arm.com;
>> > >> catalin.marinas at arm.com; will.deacon at arm.com;
>> > >> linux at armlinux.org.uk; devicetree at vger.kernel.org;
>> > >> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
>> > >> kernel at lists.infradead.org
>> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> > >> incr-burst- type-adjustment" for INCR burst type
>> > >>
>> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> > >> > USB3.0
>> > >> DWC3.
>> > >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> > >> > Field
>> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
>> type.
>> > >> >
>> > >> > While enabling undefined length INCR burst type and INCR16 burst
>> > >> > type, get better write performance on NXP Layerscape platform:
>> > >> > around 3% improvement (from 364MB/s to 375MB/s).
>> > >> >
>> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> > >> > ---
>> > >> > Changes in v3:
>> > >> >   - add new property for INCR burst in usb node.
>> > >> >
>> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> > >> >  4 files changed, 11 insertions(+)
>> > >> >
>> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > index e3e6983..8c405a3 100644
>> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> > >> > @@ -55,6 +55,10 @@ Optional properties:
>> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> > >> >
>> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to
>> > >> > be
>> > >> reallocated.
>> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> > >> GSBUSCFG0
>> > >> > +   register, undefined length INCR burst type enable and INCRx type.
>> > >> > +   First field is for undefined length INCR burst type enable or not.
>> > >> > +   Second field is for largest INCRx type enabled.
>> > >>
>> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> > >> If not, then just use the presence of the property to enable or not.
>> > > The first field is one switch.
>> > > When it is 1, means undefined length INCR burst type enabled, we can
>> > > use
>> > any length less than or equal to the largest-enabled burst length of
>> > INCR4/8/16/32/64/128/256.
>> > > When it is zero, means INCRx burst mode enabled, we can use one
>> > > fixed
>> > burst length of 1/4/8/16/32/64/128/256 byte.
>> > > So, the 2nd field is used if the 1st is 0, we need to select one
>> > > largest burst
>> > length the USB controller can support.
>> > > If we don't want to change the value of this register (use the
>> > > default value),
>> > we don't need to add this property to usb node.
>> >
>> > Just make this a single value with 0 meaning INCR and 4/8/16/etc being
>> INCRx.
>> Maybe, I didn't describe it clearly.
>> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
>> burst mode, 1 means INCR burst mode.
>> Regardless of the value of INCRBrstEna [bit0], we need to modify the other
>> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
>> Ad you mentioned, if we just use a single value with 0 meaning INCR and
>> 4/8/16/etc being INCRx.
>> I understand totally that when it is none-zero, we can use it for INCR burst
>> mode.
>> Then, when it is 0, how to select the INCRx value?
>> 
>> So, I think we still need two vaue to specify INCRBrstEna and INCRx burst
>> type.
> Hi, Balbi, 
> It seems there is no feedback for my comment, so these patches can be accepted?

probably not, we need to really understand what information we need so
it can be described properly. The last thing we want is unnecessary DT
properties.

It seems to me that we can extrapolate INCRBrstEna based on which burst
modes are enabled. If only 0 is passed, then that bit should be 1, if 0
and any other size is passed, then that bit should be 0, no?

-- 
balbi
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RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi@kernel.org]
> Sent: Monday, January 16, 2017 4:50 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> >> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> >> wrote:
> >> > > Hi, Rob,
> >> > >> -----Original Message-----
> >> > >> From: Rob Herring [mailto:robh@kernel.org]
> >> > >> Sent: Friday, December 23, 2016 2:45 AM
> >> > >> To: Jerry Huang <jerry.huang@nxp.com>
> >> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
> >> > >> catalin.marinas@arm.com; will.deacon@arm.com;
> >> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> >> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> > >> linux-arm- kernel@lists.infradead.org
> >> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> > >> incr-burst- type-adjustment" for INCR burst type
> >> > >>
> >> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > >> > USB3.0
> >> > >> DWC3.
> >> > >> > Field "x": 1/0 - undefined length INCR burst type enable or
> >> > >> > not; Field
> >> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> >> type.
> >> > >> >
> >> > >> > While enabling undefined length INCR burst type and INCR16
> >> > >> > burst type, get better write performance on NXP Layerscape
> platform:
> >> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> > >> >
> >> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > >> > ---
> >> > >> > Changes in v3:
> >> > >> >   - add new property for INCR burst in usb node.
> >> > >> >
> >> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> > >> >  4 files changed, 11 insertions(+)
> >> > >> >
> >> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > index e3e6983..8c405a3 100644
> >> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > @@ -55,6 +55,10 @@ Optional properties:
> >> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> > >> >
> >> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has*
> >> > >> > to be
> >> > >> reallocated.
> >> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type
> >> > >> > + of
> >> > >> GSBUSCFG0
> >> > >> > +   register, undefined length INCR burst type enable and INCRx
> type.
> >> > >> > +   First field is for undefined length INCR burst type enable or not.
> >> > >> > +   Second field is for largest INCRx type enabled.
> >> > >>
> >> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> > >> If not, then just use the presence of the property to enable or not.
> >> > > The first field is one switch.
> >> > > When it is 1, means undefined length INCR burst type enabled, we
> >> > > can use
> >> > any length less than or equal to the largest-enabled burst length
> >> > of INCR4/8/16/32/64/128/256.
> >> > > When it is zero, means INCRx burst mode enabled, we can use one
> >> > > fixed
> >> > burst length of 1/4/8/16/32/64/128/256 byte.
> >> > > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > > largest burst
> >> > length the USB controller can support.
> >> > > If we don't want to change the value of this register (use the
> >> > > default value),
> >> > we don't need to add this property to usb node.
> >> >
> >> > Just make this a single value with 0 meaning INCR and 4/8/16/etc
> >> > being
> >> INCRx.
> >> Maybe, I didn't describe it clearly.
> >> According to DWC3 spec, the value "0" of field INCRBrstEna means
> >> INCRx burst mode, 1 means INCR burst mode.
> >> Regardless of the value of INCRBrstEna [bit0], we need to modify the
> >> other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform
> supported.
> >> Ad you mentioned, if we just use a single value with 0 meaning INCR
> >> and 4/8/16/etc being INCRx.
> >> I understand totally that when it is none-zero, we can use it for
> >> INCR burst mode.
> >> Then, when it is 0, how to select the INCRx value?
> >>
> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
> >> burst type.
> > Hi, Balbi,
> > It seems there is no feedback for my comment, so these patches can be
> accepted?
> 
> probably not, we need to really understand what information we need so it
> can be described properly. The last thing we want is unnecessary DT
> properties.
> 
> It seems to me that we can extrapolate INCRBrstEna based on which burst
> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
> other size is passed, then that bit should be 0, no?
Hi, Balbi,
Below is the definition for this property,
snps,incr-burst-type-adjustment = <x>, <y>
x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
    0 - INCRX burst mode (not enable INCRBrstEna)
    1 - INCR (undefined length) burst mode (enable INCRBrstEna)
y: the burst length

1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear it) , we select one of INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y")to set the fix burst length controller supported.
For example:
snps,incr-burst-type-adjustment = <0>, <16>
driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type Enabled), controller will use INCR16 (with 16 bytes) to transfer data.

2> if x = 1: means INCRBrstEna enabled, we select one of INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y") to set the burst length, and controller will use any length less than or equal to that we selected.
For example:
snps,incr-burst-type-adjustment = <1>, <32>
driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type Enabled), controller will use any burst length less than (such as 4, 8, 16 byte) or equal to 32 byte to transfer data.

Therefore, I think this two fileds are needed. Do you think about it?

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi@kernel.org]
> Sent: Monday, January 16, 2017 4:50 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> >> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> >> wrote:
> >> > > Hi, Rob,
> >> > >> -----Original Message-----
> >> > >> From: Rob Herring [mailto:robh@kernel.org]
> >> > >> Sent: Friday, December 23, 2016 2:45 AM
> >> > >> To: Jerry Huang <jerry.huang@nxp.com>
> >> > >> Cc: balbi@kernel.org; mark.rutland@arm.com;
> >> > >> catalin.marinas@arm.com; will.deacon@arm.com;
> >> > >> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> >> > >> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org;
> >> > >> linux-arm- kernel@lists.infradead.org
> >> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> > >> incr-burst- type-adjustment" for INCR burst type
> >> > >>
> >> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > >> > USB3.0
> >> > >> DWC3.
> >> > >> > Field "x": 1/0 - undefined length INCR burst type enable or
> >> > >> > not; Field
> >> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> >> type.
> >> > >> >
> >> > >> > While enabling undefined length INCR burst type and INCR16
> >> > >> > burst type, get better write performance on NXP Layerscape
> platform:
> >> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> > >> >
> >> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > >> > ---
> >> > >> > Changes in v3:
> >> > >> >   - add new property for INCR burst in usb node.
> >> > >> >
> >> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> > >> >  4 files changed, 11 insertions(+)
> >> > >> >
> >> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > index e3e6983..8c405a3 100644
> >> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > @@ -55,6 +55,10 @@ Optional properties:
> >> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> > >> >
> >> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has*
> >> > >> > to be
> >> > >> reallocated.
> >> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type
> >> > >> > + of
> >> > >> GSBUSCFG0
> >> > >> > +   register, undefined length INCR burst type enable and INCRx
> type.
> >> > >> > +   First field is for undefined length INCR burst type enable or not.
> >> > >> > +   Second field is for largest INCRx type enabled.
> >> > >>
> >> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> > >> If not, then just use the presence of the property to enable or not.
> >> > > The first field is one switch.
> >> > > When it is 1, means undefined length INCR burst type enabled, we
> >> > > can use
> >> > any length less than or equal to the largest-enabled burst length
> >> > of INCR4/8/16/32/64/128/256.
> >> > > When it is zero, means INCRx burst mode enabled, we can use one
> >> > > fixed
> >> > burst length of 1/4/8/16/32/64/128/256 byte.
> >> > > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > > largest burst
> >> > length the USB controller can support.
> >> > > If we don't want to change the value of this register (use the
> >> > > default value),
> >> > we don't need to add this property to usb node.
> >> >
> >> > Just make this a single value with 0 meaning INCR and 4/8/16/etc
> >> > being
> >> INCRx.
> >> Maybe, I didn't describe it clearly.
> >> According to DWC3 spec, the value "0" of field INCRBrstEna means
> >> INCRx burst mode, 1 means INCR burst mode.
> >> Regardless of the value of INCRBrstEna [bit0], we need to modify the
> >> other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform
> supported.
> >> Ad you mentioned, if we just use a single value with 0 meaning INCR
> >> and 4/8/16/etc being INCRx.
> >> I understand totally that when it is none-zero, we can use it for
> >> INCR burst mode.
> >> Then, when it is 0, how to select the INCRx value?
> >>
> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
> >> burst type.
> > Hi, Balbi,
> > It seems there is no feedback for my comment, so these patches can be
> accepted?
> 
> probably not, we need to really understand what information we need so it
> can be described properly. The last thing we want is unnecessary DT
> properties.
> 
> It seems to me that we can extrapolate INCRBrstEna based on which burst
> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
> other size is passed, then that bit should be 0, no?
Hi, Balbi,
Below is the definition for this property,
snps,incr-burst-type-adjustment = <x>, <y>
x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
    0 - INCRX burst mode (not enable INCRBrstEna)
    1 - INCR (undefined length) burst mode (enable INCRBrstEna)
y: the burst length

1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear it) , we select one of INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y")to set the fix burst length controller supported.
For example:
snps,incr-burst-type-adjustment = <0>, <16>
driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type Enabled), controller will use INCR16 (with 16 bytes) to transfer data.

2> if x = 1: means INCRBrstEna enabled, we select one of INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y") to set the burst length, and controller will use any length less than or equal to that we selected.
For example:
snps,incr-burst-type-adjustment = <1>, <32>
driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type Enabled), controller will use any burst length less than (such as 4, 8, 16 byte) or equal to 32 byte to transfer data.

Therefore, I think this two fileds are needed. Do you think about it?

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi at kernel.org]
> Sent: Monday, January 16, 2017 4:50 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland at arm.com; catalin.marinas at arm.com;
> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> >> > On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com>
> >> wrote:
> >> > > Hi, Rob,
> >> > >> -----Original Message-----
> >> > >> From: Rob Herring [mailto:robh at kernel.org]
> >> > >> Sent: Friday, December 23, 2016 2:45 AM
> >> > >> To: Jerry Huang <jerry.huang@nxp.com>
> >> > >> Cc: balbi at kernel.org; mark.rutland at arm.com;
> >> > >> catalin.marinas at arm.com; will.deacon at arm.com;
> >> > >> linux at armlinux.org.uk; devicetree at vger.kernel.org;
> >> > >> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org;
> >> > >> linux-arm- kernel at lists.infradead.org
> >> > >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
> >> > >> incr-burst- type-adjustment" for INCR burst type
> >> > >>
> >> > >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> >> > >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
> >> > >> > USB3.0
> >> > >> DWC3.
> >> > >> > Field "x": 1/0 - undefined length INCR burst type enable or
> >> > >> > not; Field
> >> > >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst
> >> type.
> >> > >> >
> >> > >> > While enabling undefined length INCR burst type and INCR16
> >> > >> > burst type, get better write performance on NXP Layerscape
> platform:
> >> > >> > around 3% improvement (from 364MB/s to 375MB/s).
> >> > >> >
> >> > >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> >> > >> > ---
> >> > >> > Changes in v3:
> >> > >> >   - add new property for INCR burst in usb node.
> >> > >> >
> >> > >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
> >> > >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
> >> > >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
> >> > >> >  4 files changed, 11 insertions(+)
> >> > >> >
> >> > >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > index e3e6983..8c405a3 100644
> >> > >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> >> > >> > @@ -55,6 +55,10 @@ Optional properties:
> >> > >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
> >> > >> >
> >> > >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has*
> >> > >> > to be
> >> > >> reallocated.
> >> > >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type
> >> > >> > + of
> >> > >> GSBUSCFG0
> >> > >> > +   register, undefined length INCR burst type enable and INCRx
> type.
> >> > >> > +   First field is for undefined length INCR burst type enable or not.
> >> > >> > +   Second field is for largest INCRx type enabled.
> >> > >>
> >> > >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> > >> If not, then just use the presence of the property to enable or not.
> >> > > The first field is one switch.
> >> > > When it is 1, means undefined length INCR burst type enabled, we
> >> > > can use
> >> > any length less than or equal to the largest-enabled burst length
> >> > of INCR4/8/16/32/64/128/256.
> >> > > When it is zero, means INCRx burst mode enabled, we can use one
> >> > > fixed
> >> > burst length of 1/4/8/16/32/64/128/256 byte.
> >> > > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > > largest burst
> >> > length the USB controller can support.
> >> > > If we don't want to change the value of this register (use the
> >> > > default value),
> >> > we don't need to add this property to usb node.
> >> >
> >> > Just make this a single value with 0 meaning INCR and 4/8/16/etc
> >> > being
> >> INCRx.
> >> Maybe, I didn't describe it clearly.
> >> According to DWC3 spec, the value "0" of field INCRBrstEna means
> >> INCRx burst mode, 1 means INCR burst mode.
> >> Regardless of the value of INCRBrstEna [bit0], we need to modify the
> >> other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform
> supported.
> >> Ad you mentioned, if we just use a single value with 0 meaning INCR
> >> and 4/8/16/etc being INCRx.
> >> I understand totally that when it is none-zero, we can use it for
> >> INCR burst mode.
> >> Then, when it is 0, how to select the INCRx value?
> >>
> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
> >> burst type.
> > Hi, Balbi,
> > It seems there is no feedback for my comment, so these patches can be
> accepted?
> 
> probably not, we need to really understand what information we need so it
> can be described properly. The last thing we want is unnecessary DT
> properties.
> 
> It seems to me that we can extrapolate INCRBrstEna based on which burst
> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
> other size is passed, then that bit should be 0, no?
Hi, Balbi,
Below is the definition for this property,
snps,incr-burst-type-adjustment = <x>, <y>
x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
    0 - INCRX burst mode (not enable INCRBrstEna)
    1 - INCR (undefined length) burst mode (enable INCRBrstEna)
y: the burst length

1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear it) , we select one of INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y")to set the fix burst length controller supported.
For example:
snps,incr-burst-type-adjustment = <0>, <16>
driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type Enabled), controller will use INCR16 (with 16 bytes) to transfer data.

2> if x = 1: means INCRBrstEna enabled, we select one of INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value through "y") to set the burst length, and controller will use any length less than or equal to that we selected.
For example:
snps,incr-burst-type-adjustment = <1>, <32>
driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type Enabled), controller will use any burst length less than (such as 4, 8, 16 byte) or equal to 32 byte to transfer data.

Therefore, I think this two fileds are needed. Do you think about it?

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2491 bytes --]


Hi,

Jerry Huang <jerry.huang@nxp.com> writes:

<snip>

>> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
>> >> burst type.
>> > Hi, Balbi,
>> > It seems there is no feedback for my comment, so these patches can be
>> accepted?
>> 
>> probably not, we need to really understand what information we need so it
>> can be described properly. The last thing we want is unnecessary DT
>> properties.
>> 
>> It seems to me that we can extrapolate INCRBrstEna based on which burst
>> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
>> other size is passed, then that bit should be 0, no?
> Hi, Balbi,
> Below is the definition for this property,
> snps,incr-burst-type-adjustment = <x>, <y>
> x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
>     0 - INCRX burst mode (not enable INCRBrstEna)
>     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> y: the burst length
>
> 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> it) , we select one of
> INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> value through "y")to set the fix burst length controller supported.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <0>, <16>
>
> driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
>
> 2> if x = 1: means INCRBrstEna enabled, we select one of
> INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> through "y") to set the burst length, and controller will use any
> length less than or equal to that we selected.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <1>, <32>
>
> driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> Enabled), controller will use any burst length less than (such as 4,
> 8, 16 byte) or equal to 32 byte to transfer data.
>
> Therefore, I think this two fileds are needed. Do you think about it?

no, I don't think two values are needed, because first value can be
extrapolated from the second. Something like this:

	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;

This is basically telling us that we can support anything in this
list. So INCRBrstEna should be set to 1.

If DT, on the other hand, says:

	snps,incr-burst-type-adjustment = <32>;

this means that we can only support INCR32, so INCRBrstEna should be
cleared to 0.

-- 
balbi

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RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2491 bytes --]


Hi,

Jerry Huang <jerry.huang@nxp.com> writes:

<snip>

>> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
>> >> burst type.
>> > Hi, Balbi,
>> > It seems there is no feedback for my comment, so these patches can be
>> accepted?
>> 
>> probably not, we need to really understand what information we need so it
>> can be described properly. The last thing we want is unnecessary DT
>> properties.
>> 
>> It seems to me that we can extrapolate INCRBrstEna based on which burst
>> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
>> other size is passed, then that bit should be 0, no?
> Hi, Balbi,
> Below is the definition for this property,
> snps,incr-burst-type-adjustment = <x>, <y>
> x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
>     0 - INCRX burst mode (not enable INCRBrstEna)
>     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> y: the burst length
>
> 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> it) , we select one of
> INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> value through "y")to set the fix burst length controller supported.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <0>, <16>
>
> driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
>
> 2> if x = 1: means INCRBrstEna enabled, we select one of
> INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> through "y") to set the burst length, and controller will use any
> length less than or equal to that we selected.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <1>, <32>
>
> driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> Enabled), controller will use any burst length less than (such as 4,
> 8, 16 byte) or equal to 32 byte to transfer data.
>
> Therefore, I think this two fileds are needed. Do you think about it?

no, I don't think two values are needed, because first value can be
extrapolated from the second. Something like this:

	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;

This is basically telling us that we can support anything in this
list. So INCRBrstEna should be set to 1.

If DT, on the other hand, says:

	snps,incr-burst-type-adjustment = <32>;

this means that we can only support INCR32, so INCRBrstEna should be
cleared to 0.

-- 
balbi

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[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Felipe Balbi]

Hi,

Jerry Huang <jerry.huang@nxp.com> writes:

<snip>

>> >> So, I think we still need two vaue to specify INCRBrstEna and INCRx
>> >> burst type.
>> > Hi, Balbi,
>> > It seems there is no feedback for my comment, so these patches can be
>> accepted?
>> 
>> probably not, we need to really understand what information we need so it
>> can be described properly. The last thing we want is unnecessary DT
>> properties.
>> 
>> It seems to me that we can extrapolate INCRBrstEna based on which burst
>> modes are enabled. If only 0 is passed, then that bit should be 1, if 0 and any
>> other size is passed, then that bit should be 0, no?
> Hi, Balbi,
> Below is the definition for this property,
> snps,incr-burst-type-adjustment = <x>, <y>
> x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
>     0 - INCRX burst mode (not enable INCRBrstEna)
>     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> y: the burst length
>
> 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> it) , we select one of
> INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> value through "y")to set the fix burst length controller supported.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <0>, <16>
>
> driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
>
> 2> if x = 1: means INCRBrstEna enabled, we select one of
> INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> through "y") to set the burst length, and controller will use any
> length less than or equal to that we selected.
>
> For example:
>
> 	snps,incr-burst-type-adjustment = <1>, <32>
>
> driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> Enabled), controller will use any burst length less than (such as 4,
> 8, 16 byte) or equal to 32 byte to transfer data.
>
> Therefore, I think this two fileds are needed. Do you think about it?

no, I don't think two values are needed, because first value can be
extrapolated from the second. Something like this:

	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;

This is basically telling us that we can support anything in this
list. So INCRBrstEna should be set to 1.

If DT, on the other hand, says:

	snps,incr-burst-type-adjustment = <32>;

this means that we can only support INCR32, so INCRBrstEna should be
cleared to 0.

-- 
balbi
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RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi@kernel.org]
> Sent: Tuesday, January 17, 2017 6:45 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> 
> <snip>
> 
> >> >> So, I think we still need two vaue to specify INCRBrstEna and
> >> >> INCRx burst type.
> >> > Hi, Balbi,
> >> > It seems there is no feedback for my comment, so these patches can
> >> > be
> >> accepted?
> >>
> >> probably not, we need to really understand what information we need
> >> so it can be described properly. The last thing we want is
> >> unnecessary DT properties.
> >>
> >> It seems to me that we can extrapolate INCRBrstEna based on which
> >> burst modes are enabled. If only 0 is passed, then that bit should be
> >> 1, if 0 and any other size is passed, then that bit should be 0, no?
> > Hi, Balbi,
> > Below is the definition for this property,
> > snps,incr-burst-type-adjustment = <x>, <y>
> > x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
> >     0 - INCRX burst mode (not enable INCRBrstEna)
> >     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> > y: the burst length
> >
> > 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> > it) , we select one of
> > INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> > value through "y")to set the fix burst length controller supported.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <0>, <16>
> >
> > driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> > Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
> >
> > 2> if x = 1: means INCRBrstEna enabled, we select one of
> > INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> > through "y") to set the burst length, and controller will use any
> > length less than or equal to that we selected.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <1>, <32>
> >
> > driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> > Enabled), controller will use any burst length less than (such as 4,
> > 8, 16 byte) or equal to 32 byte to transfer data.
> >
> > Therefore, I think this two fileds are needed. Do you think about it?
> 
> no, I don't think two values are needed, because first value can be
> extrapolated from the second. Something like this:
> 
> 	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;
> 
> This is basically telling us that we can support anything in this list. So
> INCRBrstEna should be set to 1.
> 
> If DT, on the other hand, says:
> 
> 	snps,incr-burst-type-adjustment = <32>;
> 
> this means that we can only support INCR32, so INCRBrstEna should be
> cleared to 0.
Got it, I will try this mode.
Thanks a lot, Balbi,

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi@kernel.org]
> Sent: Tuesday, January 17, 2017 6:45 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> 
> <snip>
> 
> >> >> So, I think we still need two vaue to specify INCRBrstEna and
> >> >> INCRx burst type.
> >> > Hi, Balbi,
> >> > It seems there is no feedback for my comment, so these patches can
> >> > be
> >> accepted?
> >>
> >> probably not, we need to really understand what information we need
> >> so it can be described properly. The last thing we want is
> >> unnecessary DT properties.
> >>
> >> It seems to me that we can extrapolate INCRBrstEna based on which
> >> burst modes are enabled. If only 0 is passed, then that bit should be
> >> 1, if 0 and any other size is passed, then that bit should be 0, no?
> > Hi, Balbi,
> > Below is the definition for this property,
> > snps,incr-burst-type-adjustment = <x>, <y>
> > x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
> >     0 - INCRX burst mode (not enable INCRBrstEna)
> >     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> > y: the burst length
> >
> > 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> > it) , we select one of
> > INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> > value through "y")to set the fix burst length controller supported.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <0>, <16>
> >
> > driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> > Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
> >
> > 2> if x = 1: means INCRBrstEna enabled, we select one of
> > INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> > through "y") to set the burst length, and controller will use any
> > length less than or equal to that we selected.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <1>, <32>
> >
> > driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> > Enabled), controller will use any burst length less than (such as 4,
> > 8, 16 byte) or equal to 32 byte to transfer data.
> >
> > Therefore, I think this two fileds are needed. Do you think about it?
> 
> no, I don't think two values are needed, because first value can be
> extrapolated from the second. Something like this:
> 
> 	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;
> 
> This is basically telling us that we can support anything in this list. So
> INCRBrstEna should be set to 1.
> 
> If DT, on the other hand, says:
> 
> 	snps,incr-burst-type-adjustment = <32>;
> 
> this means that we can only support INCR32, so INCRBrstEna should be
> cleared to 0.
Got it, I will try this mode.
Thanks a lot, Balbi,

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> -----Original Message-----
> From: Felipe Balbi [mailto:balbi at kernel.org]
> Sent: Tuesday, January 17, 2017 6:45 PM
> To: Jerry Huang <jerry.huang@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: mark.rutland at arm.com; catalin.marinas at arm.com;
> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
> type-adjustment" for INCR burst type
> 
> 
> Hi,
> 
> Jerry Huang <jerry.huang@nxp.com> writes:
> 
> <snip>
> 
> >> >> So, I think we still need two vaue to specify INCRBrstEna and
> >> >> INCRx burst type.
> >> > Hi, Balbi,
> >> > It seems there is no feedback for my comment, so these patches can
> >> > be
> >> accepted?
> >>
> >> probably not, we need to really understand what information we need
> >> so it can be described properly. The last thing we want is
> >> unnecessary DT properties.
> >>
> >> It seems to me that we can extrapolate INCRBrstEna based on which
> >> burst modes are enabled. If only 0 is passed, then that bit should be
> >> 1, if 0 and any other size is passed, then that bit should be 0, no?
> > Hi, Balbi,
> > Below is the definition for this property,
> > snps,incr-burst-type-adjustment = <x>, <y>
> > x: Undefined Length INCR Burst Type Enable (INCRBrstEna)
> >     0 - INCRX burst mode (not enable INCRBrstEna)
> >     1 - INCR (undefined length) burst mode (enable INCRBrstEna)
> > y: the burst length
> >
> > 1> if x = 0: means INCRBrstEna not enabled, set bit0 to zero (or clear
> > it) , we select one of
> > INCR1/INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this
> > value through "y")to set the fix burst length controller supported.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <0>, <16>
> >
> > driver will set bit0 to zero and set bit3 to 1 (INCR16 Burst Type
> > Enabled), controller will use INCR16 (with 16 bytes) to transfer data.
> >
> > 2> if x = 1: means INCRBrstEna enabled, we select one of
> > INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 (pass this value
> > through "y") to set the burst length, and controller will use any
> > length less than or equal to that we selected.
> >
> > For example:
> >
> > 	snps,incr-burst-type-adjustment = <1>, <32>
> >
> > driver will set bit0 to 1 and set bit4 to 1 (INCR32 Burst Type
> > Enabled), controller will use any burst length less than (such as 4,
> > 8, 16 byte) or equal to 32 byte to transfer data.
> >
> > Therefore, I think this two fileds are needed. Do you think about it?
> 
> no, I don't think two values are needed, because first value can be
> extrapolated from the second. Something like this:
> 
> 	snps,incr-burst-type-adjustment = <4>, <8>, <16>, <32>;
> 
> This is basically telling us that we can support anything in this list. So
> INCRBrstEna should be set to 1.
> 
> If DT, on the other hand, says:
> 
> 	snps,incr-burst-type-adjustment = <32>;
> 
> this means that we can only support INCR32, so INCRBrstEna should be
> cleared to 0.
Got it, I will try this mode.
Thanks a lot, Balbi,

Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Tue, Jan 3, 2017 at 8:24 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> Hi, Rob,
>
>> -----Original Message-----
>> From: Rob Herring [mailto:robh@kernel.org]
>> Sent: Wednesday, January 04, 2017 5:24 AM
>> To: Jerry Huang <jerry.huang@nxp.com>
>> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
>> will.deacon@arm.com; linux@armlinux.org.uk; devicetree@vger.kernel.org;
>> linux-usb@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
>> > Hi, Rob,
>> >> -----Original Message-----
>> >> From: Rob Herring [mailto:robh@kernel.org]
>> >> Sent: Friday, December 23, 2016 2:45 AM
>> >> To: Jerry Huang <jerry.huang@nxp.com>
>> >> Cc: balbi@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
>> >> will.deacon@arm.com; linux@armlinux.org.uk;
>> >> devicetree@vger.kernel.org; linux-usb@vger.kernel.org;
>> >> linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org
>> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> >> incr-burst- type-adjustment" for INCR burst type
>> >>
>> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> >> > USB3.0
>> >> DWC3.
>> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> >> > Field
>> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >> >
>> >> > While enabling undefined length INCR burst type and INCR16 burst
>> >> > type, get better write performance on NXP Layerscape platform:
>> >> > around 3% improvement (from 364MB/s to 375MB/s).
>> >> >
>> >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> >> > ---
>> >> > Changes in v3:
>> >> >   - add new property for INCR burst in usb node.
>> >> >
>> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >> >  4 files changed, 11 insertions(+)
>> >> >
>> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > index e3e6983..8c405a3 100644
>> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > @@ -55,6 +55,10 @@ Optional properties:
>> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >> >
>> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> >> reallocated.
>> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> >> GSBUSCFG0
>> >> > +   register, undefined length INCR burst type enable and INCRx type.
>> >> > +   First field is for undefined length INCR burst type enable or not.
>> >> > +   Second field is for largest INCRx type enabled.
>> >>
>> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> >> If not, then just use the presence of the property to enable or not.
>> > The first field is one switch.
>> > When it is 1, means undefined length INCR burst type enabled, we can use
>> any length less than or equal to the largest-enabled burst length of
>> INCR4/8/16/32/64/128/256.
>> > When it is zero, means INCRx burst mode enabled, we can use one fixed
>> burst length of 1/4/8/16/32/64/128/256 byte.
>> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
>> length the USB controller can support.
>> > If we don't want to change the value of this register (use the default value),
>> we don't need to add this property to usb node.
>>
>> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst mode.
> Then, when it is 0, how to select the INCRx value?

What I mean is:
<no prop> - burst disabled
0 - INCR burst. INCR is undefined length burst IIRC.
4/8/16/etc. - INCR4/INCR8/INCR16/etc.

What case does this not cover?

Rob

Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Tue, Jan 3, 2017 at 8:24 PM, Jerry Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org> wrote:
> Hi, Rob,
>
>> -----Original Message-----
>> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
>> Sent: Wednesday, January 04, 2017 5:24 AM
>> To: Jerry Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
>> Cc: balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org;
>> will.deacon-5wv7dgnIgG8@public.gmane.org; linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
>> linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
>> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org> wrote:
>> > Hi, Rob,
>> >> -----Original Message-----
>> >> From: Rob Herring [mailto:robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
>> >> Sent: Friday, December 23, 2016 2:45 AM
>> >> To: Jerry Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
>> >> Cc: balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; catalin.marinas-5wv7dgnIgG8@public.gmane.org;
>> >> will.deacon-5wv7dgnIgG8@public.gmane.org; linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org;
>> >> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
>> >> linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm- kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> >> incr-burst- type-adjustment" for INCR burst type
>> >>
>> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> >> > USB3.0
>> >> DWC3.
>> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> >> > Field
>> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >> >
>> >> > While enabling undefined length INCR burst type and INCR16 burst
>> >> > type, get better write performance on NXP Layerscape platform:
>> >> > around 3% improvement (from 364MB/s to 375MB/s).
>> >> >
>> >> > Signed-off-by: Changming Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
>> >> > ---
>> >> > Changes in v3:
>> >> >   - add new property for INCR burst in usb node.
>> >> >
>> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >> >  4 files changed, 11 insertions(+)
>> >> >
>> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > index e3e6983..8c405a3 100644
>> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > @@ -55,6 +55,10 @@ Optional properties:
>> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >> >
>> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> >> reallocated.
>> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> >> GSBUSCFG0
>> >> > +   register, undefined length INCR burst type enable and INCRx type.
>> >> > +   First field is for undefined length INCR burst type enable or not.
>> >> > +   Second field is for largest INCRx type enabled.
>> >>
>> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> >> If not, then just use the presence of the property to enable or not.
>> > The first field is one switch.
>> > When it is 1, means undefined length INCR burst type enabled, we can use
>> any length less than or equal to the largest-enabled burst length of
>> INCR4/8/16/32/64/128/256.
>> > When it is zero, means INCRx burst mode enabled, we can use one fixed
>> burst length of 1/4/8/16/32/64/128/256 byte.
>> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
>> length the USB controller can support.
>> > If we don't want to change the value of this register (use the default value),
>> we don't need to add this property to usb node.
>>
>> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst mode.
> Then, when it is 0, how to select the INCRx value?

What I mean is:
<no prop> - burst disabled
0 - INCR burst. INCR is undefined length burst IIRC.
4/8/16/etc. - INCR4/INCR8/INCR16/etc.

What case does this not cover?

Rob
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[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Rob Herring]

On Tue, Jan 3, 2017 at 8:24 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
> Hi, Rob,
>
>> -----Original Message-----
>> From: Rob Herring [mailto:robh at kernel.org]
>> Sent: Wednesday, January 04, 2017 5:24 AM
>> To: Jerry Huang <jerry.huang@nxp.com>
>> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
>> will.deacon at arm.com; linux at armlinux.org.uk; devicetree at vger.kernel.org;
>> linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
>> kernel at lists.infradead.org
>> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-
>> type-adjustment" for INCR burst type
>>
>> On Thu, Dec 22, 2016 at 8:52 PM, Jerry Huang <jerry.huang@nxp.com> wrote:
>> > Hi, Rob,
>> >> -----Original Message-----
>> >> From: Rob Herring [mailto:robh at kernel.org]
>> >> Sent: Friday, December 23, 2016 2:45 AM
>> >> To: Jerry Huang <jerry.huang@nxp.com>
>> >> Cc: balbi at kernel.org; mark.rutland at arm.com; catalin.marinas at arm.com;
>> >> will.deacon at arm.com; linux at armlinux.org.uk;
>> >> devicetree at vger.kernel.org; linux-usb at vger.kernel.org;
>> >> linux-kernel at vger.kernel.org; linux-arm- kernel at lists.infradead.org
>> >> Subject: Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps,
>> >> incr-burst- type-adjustment" for INCR burst type
>> >>
>> >> On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
>> >> > New property "snps,incr-burst-type-adjustment = <x>, <y>" for
>> >> > USB3.0
>> >> DWC3.
>> >> > Field "x": 1/0 - undefined length INCR burst type enable or not;
>> >> > Field
>> >> > "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>> >> >
>> >> > While enabling undefined length INCR burst type and INCR16 burst
>> >> > type, get better write performance on NXP Layerscape platform:
>> >> > around 3% improvement (from 364MB/s to 375MB/s).
>> >> >
>> >> > Signed-off-by: Changming Huang <jerry.huang@nxp.com>
>> >> > ---
>> >> > Changes in v3:
>> >> >   - add new property for INCR burst in usb node.
>> >> >
>> >> >  Documentation/devicetree/bindings/usb/dwc3.txt |    5 +++++
>> >> >  arch/arm/boot/dts/ls1021a.dtsi                 |    1 +
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    3 +++
>> >> >  arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |    2 ++
>> >> >  4 files changed, 11 insertions(+)
>> >> >
>> >> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > index e3e6983..8c405a3 100644
>> >> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> >> > @@ -55,6 +55,10 @@ Optional properties:
>> >> >     fladj_30mhz_sdbnd signal is invalid or incorrect.
>> >> >
>> >> >   - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be
>> >> reallocated.
>> >> > + - snps,incr-burst-type-adjustment: Value for INCR burst type of
>> >> GSBUSCFG0
>> >> > +   register, undefined length INCR burst type enable and INCRx type.
>> >> > +   First field is for undefined length INCR burst type enable or not.
>> >> > +   Second field is for largest INCRx type enabled.
>> >>
>> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
>> >> If not, then just use the presence of the property to enable or not.
>> > The first field is one switch.
>> > When it is 1, means undefined length INCR burst type enabled, we can use
>> any length less than or equal to the largest-enabled burst length of
>> INCR4/8/16/32/64/128/256.
>> > When it is zero, means INCRx burst mode enabled, we can use one fixed
>> burst length of 1/4/8/16/32/64/128/256 byte.
>> > So, the 2nd field is used if the 1st is 0, we need to select one largest burst
>> length the USB controller can support.
>> > If we don't want to change the value of this register (use the default value),
>> we don't need to add this property to usb node.
>>
>> Just make this a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> Maybe, I didn't describe it clearly.
> According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx burst mode, 1 means INCR burst mode.
> Regardless of the value of INCRBrstEna [bit0], we need to modify the other field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> Ad you mentioned, if we just use a single value with 0 meaning INCR and 4/8/16/etc being INCRx.
> I understand totally that when it is none-zero, we can use it for INCR burst mode.
> Then, when it is 0, how to select the INCRx value?

What I mean is:
<no prop> - burst disabled
0 - INCR burst. INCR is undefined length burst IIRC.
4/8/16/etc. - INCR4/INCR8/INCR16/etc.

What case does this not cover?

Rob

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> >> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> >> If not, then just use the presence of the property to enable or not.
> >> > The first field is one switch.
> >> > When it is 1, means undefined length INCR burst type enabled, we
> >> > can use
> >> any length less than or equal to the largest-enabled burst length of
> >> INCR4/8/16/32/64/128/256.
> >> > When it is zero, means INCRx burst mode enabled, we can use one
> >> > fixed
> >> burst length of 1/4/8/16/32/64/128/256 byte.
> >> > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > largest burst
> >> length the USB controller can support.
> >> > If we don't want to change the value of this register (use the
> >> > default value),
> >> we don't need to add this property to usb node.
> >>
> >> Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> > Maybe, I didn't describe it clearly.
> > According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> > Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> > Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> > I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> > Then, when it is 0, how to select the INCRx value?
> 
> What I mean is:
> <no prop> - burst disabled
Yes, I understand it.
> 0 - INCR burst. INCR is undefined length burst IIRC.
When INCR is undefined length, we need to set the max INCR type, too, such as when setting INCR16, controller can use any length less than or equal to the 16 byte.
> 4/8/16/etc. - INCR4/INCR8/INCR16/etc.
I understand it, too.
> 
> What case does this not cover?
According to Balbi's suggestion, I changed the property like below, you can see the detail in v4 (sent by 1/18/2017)
Property "snps,incr-burst-type-adjustment = <x>, <y>..." for USB3.0 DWC3.
When Just one value means INCRx mode with fix burst type.
When more than one value, means undefined length burst mode, USB controller can use the length less than or equal to the largest enabled burst length.

RE: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> >> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> >> If not, then just use the presence of the property to enable or not.
> >> > The first field is one switch.
> >> > When it is 1, means undefined length INCR burst type enabled, we
> >> > can use
> >> any length less than or equal to the largest-enabled burst length of
> >> INCR4/8/16/32/64/128/256.
> >> > When it is zero, means INCRx burst mode enabled, we can use one
> >> > fixed
> >> burst length of 1/4/8/16/32/64/128/256 byte.
> >> > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > largest burst
> >> length the USB controller can support.
> >> > If we don't want to change the value of this register (use the
> >> > default value),
> >> we don't need to add this property to usb node.
> >>
> >> Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> > Maybe, I didn't describe it clearly.
> > According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> > Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> > Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> > I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> > Then, when it is 0, how to select the INCRx value?
> 
> What I mean is:
> <no prop> - burst disabled
Yes, I understand it.
> 0 - INCR burst. INCR is undefined length burst IIRC.
When INCR is undefined length, we need to set the max INCR type, too, such as when setting INCR16, controller can use any length less than or equal to the 16 byte.
> 4/8/16/etc. - INCR4/INCR8/INCR16/etc.
I understand it, too.
> 
> What case does this not cover?
According to Balbi's suggestion, I changed the property like below, you can see the detail in v4 (sent by 1/18/2017)
Property "snps,incr-burst-type-adjustment = <x>, <y>..." for USB3.0 DWC3.
When Just one value means INCRx mode with fix burst type.
When more than one value, means undefined length burst mode, USB controller can use the length less than or equal to the largest enabled burst length.

[PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type

[Jerry Huang]

> >> >> Why do you need the first field? Is the 2nd field used if the 1st is 0?
> >> >> If not, then just use the presence of the property to enable or not.
> >> > The first field is one switch.
> >> > When it is 1, means undefined length INCR burst type enabled, we
> >> > can use
> >> any length less than or equal to the largest-enabled burst length of
> >> INCR4/8/16/32/64/128/256.
> >> > When it is zero, means INCRx burst mode enabled, we can use one
> >> > fixed
> >> burst length of 1/4/8/16/32/64/128/256 byte.
> >> > So, the 2nd field is used if the 1st is 0, we need to select one
> >> > largest burst
> >> length the USB controller can support.
> >> > If we don't want to change the value of this register (use the
> >> > default value),
> >> we don't need to add this property to usb node.
> >>
> >> Just make this a single value with 0 meaning INCR and 4/8/16/etc being
> INCRx.
> > Maybe, I didn't describe it clearly.
> > According to DWC3 spec, the value "0" of field INCRBrstEna means INCRx
> burst mode, 1 means INCR burst mode.
> > Regardless of the value of INCRBrstEna [bit0], we need to modify the other
> field bit[1,2,3,4,5,6,7] to one INCR burst type  for the platform supported.
> > Ad you mentioned, if we just use a single value with 0 meaning INCR and
> 4/8/16/etc being INCRx.
> > I understand totally that when it is none-zero, we can use it for INCR burst
> mode.
> > Then, when it is 0, how to select the INCRx value?
> 
> What I mean is:
> <no prop> - burst disabled
Yes, I understand it.
> 0 - INCR burst. INCR is undefined length burst IIRC.
When INCR is undefined length, we need to set the max INCR type, too, such as when setting INCR16, controller can use any length less than or equal to the 16 byte.
> 4/8/16/etc. - INCR4/INCR8/INCR16/etc.
I understand it, too.
> 
> What case does this not cover?
According to Balbi's suggestion, I changed the property like below, you can see the detail in v4 (sent by 1/18/2017)
Property "snps,incr-burst-type-adjustment = <x>, <y>..." for USB3.0 DWC3.
When Just one value means INCRx mode with fix burst type.
When more than one value, means undefined length burst mode, USB controller can use the length less than or equal to the largest enabled burst length.