* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
@ 2017-01-06 16:29 vathsala nagaraju
2017-01-06 17:26 ` Vivi, Rodrigo
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-06 16:29 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right
after setup_vsc
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 9 ++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7020f42..bcfe0db 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -348,7 +348,6 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_TP2_TIME_100;
else
val |= EDP_PSR2_TP2_TIME_50;
-
I915_WRITE(EDP_PSR2_CTL, val);
}
@@ -475,6 +474,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ uint32_t chicken_trans = 0;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +505,13 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans = CHICKEN_TRANS_BIT15;
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-06 16:29 [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
@ 2017-01-06 17:26 ` Vivi, Rodrigo
0 siblings, 0 replies; 18+ messages in thread
From: Vivi, Rodrigo @ 2017-01-06 17:26 UTC (permalink / raw)
To: Nagaraju, Vathsala; +Cc: intel-gfx, Patil, Deepti, dri-devel
On Fri, 2017-01-06 at 21:59 +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right
> after setup_vsc
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_psr.c | 9 ++++++++-
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +#define CHICKEN_TRANS_BIT12 (1<<12)
> +#define CHICKEN_TRANS_BIT15 (1<<15)
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 7020f42..bcfe0db 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -348,7 +348,6 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
> val |= EDP_PSR2_TP2_TIME_100;
> else
> val |= EDP_PSR2_TP2_TIME_50;
> -
I'm afraid you missed this space here and removed one extra line.
> I915_WRITE(EDP_PSR2_CTL, val);
> }
>
> @@ -475,6 +474,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + uint32_t chicken_trans = 0;
what about invert the order below so you don't need to initialize this
as 0 here.
chicken_trans = CHICKEN_TRANS_BIT12;
if (dev_priv->psr.y_cord_support)
chicken_trans |= CHICKEN_TRANS_BIT15;
>
> if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +505,13 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = false;
> else
> skl_psr_setup_su_vsc(intel_dp);
> +
> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans = CHICKEN_TRANS_BIT15;
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
or at least use |= here...
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
@ 2017-01-11 15:22 vathsala nagaraju
2017-01-12 19:01 ` vathsala nagaraju
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-11 15:22 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
psr2 enable sequence.
bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
header packet.
bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
v4:(chris wilson)
- use BIT(12), remove CHICKEN_TRANS_BIT12
- remove unnecessary comments
- update commit message
v5:
- rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
- rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..7a325fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
+#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 3cf5cc4..b582220 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -480,6 +480,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 chicken;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
if (HAS_DDI(dev_priv)) {
if (dev_priv->psr.psr2_support) {
skl_psr_setup_su_vsc(intel_dp);
+ chicken = PSR2_VSC_ENABLE_PROG_HEADER;
+ if (dev_priv->psr.y_cord_support)
+ chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-11 15:22 vathsala nagaraju
@ 2017-01-12 19:01 ` vathsala nagaraju
2017-01-12 20:12 ` Vivi, Rodrigo
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-12 19:01 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
psr2 enable sequence.
bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
header packet.
bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
v4:(chris wilson)
- use BIT(12), remove CHICKEN_TRANS_BIT12
- remove unnecessary comments
- update commit message
v5:
- rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
- rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
v6:(Rodrigo)
- remove TRANS_EDP=3, use cpu_transcoder
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..c9c1ccd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,12 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
+#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 36c4045..935402e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
+ u32 chicken;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
if (HAS_DDI(dev_priv)) {
if (dev_priv->psr.psr2_support) {
skl_psr_setup_su_vsc(intel_dp);
+ chicken = PSR2_VSC_ENABLE_PROG_HEADER;
+ if (dev_priv->psr.y_cord_support)
+ chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
+ I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-12 19:01 ` vathsala nagaraju
@ 2017-01-12 20:12 ` Vivi, Rodrigo
2017-01-13 18:50 ` [Intel-gfx] " Rodrigo Vivi
0 siblings, 1 reply; 18+ messages in thread
From: Vivi, Rodrigo @ 2017-01-12 20:12 UTC (permalink / raw)
To: Nagaraju, Vathsala; +Cc: intel-gfx, Patil, Deepti, jim.bride, dri-devel
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
> psr2 enable sequence.
> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
> PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
> header packet.
> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>
> v4:(chris wilson)
> - use BIT(12), remove CHICKEN_TRANS_BIT12
> - remove unnecessary comments
> - update commit message
>
> v5:
> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
>
> v6:(Rodrigo)
> - remove TRANS_EDP=3, use cpu_transcoder
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..c9c1ccd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,12 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 36c4045..935402e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> + u32 chicken;
>
> if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> if (HAS_DDI(dev_priv)) {
> if (dev_priv->psr.psr2_support) {
> skl_psr_setup_su_vsc(intel_dp);
> + chicken = PSR2_VSC_ENABLE_PROG_HEADER;
> + if (dev_priv->psr.y_cord_support)
> + chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
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^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-12 20:12 ` Vivi, Rodrigo
@ 2017-01-13 18:50 ` Rodrigo Vivi
2017-01-16 10:04 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2017-01-13 18:50 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Nagaraju, Vathsala, intel-gfx, Patil, Deepti, dri-devel
This and all the remaining patches on this series (6,7,8 and 9) got
merged to dinq.
Thanks for the patches.
On Thu, Jan 12, 2017 at 12:12 PM, Vivi, Rodrigo <rodrigo.vivi@intel.com> wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
>> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
>> psr2 enable sequence.
>> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
>> PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
>> header packet.
>> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>>
>> v2: (Rodrigo)
>> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>>
>> v3:(Rodrigo)
>> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>>
>> v4:(chris wilson)
>> - use BIT(12), remove CHICKEN_TRANS_BIT12
>> - remove unnecessary comments
>> - update commit message
>>
>> v5:
>> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
>> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
>>
>> v6:(Rodrigo)
>> - remove TRANS_EDP=3, use cpu_transcoder
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Jim Bride <jim.bride@linux.intel.com>
>> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
>> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7830e6e..c9c1ccd 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6449,6 +6449,12 @@ enum {
>> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
>> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>>
>> +#define CHICKEN_TRANS_A 0x420c0
>> +#define CHICKEN_TRANS_B 0x420c4
>> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
>> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
>> +
>> #define DISP_ARB_CTL _MMIO(0x45000)
>> #define DISP_FBC_MEMORY_WAKE (1<<31)
>> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 36c4045..935402e 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> struct drm_device *dev = intel_dig_port->base.base.dev;
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>> + u32 chicken;
>>
>> if (!HAS_PSR(dev_priv)) {
>> DRM_DEBUG_KMS("PSR not supported on this platform\n");
>> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>> if (HAS_DDI(dev_priv)) {
>> if (dev_priv->psr.psr2_support) {
>> skl_psr_setup_su_vsc(intel_dp);
>> + chicken = PSR2_VSC_ENABLE_PROG_HEADER;
>> + if (dev_priv->psr.y_cord_support)
>> + chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
>> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>> } else {
>> /* set up vsc header for psr1 */
>> hsw_psr_setup_vsc(intel_dp);
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-13 18:50 ` [Intel-gfx] " Rodrigo Vivi
@ 2017-01-16 10:04 ` Jani Nikula
2017-01-17 17:33 ` Rodrigo Vivi
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2017-01-16 10:04 UTC (permalink / raw)
To: Rodrigo Vivi, Vivi, Rodrigo; +Cc: intel-gfx, Patil, Deepti, dri-devel
On Fri, 13 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> This and all the remaining patches on this series (6,7,8 and 9) got
> merged to dinq.
Given that this patch series was not properly sent as a thread, I don't
think our CI ran it as a whole, and it should not have been pushed
before that.
BR,
Jani.
>
> Thanks for the patches.
>
> On Thu, Jan 12, 2017 at 12:12 PM, Vivi, Rodrigo <rodrigo.vivi@intel.com> wrote:
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
>>> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
>>> psr2 enable sequence.
>>> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
>>> PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
>>> header packet.
>>> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>>>
>>> v2: (Rodrigo)
>>> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>>>
>>> v3:(Rodrigo)
>>> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>>>
>>> v4:(chris wilson)
>>> - use BIT(12), remove CHICKEN_TRANS_BIT12
>>> - remove unnecessary comments
>>> - update commit message
>>>
>>> v5:
>>> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
>>> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
>>>
>>> v6:(Rodrigo)
>>> - remove TRANS_EDP=3, use cpu_transcoder
>>>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Jim Bride <jim.bride@linux.intel.com>
>>> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
>>> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>>> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>>> 2 files changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 7830e6e..c9c1ccd 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6449,6 +6449,12 @@ enum {
>>> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
>>> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>>>
>>> +#define CHICKEN_TRANS_A 0x420c0
>>> +#define CHICKEN_TRANS_B 0x420c4
>>> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
>>> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>>> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
>>> +
>>> #define DISP_ARB_CTL _MMIO(0x45000)
>>> #define DISP_FBC_MEMORY_WAKE (1<<31)
>>> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>> index 36c4045..935402e 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>> struct drm_device *dev = intel_dig_port->base.base.dev;
>>> struct drm_i915_private *dev_priv = to_i915(dev);
>>> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>>> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>>> + u32 chicken;
>>>
>>> if (!HAS_PSR(dev_priv)) {
>>> DRM_DEBUG_KMS("PSR not supported on this platform\n");
>>> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>> if (HAS_DDI(dev_priv)) {
>>> if (dev_priv->psr.psr2_support) {
>>> skl_psr_setup_su_vsc(intel_dp);
>>> + chicken = PSR2_VSC_ENABLE_PROG_HEADER;
>>> + if (dev_priv->psr.y_cord_support)
>>> + chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
>>> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>>> } else {
>>> /* set up vsc header for psr1 */
>>> hsw_psr_setup_vsc(intel_dp);
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-16 10:04 ` Jani Nikula
@ 2017-01-17 17:33 ` Rodrigo Vivi
2017-01-18 8:12 ` [Intel-gfx] " Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2017-01-17 17:33 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Patil, Deepti, dri-devel, Vivi, Rodrigo
On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula
<jani.nikula@linux.intel.com> wrote:
> On Fri, 13 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> This and all the remaining patches on this series (6,7,8 and 9) got
>> merged to dinq.
>
> Given that this patch series was not properly sent as a thread, I don't
> think our CI ran it as a whole, and it should not have been pushed
> before that.
I assumed "[Intel-gfx] ✓ Fi.CI.BAT: success for enable psr2 for
idle_screen on y-cordinate panel"
was enough, giving the patches haven't drastically changed after.
>
> BR,
> Jani.
>
>>
>> Thanks for the patches.
>>
>> On Thu, Jan 12, 2017 at 12:12 PM, Vivi, Rodrigo <rodrigo.vivi@intel.com> wrote:
>>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>
>>> On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
>>>> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
>>>> psr2 enable sequence.
>>>> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
>>>> PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
>>>> header packet.
>>>> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>>>>
>>>> v2: (Rodrigo)
>>>> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>>>>
>>>> v3:(Rodrigo)
>>>> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>>>>
>>>> v4:(chris wilson)
>>>> - use BIT(12), remove CHICKEN_TRANS_BIT12
>>>> - remove unnecessary comments
>>>> - update commit message
>>>>
>>>> v5:
>>>> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
>>>> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
>>>>
>>>> v6:(Rodrigo)
>>>> - remove TRANS_EDP=3, use cpu_transcoder
>>>>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> Cc: Jim Bride <jim.bride@linux.intel.com>
>>>> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
>>>> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>>>> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>>>> 2 files changed, 13 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index 7830e6e..c9c1ccd 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -6449,6 +6449,12 @@ enum {
>>>> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
>>>> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>>>>
>>>> +#define CHICKEN_TRANS_A 0x420c0
>>>> +#define CHICKEN_TRANS_B 0x420c4
>>>> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
>>>> +#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
>>>> +#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
>>>> +
>>>> #define DISP_ARB_CTL _MMIO(0x45000)
>>>> #define DISP_FBC_MEMORY_WAKE (1<<31)
>>>> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
>>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>>> index 36c4045..935402e 100644
>>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>>> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>>> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>>>> struct drm_device *dev = intel_dig_port->base.base.dev;
>>>> struct drm_i915_private *dev_priv = to_i915(dev);
>>>> + struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>>>> + enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
>>>> + u32 chicken;
>>>>
>>>> if (!HAS_PSR(dev_priv)) {
>>>> DRM_DEBUG_KMS("PSR not supported on this platform\n");
>>>> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>>>> if (HAS_DDI(dev_priv)) {
>>>> if (dev_priv->psr.psr2_support) {
>>>> skl_psr_setup_su_vsc(intel_dp);
>>>> + chicken = PSR2_VSC_ENABLE_PROG_HEADER;
>>>> + if (dev_priv->psr.y_cord_support)
>>>> + chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
>>>> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>>>> } else {
>>>> /* set up vsc header for psr1 */
>>>> hsw_psr_setup_vsc(intel_dp);
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-17 17:33 ` Rodrigo Vivi
@ 2017-01-18 8:12 ` Jani Nikula
2017-01-18 21:50 ` Vivi, Rodrigo
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2017-01-18 8:12 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Nagaraju, Vathsala, intel-gfx, Patil, Deepti, dri-devel, Vivi, Rodrigo
On Tue, 17 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula
> <jani.nikula@linux.intel.com> wrote:
>> On Fri, 13 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>>> This and all the remaining patches on this series (6,7,8 and 9) got
>>> merged to dinq.
>>
>> Given that this patch series was not properly sent as a thread, I don't
>> think our CI ran it as a whole, and it should not have been pushed
>> before that.
>
> I assumed "[Intel-gfx] ✓ Fi.CI.BAT: success for enable psr2 for
> idle_screen on y-cordinate panel"
> was enough, giving the patches haven't drastically changed after.
The idea is to test the code that gets pushed...
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-18 8:12 ` [Intel-gfx] " Jani Nikula
@ 2017-01-18 21:50 ` Vivi, Rodrigo
0 siblings, 0 replies; 18+ messages in thread
From: Vivi, Rodrigo @ 2017-01-18 21:50 UTC (permalink / raw)
To: jani.nikula; +Cc: Patil, Deepti, intel-gfx, dri-devel
On Wed, 2017-01-18 at 10:12 +0200, Jani Nikula wrote:
> On Tue, 17 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> > On Mon, Jan 16, 2017 at 2:04 AM, Jani Nikula
> > <jani.nikula@linux.intel.com> wrote:
> >> On Fri, 13 Jan 2017, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> >>> This and all the remaining patches on this series (6,7,8 and 9) got
> >>> merged to dinq.
> >>
> >> Given that this patch series was not properly sent as a thread, I don't
> >> think our CI ran it as a whole, and it should not have been pushed
> >> before that.
> >
> > I assumed "[Intel-gfx] ✓ Fi.CI.BAT: success for enable psr2 for
> > idle_screen on y-cordinate panel"
> > was enough, giving the patches haven't drastically changed after.
>
> The idea is to test the code that gets pushed...
Yep, this makes sense, although I'm sure that BAT doesn't test any of
the code touched...
But this is another problem.
Anyway, that won't happen again. But question:
should it be resent to mailing list or try-bot is fine?
>
> BR,
> Jani.
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
@ 2017-01-06 18:58 vathsala nagaraju
2017-01-06 19:15 ` Vivi, Rodrigo
` (2 more replies)
0 siblings, 3 replies; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-06 18:58 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7020f42..7573c2f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ uint32_t chicken_trans = CHICKEN_TRANS_BIT12;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +507,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans |= CHICKEN_TRANS_BIT15;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-06 18:58 vathsala nagaraju
@ 2017-01-06 19:15 ` Vivi, Rodrigo
2017-01-07 2:52 ` vathsala nagaraju
2017-01-07 18:12 ` vathsala nagaraju
2 siblings, 0 replies; 18+ messages in thread
From: Vivi, Rodrigo @ 2017-01-06 19:15 UTC (permalink / raw)
To: Nagaraju, Vathsala; +Cc: intel-gfx, Patil, Deepti, dri-devel
On Sat, 2017-01-07 at 00:28 +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_psr.c | 6 ++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +#define CHICKEN_TRANS_BIT12 (1<<12)
> +#define CHICKEN_TRANS_BIT15 (1<<15)
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 7020f42..7573c2f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -475,6 +475,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + uint32_t chicken_trans = CHICKEN_TRANS_BIT12;
+ uint32_t chicken_trans;
>
> if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +507,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = false;
> else
> skl_psr_setup_su_vsc(intel_dp);
+
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = CHICKEN_TRANS_BIT12;
> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans |= CHICKEN_TRANS_BIT15;
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-06 18:58 vathsala nagaraju
2017-01-06 19:15 ` Vivi, Rodrigo
@ 2017-01-07 2:52 ` vathsala nagaraju
2017-01-07 18:12 ` vathsala nagaraju
2 siblings, 0 replies; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-07 2:52 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
v4:(Rodrigo)
- initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7020f42..b804066 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ uint32_t chicken_trans = 0;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = CHICKEN_TRANS_BIT12;
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans |= CHICKEN_TRANS_BIT15;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-06 18:58 vathsala nagaraju
2017-01-06 19:15 ` Vivi, Rodrigo
2017-01-07 2:52 ` vathsala nagaraju
@ 2017-01-07 18:12 ` vathsala nagaraju
2017-01-07 19:44 ` [Intel-gfx] " Chris Wilson
2017-01-09 13:08 ` vathsala nagaraju
2 siblings, 2 replies; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-07 18:12 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
v4:(Rodrigo)
- initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b28891b..1e5dd8f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ uint32_t chicken_trans = 0;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = CHICKEN_TRANS_BIT12;
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans |= CHICKEN_TRANS_BIT15;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-07 18:12 ` vathsala nagaraju
@ 2017-01-07 19:44 ` Chris Wilson
2017-01-09 4:09 ` vathsala nagaraju
2017-01-09 13:08 ` vathsala nagaraju
1 sibling, 1 reply; 18+ messages in thread
From: Chris Wilson @ 2017-01-07 19:44 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx, Patil Deepti, dri-devel, Rodrigo Vivi
On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>
> v4:(Rodrigo)
> - initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12
Weird. Just scope the variable properly, use the correct type.
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +#define CHICKEN_TRANS_BIT12 (1<<12)
> +#define CHICKEN_TRANS_BIT15 (1<<15)
Useless naming. Either given them proper names or don't.
> if (!HAS_PSR(dev_priv)) {
u32 chicken;
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = false;
> else
> skl_psr_setup_su_vsc(intel_dp);
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + chicken_trans = CHICKEN_TRANS_BIT12;
We can see you are setting CHICKEN_TRANS_BIT12, so don't bother
repeating that. What programmable header? Why is this in a chicken bit,
what is the bspec reference, all of those would be useful to answer.
> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans |= CHICKEN_TRANS_BIT15;
Again. Tell us why, we can read the code. Are the names meaningful? More
meaningful than chicken |= BIT(15); ?
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-07 19:44 ` [Intel-gfx] " Chris Wilson
@ 2017-01-09 4:09 ` vathsala nagaraju
0 siblings, 0 replies; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-09 4:09 UTC (permalink / raw)
To: Chris Wilson, dri-devel, intel-gfx, Patil Deepti, Rodrigo Vivi
On Sunday 08 January 2017 01:14 AM, Chris Wilson wrote:
> On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote:
>> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
>> must be programmed.
>> Enable bit 12 for programmable header packet.
>> Enable bit 15 for Y cordinate support.
>>
>> v2: (Rodrigo)
>> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>>
>> v3:(Rodrigo)
>> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>>
>> v4:(Rodrigo)
>> - initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12
> Weird. Just scope the variable properly, use the correct type.
>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Jim Bride <jim.bride@linux.intel.com>
>> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
>> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
>> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 7830e6e..5ca506a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6449,6 +6449,13 @@ enum {
>> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
>> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>>
>> +#define CHICKEN_TRANS_A 0x420c0
>> +#define CHICKEN_TRANS_B 0x420c4
>> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
>> +#define TRANS_EDP 3
>> +#define CHICKEN_TRANS_BIT12 (1<<12)
>> +#define CHICKEN_TRANS_BIT15 (1<<15)
> Useless naming. Either given them proper names or don't.
>
>> if (!HAS_PSR(dev_priv)) {
> u32 chicken;
>
>> DRM_DEBUG_KMS("PSR not supported on this platform\n");
>> @@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>> dev_priv->psr.psr2_support = false;
>> else
>> skl_psr_setup_su_vsc(intel_dp);
>> + /* Set CHICKEN_TRANS_BIT12 for programable header */
>> + chicken_trans = CHICKEN_TRANS_BIT12;
> We can see you are setting CHICKEN_TRANS_BIT12, so don't bother
> repeating that. What programmable header? Why is this in a chicken bit,
> what is the bspec reference, all of those would be useful to answer.
Thanks for the review.
In bspec, it's part of psr2 enable sequence.
"Program Transcoder EDP VSC DIP header with a valid setting for PSR2 and
Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header packet"
Will remove the comment.
>
>> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
>> + if (dev_priv->psr.y_cord_support)
>> + chicken_trans |= CHICKEN_TRANS_BIT15;
> Again. Tell us why, we can read the code. Are the names meaningful? More
> meaningful than chicken |= BIT(15); ?
In bspec, for register CHICKEN_TRANS, bit field name for 12 and 15 are spare 12 and spare 15.
Named CHICKEN_TRANS_BIT15 instead of spare 15. Will remove the comment and change to BIT(12) and BIT(15)
>
>> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
>> } else {
>> /* set up vsc header for psr1 */
>> hsw_psr_setup_vsc(intel_dp);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-07 18:12 ` vathsala nagaraju
2017-01-07 19:44 ` [Intel-gfx] " Chris Wilson
@ 2017-01-09 13:08 ` vathsala nagaraju
2017-01-10 11:08 ` Ville Syrjälä
1 sibling, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-09 13:08 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
psr2 enable sequence.
Program Transcoder EDP VSC DIP header with a valid setting for PSR2
and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header
packet.
Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
v4:(chris wilson)
- use BIT(12), remove CHICKEN_TRANS_BIT12
- remove unnecessary comments
- update commit message
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_psr.c | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..3299e01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,11 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b28891b..b1686c2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+ u32 chicken = 0;
if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+ chicken = BIT(12);
+ if (dev_priv->psr.y_cord_support)
+ chicken |= BIT(15);
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-09 13:08 ` vathsala nagaraju
@ 2017-01-10 11:08 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2017-01-10 11:08 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx, Patil Deepti, dri-devel, Rodrigo Vivi
On Mon, Jan 09, 2017 at 06:38:15PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
> psr2 enable sequence.
> Program Transcoder EDP VSC DIP header with a valid setting for PSR2
> and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header
> packet.
> Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
>
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
>
> v4:(chris wilson)
> - use BIT(12), remove CHICKEN_TRANS_BIT12
> - remove unnecessary comments
> - update commit message
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_psr.c | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..3299e01 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,11 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index b28891b..b1686c2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + u32 chicken = 0;
>
> if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +506,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = false;
> else
> skl_psr_setup_su_vsc(intel_dp);
> + chicken = BIT(12);
> + if (dev_priv->psr.y_cord_support)
> + chicken |= BIT(15);
In cases like this I think the better option is to invent a decent
name for the bit. Otherwise no one can figure out what the code does
without consulting the spec.
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel
@ 2017-01-02 11:30 vathsala nagaraju
2017-01-02 11:30 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-02 11:30 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Rodrigo Vivi
This series enables psr2 on idle on screen for y cordinate panel.
Code is tested on sharp 32X18 edp 1.4 y cordinate enabled panel.
if system enters psr2, the system must go to deep sleep state.
Can be verifed by checking psr2_status register bit 31:28.
DEEP_SLEEP[value 8] must be entered while in idle on screen with psr2
panel.
PSR1 and PSR2 are mutually exclusive.
In the current code, when PSR2 is enabled , psr1 is also enabled,
and for psr2 the status is read from psr1 registers, leading to
blank screen.
1-3: Fixes vsc header programming for psr2 as per edp1.4 a
table 6-11 and blank screen issue for psr2 panel.
4-5: Enables alpm and disables aux frame sync , need for psr2.
6-7: Progarms CHICKEN_TRANS and PSR_MASK for deep sleep state, as per bspec
8: Psr2 is enabled only for y cordinate enabled psr2 panel.
this restriction will be removed after adding gtc support.
9-10: Adds debug support for psr2.It also enables reading of
EDP_PSR_PERF_CNT on skl+ platforms, when dc6 is disabled through
kernel parameter i915.enable_dc=0
Vathsala Nagaraju (10):
drm : adds Y-coordinate and Colorimetry Format
drm/i915/psr: program vsc header for psr2
drm/i915/psr: fix blank screen issue for psr2
drm/i915/psr: disable aux_frame_sync on psr2 exit
drm/i915/psr: enable ALPM for psr2
drm/i915/psr: set CHICKEN_TRANS for psr2
drm/i915/psr: set PSR_MASK bits for deep sleep
drm/i915/psr: enable psr2 for y cordinate panels
drm/i915/psr: report live PSR2 State
drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2
drivers/gpu/drm/i915/i915_debugfs.c | 38 ++++++-
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 19 ++++
drivers/gpu/drm/i915/intel_dp.c | 35 +++++++
drivers/gpu/drm/i915/intel_psr.c | 199 ++++++++++++++++++++++++++++--------
include/drm/drm_dp_helper.h | 13 ++-
6 files changed, 263 insertions(+), 44 deletions(-)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-02 11:30 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
@ 2017-01-02 11:30 ` vathsala nagaraju
2017-01-05 17:57 ` Rodrigo Vivi
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2017-01-02 11:30 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 494e4b2..2e75ef6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = EDP_PSR_ENABLE;
+ uint32_t chicken_trans = 0;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
else
val |= EDP_PSR2_TP2_TIME_50;
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans = CHICKEN_TRANS_BIT15;
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
I915_WRITE(EDP_PSR2_CTL, val);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2017-01-02 11:30 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
@ 2017-01-05 17:57 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2017-01-05 17:57 UTC (permalink / raw)
To: vathsala nagaraju; +Cc: intel-gfx, Patil Deepti, dri-devel
Please don't forget about the bit 11 for KBL. In a separated patch.
This patch is correct and count with my rv-b, but I believe the best place for this is
on intel_psr_enable, right after setup_vsc.
On Mon, Jan 02, 2017 at 05:00:59PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +#define CHICKEN_TRANS_BIT12 (1<<12)
> +#define CHICKEN_TRANS_BIT15 (1<<15)
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 494e4b2..2e75ef6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val = EDP_PSR_ENABLE;
> + uint32_t chicken_trans = 0;
>
> val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
> else
> val |= EDP_PSR2_TP2_TIME_50;
>
> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans = CHICKEN_TRANS_BIT15;
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
> I915_WRITE(EDP_PSR2_CTL, val);
> }
>
> --
> 1.9.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel
@ 2016-12-30 5:25 vathsala nagaraju
2016-12-30 5:25 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
0 siblings, 1 reply; 18+ messages in thread
From: vathsala nagaraju @ 2016-12-30 5:25 UTC (permalink / raw)
To: intel-gfx
This series enables psr2 on idle on screen for y cordinate panel.
Code is tested on sharp 32X18 edp 1.4 y cordinate enabled panel.
if system enters psr2, the system must go to deep sleep state.
Can be verifed by checking psr2_status register bit 31:28.
DEEP_SLEEP[value 8] must be entered while in idle on screen with psr2
panel.
PSR1 and PSR2 are mutually exclusive.
In the current code, when PSR2 is enabled , psr1 is also enabled,
and for psr2 the status is read from psr1 registers, leading to
blank screen.
1-3: Fixes vsc header programming for psr2 as per edp1.4 a
table 6-11 and blank screen issue for psr2 panel.
4-5: Enables alpm and disables aux frame sync , need for psr2.
6-7: Progarms CHICKEN_TRANS and PSR_MASK for deep sleep state, as per bspec
8: Psr2 is enabled only for y cordinate enabled psr2 panel.
this restriction will be removed after adding gtc support.
9-10: Adds debug support for psr2.It also enables reading of
EDP_PSR_PERF_CNT on skl+ platforms, when dc6 is disabled through
kernel parameter i915.enable_dc=0
Vathsala Nagaraju (10):
drm : adds Y-coordinate and Colorimetry Format
drm/i915/psr: program vsc header for psr2
drm/i915/psr: fix blank screen issue for psr2
drm/i915/psr: disable aux_frame_sync on psr2 exit
drm/i915/psr: enable ALPM for psr2
drm/i915/psr: set CHICKEN_TRANS for psr2
drm/i915/psr: set PSR_MASK bits for deep sleep
drm/i915/psr: enable psr2 for y cordinate panels
drm/i915/psr: report live PSR2 State
drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2
drivers/gpu/drm/i915/i915_debugfs.c | 38 ++++++-
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 19 ++++
drivers/gpu/drm/i915/intel_dp.c | 35 +++++++
drivers/gpu/drm/i915/intel_psr.c | 199 ++++++++++++++++++++++++++++--------
include/drm/drm_dp_helper.h | 13 ++-
6 files changed, 263 insertions(+), 44 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2
2016-12-30 5:25 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
@ 2016-12-30 5:25 ` vathsala nagaraju
0 siblings, 0 replies; 18+ messages in thread
From: vathsala nagaraju @ 2016-12-30 5:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Patil Deepti, Rodrigo Vivi
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP 3
+#define CHICKEN_TRANS_BIT12 (1<<12)
+#define CHICKEN_TRANS_BIT15 (1<<15)
+
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 494e4b2..2e75ef6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = EDP_PSR_ENABLE;
+ uint32_t chicken_trans = 0;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
@@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
else
val |= EDP_PSR2_TP2_TIME_50;
+ /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+ if (dev_priv->psr.y_cord_support)
+ chicken_trans = CHICKEN_TRANS_BIT15;
+ /* Set CHICKEN_TRANS_BIT12 for programable header */
+ chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
+ I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
I915_WRITE(EDP_PSR2_CTL, val);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2017-01-18 21:50 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-06 16:29 [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
2017-01-06 17:26 ` Vivi, Rodrigo
-- strict thread matches above, loose matches on Subject: below --
2017-01-11 15:22 vathsala nagaraju
2017-01-12 19:01 ` vathsala nagaraju
2017-01-12 20:12 ` Vivi, Rodrigo
2017-01-13 18:50 ` [Intel-gfx] " Rodrigo Vivi
2017-01-16 10:04 ` Jani Nikula
2017-01-17 17:33 ` Rodrigo Vivi
2017-01-18 8:12 ` [Intel-gfx] " Jani Nikula
2017-01-18 21:50 ` Vivi, Rodrigo
2017-01-06 18:58 vathsala nagaraju
2017-01-06 19:15 ` Vivi, Rodrigo
2017-01-07 2:52 ` vathsala nagaraju
2017-01-07 18:12 ` vathsala nagaraju
2017-01-07 19:44 ` [Intel-gfx] " Chris Wilson
2017-01-09 4:09 ` vathsala nagaraju
2017-01-09 13:08 ` vathsala nagaraju
2017-01-10 11:08 ` Ville Syrjälä
2017-01-02 11:30 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
2017-01-02 11:30 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
2017-01-05 17:57 ` Rodrigo Vivi
2016-12-30 5:25 [PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel vathsala nagaraju
2016-12-30 5:25 ` [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2 vathsala nagaraju
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