From: Chee Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 04/28] arm: socfpga: arria10: add system manager defines
Date: Tue, 10 Jan 2017 13:20:17 +0800 [thread overview]
Message-ID: <1484025641-5412-5-git-send-email-tien.fong.chee@intel.com> (raw)
In-Reply-To: <1484025641-5412-1-git-send-email-tien.fong.chee@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122 +++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga; /* 0x738 */
};
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+ u32 siliconid1;
+ u32 siliconid2;
+ u32 wddbg;
+ u32 bootinfo;
+ u32 mpu_ctrl_l2_ecc;
+ u32 _pad_0x14_0x1f[3];
+ u32 dma;
+ u32 dma_periph;
+ u32 sdmmcgrp_ctrl;
+ u32 sdmmc_l3master;
+ u32 nand_bootstrap;
+ u32 nand_l3master;
+ u32 usb0_l3master;
+ u32 usb1_l3master;
+ u32 emac_global;
+ u32 emac0;
+ u32 emac1;
+ u32 emac2;
+ u32 _pad_0x50_0x5f[4];
+ u32 fpgaintf_en_global;
+ u32 fpgaintf_en_0;
+ u32 fpgaintf_en_1;
+ u32 fpgaintf_en_2;
+ u32 fpgaintf_en_3;
+ u32 _pad_0x74_0x7f[3];
+ u32 noc_addr_remap_value;
+ u32 noc_addr_remap_set;
+ u32 noc_addr_remap_clear;
+ u32 _pad_0x8c_0x8f;
+ u32 ecc_intmask_value;
+ u32 ecc_intmask_set;
+ u32 ecc_intmask_clr;
+ u32 ecc_intstatus_serr;
+ u32 ecc_intstatus_derr;
+ u32 mpu_status_l2_ecc;
+ u32 mpu_clear_l2_ecc;
+ u32 mpu_status_l1_parity;
+ u32 mpu_clear_l1_parity;
+ u32 mpu_set_l1_parity;
+ u32 _pad_0xb8_0xbf[2];
+ u32 noc_timeout;
+ u32 noc_idlereq_set;
+ u32 noc_idlereq_clr;
+ u32 noc_idlereq_value;
+ u32 noc_idleack;
+ u32 noc_idlestatus;
+ u32 fpga2soc_ctrl;
+ u32 _pad_0xdc_0xff[9];
+ u32 tsmc_tsel_0;
+ u32 tsmc_tsel_1;
+ u32 tsmc_tsel_2;
+ u32 tsmc_tsel_3;
+ u32 _pad_0x110_0x200[60];
+ u32 romhw_ctrl;
+ u32 romcode_ctrl;
+ u32 romcode_cpu1startaddr;
+ u32 romcode_initswstate;
+ u32 romcode_initswlastld;
+ u32 _pad_0x214_0x217;
+ u32 warmram_enable;
+ u32 warmram_datastart;
+ u32 warmram_length;
+ u32 warmram_execution;
+ u32 warmram_crc;
+ u32 _pad_0x22c_0x22f;
+ u32 isw_handoff[8];
+ u32 romcode_bootromswstate[8];
+};
+#endif
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V 0x1
+#define VOLTAGE_SEL_2P5V 0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE 0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V 2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE 0
+#define WK_PU_ENABLE 1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT 0x10
+#define PD_DRV_STRG_DEFAULT 0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB 0
+#define PD_SLW_RT_LSB 5
+#define PU_DRV_STRG_LSB 8
+#define PU_SLW_RT_LSB 13
+#define WK_PU_LSB 16
+#define INPUT_BUF_LSB 17
+#define BIAS_TRIM_LSB 19
+#define VOLTAGE_SEL_LSB 0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x00000001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x00000010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x00000100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x00010000
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x00100000
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x01000000
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002
+
#endif /* _SYSTEM_MANAGER_H_ */
--
2.2.0
next prev parent reply other threads:[~2017-01-10 5:20 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-10 5:20 [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE *** Chee Tien Fong
2017-01-10 5:20 ` [U-Boot] [PATCH v4 01/28] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2017-01-23 3:38 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 02/28] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
2017-01-23 3:40 ` Marek Vasut
2017-02-17 10:12 ` Ley Foon Tan
2017-01-10 5:20 ` [U-Boot] [PATCH v4 03/28] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
2017-01-23 3:42 ` Marek Vasut
2017-01-10 5:20 ` Chee Tien Fong [this message]
2017-01-23 3:43 ` [U-Boot] [PATCH v4 04/28] arm: socfpga: arria10: add system manager defines Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 05/28] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
2017-01-23 3:45 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 06/28] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
2017-01-23 3:46 ` Marek Vasut
2017-02-17 10:18 ` Ley Foon Tan
2017-02-17 21:12 ` Marek Vasut
2017-02-17 21:53 ` Dalon Westergreen
2017-02-17 21:57 ` Marek Vasut
2017-02-18 14:18 ` Dalon Westergreen
2017-02-18 15:20 ` Marek Vasut
2017-02-17 22:53 ` Dalon Westergreen
2017-01-10 5:20 ` [U-Boot] [PATCH v4 07/28] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
2017-01-23 3:46 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 08/28] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
2017-01-23 3:48 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 09/28] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
2017-01-23 3:49 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 10/28] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
2017-01-23 3:52 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 11/28] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
2017-01-23 3:53 ` Marek Vasut
2017-02-17 10:20 ` Ley Foon Tan
2017-02-17 21:12 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 12/28] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
2017-01-23 3:54 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 13/28] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
2017-01-23 3:55 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 14/28] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
2017-01-23 3:56 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 15/28] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
2017-01-23 3:58 ` Marek Vasut
2017-02-16 3:34 ` Ley Foon Tan
2017-02-17 7:54 ` Marek Vasut
2017-02-17 9:10 ` Ley Foon Tan
2017-02-17 21:11 ` Marek Vasut
2017-02-17 21:05 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 16/28] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
2017-01-23 3:58 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 17/28] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
2017-01-23 4:00 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 18/28] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc Chee Tien Fong
2017-01-23 4:03 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 19/28] arm: socfpga: arria10: Enable SPL for Arria 10 Chee Tien Fong
2017-01-23 4:04 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 20/28] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2017-01-23 4:05 ` Marek Vasut
2017-02-16 10:28 ` Ley Foon Tan
2017-01-10 5:20 ` [U-Boot] [PATCH v4 21/28] arm: socfpga: arria10: Added some hardware base address for Arria 10 Chee Tien Fong
2017-01-23 4:06 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 22/28] arm: socfpga: arria10: Added support for Arria 10 socdk Chee Tien Fong
2017-01-23 4:07 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 23/28] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager Chee Tien Fong
2017-01-23 4:13 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 24/28] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10 Chee Tien Fong
2017-01-23 4:16 ` Marek Vasut
2017-02-17 3:31 ` Ley Foon Tan
2017-01-10 5:20 ` [U-Boot] [PATCH v4 25/28] arm: socfpga: arria10: Added drivers for Arria10 clock manager Chee Tien Fong
2017-01-23 4:18 ` Marek Vasut
2017-02-17 8:56 ` Ley Foon Tan
2017-02-17 21:10 ` Marek Vasut
2017-02-20 2:34 ` Ley Foon Tan
2017-02-20 7:28 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 26/28] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration Chee Tien Fong
2017-01-23 4:19 ` Marek Vasut
2017-02-17 10:06 ` Ley Foon Tan
2017-01-10 5:20 ` [U-Boot] [PATCH v4 27/28] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl Chee Tien Fong
2017-01-23 4:21 ` Marek Vasut
2017-01-10 5:20 ` [U-Boot] [PATCH v4 28/28] arm: socfpga: arria10: Enable fpga driver build for SPL Chee Tien Fong
2017-01-23 4:22 ` Marek Vasut
2017-01-10 22:06 ` [U-Boot] [PATCH v4 00/28] *** SUBJECT HERE *** Marek Vasut
2017-01-11 4:03 ` Chee, Tien Fong
2017-01-11 6:59 ` Chee, Tien Fong
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