* [RFC 00/16] Enable Memory Bandwidth Allocation in Xen
@ 2017-01-10 7:42 Yi Sun
2017-01-10 7:42 ` [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
` (15 more replies)
0 siblings, 16 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
Hi, all,
We plan to bring a new PSR (Platform Shared Resource) feature called
Intel Memory Bandwidth Allocation (MBA) to Xen.
Besides the MBA enabling, we change some interfaces to make them more
general but not only for CAT.
The implementation bases on below patch set which is being reviewed.
[PATCH v4 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c
https://lists.xen.org/archives/html/xen-devel/2016-12/msg01771.html
Any comments are welcome!
Yi Sun (16):
docs: create Memory Bandwidth Allocation (MBA) feature document.
Rename sysctl/domctl interface and xsm policy to make them general.
x86: change 'cbm_type' to 'psr_val_type' to make it general.
x86: implement data structure of MBA.
x86: parse config parameters for MBA.
x86: implement init flow for MBA.
x86: implement get hw info flow for MBA.
x86: implement get value flow for MBA.
x86: implement set value flow for MBA.
tools: refactor codes to make get hw info interface be general.
tools: refactor codes to make get val be more general.
tools: refactor codes to make set val be more general.
tools: implemet get hw info flow for MBA.
tools: implemet get value flow for MBA.
tools: implemet set value flow for MBA.
docs: add MBA description in docs.
docs/features/intel_psr_mba.pandoc | 226 +++++++++++++++++++++++
docs/man/xl.pod.1.in | 35 ++++
docs/misc/xl-psr.markdown | 60 ++++++
tools/flask/policy/modules/dom0.te | 4 +-
tools/flask/policy/modules/xen.if | 2 +-
tools/libxc/include/xenctrl.h | 47 +++--
tools/libxc/xc_psr.c | 88 ++++++---
tools/libxl/libxl.h | 18 +-
tools/libxl/libxl_psr.c | 223 +++++++++++++++++++---
tools/libxl/libxl_types.idl | 22 +++
tools/libxl/xl.h | 4 +
tools/libxl/xl_cmdimpl.c | 247 ++++++++++++++++++++++---
tools/libxl/xl_cmdtable.c | 17 ++
xen/arch/x86/domctl.c | 65 ++++---
xen/arch/x86/psr.c | 359 +++++++++++++++++++++++++++++++-----
xen/arch/x86/sysctl.c | 52 ++++--
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 20 +-
xen/include/public/domctl.h | 14 +-
xen/include/public/sysctl.h | 20 +-
xen/xsm/flask/hooks.c | 8 +-
xen/xsm/flask/policy/access_vectors | 8 +-
22 files changed, 1326 insertions(+), 214 deletions(-)
create mode 100644 docs/features/intel_psr_mba.pandoc
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-02-23 20:46 ` Meng Xu
2017-01-10 7:42 ` [RFC 02/16] Rename sysctl/domctl interface and xsm policy to make them general Yi Sun
` (14 subsequent siblings)
15 siblings, 1 reply; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch creates MBA feature document in doc/features/. It
describes details for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
docs/features/intel_psr_mba.pandoc | 226 +++++++++++++++++++++++++++++++++++++
1 file changed, 226 insertions(+)
create mode 100644 docs/features/intel_psr_mba.pandoc
diff --git a/docs/features/intel_psr_mba.pandoc b/docs/features/intel_psr_mba.pandoc
new file mode 100644
index 0000000..8c04f01
--- /dev/null
+++ b/docs/features/intel_psr_mba.pandoc
@@ -0,0 +1,226 @@
+% Intel Memory Bandwidth Allocation (MBA) Feature
+% Revision 1.0
+
+\clearpage
+
+# Basics
+
+---------------- ----------------------------------------------------
+ Status: **Tech Preview**
+
+Architecture(s): Intel x86
+
+ Component(s): Hypervisor, toolstack
+
+ Hardware: MBA is supported on Skylake Server and beyond
+---------------- ----------------------------------------------------
+
+# Overview
+
+The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate
+control over memory bandwidth available per-core. This feature provides OS/VMMs
+the ability to slow misbehaving apps/VMs or create advanced closed-loop control
+system via exposing control over a credit-based throttling mechanism.
+
+## Terminology
+
+* CAT Cache Allocation Technology
+* COS/CLOS Class of Service
+* MSRs Machine Specific Registers
+* PSR Intel Platform Shared Resource
+* VMM Virtual Machine Monitor
+* THRTL Throttle value or delay value
+
+# User details
+
+* Feature Enabling:
+
+ Add "psr=mba" to boot line parameter to enable MBA feature.
+
+* xl interfaces:
+
+ 1. `psr-mba-show [domain-id]`:
+
+ Show system/domain MBA information.
+
+ 2. `psr-mba-set [OPTIONS] domain-id throttling`:
+
+ Set memory bandwidth throttling for domain.
+
+ Options:
+ '-s': Specify the socket to process, otherwise all sockets are processed.
+
+ Throttling value set in register implies memory bandwidth blocked, i.e.
+ higher throttling value results in lower bandwidth. The max throttling
+ value can be got through CPUID.
+
+ The response of the throttling value could be linear mode or non-linear
+ mode.
+
+ Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
+ if the MBA_MAX value is 90, the input precision is 10%. Values not an even
+ multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
+ delay applied) by HW automatically.
+
+ Non-linear mode: input delay values are powers-of-two from zero to the
+ MBA_MAX value from CPUID. In this case any values not a power of two will
+ be rounded down the next nearest power of two by HW automatically.
+
+# Technical details
+
+MBA is a member of Intel PSR features, it would share some base PSR
+infrastructure in Xen.
+
+## Hardware perspective
+
+MBA provides an architectural consistent method to map cores’ to a Class
+of Service (COS). This infrastructure will be shared with the previously
+introduced CAT technologies.
+
+Furthermore, MBA also defines a new range MSRs to support specifying a
+delay value (Thrtl) per COS, with details below.
+
++----------------------------+----------------+
+| MSR (per socket) | Address |
++----------------------------+----------------+
+| IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
++----------------------------+----------------+
+| ... | ... |
++----------------------------+----------------+
+| IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n (n<64) |
++----------------------------+----------------+
+
+When context switch happens, the COS of VCPU is written to per-thread
+MSR `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation
+according to the throttling value corresponding to the COS.
+
+## The relationship between MBA and CAT/CDP
+
+Generally speaking, MBA is completely independent of CAT/CDP, and any
+combination may be applied at any time, e.g. enabling MBA with CAT
+disabled.
+
+But it needs to be noticed that MBA shares COS infrastructure with CAT,
+although MBA is enumerated by different CPUID leaf from CAT (which
+indicates that the max COS of MBA may be different from CAT).
+
+## Design Overview
+
+* Core COS/Thrtl association
+
+ When enforcing Memory Bandwidth Allocation, all cores of domains have
+ the same default COS (COS0) which correspond to the same Thrtl (0).
+ The default COS is used only in hypervisor and is transparent to tool
+ stack and user.
+
+ System administrator can change PSR allocation policy at runtime by
+ tool stack. Since MBA shares COS with CAT/CDP, a COS corresponds to a
+ 2-tuple, like [CBM, Thrtl] with only-CAT enalbed, when CDP is enable,
+ the COS corresponds to a 3-tuple, like [Code_CBM, Data_CBM, Thrtl]. If
+ neither CAT nor CDP is enabled, things would be easier, one COS
+ corresponds to one Thrtl.
+
+* VCPU schedule
+
+ This part reuses CAT COS infrastructure.
+
+* Multi-sockets
+
+ Different sockets may have different MBA ability (like max COS)
+ although it is consistent on the same socket. So the capability
+ of per-socket MBA is specified.
+
+## Implementation Description
+
+* Hypervisor interfaces:
+
+ 1. Boot line param: "psr=mba" to enable the feature.
+
+ 2. SYSCTL:
+ - XEN_SYSCTL_PSR_MBA_get_info: Get system MBA information.
+
+ 3. DOMCTL:
+ - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get Throttling for a domain.
+ - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set Throttling for a domain.
+
+* xl interfaces:
+
+ 1. psr-mba-show [domain-id]
+ Show system/runtime MBA information.
+ => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
+
+ 2. psr-mba-set [OPTIONS] domain-id throttling
+ Set bandwidth throttling for a domain.
+ => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
+
+* Key data structure:
+
+ 1. Feature HW info
+
+ ```
+ struct psr_mba_hw_info {
+ unsigned int thrtl_max;
+ unsigned int cos_max;
+ unsigned int linear;
+ };
+
+ - Member `thrtl_max`
+
+ `thrtl_max` is the max throttling value to be set.
+
+ - Member `cos_max`
+
+ `cos_max` is one of the hardware info of CAT.
+
+ - Member `linear`
+
+ `thrtl_max` means the response of delay value is linear or not.
+
+ As mentioned above, MBA is a member of Intel PSR features, it would
+ share some base PSR infrastructure in Xen. So, for other data structure
+ details, please refer 'intel_psr_l2_cat.pandoc'.
+
+# Limitations
+
+MBA can only work on HW which enables it (check by CPUID).
+
+# Testing
+
+We can execute these commands to verify MBA on different HWs supporting them.
+
+For example:
+ root@:~$ xl psr-hwinfo --mba
+ Memory Bandwidth Allocation (MBA):
+ Socket ID : 0
+ Linear Mode : Enabled
+ Maximum COS : 7
+ Maximum Throttling Value: 90
+ Default Throttling Value: 0
+
+ root@:~$ xl psr-mba-set 1 0xa
+
+ root@:~$ xl psr-mba-show 1
+ Socket ID : 0
+ Default THRTL : 0
+ ID NAME CBM
+ 1 ubuntu14 0xa
+
+# Areas for improvement
+
+N/A
+
+# Known issues
+
+N/A
+
+# References
+
+"INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES" [Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
+
+# History
+
+------------------------------------------------------------------------
+Date Revision Version Notes
+---------- -------- -------- -------------------------------------------
+2017-01-10 1.0 Xen 4.9 Design document written
+---------- -------- -------- -------------------------------------------
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 02/16] Rename sysctl/domctl interface and xsm policy to make them general.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-01-10 7:42 ` [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 03/16] x86: change 'cbm_type' to 'psr_val_type' to make it general Yi Sun
` (13 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch renames sysctl/domctl interfaces and related xsm policy to
make them general but not only for CAT. Then, we can resuse the
interfaces for all allocation features.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/flask/policy/modules/dom0.te | 4 ++--
tools/flask/policy/modules/xen.if | 2 +-
tools/libxc/xc_psr.c | 34 +++++++++++++++++-----------------
xen/arch/x86/domctl.c | 36 ++++++++++++++++++------------------
xen/arch/x86/sysctl.c | 30 +++++++++++++++---------------
xen/include/public/domctl.h | 12 ++++++------
xen/include/public/sysctl.h | 12 ++++++------
xen/xsm/flask/hooks.c | 8 ++++----
xen/xsm/flask/policy/access_vectors | 8 ++++----
9 files changed, 73 insertions(+), 73 deletions(-)
diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index d0a4d91..1a376ac 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -14,7 +14,7 @@ allow dom0_t xen_t:xen {
tmem_control getscheduler setscheduler
};
allow dom0_t xen_t:xen2 {
- resource_op psr_cmt_op psr_cat_op pmu_ctrl get_symbol
+ resource_op psr_cmt_op psr_alloc_op pmu_ctrl get_symbol
get_cpu_levelling_caps get_cpu_featureset livepatch_op
gcov_op
};
@@ -39,7 +39,7 @@ allow dom0_t dom0_t:domain {
};
allow dom0_t dom0_t:domain2 {
set_cpuid gettsc settsc setscheduler set_max_evtchn set_vnumainfo
- get_vnumainfo psr_cmt_op psr_cat_op
+ get_vnumainfo psr_cmt_op psr_alloc_op
};
allow dom0_t dom0_t:resource { add remove };
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index 1aca75d..1b69b43 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -52,7 +52,7 @@ define(`create_domain_common', `
settime setdomainhandle getvcpucontext set_misc_info };
allow $1 $2:domain2 { set_cpuid settsc setscheduler setclaim
set_max_evtchn set_vnumainfo get_vnumainfo cacheflush
- psr_cmt_op psr_cat_op soft_reset };
+ psr_cmt_op psr_alloc_op soft_reset };
allow $1 $2:security check_context;
allow $1 $2:shadow enable;
allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 31c99da..0098a4d 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -274,11 +274,11 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc_op;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
- domctl.u.psr_cat_op.data = data;
+ domctl.u.psr_alloc_op.cmd = cmd;
+ domctl.u.psr_alloc_op.target = target;
+ domctl.u.psr_alloc_op.data = data;
return do_domctl(xch, &domctl);
}
@@ -310,15 +310,15 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc_op;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
+ domctl.u.psr_alloc_op.cmd = cmd;
+ domctl.u.psr_alloc_op.target = target;
rc = do_domctl(xch, &domctl);
if ( !rc )
- *data = domctl.u.psr_cat_op.data;
+ *data = domctl.u.psr_alloc_op.data;
return rc;
}
@@ -329,28 +329,28 @@ int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
int rc = -1;
DECLARE_SYSCTL;
- sysctl.cmd = XEN_SYSCTL_psr_cat_op;
- sysctl.u.psr_cat_op.target = socket;
+ sysctl.cmd = XEN_SYSCTL_psr_alloc_op;
+ sysctl.u.psr_alloc_op.target = socket;
switch ( lvl ) {
case 2:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.l2_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.l2_info.cbm_len;
+ *cos_max = sysctl.u.psr_alloc_op.u.l2_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc_op.u.l2_info.cbm_len;
*cdp_enabled = false;
}
break;
case 3:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.l3_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.l3_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_cat_op.u.l3_info.flags &
+ *cos_max = sysctl.u.psr_alloc_op.u.l3_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc_op.u.l3_info.cbm_len;
+ *cdp_enabled = sysctl.u.psr_alloc_op.u.l3_info.flags &
XEN_SYSCTL_PSR_CAT_L3_CDP;
}
break;
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 175350c..3b6534b 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1366,57 +1366,57 @@ long arch_do_domctl(
}
break;
- case XEN_DOMCTL_psr_cat_op:
- switch ( domctl->u.psr_cat_op.cmd )
+ case XEN_DOMCTL_psr_alloc_op:
+ switch ( domctl->u.psr_alloc_op.cmd )
{
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_CODE);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_DATA);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L2);
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_CODE);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_DATA);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
- &domctl->u.psr_cat_op.data,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L2);
copyback = 1;
break;
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index dede62c..cff56bb 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -172,20 +172,20 @@ long arch_do_sysctl(
break;
- case XEN_SYSCTL_psr_cat_op:
- switch ( sysctl->u.psr_cat_op.cmd )
+ case XEN_SYSCTL_psr_alloc_op:
+ switch ( sysctl->u.psr_alloc_op.cmd )
{
case XEN_SYSCTL_PSR_CAT_get_l3_info:
{
uint32_t dat[3];
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
PSR_CBM_TYPE_L3, dat, 3);
if ( !ret )
{
- sysctl->u.psr_cat_op.u.l3_info.cbm_len = dat[CBM_LEN];
- sysctl->u.psr_cat_op.u.l3_info.cos_max = dat[COS_MAX];
- sysctl->u.psr_cat_op.u.l3_info.flags = dat[CDP_FLAG];
+ sysctl->u.psr_alloc_op.u.l3_info.cbm_len = dat[CBM_LEN];
+ sysctl->u.psr_alloc_op.u.l3_info.cos_max = dat[COS_MAX];
+ sysctl->u.psr_alloc_op.u.l3_info.flags = dat[CDP_FLAG];
} else {
/*
* Check if CDP is enabled.
@@ -193,32 +193,32 @@ long arch_do_sysctl(
* Per spec, L3 CAT and CDP cannot co-exist. So, we need replace
* output values to CDP's if it is enabled.
*/
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
PSR_CBM_TYPE_L3_CODE, dat, 3);
if ( !ret )
{
- sysctl->u.psr_cat_op.u.l3_info.cbm_len = dat[CBM_LEN];
- sysctl->u.psr_cat_op.u.l3_info.cos_max = dat[COS_MAX];
- sysctl->u.psr_cat_op.u.l3_info.flags = dat[CDP_FLAG];
+ sysctl->u.psr_alloc_op.u.l3_info.cbm_len = dat[CBM_LEN];
+ sysctl->u.psr_alloc_op.u.l3_info.cos_max = dat[COS_MAX];
+ sysctl->u.psr_alloc_op.u.l3_info.flags = dat[CDP_FLAG];
}
}
- if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
ret = -EFAULT;
break;
}
case XEN_SYSCTL_PSR_CAT_get_l2_info:
{
uint32_t dat[2];
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
PSR_CBM_TYPE_L2, dat, 2);
if ( ret )
break;
- sysctl->u.psr_cat_op.u.l2_info.cbm_len = dat[CBM_LEN];
- sysctl->u.psr_cat_op.u.l2_info.cos_max = dat[COS_MAX];
+ sysctl->u.psr_alloc_op.u.l2_info.cbm_len = dat[CBM_LEN];
+ sysctl->u.psr_alloc_op.u.l2_info.cos_max = dat[COS_MAX];
- if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
ret = -EFAULT;
break;
}
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 523a2cd..f5b1466 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1131,7 +1131,7 @@ struct xen_domctl_monitor_op {
typedef struct xen_domctl_monitor_op xen_domctl_monitor_op_t;
DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
-struct xen_domctl_psr_cat_op {
+struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE 2
@@ -1140,12 +1140,12 @@ struct xen_domctl_psr_cat_op {
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
- uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
+ uint32_t cmd; /* IN: XEN_DOMCTL_PSR_*_OP_* */
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
};
-typedef struct xen_domctl_psr_cat_op xen_domctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_cat_op_t);
+typedef struct xen_domctl_psr_alloc_op xen_domctl_psr_alloc_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_alloc_op_t);
struct xen_domctl {
uint32_t cmd;
@@ -1222,7 +1222,7 @@ struct xen_domctl {
#define XEN_DOMCTL_setvnumainfo 74
#define XEN_DOMCTL_psr_cmt_op 75
#define XEN_DOMCTL_monitor_op 77
-#define XEN_DOMCTL_psr_cat_op 78
+#define XEN_DOMCTL_psr_alloc_op 78
#define XEN_DOMCTL_soft_reset 79
#define XEN_DOMCTL_gdbsx_guestmemio 1000
#define XEN_DOMCTL_gdbsx_pausevcpu 1001
@@ -1285,7 +1285,7 @@ struct xen_domctl {
struct xen_domctl_vnuma vnuma;
struct xen_domctl_psr_cmt_op psr_cmt_op;
struct xen_domctl_monitor_op monitor_op;
- struct xen_domctl_psr_cat_op psr_cat_op;
+ struct xen_domctl_psr_alloc_op psr_alloc_op;
uint8_t pad[128];
} u;
};
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index cbf5372..71edcf0 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -745,8 +745,8 @@ DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
-struct xen_sysctl_psr_cat_op {
- uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
+struct xen_sysctl_psr_alloc_op {
+ uint32_t cmd; /* IN: XEN_SYSCTL_PSR_* */
uint32_t target; /* IN */
union {
struct {
@@ -762,8 +762,8 @@ struct xen_sysctl_psr_cat_op {
} l2_info;
} u;
};
-typedef struct xen_sysctl_psr_cat_op xen_sysctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_cat_op_t);
+typedef struct xen_sysctl_psr_alloc_op xen_sysctl_psr_alloc_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_alloc_op_t);
#define XEN_SYSCTL_TMEM_OP_ALL_CLIENTS 0xFFFFU
@@ -1117,7 +1117,7 @@ struct xen_sysctl {
#define XEN_SYSCTL_gcov_op 20
#define XEN_SYSCTL_psr_cmt_op 21
#define XEN_SYSCTL_pcitopoinfo 22
-#define XEN_SYSCTL_psr_cat_op 23
+#define XEN_SYSCTL_psr_alloc_op 23
#define XEN_SYSCTL_tmem_op 24
#define XEN_SYSCTL_get_cpu_levelling_caps 25
#define XEN_SYSCTL_get_cpu_featureset 26
@@ -1145,7 +1145,7 @@ struct xen_sysctl {
struct xen_sysctl_scheduler_op scheduler_op;
struct xen_sysctl_gcov_op gcov_op;
struct xen_sysctl_psr_cmt_op psr_cmt_op;
- struct xen_sysctl_psr_cat_op psr_cat_op;
+ struct xen_sysctl_psr_alloc_op psr_alloc_op;
struct xen_sysctl_tmem_op tmem_op;
struct xen_sysctl_cpu_levelling_caps cpu_levelling_caps;
struct xen_sysctl_cpu_featureset cpu_featureset;
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 040a251..2c2ae86 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -742,8 +742,8 @@ static int flask_domctl(struct domain *d, int cmd)
case XEN_DOMCTL_psr_cmt_op:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CMT_OP);
- case XEN_DOMCTL_psr_cat_op:
- return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CAT_OP);
+ case XEN_DOMCTL_psr_alloc_op:
+ return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_ALLOC_OP);
case XEN_DOMCTL_soft_reset:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
@@ -806,9 +806,9 @@ static int flask_sysctl(int cmd)
case XEN_SYSCTL_psr_cmt_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PSR_CMT_OP, NULL);
- case XEN_SYSCTL_psr_cat_op:
+ case XEN_SYSCTL_psr_alloc_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
- XEN2__PSR_CAT_OP, NULL);
+ XEN2__PSR_ALLOC_OP, NULL);
case XEN_SYSCTL_tmem_op:
return domain_has_xen(current->domain, XEN__TMEM_CONTROL);
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 92e6da9..14772f4 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -85,8 +85,8 @@ class xen2
resource_op
# XEN_SYSCTL_psr_cmt_op
psr_cmt_op
-# XEN_SYSCTL_psr_cat_op
- psr_cat_op
+# XEN_SYSCTL_psr_alloc_op
+ psr_alloc_op
# XENPF_get_symbol
get_symbol
# PMU control
@@ -244,8 +244,8 @@ class domain2
mem_paging
# XENMEM_sharing_op
mem_sharing
-# XEN_DOMCTL_psr_cat_op
- psr_cat_op
+# XEN_DOMCTL_psr_alloc_op
+ psr_alloc_op
}
# Similar to class domain, but primarily contains domctls related to HVM domains
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 03/16] x86: change 'cbm_type' to 'psr_val_type' to make it general.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-01-10 7:42 ` [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-01-10 7:42 ` [RFC 02/16] Rename sysctl/domctl interface and xsm policy to make them general Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 04/16] x86: implement data structure of MBA Yi Sun
` (12 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch changes 'cbm_type' to 'psr_val_type' to make it general.
Then, we can reuse this for every psr allocation feature.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/domctl.c | 16 +++++-----
xen/arch/x86/psr.c | 80 +++++++++++++++++++++++------------------------
xen/arch/x86/sysctl.c | 6 ++--
xen/include/asm-x86/psr.h | 16 +++++-----
4 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 3b6534b..1f83ab2 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1372,52 +1372,52 @@ long arch_do_domctl(
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3);
+ PSR_VAL_TYPE_L3);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_CODE);
+ PSR_VAL_TYPE_L3_CODE);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_DATA);
+ PSR_VAL_TYPE_L3_DATA);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L2);
+ PSR_VAL_TYPE_L2);
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3);
+ PSR_VAL_TYPE_L3);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_CODE);
+ PSR_VAL_TYPE_L3_CODE);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_DATA);
+ PSR_VAL_TYPE_L3_DATA);
copyback = 1;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L2);
+ PSR_VAL_TYPE_L2);
copyback = 1;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index ed1ec2f..2c69cc0 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -118,11 +118,11 @@ struct feat_ops {
/* get_max_cos_max is used to get feature's cos_max. */
unsigned int (*get_max_cos_max)(const struct feat_node *feat);
/* get_feat_info is used to get feature HW info. */
- bool (*get_feat_info)(const struct feat_node *feat, enum cbm_type type,
+ bool (*get_feat_info)(const struct feat_node *feat, enum psr_val_type type,
uint32_t dat[], uint32_t array_len);
/* get_val is used to get feature COS register value. */
bool (*get_val)(const struct feat_node *feat, unsigned int cos,
- enum cbm_type type, uint64_t *val);
+ enum psr_val_type type, uint64_t *val);
/*
* get_cos_num is used to get the COS registers amount used by the
* feature for one setting, e.g. CDP uses 2 COSs but CAT uses 1.
@@ -150,14 +150,14 @@ struct feat_ops {
int (*set_new_val)(uint64_t val[],
const struct feat_node *feat,
unsigned int old_cos,
- enum cbm_type type,
+ enum psr_val_type type,
uint64_t m);
/*
* get_cos_max_from_type is used to get the cos_max value of the feature
* according to input type.
*/
unsigned int (*get_cos_max_from_type)(const struct feat_node *feat,
- enum cbm_type type);
+ enum psr_val_type type);
/*
* compare_val is used in set value process to compare if the
* input value array can match all the features' COS registers values
@@ -350,10 +350,10 @@ static unsigned int l3_cat_get_max_cos_max(const struct feat_node *feat)
}
static bool l3_cat_get_feat_info(const struct feat_node *feat,
- enum cbm_type type,
+ enum psr_val_type type,
uint32_t dat[], uint32_t array_len)
{
- if ( !dat || 3 > array_len || type != PSR_CBM_TYPE_L3 )
+ if ( !dat || 3 > array_len || type != PSR_VAL_TYPE_L3 )
return false;
dat[CBM_LEN] = feat->info.l3_cat_info.cbm_len;
@@ -364,9 +364,9 @@ static bool l3_cat_get_feat_info(const struct feat_node *feat,
}
static bool l3_cat_get_val(const struct feat_node *feat, unsigned int cos,
- enum cbm_type type, uint64_t *val)
+ enum psr_val_type type, uint64_t *val)
{
- if ( type != PSR_CBM_TYPE_L3 )
+ if ( type != PSR_VAL_TYPE_L3 )
return false;
if ( cos > feat->info.l3_cat_info.cos_max )
@@ -401,10 +401,10 @@ static int l3_cat_get_old_val(uint64_t val[],
static int l3_cat_set_new_val(uint64_t val[],
const struct feat_node *feat,
unsigned int old_cos,
- enum cbm_type type,
+ enum psr_val_type type,
uint64_t m)
{
- if ( type != PSR_CBM_TYPE_L3 )
+ if ( type != PSR_VAL_TYPE_L3 )
/* L3 CAT uses one COS. Skip it. */
return 1;
@@ -418,9 +418,9 @@ static int l3_cat_set_new_val(uint64_t val[],
}
static unsigned int l3_cat_get_cos_max_from_type(const struct feat_node *feat,
- enum cbm_type type)
+ enum psr_val_type type)
{
- if ( type != PSR_CBM_TYPE_L3 )
+ if ( type != PSR_VAL_TYPE_L3 )
return 0;
return feat->info.l3_cat_info.cos_max;
@@ -557,11 +557,11 @@ static unsigned int l3_cdp_get_max_cos_max(const struct feat_node *feat)
}
static bool l3_cdp_get_feat_info(const struct feat_node *feat,
- enum cbm_type type,
+ enum psr_val_type type,
uint32_t dat[], uint32_t array_len)
{
if ( !dat || 3 > array_len ||
- ( type != PSR_CBM_TYPE_L3_DATA && type != PSR_CBM_TYPE_L3_CODE) )
+ ( type != PSR_VAL_TYPE_L3_DATA && type != PSR_VAL_TYPE_L3_CODE) )
return false;
dat[CBM_LEN] = feat->info.l3_cdp_info.cbm_len;
@@ -572,16 +572,16 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
}
static bool l3_cdp_get_val(const struct feat_node *feat, unsigned int cos,
- enum cbm_type type, uint64_t *val)
+ enum psr_val_type type, uint64_t *val)
{
- if ( type != PSR_CBM_TYPE_L3_DATA && type != PSR_CBM_TYPE_L3_CODE )
+ if ( type != PSR_VAL_TYPE_L3_DATA && type != PSR_VAL_TYPE_L3_CODE )
return false;
if ( cos > feat->info.l3_cdp_info.cos_max )
/* Use default value. */
cos = 0;
- if ( type == PSR_CBM_TYPE_L3_DATA )
+ if ( type == PSR_VAL_TYPE_L3_DATA )
*val = get_cdp_data(feat, cos);
else
*val = get_cdp_code(feat, cos);
@@ -614,17 +614,17 @@ static int l3_cdp_get_old_val(uint64_t val[],
static int l3_cdp_set_new_val(uint64_t val[],
const struct feat_node *feat,
unsigned int old_cos,
- enum cbm_type type,
+ enum psr_val_type type,
uint64_t m)
{
- if ( type != PSR_CBM_TYPE_L3_DATA && type != PSR_CBM_TYPE_L3_CODE )
+ if ( type != PSR_VAL_TYPE_L3_DATA && type != PSR_VAL_TYPE_L3_CODE )
/* CDP uses two COSs. Skip them outside. */
return 2;
if ( !psr_check_cbm(feat->info.l3_cdp_info.cbm_len, m) )
return -EINVAL;
- if ( type == PSR_CBM_TYPE_L3_DATA )
+ if ( type == PSR_VAL_TYPE_L3_DATA )
val[0] = m;
else
val[1] = m;
@@ -634,9 +634,9 @@ static int l3_cdp_set_new_val(uint64_t val[],
}
static unsigned int l3_cdp_get_cos_max_from_type(const struct feat_node *feat,
- enum cbm_type type)
+ enum psr_val_type type)
{
- if ( type != PSR_CBM_TYPE_L3_DATA && type != PSR_CBM_TYPE_L3_CODE )
+ if ( type != PSR_VAL_TYPE_L3_DATA && type != PSR_VAL_TYPE_L3_CODE )
return 0;
return feat->info.l3_cdp_info.cos_max;
@@ -775,10 +775,10 @@ static unsigned int l2_cat_get_max_cos_max(const struct feat_node *feat)
}
static bool l2_cat_get_feat_info(const struct feat_node *feat,
- enum cbm_type type,
+ enum psr_val_type type,
uint32_t dat[], uint32_t array_len)
{
- if ( !dat || 2 > array_len || type != PSR_CBM_TYPE_L2 )
+ if ( !dat || 2 > array_len || type != PSR_VAL_TYPE_L2 )
return false;
dat[CBM_LEN] = feat->info.l2_cat_info.cbm_len;
@@ -788,9 +788,9 @@ static bool l2_cat_get_feat_info(const struct feat_node *feat,
}
static bool l2_cat_get_val(const struct feat_node *feat, unsigned int cos,
- enum cbm_type type, uint64_t *val)
+ enum psr_val_type type, uint64_t *val)
{
- if ( type != PSR_CBM_TYPE_L2 )
+ if ( type != PSR_VAL_TYPE_L2 )
return false;
if ( cos > feat->info.l2_cat_info.cos_max )
@@ -824,10 +824,10 @@ static int l2_cat_get_old_val(uint64_t val[],
static int l2_cat_set_new_val(uint64_t val[],
const struct feat_node *feat,
unsigned int old_cos,
- enum cbm_type type,
+ enum psr_val_type type,
uint64_t m)
{
- if ( type != PSR_CBM_TYPE_L2 )
+ if ( type != PSR_VAL_TYPE_L2 )
return 1;
if ( !psr_check_cbm(feat->info.l2_cat_info.cbm_len, m) )
@@ -840,9 +840,9 @@ static int l2_cat_set_new_val(uint64_t val[],
}
static unsigned int l2_cat_get_cos_max_from_type(const struct feat_node *feat,
- enum cbm_type type)
+ enum psr_val_type type)
{
- if ( type != PSR_CBM_TYPE_L2 )
+ if ( type != PSR_VAL_TYPE_L2 )
return 0;
return feat->info.l2_cat_info.cos_max;
@@ -1134,7 +1134,7 @@ static struct psr_socket_info *get_socket_info(unsigned int socket)
return socket_info + socket;
}
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_val_type type,
uint32_t dat[], uint32_t array_len)
{
struct psr_socket_info *info = get_socket_info(socket);
@@ -1151,7 +1151,7 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
}
int psr_get_val(struct domain *d, unsigned int socket,
- uint64_t *val, enum cbm_type type)
+ uint64_t *val, enum psr_val_type type)
{
const struct psr_socket_info *info = get_socket_info(socket);
unsigned int cos = d->arch.psr_cos_ids[socket];
@@ -1187,7 +1187,7 @@ static int get_old_set_new(uint64_t *val,
uint32_t array_len,
const struct psr_socket_info *info,
unsigned int old_cos,
- enum cbm_type type,
+ enum psr_val_type type,
uint64_t m)
{
const struct feat_node *feat_tmp;
@@ -1226,7 +1226,7 @@ static int get_old_set_new(uint64_t *val,
}
static int find_cos(const uint64_t *val, uint32_t array_len,
- enum cbm_type type,
+ enum psr_val_type type,
const struct psr_socket_info *info)
{
unsigned int cos;
@@ -1309,7 +1309,7 @@ static bool exceeds_cos_max(const uint64_t *val,
static int alloc_new_cos(const struct psr_socket_info *info,
const uint64_t *val, uint32_t array_len,
unsigned int old_cos,
- enum cbm_type type)
+ enum psr_val_type type)
{
unsigned int cos;
unsigned int cos_max = 0;
@@ -1419,7 +1419,7 @@ static int write_psr_msr(unsigned int socket, unsigned int cos,
}
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t val, enum cbm_type type)
+ uint64_t val, enum psr_val_type type)
{
unsigned int old_cos;
int cos, ret;
@@ -1434,14 +1434,14 @@ int psr_set_val(struct domain *d, unsigned int socket,
/* Judge if feature is enabled. */
switch ( type ) {
- case PSR_CBM_TYPE_L3:
+ case PSR_VAL_TYPE_L3:
flag = PSR_SOCKET_L3_CAT;
break;
- case PSR_CBM_TYPE_L3_DATA:
- case PSR_CBM_TYPE_L3_CODE:
+ case PSR_VAL_TYPE_L3_DATA:
+ case PSR_VAL_TYPE_L3_CODE:
flag = PSR_SOCKET_L3_CDP;
break;
- case PSR_CBM_TYPE_L2:
+ case PSR_VAL_TYPE_L2:
flag = PSR_SOCKET_L2_CAT;
break;
default:
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index cff56bb..739909b 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -179,7 +179,7 @@ long arch_do_sysctl(
{
uint32_t dat[3];
ret = psr_get_info(sysctl->u.psr_alloc_op.target,
- PSR_CBM_TYPE_L3, dat, 3);
+ PSR_VAL_TYPE_L3, dat, 3);
if ( !ret )
{
@@ -194,7 +194,7 @@ long arch_do_sysctl(
* output values to CDP's if it is enabled.
*/
ret = psr_get_info(sysctl->u.psr_alloc_op.target,
- PSR_CBM_TYPE_L3_CODE, dat, 3);
+ PSR_VAL_TYPE_L3_CODE, dat, 3);
if ( !ret )
{
sysctl->u.psr_alloc_op.u.l3_info.cbm_len = dat[CBM_LEN];
@@ -211,7 +211,7 @@ long arch_do_sysctl(
{
uint32_t dat[2];
ret = psr_get_info(sysctl->u.psr_alloc_op.target,
- PSR_CBM_TYPE_L2, dat, 2);
+ PSR_VAL_TYPE_L2, dat, 2);
if ( ret )
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index ee65fe5..4d52918 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -52,11 +52,11 @@ struct psr_cmt {
struct psr_cmt_l3 l3;
};
-enum cbm_type {
- PSR_CBM_TYPE_L3,
- PSR_CBM_TYPE_L3_CODE,
- PSR_CBM_TYPE_L3_DATA,
- PSR_CBM_TYPE_L2,
+enum psr_val_type {
+ PSR_VAL_TYPE_L3,
+ PSR_VAL_TYPE_L3_CODE,
+ PSR_VAL_TYPE_L3_DATA,
+ PSR_VAL_TYPE_L2,
};
extern struct psr_cmt *psr_cmt;
@@ -70,12 +70,12 @@ int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
void psr_ctxt_switch_to(struct domain *d);
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_val_type type,
uint32_t dat[], uint32_t array_len);
int psr_get_val(struct domain *d, unsigned int socket,
- uint64_t *val, enum cbm_type type);
+ uint64_t *val, enum psr_val_type type);
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t val, enum cbm_type type);
+ uint64_t val, enum psr_val_type type);
int psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 04/16] x86: implement data structure of MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (2 preceding siblings ...)
2017-01-10 7:42 ` [RFC 03/16] x86: change 'cbm_type' to 'psr_val_type' to make it general Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 05/16] x86: parse config parameters for MBA Yi Sun
` (11 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements main data structures of MBA.
Like CAT features, MBA HW info has cos_max which means the max cos
registers number, and thrtl_max which means the max throttle value
(delay value). It also have a flag to represent if the throttle
value is linear or not.
One COS register of MBA stores a throttle value for one or more
domains. That means the transaction time between L2 cache and next
level memory will be delayed.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/psr.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 2c69cc0..58d3555 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -27,17 +27,23 @@
* - CDP Code and Data Prioritization
* - COS/CLOS Class of Service. Also mean COS registers.
* - COS_MAX Max number of COS for the feature (minus 1)
+ * - MBA Memory Bandwidth Allocation
* - MSRs Machine Specific Registers
* - PSR Intel Platform Shared Resource
+ * - THRTL_MAX Max throttle value (delay value) of MBA
*/
#define PSR_CMT (1<<0)
#define PSR_CAT (1<<1)
#define PSR_CDP (1<<2)
+#define PSR_MBA (1<<3)
#define CAT_CBM_LEN_MASK 0x1f
#define CAT_COS_MAX_MASK 0xffff
+/* Linear bit. */
+#define MBA_LINEAR (1<<2)
+
/*
* Per SDM 17.17.3.3 'Cache Allocation Technology: Cache Mask Configuration',
* the MSRs range from 0C90H through 0D0FH (inclusive), enables support for
@@ -79,6 +85,14 @@ enum psr_feat_type {
PSR_SOCKET_L3_CAT = 0,
PSR_SOCKET_L3_CDP,
PSR_SOCKET_L2_CAT,
+ PSR_SOCKET_MBA = 16,
+};
+
+/* MBA HW info data structure. */
+struct psr_mba_hw_info {
+ unsigned int thrtl_max;
+ unsigned int cos_max;
+ unsigned int linear;
};
/* CAT/CDP HW info data structure. */
@@ -93,6 +107,7 @@ struct feat_hw_info {
struct psr_cat_hw_info l3_cat_info;
struct psr_cat_hw_info l3_cdp_info;
struct psr_cat_hw_info l2_cat_info;
+ struct psr_mba_hw_info mba_info;
};
};
--
1.9.1
_______________________________________________
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https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 05/16] x86: parse config parameters for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (3 preceding siblings ...)
2017-01-10 7:42 ` [RFC 04/16] x86: implement data structure of MBA Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 06/16] x86: implement init flow " Yi Sun
` (10 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch parses MBA parameters in configuration file. The parameter
means whether MBA is supported.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/psr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 58d3555..eca9c43 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -969,6 +969,7 @@ static void __init parse_psr_param(char *s)
parse_psr_bool(s, val_str, "cmt", PSR_CMT);
parse_psr_bool(s, val_str, "cat", PSR_CAT);
parse_psr_bool(s, val_str, "cdp", PSR_CDP);
+ parse_psr_bool(s, val_str, "mba", PSR_MBA);
if ( val_str && !strcmp(s, "rmid_max") )
opt_rmid_max = simple_strtoul(val_str, NULL, 0);
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 06/16] x86: implement init flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (4 preceding siblings ...)
2017-01-10 7:42 ` [RFC 05/16] x86: parse config parameters for MBA Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 07/16] x86: implement get hw info " Yi Sun
` (9 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements init flow for MBA including its callback
functions.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/psr.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++-
xen/include/asm-x86/psr.h | 1 +
2 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index eca9c43..e2ca6fb 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -41,6 +41,7 @@
#define CAT_CBM_LEN_MASK 0x1f
#define CAT_COS_MAX_MASK 0xffff
+#define MBA_THRTL_MAX_MASK 0xfff
/* Linear bit. */
#define MBA_LINEAR (1<<2)
@@ -265,6 +266,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
static struct feat_node *feat_l3_cat;
static struct feat_node *feat_l3_cdp;
static struct feat_node *feat_l2_cat;
+static struct feat_node *feat_mba;
/* Common functions. */
static void free_feature(struct psr_socket_info *info)
@@ -299,6 +301,12 @@ static void free_feature(struct psr_socket_info *info)
xfree(feat_l2_cat);
feat_l2_cat = NULL;
}
+
+ if ( feat_mba )
+ {
+ xfree(feat_mba);
+ feat_mba = NULL;
+ }
}
static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
@@ -934,6 +942,53 @@ struct feat_ops l2_cat_ops = {
.write_msr = l2_cat_write_msr,
};
+/* MBA callback functions implementation. */
+static void mba_init_feature(unsigned int eax, unsigned int ebx,
+ unsigned int ecx, unsigned int edx,
+ struct feat_node *feat,
+ struct psr_socket_info *info)
+{
+ struct psr_mba_hw_info mba_info;
+ unsigned int socket;
+
+ /* No valid values so do not enable the feature. */
+ if ( !eax || !edx )
+ return;
+
+ mba_info.thrtl_max = (eax & 0xfff) + 1;
+ mba_info.cos_max = min(opt_cos_max, edx & CAT_COS_MAX_MASK);
+ if ( ecx & MBA_LINEAR )
+ mba_info.linear = 1;
+
+ /* cos=0 is reserved as default thrtl(0), the max bandwidth. */
+ feat->cos_reg_val[0] = 0;
+
+ feat->feature = PSR_SOCKET_MBA;
+ __set_bit(PSR_SOCKET_MBA, &info->feat_mask);
+
+ feat->info.mba_info = mba_info;
+
+ info->nr_feat++;
+
+ /* Add this feature into list. */
+ list_add_tail(&feat->list, &info->feat_list);
+
+ socket = cpu_to_socket(smp_processor_id());
+ printk(XENLOG_INFO "MBA: enabled on socket %u, cos_max:%u, thrtl_max:%u, linear:%u.\n",
+ socket, feat->info.mba_info.cos_max,
+ feat->info.mba_info.thrtl_max, feat->info.mba_info.linear);
+}
+
+static unsigned int mba_get_max_cos_max(const struct feat_node *feat)
+{
+ return feat->info.mba_info.cos_max;
+}
+
+struct feat_ops mba_ops = {
+ .init_feature = mba_init_feature,
+ .get_max_cos_max = mba_get_max_cos_max,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -1659,6 +1714,20 @@ static int cpu_prepare_work(unsigned int cpu)
return -ENOMEM;
}
+ if ( feat_mba == NULL &&
+ (feat_mba = xzalloc(struct feat_node)) == NULL )
+ {
+ xfree(feat_l3_cat);
+ feat_l3_cat = NULL;
+
+ xfree(feat_l3_cdp);
+ feat_l3_cdp = NULL;
+
+ xfree(feat_l2_cat);
+ feat_l2_cat = NULL;
+ return -ENOMEM;
+ }
+
return 0;
}
@@ -1712,6 +1781,18 @@ static void cpu_init_work(void)
feat_tmp->ops = l2_cat_ops;
feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info);
}
+
+ cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
+ if ( ebx & PSR_RESOURCE_TYPE_MBA )
+ {
+ feat_tmp = feat_mba;
+ feat_mba = NULL;
+
+ /* Initialize MBA according to CPUID. */
+ cpuid_count(PSR_CPUID_LEVEL_CAT, 3, &eax, &ebx, &ecx, &edx);
+ feat_tmp->ops = mba_ops;
+ feat_tmp->ops.init_feature(eax, ebx, ecx, edx, feat_tmp, info);
+ }
}
static void cpu_fini_work(unsigned int cpu)
@@ -1817,7 +1898,7 @@ static int __init psr_presmp_init(void)
if ( (opt_psr & PSR_CMT) && opt_rmid_max )
init_psr_cmt(opt_rmid_max);
- if ( opt_psr & PSR_CAT )
+ if ( opt_psr & (PSR_CAT | PSR_MBA) )
init_psr();
if ( psr_cpu_prepare(0) )
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 4d52918..9dd7782 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -24,6 +24,7 @@
/* Resource Type Enumeration */
#define PSR_RESOURCE_TYPE_L3 0x2
#define PSR_RESOURCE_TYPE_L2 0x4
+#define PSR_RESOURCE_TYPE_MBA 0x8
/* L3 Monitoring Features */
#define PSR_CMT_L3_OCCUPANCY 0x1
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 07/16] x86: implement get hw info flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (5 preceding siblings ...)
2017-01-10 7:42 ` [RFC 06/16] x86: implement init flow " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 08/16] x86: implement get value " Yi Sun
` (8 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements get HW info flow for MBA including its callback
function and sysctl interface.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/psr.c | 15 +++++++++++++++
xen/arch/x86/sysctl.c | 16 ++++++++++++++++
xen/include/asm-x86/psr.h | 3 +++
xen/include/public/sysctl.h | 8 ++++++++
4 files changed, 42 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index e2ca6fb..52452a7 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -984,9 +984,24 @@ static unsigned int mba_get_max_cos_max(const struct feat_node *feat)
return feat->info.mba_info.cos_max;
}
+static bool mba_get_feat_info(const struct feat_node *feat,
+ enum psr_val_type type,
+ uint32_t dat[], uint32_t array_len)
+{
+ if ( !dat || 3 > array_len || type != PSR_VAL_TYPE_MBA )
+ return false;
+
+ dat[THRTL_MAX] = feat->info.mba_info.thrtl_max;
+ dat[COS_MAX] = feat->info.mba_info.cos_max;
+ dat[LINEAR] = feat->info.mba_info.linear;
+
+ return true;
+}
+
struct feat_ops mba_ops = {
.init_feature = mba_init_feature,
.get_max_cos_max = mba_get_max_cos_max,
+ .get_feat_info = mba_get_feat_info,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 739909b..3dd0aa3 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -222,6 +222,22 @@ long arch_do_sysctl(
ret = -EFAULT;
break;
}
+ case XEN_SYSCTL_PSR_MBA_get_info:
+ {
+ uint32_t dat[3];
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
+ PSR_VAL_TYPE_MBA, dat, 3);
+ if ( ret )
+ break;
+
+ sysctl->u.psr_alloc_op.u.mba_info.thrtl_max = dat[THRTL_MAX];
+ sysctl->u.psr_alloc_op.u.mba_info.cos_max = dat[COS_MAX];
+ sysctl->u.psr_alloc_op.u.mba_info.linear = dat[LINEAR];
+
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
+ ret = -EFAULT;
+ break;
+ }
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 9dd7782..a37abdf 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -39,6 +39,8 @@
#define CBM_LEN 0
#define COS_MAX 1
#define CDP_FLAG 2
+#define THRTL_MAX 0
+#define LINEAR 2
struct psr_cmt_l3 {
unsigned int features;
@@ -58,6 +60,7 @@ enum psr_val_type {
PSR_VAL_TYPE_L3_CODE,
PSR_VAL_TYPE_L3_DATA,
PSR_VAL_TYPE_L2,
+ PSR_VAL_TYPE_MBA,
};
extern struct psr_cmt *psr_cmt;
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 71edcf0..f14c921 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -745,6 +745,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
+#define XEN_SYSCTL_PSR_MBA_get_info 2
struct xen_sysctl_psr_alloc_op {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_* */
uint32_t target; /* IN */
@@ -760,6 +761,13 @@ struct xen_sysctl_psr_alloc_op {
uint32_t cbm_len; /* OUT: CBM length */
uint32_t cos_max; /* OUT: Maximum COS */
} l2_info;
+
+ struct {
+ uint32_t thrtl_max; /* OUT: Maximum throttle */
+ uint32_t cos_max; /* OUT: Maximum COS */
+#define XEN_SYSCTL_PSR_MBA_LINEAR (1u << 0)
+ uint32_t linear; /* OUT: Linear mode */
+ } mba_info;
} u;
};
typedef struct xen_sysctl_psr_alloc_op xen_sysctl_psr_alloc_op_t;
--
1.9.1
_______________________________________________
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https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 08/16] x86: implement get value flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (6 preceding siblings ...)
2017-01-10 7:42 ` [RFC 07/16] x86: implement get hw info " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 09/16] x86: implement set " Yi Sun
` (7 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements get value callback function and domctl
interface for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/domctl.c | 7 +++++++
xen/arch/x86/psr.c | 15 +++++++++++++++
xen/include/public/domctl.h | 1 +
3 files changed, 23 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 1f83ab2..6145cf4 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1421,6 +1421,13 @@ long arch_do_domctl(
copyback = 1;
break;
+ case XEN_DOMCTL_PSR_MBA_OP_GET_THRTL:
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &domctl->u.psr_alloc_op.data,
+ PSR_VAL_TYPE_MBA);
+ copyback = 1;
+ break;
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 52452a7..fd95a6d 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -998,10 +998,25 @@ static bool mba_get_feat_info(const struct feat_node *feat,
return true;
}
+static bool mba_get_val(const struct feat_node *feat, unsigned int cos,
+ enum psr_val_type type, uint64_t *val)
+{
+ if ( type != PSR_VAL_TYPE_MBA )
+ return false;
+
+ if ( cos > feat->info.mba_info.cos_max )
+ cos = 0;
+
+ *val = feat->cos_reg_val[cos];
+
+ return true;
+}
+
struct feat_ops mba_ops = {
.init_feature = mba_init_feature,
.get_max_cos_max = mba_get_max_cos_max,
.get_feat_info = mba_get_feat_info,
+ .get_val = mba_get_val,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index f5b1466..2de7214 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1140,6 +1140,7 @@ struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_*_OP_* */
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 09/16] x86: implement set value flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (7 preceding siblings ...)
2017-01-10 7:42 ` [RFC 08/16] x86: implement get value " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 10/16] tools: refactor codes to make get hw info interface be general Yi Sun
` (6 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements set value flow for MBA including its callback
function and domctl interface.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/domctl.c | 6 ++
xen/arch/x86/psr.c | 152 +++++++++++++++++++++++++++++++++++++---
xen/include/asm-x86/msr-index.h | 1 +
xen/include/public/domctl.h | 1 +
4 files changed, 149 insertions(+), 11 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 6145cf4..a7cf690 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1393,6 +1393,12 @@ long arch_do_domctl(
PSR_VAL_TYPE_L2);
break;
+ case XEN_DOMCTL_PSR_MBA_OP_SET_THRTL:
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
+ PSR_VAL_TYPE_MBA);
+ break;
+
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&domctl->u.psr_alloc_op.data,
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index fd95a6d..965ed17 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -332,6 +332,14 @@ static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
return 1;
}
+static bool_t psr_check_thrtl(unsigned int thrtl_max, uint64_t thrtl)
+{
+ if ( thrtl > thrtl_max )
+ return 0;
+
+ return 1;
+}
+
/* L3 CAT callback functions implementation. */
static void l3_cat_init_feature(unsigned int eax, unsigned int ebx,
unsigned int ecx, unsigned int edx,
@@ -1012,11 +1020,121 @@ static bool mba_get_val(const struct feat_node *feat, unsigned int cos,
return true;
}
+static unsigned int mba_get_cos_num(const struct feat_node *feat)
+{
+ /* MBA uses one COS. */
+ return 1;
+}
+
+static int mba_get_old_val(uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int old_cos)
+{
+ if ( old_cos > feat->info.mba_info.cos_max )
+ /* Use default value. */
+ old_cos = 0;
+
+ val[0] = feat->cos_reg_val[old_cos];
+
+ /* MBA uses one COS. */
+ return 1;
+}
+
+static int mba_set_new_val(uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int old_cos,
+ enum psr_val_type type,
+ uint64_t m)
+{
+ if ( type != PSR_VAL_TYPE_MBA )
+ return 1;
+
+ if ( !psr_check_thrtl(feat->info.mba_info.thrtl_max, m) )
+ return -EINVAL;
+
+ val[0] = m;
+
+ /* MBA uses one COS. */
+ return 1;
+}
+
+static unsigned int mba_get_cos_max_from_type(const struct feat_node *feat,
+ enum psr_val_type type)
+{
+ if ( type != PSR_VAL_TYPE_MBA )
+ return 0;
+
+ return feat->info.mba_info.cos_max;
+}
+
+static int mba_compare_val(const uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int cos, bool *found)
+{
+ uint64_t mba_def = 0;
+
+ if ( cos > feat->info.mba_info.cos_max )
+ {
+ if ( val[0] != mba_def )
+ {
+ *found = false;
+ return -ENOENT;
+ }
+ *found = true;
+ }
+ else
+ *found = (val[0] == feat->cos_reg_val[cos]);
+
+ /* MBA uses one COS. */
+ return 1;
+}
+
+static unsigned int mba_exceeds_cos_max(const uint64_t val[],
+ const struct feat_node *feat,
+ unsigned int cos)
+{
+ uint64_t mba_def = 0;
+
+ if ( cos > feat->info.mba_info.cos_max &&
+ val[0] != mba_def )
+ /*
+ * Exceed cos_max and value to set is not default,
+ * return error.
+ */
+ return 0;
+
+ /* MBA uses one COS. */
+ return 1;
+}
+
+static int mba_write_msr(unsigned int cos, const uint64_t val[],
+ struct feat_node *feat)
+{
+ if ( cos > feat->info.mba_info.cos_max )
+ return 1;
+
+ if ( feat->cos_reg_val[cos] != val[0] )
+ {
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(cos), val[0]);
+ feat->cos_reg_val[cos] = val[0];
+ }
+
+ /* MBA uses one COS. */
+ return 1;
+}
+
struct feat_ops mba_ops = {
.init_feature = mba_init_feature,
.get_max_cos_max = mba_get_max_cos_max,
.get_feat_info = mba_get_feat_info,
.get_val = mba_get_val,
+ .get_cos_num = mba_get_cos_num,
+ .get_old_val = mba_get_old_val,
+ .set_new_val = mba_set_new_val,
+ .get_cos_max_from_type = mba_get_cos_max_from_type,
+ .compare_val = mba_compare_val,
+ .exceeds_cos_max = mba_exceeds_cos_max,
+ .write_msr = mba_write_msr,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -1519,20 +1637,10 @@ static int write_psr_msr(unsigned int socket, unsigned int cos,
return 0;
}
-int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t val, enum psr_val_type type)
+static uint32_t psr_val_type_to_feat_flag(enum psr_val_type type)
{
- unsigned int old_cos;
- int cos, ret;
- unsigned int *ref;
- uint64_t *val_array;
- struct psr_socket_info *info = get_socket_info(socket);
- uint32_t array_len;
uint32_t flag;
- if ( IS_ERR(info) )
- return PTR_ERR(info);
-
/* Judge if feature is enabled. */
switch ( type ) {
case PSR_VAL_TYPE_L3:
@@ -1545,10 +1653,32 @@ int psr_set_val(struct domain *d, unsigned int socket,
case PSR_VAL_TYPE_L2:
flag = PSR_SOCKET_L2_CAT;
break;
+ case PSR_VAL_TYPE_MBA:
+ flag = PSR_SOCKET_MBA;
+ break;
default:
flag = 0xFFFF;
break;
}
+
+ return flag;
+}
+
+int psr_set_val(struct domain *d, unsigned int socket,
+ uint64_t val, enum psr_val_type type)
+{
+ unsigned int old_cos;
+ int cos, ret;
+ unsigned int *ref;
+ uint64_t *val_array;
+ struct psr_socket_info *info = get_socket_info(socket);
+ uint32_t array_len;
+ uint32_t flag;
+
+ if ( IS_ERR(info) )
+ return PTR_ERR(info);
+
+ flag = psr_val_type_to_feat_flag(type);
if ( !test_bit(flag, &info->feat_mask) )
return -ENODEV;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index a41e63a..2e97c6c 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -344,6 +344,7 @@
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n))
+#define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 2de7214..11609bc 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1140,6 +1140,7 @@ struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_MBA_OP_SET_THRTL 8
#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_*_OP_* */
uint32_t target; /* IN */
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 10/16] tools: refactor codes to make get hw info interface be general.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (8 preceding siblings ...)
2017-01-10 7:42 ` [RFC 09/16] x86: implement set " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 11/16] tools: refactor codes to make get val be more general Yi Sun
` (5 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch changes some interfaces in tools/ to make get hw info be
general but not only for CAT.
Add 'LIBXL_HAVE_PSR_MBA' to indicate interface change.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 23 +++++++++++--
tools/libxc/xc_psr.c | 32 +++++++++++-------
tools/libxl/libxl.h | 12 +++++--
tools/libxl/libxl_psr.c | 75 +++++++++++++++++++++++++++++++++++++++----
tools/libxl/libxl_types.idl | 15 +++++++++
tools/libxl/xl_cmdimpl.c | 45 ++++++++++++++------------
6 files changed, 159 insertions(+), 43 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index a009625..fa62e2a 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2606,6 +2606,24 @@ enum xc_psr_cat_type {
};
typedef enum xc_psr_cat_type xc_psr_cat_type;
+enum xc_psr_feat_type {
+ XC_PSR_FEAT_UNKNOWN = 0,
+ XC_PSR_FEAT_CAT_L3 = 1,
+ XC_PSR_FEAT_CAT_L2 = 2,
+};
+typedef enum xc_psr_feat_type xc_psr_feat_type;
+
+struct xc_psr_hw_info {
+ union {
+ struct {
+ uint32_t cos_max;
+ uint32_t cbm_len;
+ bool cdp_enabled;
+ } xc_cat_info;
+ } u;
+};
+typedef struct xc_psr_hw_info xc_psr_hw_info;
+
int xc_psr_cmt_attach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_detach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_get_domain_rmid(xc_interface *xch, uint32_t domid,
@@ -2627,9 +2645,8 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_cat_type type, uint32_t target,
uint64_t *data);
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len,
- bool *cdp_enabled);
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info);
int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 0098a4d..af648eb 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -323,35 +323,43 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
return rc;
}
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len, bool *cdp_enabled)
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info)
{
int rc = -1;
DECLARE_SYSCTL;
+ if ( !hw_info )
+ return rc;
+
sysctl.cmd = XEN_SYSCTL_psr_alloc_op;
sysctl.u.psr_alloc_op.target = socket;
- switch ( lvl ) {
- case 2:
+ switch ( type ) {
+ case XC_PSR_FEAT_CAT_L2:
sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc_op.u.l2_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc_op.u.l2_info.cbm_len;
- *cdp_enabled = false;
+ hw_info->u.xc_cat_info.cos_max =
+ sysctl.u.psr_alloc_op.u.l2_info.cos_max;
+ hw_info->u.xc_cat_info.cbm_len =
+ sysctl.u.psr_alloc_op.u.l2_info.cbm_len;
+ hw_info->u.xc_cat_info.cdp_enabled = false;
}
break;
- case 3:
+ case XC_PSR_FEAT_CAT_L3:
sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc_op.u.l3_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc_op.u.l3_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_alloc_op.u.l3_info.flags &
- XEN_SYSCTL_PSR_CAT_L3_CDP;
+ hw_info->u.xc_cat_info.cos_max =
+ sysctl.u.psr_alloc_op.u.l3_info.cos_max;
+ hw_info->u.xc_cat_info.cbm_len =
+ sysctl.u.psr_alloc_op.u.l3_info.cbm_len;
+ hw_info->u.xc_cat_info.cdp_enabled =
+ sysctl.u.psr_alloc_op.u.l3_info.flags &
+ XEN_SYSCTL_PSR_CAT_L3_CDP;
}
break;
default:
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 45a9978..7575ccd 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -911,6 +911,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
* If this is defined, the L2 Cache Allocation Technology feature is supported.
*/
#define LIBXL_HAVE_PSR_L2_CAT 1
+
+/*
+ * LIBXL_HAVE_PSR_MBA
+ *
+ * If this is defined, the Memory Bandwidth Allocation feature is supported.
+ */
+#define LIBXL_HAVE_PSR_MBA 1
#endif
/*
@@ -2173,8 +2180,9 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
* On success, the function returns an array of elements in 'info',
* and the length in 'nr'.
*/
-int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
- int *nr, unsigned int lvl);
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ int *nr, libxl_psr_feat_type type, int lvl);
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, int nr);
void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr);
#endif
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index d28ace0..2fe42b7 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -352,17 +352,64 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
return rc;
}
-int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
- int *nr, unsigned int lvl)
+static inline xc_psr_feat_type libxl__psr_feat_type_to_libxc_psr_feat_type(
+ libxl_psr_feat_type type, int lvl)
+{
+ xc_psr_feat_type xc_type = XC_PSR_FEAT_UNKNOWN;
+
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ if (lvl == 3)
+ xc_type = XC_PSR_FEAT_CAT_L3;
+ if (lvl == 2)
+ xc_type = XC_PSR_FEAT_CAT_L2;
+ break;
+ default:
+ break;
+ }
+
+ return xc_type;
+}
+
+static inline int libxc__psr_hw_info_to_libxl_psr_hw_info(
+ libxl_psr_feat_type type, xc_psr_hw_info *xc_hw_info,
+ libxl_psr_hw_info *xl_hw_info)
+{
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ xl_hw_info->u.cat_info.cos_max = xc_hw_info->u.xc_cat_info.cos_max;
+ xl_hw_info->u.cat_info.cbm_len = xc_hw_info->u.xc_cat_info.cbm_len;
+ xl_hw_info->u.cat_info.cdp_enabled =
+ xc_hw_info->u.xc_cat_info.cdp_enabled;
+ break;
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ int *nr, libxl_psr_feat_type type, int lvl)
{
GC_INIT(ctx);
int rc;
int i = 0, socketid, nr_sockets;
libxl_bitmap socketmap;
- libxl_psr_cat_info *ptr;
+ libxl_psr_hw_info *ptr;
+ xc_psr_feat_type xc_type;
+ xc_psr_hw_info hw_info;
libxl_bitmap_init(&socketmap);
+ if ( lvl != 3 && lvl != 2) {
+ LOGE(ERROR, "input lvl %d is wrong!\n", lvl);
+ rc = ERROR_FAIL;
+ goto out;
+ }
+
+ xc_type = libxl__psr_feat_type_to_libxc_psr_feat_type(type, lvl);
+
rc = libxl__count_physical_sockets(gc, &nr_sockets);
if (rc) {
LOGE(ERROR, "failed to get system socket count");
@@ -376,17 +423,24 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
goto out;
}
- ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
+ ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_hw_info));
libxl_for_each_set_bit(socketid, socketmap) {
ptr[i].id = socketid;
- if (xc_psr_cat_get_info(ctx->xch, socketid, lvl, &ptr[i].cos_max,
- &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
+ if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
libxl__psr_cat_log_err_msg(gc, errno);
rc = ERROR_FAIL;
free(ptr);
goto out;
}
+
+ if (libxc__psr_hw_info_to_libxl_psr_hw_info(type, &hw_info, &ptr[i])) {
+ LOGE(ERROR, "Input type %d is wrong!\n", type);
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+
i++;
}
@@ -398,6 +452,15 @@ out:
return rc;
}
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, int nr)
+{
+ int i;
+
+ for (i = 0; i < nr; i++)
+ libxl_psr_hw_info_dispose(&list[i]);
+ free(list);
+}
+
void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr)
{
int i;
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index 5a401b8..a15d9ef 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -908,3 +908,18 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
("cbm_len", uint32),
("cdp_enabled", bool),
])
+
+libxl_psr_feat_type = Enumeration("psr_feat_type", [
+ (1, "CAT_INFO"),
+ ])
+
+libxl_psr_hw_info = Struct("psr_hw_info", [
+ ("id", uint32),
+ ("u", KeyedUnion(None, libxl_psr_feat_type, "type",
+ [("cat_info", Struct(None, [
+ ("cos_max", uint32),
+ ("cbm_len", uint32),
+ ("cdp_enabled", bool),
+ ])),
+ ]))
+ ])
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index 58b4eef..5bf56e8 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9337,11 +9337,12 @@ static int psr_l3_cat_hwinfo(void)
int rc, nr;
unsigned int i;
uint32_t l3_cache_size;
- libxl_psr_cat_info *info;
+ libxl_psr_hw_info *info;
printf("Cache Allocation Technology (CAT): L3\n");
- rc = libxl_psr_cat_get_info(ctx, &info, &nr, 3);
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_CAT_INFO, 3);
if (rc) {
fprintf(stderr, "Failed to get l3 cat info\n");
return rc;
@@ -9357,15 +9358,15 @@ static int psr_l3_cat_hwinfo(void)
printf("%-16s: %u\n", "Socket ID", info[i].id);
printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
printf("%-16s: %s\n", "CDP Status",
- info[i].cdp_enabled ? "Enabled" : "Disabled");
- printf("%-16s: %u\n", "Maximum COS", info[i].cos_max);
- printf("%-16s: %u\n", "CBM length", info[i].cbm_len);
+ info[i].u.cat_info.cdp_enabled ? "Enabled" : "Disabled");
+ printf("%-16s: %u\n", "Maximum COS", info[i].u.cat_info.cos_max);
+ printf("%-16s: %u\n", "CBM length", info[i].u.cat_info.cbm_len);
printf("%-16s: %#llx\n", "Default CBM",
- (1ull << info[i].cbm_len) - 1);
+ (1ull << info[i].u.cat_info.cbm_len) - 1);
}
out:
- libxl_psr_cat_info_list_free(info, nr);
+ libxl_psr_hw_info_list_free(info, nr);
return rc;
}
@@ -9436,7 +9437,7 @@ static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
return 0;
}
-static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
+static int psr_cat_print_socket(uint32_t domid, libxl_psr_hw_info *info,
unsigned int lvl)
{
int rc;
@@ -9456,22 +9457,25 @@ static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
}
- printf("%-16s: %#llx\n", "Default CBM", (1ull << info->cbm_len) - 1);
- if (info->cdp_enabled)
+ printf("%-16s: %#llx\n", "Default CBM",
+ (1ull << info->u.cat_info.cbm_len) - 1);
+ if (info->u.cat_info.cdp_enabled)
printf("%5s%25s%16s%16s\n", "ID", "NAME", "CBM (code)", "CBM (data)");
else
printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
- return psr_cat_print_domain_cbm(domid, info->id, info->cdp_enabled, lvl);
+ return psr_cat_print_domain_cbm(domid, info->id,
+ info->u.cat_info.cdp_enabled, lvl);
}
static int psr_cat_show(uint32_t domid, unsigned int lvl)
{
int i, nr;
int rc;
- libxl_psr_cat_info *info;
+ libxl_psr_hw_info *info;
- rc = libxl_psr_cat_get_info(ctx, &info, &nr, lvl);
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_CAT_INFO, lvl);
if (rc) {
fprintf(stderr, "Failed to get %s cat info\n", (lvl == 3)?"L3":"L2");
return rc;
@@ -9484,7 +9488,7 @@ static int psr_cat_show(uint32_t domid, unsigned int lvl)
}
out:
- libxl_psr_cat_info_list_free(info, nr);
+ libxl_psr_hw_info_list_free(info, nr);
return rc;
}
@@ -9493,11 +9497,12 @@ static int psr_l2_cat_hwinfo(void)
int rc;
unsigned int i;
int nr;
- libxl_psr_cat_info *info;
+ libxl_psr_hw_info *info;
printf("Cache Allocation Technology (CAT): L2\n");
- rc = libxl_psr_cat_get_info(ctx, &info, &nr, 2);
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_CAT_INFO, 2);
if (rc) {
fprintf(stderr, "Failed to get l2 cat info\n");
return rc;
@@ -9506,13 +9511,13 @@ static int psr_l2_cat_hwinfo(void)
for (i = 0; i < nr; i++) {
/* There is no CMT on L2 cache so far. */
printf("%-16s: %u\n", "Socket ID", info[i].id);
- printf("%-16s: %u\n", "Maximum COS", info[i].cos_max);
- printf("%-16s: %u\n", "CBM length", info[i].cbm_len);
+ printf("%-16s: %u\n", "Maximum COS", info[i].u.cat_info.cos_max);
+ printf("%-16s: %u\n", "CBM length", info[i].u.cat_info.cbm_len);
printf("%-16s: %#llx\n", "Default CBM",
- (1ull << info[i].cbm_len) - 1);
+ (1ull << info[i].u.cat_info.cbm_len) - 1);
}
- libxl_psr_cat_info_list_free(info, nr);
+ libxl_psr_hw_info_list_free(info, nr);
return rc;
}
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 11/16] tools: refactor codes to make get val be more general.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (9 preceding siblings ...)
2017-01-10 7:42 ` [RFC 10/16] tools: refactor codes to make get hw info interface be general Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 12/16] tools: refactor codes to make set " Yi Sun
` (4 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch refactors some codes in tools/ to make get value
be more general.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 12 +++----
tools/libxc/xc_psr.c | 8 ++---
tools/libxl/libxl_psr.c | 80 +++++++++++++++++++++++++++++++++++--------
3 files changed, 75 insertions(+), 25 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index fa62e2a..69f9343 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2598,13 +2598,13 @@ enum xc_psr_cmt_type {
};
typedef enum xc_psr_cmt_type xc_psr_cmt_type;
-enum xc_psr_cat_type {
+enum xc_psr_val_type {
XC_PSR_CAT_L3_CBM = 1,
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
};
-typedef enum xc_psr_cat_type xc_psr_cat_type;
+typedef enum xc_psr_val_type xc_psr_val_type;
enum xc_psr_feat_type {
XC_PSR_FEAT_UNKNOWN = 0,
@@ -2640,11 +2640,11 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
int xc_psr_cmt_enabled(xc_interface *xch);
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t data);
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
- uint64_t *data);
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t *data);
int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
xc_psr_feat_type type, xc_psr_hw_info *hw_info);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index af648eb..4dbb7c6 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -249,7 +249,7 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t data)
{
DECLARE_DOMCTL;
@@ -283,9 +283,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
return do_domctl(xch, &domctl);
}
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
- uint64_t *data)
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t *data)
{
int rc;
DECLARE_DOMCTL;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 2fe42b7..07c4bc4 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -71,16 +71,35 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
LOGE(ERROR, "%s", msg);
}
-static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
+static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
+ libxl_psr_cbm_type type, int err)
{
char *msg;
+ char *feat;
+
+ switch (type) {
+ case LIBXL_PSR_CBM_TYPE_L3_CBM:
+ feat = "L3 CAT";
+ break;
+ case LIBXL_PSR_CBM_TYPE_L3_CBM_CODE:
+ case LIBXL_PSR_CBM_TYPE_L3_CBM_DATA:
+ feat = "L3 CDP";
+ break;
+ case LIBXL_PSR_CBM_TYPE_L2_CBM:
+ feat = "L2 CAT";
+ break;
+ default:
+ LOGE(ERROR, "Input type %d is wrong!\n", type);
+ libxl__psr_log_err_msg(gc, err);
+ return;
+ }
switch (err) {
case ENODEV:
- msg = "CAT is not supported in this system";
+ msg = "is not supported in this system";
break;
case ENOENT:
- msg = "CAT is not enabled on the socket";
+ msg = "is not enabled on the socket";
break;
case EOVERFLOW:
msg = "no free COS available";
@@ -97,7 +116,38 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
return;
}
- LOGE(ERROR, "%s", msg);
+ LOGE(ERROR, "%s: %s", feat, msg);
+}
+
+static void libxl__psr_hw_info_log_err_msg(libxl__gc *gc, int lvl,
+ libxl_psr_feat_type type, int err)
+{
+ char *msg;
+ char *feat;
+
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ if (lvl == 3)
+ feat = "L3 CAT";
+ else
+ feat = "L2 CAT";
+ break;
+ default:
+ LOGE(ERROR, "Input type %d is wrong!\n", type);
+ libxl__psr_log_err_msg(gc, err);
+ return;
+ }
+
+ switch (err) {
+ case ENOENT:
+ msg = "is not enabled on the socket";
+ break;
+ default:
+ libxl__psr_log_err_msg(gc, err);
+ return;
+ }
+
+ LOGE(ERROR, "%s: %s", feat, msg);
}
static int libxl__pick_socket_cpu(libxl__gc *gc, uint32_t socketid)
@@ -294,11 +344,11 @@ out:
return rc;
}
-static inline xc_psr_cat_type libxl__psr_cbm_type_to_libxc_psr_cat_type(
+static inline xc_psr_val_type libxl__psr_cbm_type_to_libxc_psr_val_type(
libxl_psr_cbm_type type)
{
- BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_cat_type));
- return (xc_psr_cat_type)type;
+ BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_val_type));
+ return (xc_psr_val_type)type;
}
int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
@@ -316,15 +366,15 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
}
libxl_for_each_set_bit(socketid, *target_map) {
- xc_psr_cat_type xc_type;
+ xc_psr_val_type xc_type;
if (socketid >= nr_sockets)
break;
- xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
socketid, cbm)) {
- libxl__psr_cat_log_err_msg(gc, errno);
+ libxl__psr_alloc_log_err_msg(gc, type, errno);
rc = ERROR_FAIL;
}
}
@@ -340,11 +390,11 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
{
GC_INIT(ctx);
int rc = 0;
- xc_psr_cat_type xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_psr_val_type xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
- if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
- target, cbm_r)) {
- libxl__psr_cat_log_err_msg(gc, errno);
+ if (xc_psr_get_domain_data(ctx->xch, domid, xc_type,
+ target, cbm_r)) {
+ libxl__psr_alloc_log_err_msg(gc, type, errno);
rc = ERROR_FAIL;
}
@@ -428,7 +478,7 @@ int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
libxl_for_each_set_bit(socketid, socketmap) {
ptr[i].id = socketid;
if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
- libxl__psr_cat_log_err_msg(gc, errno);
+ libxl__psr_hw_info_log_err_msg(gc, lvl, type, errno);
rc = ERROR_FAIL;
free(ptr);
goto out;
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 12/16] tools: refactor codes to make set val be more general.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (10 preceding siblings ...)
2017-01-10 7:42 ` [RFC 11/16] tools: refactor codes to make get val be more general Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 13/16] tools: implemet get hw info flow for MBA Yi Sun
` (3 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch refactors some codes in tools/ to make set value
be more general.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 6 +++---
tools/libxc/xc_psr.c | 6 +++---
tools/libxl/libxl_psr.c | 4 ++--
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 69f9343..9233b86 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2639,9 +2639,9 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
uint64_t *tsc);
int xc_psr_cmt_enabled(xc_interface *xch);
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t data);
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t data);
int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_val_type type, uint32_t target,
uint64_t *data);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 4dbb7c6..a7ffb1b 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -248,9 +248,9 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t data)
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t data)
{
DECLARE_DOMCTL;
uint32_t cmd;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 07c4bc4..1245e1e 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -372,8 +372,8 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
break;
xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
- if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
- socketid, cbm)) {
+ if (xc_psr_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, cbm)) {
libxl__psr_alloc_log_err_msg(gc, type, errno);
rc = ERROR_FAIL;
}
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 13/16] tools: implemet get hw info flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (11 preceding siblings ...)
2017-01-10 7:42 ` [RFC 12/16] tools: refactor codes to make set " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 14/16] tools: implemet get value " Yi Sun
` (2 subsequent siblings)
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements get HW info flow in tools for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 7 +++++++
tools/libxc/xc_psr.c | 14 +++++++++++++
tools/libxl/libxl_psr.c | 12 ++++++++++-
tools/libxl/libxl_types.idl | 6 ++++++
tools/libxl/xl_cmdimpl.c | 46 +++++++++++++++++++++++++++++++++++++++++--
tools/libxl/xl_cmdtable.c | 3 +++
6 files changed, 85 insertions(+), 3 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 9233b86..ffd0f63 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2610,6 +2610,7 @@ enum xc_psr_feat_type {
XC_PSR_FEAT_UNKNOWN = 0,
XC_PSR_FEAT_CAT_L3 = 1,
XC_PSR_FEAT_CAT_L2 = 2,
+ XC_PSR_FEAT_MBA = 3,
};
typedef enum xc_psr_feat_type xc_psr_feat_type;
@@ -2620,6 +2621,12 @@ struct xc_psr_hw_info {
uint32_t cbm_len;
bool cdp_enabled;
} xc_cat_info;
+
+ struct {
+ uint32_t cos_max;
+ uint32_t thrtl_max;
+ bool linear;
+ } xc_mba_info;
} u;
};
typedef struct xc_psr_hw_info xc_psr_hw_info;
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index a7ffb1b..381ef01 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -362,6 +362,20 @@ int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
XEN_SYSCTL_PSR_CAT_L3_CDP;
}
break;
+ case XC_PSR_FEAT_MBA:
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_MBA_get_info;
+ rc = xc_sysctl(xch, &sysctl);
+ if ( !rc )
+ {
+ hw_info->u.xc_mba_info.cos_max =
+ sysctl.u.psr_alloc_op.u.mba_info.cos_max;
+ hw_info->u.xc_mba_info.thrtl_max =
+ sysctl.u.psr_alloc_op.u.mba_info.thrtl_max;
+ hw_info->u.xc_mba_info.linear =
+ sysctl.u.psr_alloc_op.u.mba_info.linear &
+ XEN_SYSCTL_PSR_MBA_LINEAR;
+ }
+ break;
default:
errno = EOPNOTSUPP;
return rc;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 1245e1e..13d44b6 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -132,6 +132,9 @@ static void libxl__psr_hw_info_log_err_msg(libxl__gc *gc, int lvl,
else
feat = "L2 CAT";
break;
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ feat = "MBA";
+ break;
default:
LOGE(ERROR, "Input type %d is wrong!\n", type);
libxl__psr_log_err_msg(gc, err);
@@ -414,6 +417,8 @@ static inline xc_psr_feat_type libxl__psr_feat_type_to_libxc_psr_feat_type(
if (lvl == 2)
xc_type = XC_PSR_FEAT_CAT_L2;
break;
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ xc_type = XC_PSR_FEAT_MBA;
default:
break;
}
@@ -432,6 +437,11 @@ static inline int libxc__psr_hw_info_to_libxl_psr_hw_info(
xl_hw_info->u.cat_info.cdp_enabled =
xc_hw_info->u.xc_cat_info.cdp_enabled;
break;
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ xl_hw_info->u.mba_info.cos_max = xc_hw_info->u.xc_mba_info.cos_max;
+ xl_hw_info->u.mba_info.thrtl_max = xc_hw_info->u.xc_mba_info.thrtl_max;
+ xl_hw_info->u.mba_info.linear = xc_hw_info->u.xc_mba_info.linear;
+ break;
default:
return -1;
}
@@ -452,7 +462,7 @@ int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
libxl_bitmap_init(&socketmap);
- if ( lvl != 3 && lvl != 2) {
+ if ( type == LIBXL_PSR_FEAT_TYPE_CAT_INFO && lvl != 3 && lvl != 2) {
LOGE(ERROR, "input lvl %d is wrong!\n", lvl);
rc = ERROR_FAIL;
goto out;
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index a15d9ef..bd8d2b8 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -911,6 +911,7 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
libxl_psr_feat_type = Enumeration("psr_feat_type", [
(1, "CAT_INFO"),
+ (2, "MBA_INFO"),
])
libxl_psr_hw_info = Struct("psr_hw_info", [
@@ -921,5 +922,10 @@ libxl_psr_hw_info = Struct("psr_hw_info", [
("cbm_len", uint32),
("cdp_enabled", bool),
])),
+ ("mba_info", Struct(None, [
+ ("cos_max", uint32),
+ ("thrtl_max", uint32),
+ ("linear", bool),
+ ])),
]))
])
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index 5bf56e8..21ef2cf 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9521,6 +9521,38 @@ static int psr_l2_cat_hwinfo(void)
return rc;
}
+
+#ifdef LIBXL_HAVE_PSR_MBA
+static int psr_mba_hwinfo(void)
+{
+ int rc;
+ int i, nr;
+ libxl_psr_hw_info *info;
+
+ printf("Memory Bandwidth Allocation (MBA):\n");
+
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_MBA_INFO, 0);
+ if (rc) {
+ fprintf(stderr, "Failed to get mba info\n");
+ return rc;
+ }
+
+ for (i = 0; i < nr; i++) {
+ printf("%-16s: %u\n", "Socket ID", info[i].id);
+ printf("%-16s: %s\n", "Linear Mode",
+ info[i].u.mba_info.linear ? "Enabled" : "Disabled");
+ printf("%-16s: %u\n", "Maximum COS", info[i].u.mba_info.cos_max);
+ printf("%-16s: %u\n", "Maximum Throttling Value",
+ info[i].u.mba_info.thrtl_max);
+ printf("%-16s: %u\n", "Default Throttling Value", 0);
+ }
+
+ libxl_psr_hw_info_list_free(info, nr);
+ return rc;
+}
+#endif
+
int main_psr_cat_cbm_set(int argc, char **argv)
{
uint32_t domid;
@@ -9635,20 +9667,24 @@ int main_psr_cat_show(int argc, char **argv)
int main_psr_hwinfo(int argc, char **argv)
{
int opt, ret = 0;
- bool all = true, cmt = false, cat = false;
+ bool all = true, cmt = false, cat = false, mba = false;
static struct option opts[] = {
{"cmt", 0, 0, 'm'},
{"cat", 0, 0, 'a'},
+ {"mba", 0, 0, 'b'},
COMMON_LONG_OPTS
};
- SWITCH_FOREACH_OPT(opt, "ma", opts, "psr-hwinfo", 0) {
+ SWITCH_FOREACH_OPT(opt, "mab", opts, "psr-hwinfo", 0) {
case 'm':
all = false; cmt = true;
break;
case 'a':
all = false; cat = true;
break;
+ case 'b':
+ all = false; mba = true;
+ break;
}
if (!ret && (all || cmt))
@@ -9661,6 +9697,12 @@ int main_psr_hwinfo(int argc, char **argv)
if (all || cat)
ret = psr_l2_cat_hwinfo();
+#ifdef LIBXL_HAVE_PSR_MBA
+ /* MBA is independent of CMT and CAT */
+ if (all || mba)
+ ret = psr_mba_hwinfo();
+#endif
+
return ret;
}
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index 32c3ee5..9e1ee6f 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -523,6 +523,9 @@ struct cmd_spec cmd_table[] = {
"[options]",
"-m, --cmt Show Cache Monitoring Technology (CMT) hardware info\n"
"-a, --cat Show Cache Allocation Technology (CAT) hardware info\n"
+#ifdef LIBXL_HAVE_PSR_MBA
+ "-b, --mba Show Memory Bandwidth Allocation (MBA) hardware info\n"
+#endif
},
{ "psr-cmt-attach",
&main_psr_cmt_attach, 0, 1,
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 14/16] tools: implemet get value flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (12 preceding siblings ...)
2017-01-10 7:42 ` [RFC 13/16] tools: implemet get hw info flow for MBA Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 15/16] tools: implemet set " Yi Sun
2017-01-10 7:42 ` [RFC 16/16] docs: add MBA description in docs Yi Sun
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements get value flow in tools for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 1 +
tools/libxc/xc_psr.c | 3 ++
tools/libxl/libxl.h | 3 ++
tools/libxl/libxl_psr.c | 21 +++++++++
tools/libxl/libxl_types.idl | 1 +
tools/libxl/xl.h | 3 ++
tools/libxl/xl_cmdimpl.c | 101 ++++++++++++++++++++++++++++++++++++++++++
tools/libxl/xl_cmdtable.c | 8 ++++
8 files changed, 141 insertions(+)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index ffd0f63..29191d5 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2603,6 +2603,7 @@ enum xc_psr_val_type {
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
+ XC_PSR_MBA_THRTL = 5,
};
typedef enum xc_psr_val_type xc_psr_val_type;
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 381ef01..9348578 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -305,6 +305,9 @@ int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_MBA_OP_GET_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 7575ccd..4c42c00 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -2175,6 +2175,9 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, uint32_t target,
uint64_t *cbm_r);
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, uint32_t target,
+ uint64_t *val);
/*
* On success, the function returns an array of elements in 'info',
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 13d44b6..fac2617 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -88,6 +88,9 @@ static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
case LIBXL_PSR_CBM_TYPE_L2_CBM:
feat = "L2 CAT";
break;
+ case LIBXL_PSR_CBM_TYPE_MBA_THRTL:
+ feat = "MBA";
+ break;
default:
LOGE(ERROR, "Input type %d is wrong!\n", type);
libxl__psr_log_err_msg(gc, err);
@@ -405,6 +408,24 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
return rc;
}
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, uint32_t target,
+ uint64_t *val)
+{
+ GC_INIT(ctx);
+ int rc = 0;
+ xc_psr_val_type xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
+
+ if (xc_psr_get_domain_data(ctx->xch, domid, xc_type,
+ target, val)) {
+ libxl__psr_alloc_log_err_msg(gc, type, errno);
+ rc = ERROR_FAIL;
+ }
+
+ GC_FREE;
+ return rc;
+}
+
static inline xc_psr_feat_type libxl__psr_feat_type_to_libxc_psr_feat_type(
libxl_psr_feat_type type, int lvl)
{
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index bd8d2b8..579794a 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -900,6 +900,7 @@ libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
(2, "L3_CBM_CODE"),
(3, "L3_CBM_DATA"),
(4, "L2_CBM"),
+ (5, "MBA_THRTL"),
])
libxl_psr_cat_info = Struct("psr_cat_info", [
diff --git a/tools/libxl/xl.h b/tools/libxl/xl.h
index 0a8c813..2d0e676 100644
--- a/tools/libxl/xl.h
+++ b/tools/libxl/xl.h
@@ -133,6 +133,9 @@ int main_psr_cmt_show(int argc, char **argv);
int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
#endif
+#ifdef LIBXL_HAVE_PSR_MBA
+int main_psr_mba_show(int argc, char **argv);
+#endif
int main_qemu_monitor_command(int argc, char **argv);
void help(const char *command);
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index 21ef2cf..2263635 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9551,6 +9551,107 @@ static int psr_mba_hwinfo(void)
libxl_psr_hw_info_list_free(info, nr);
return rc;
}
+
+static void psr_mba_print_one_domain_thrtl_type(uint32_t domid,
+ uint32_t socketid,
+ libxl_psr_cbm_type type)
+{
+ uint64_t thrtl;
+
+ if (!libxl_psr_get_val(ctx, domid, type, socketid, &thrtl))
+ printf("%#16"PRIx64, thrtl);
+ else
+ printf("%16s", "error");
+}
+
+static void psr_mba_print_one_domain_thrtl(uint32_t domid, uint32_t socketid)
+{
+ char *domain_name;
+
+ domain_name = libxl_domid_to_name(ctx, domid);
+ printf("%5d%25s", domid, domain_name);
+ free(domain_name);
+
+ psr_mba_print_one_domain_thrtl_type(domid, socketid,
+ LIBXL_PSR_CBM_TYPE_MBA_THRTL);
+ printf("\n");
+}
+
+static int psr_mba_print_domain_thrtl(uint32_t domid, uint32_t socketid)
+{
+ int i, nr_domains;
+ libxl_dominfo *list;
+
+ if (domid != INVALID_DOMID) {
+ psr_mba_print_one_domain_thrtl(domid, socketid);
+ return 0;
+ }
+
+ if (!(list = libxl_list_domain(ctx, &nr_domains))) {
+ fprintf(stderr, "Failed to get domain list for thrtl display\n");
+ return -1;
+ }
+
+ for (i = 0; i < nr_domains; i++)
+ psr_mba_print_one_domain_thrtl(list[i].domid, socketid);
+ libxl_dominfo_list_free(list, nr_domains);
+
+ return 0;
+}
+
+static int psr_mba_print_socket(uint32_t domid, libxl_psr_hw_info *info)
+{
+ printf("%-16s: %u\n", "Socket ID", info->id);
+ printf("%-16s: %u\n", "Default THRTL", 0);
+ printf("%5s%25s%16s\n", "ID", "NAME", "THRTL");
+
+ return psr_mba_print_domain_thrtl(domid, info->id);
+}
+
+static int psr_mba_show(uint32_t domid)
+{
+ int i, nr;
+ int rc;
+ libxl_psr_hw_info *info;
+
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_MBA_INFO, 0);
+ if (rc) {
+ fprintf(stderr, "Failed to get mba info\n");
+ return rc;
+ }
+
+ for (i = 0; i < nr; i++) {
+ rc = psr_mba_print_socket(domid, info + i);
+ if (rc)
+ goto out;
+ }
+
+out:
+ libxl_psr_hw_info_list_free(info, nr);
+ return rc;
+}
+
+int main_psr_mba_show(int argc, char **argv)
+{
+ int opt;
+ uint32_t domid;
+
+ SWITCH_FOREACH_OPT(opt, "", NULL, "psr-mba-show", 0) {
+ /* No options */
+ }
+
+ if (optind >= argc)
+ domid = INVALID_DOMID;
+ else if (optind == argc - 1)
+ domid = find_domain(argv[optind]);
+ else {
+ help("psr-mba-show");
+ return 2;
+ }
+
+ return psr_mba_show(domid);
+}
#endif
int main_psr_cat_cbm_set(int argc, char **argv)
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index 9e1ee6f..b7fc276 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -565,6 +565,14 @@ struct cmd_spec cmd_table[] = {
},
#endif
+#ifdef LIBXL_HAVE_PSR_MBA
+ { "psr-mba-show",
+ &main_psr_mba_show, 0, 1,
+ "Show Memory Bandwidth Allocation information",
+ "<Domain>",
+ },
+
+#endif
{ "usbctrl-attach",
&main_usbctrl_attach, 0, 1,
"Create a virtual USB controller for a domain",
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RFC 15/16] tools: implemet set value flow for MBA.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (13 preceding siblings ...)
2017-01-10 7:42 ` [RFC 14/16] tools: implemet get value " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
2017-01-10 7:42 ` [RFC 16/16] docs: add MBA description in docs Yi Sun
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch implements set value flow in tools for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/xc_psr.c | 3 +++
tools/libxl/libxl.h | 3 +++
tools/libxl/libxl_psr.c | 33 ++++++++++++++++++++++++++++
tools/libxl/xl.h | 1 +
tools/libxl/xl_cmdimpl.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++
tools/libxl/xl_cmdtable.c | 6 ++++++
6 files changed, 101 insertions(+)
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 9348578..590700c 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -269,6 +269,9 @@ int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_MBA_OP_SET_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 4c42c00..a5ad730 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -2167,6 +2167,9 @@ int libxl_psr_cmt_get_sample(libxl_ctx *ctx,
int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, libxl_bitmap *target_map,
uint64_t cbm);
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t val);
/*
* Function to get a domain's cbm. It operates on a single 'target'.
* The definition of 'target' is related to 'type':
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index fac2617..6ba4797 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -408,6 +408,39 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
return rc;
}
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t cbm)
+{
+ GC_INIT(ctx);
+ int rc;
+ int socketid, nr_sockets;
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOGED(ERROR, domid, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_for_each_set_bit(socketid, *target_map) {
+ xc_psr_val_type xc_type;
+
+ if (socketid >= nr_sockets)
+ break;
+
+ xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
+ if (xc_psr_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, cbm)) {
+ libxl__psr_alloc_log_err_msg(gc, type, errno);
+ rc = ERROR_FAIL;
+ }
+ }
+
+out:
+ GC_FREE;
+ return rc;
+}
+
int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, uint32_t target,
uint64_t *val)
diff --git a/tools/libxl/xl.h b/tools/libxl/xl.h
index 2d0e676..c431348 100644
--- a/tools/libxl/xl.h
+++ b/tools/libxl/xl.h
@@ -134,6 +134,7 @@ int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
#endif
#ifdef LIBXL_HAVE_PSR_MBA
+int main_psr_mba_set(int argc, char **argv);
int main_psr_mba_show(int argc, char **argv);
#endif
int main_qemu_monitor_command(int argc, char **argv);
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index 2263635..e6c20b4 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9652,6 +9652,61 @@ int main_psr_mba_show(int argc, char **argv)
return psr_mba_show(domid);
}
+
+int main_psr_mba_set(int argc, char **argv)
+{
+ uint32_t domid;
+ libxl_psr_cbm_type type;
+ uint64_t thrtl;
+ int ret, opt = 0;
+ libxl_bitmap target_map;
+ char *value;
+ libxl_string_list socket_list;
+ unsigned long start, end;
+ unsigned int i, j, len;
+
+ static struct option opts[] = {
+ {"socket", 1, 0, 's'},
+ COMMON_LONG_OPTS
+ };
+
+ libxl_socket_bitmap_alloc(ctx, &target_map, 0);
+ libxl_bitmap_set_none(&target_map);
+
+ SWITCH_FOREACH_OPT(opt, "s", opts, "psr-mba-set", 0) {
+ case 's':
+ trim(isspace, optarg, &value);
+ split_string_into_string_list(value, ",", &socket_list);
+ len = libxl_string_list_length(&socket_list);
+ for (i = 0; i < len; i++) {
+ parse_range(socket_list[i], &start, &end);
+ for (j = start; j <= end; j++)
+ libxl_bitmap_set(&target_map, j);
+ }
+
+ libxl_string_list_dispose(&socket_list);
+ free(value);
+ break;
+ }
+
+ type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
+
+ if (libxl_bitmap_is_empty(&target_map))
+ libxl_bitmap_set_any(&target_map);
+
+ if (argc != optind + 2) {
+ help("psr-mba-set");
+ return 2;
+ }
+
+ domid = find_domain(argv[optind]);
+ thrtl = strtoll(argv[optind + 1], NULL , 0);
+
+ ret = libxl_psr_set_val(ctx, domid, type, &target_map, thrtl);
+
+ libxl_bitmap_dispose(&target_map);
+ return ret;
+}
#endif
int main_psr_cat_cbm_set(int argc, char **argv)
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index b7fc276..c8b83ab 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -566,6 +566,12 @@ struct cmd_spec cmd_table[] = {
#endif
#ifdef LIBXL_HAVE_PSR_MBA
+ { "psr-mba-set",
+ &main_psr_mba_set, 0, 1,
+ "Set throttling value (THRTL) for a domain",
+ "[options] <Domain> <THRTL>",
+ "-s <socket> Specify the socket to process, otherwise all sockets are processed\n"
+ },
{ "psr-mba-show",
&main_psr_mba_show, 0, 1,
"Show Memory Bandwidth Allocation information",
--
1.9.1
_______________________________________________
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* [RFC 16/16] docs: add MBA description in docs.
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (14 preceding siblings ...)
2017-01-10 7:42 ` [RFC 15/16] tools: implemet set " Yi Sun
@ 2017-01-10 7:42 ` Yi Sun
15 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-01-10 7:42 UTC (permalink / raw)
To: xen-devel
Cc: wei.liu2, he.chen, andrew.cooper3, ian.jackson, Yi Sun, jbeulich,
chao.p.peng
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
docs/man/xl.pod.1.in | 35 +++++++++++++++++++++++++++
docs/misc/xl-psr.markdown | 60 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+)
diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 2c41ea7..c101e0f 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1787,6 +1787,41 @@ processed.
=back
+=head2 Memory Bandwidth Allocation
+
+Intel Skylake and later server platforms offer capabilities to configure and
+make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
+OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
+control system via exposing control over a credit-based throttling mechanism.
+In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
+To enforce bandwidth on a specific domain, just set throttling value (THRTL)
+for the domain.
+
+=over 4
+
+=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
+
+Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-mba-show> [I<domain-id>]
+
+Show MBA settings for a certain domain or all domains.
+
+=back
+
+=back
+
=head1 IGNORED FOR COMPATIBILITY WITH XM
xl is mostly command-line compatible with the old xm utility used with
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index bd2b6bd..7d7f418 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -186,6 +186,66 @@ Setting data CBM for a domain:
Setting the same code and data CBM for a domain:
`xl psr-cat-cbm-set <domid> <cbm>`
+## Memory Bandwidth Allocation (MBA)
+
+Memory Bandwidth Allocation (MBA) is a new feature available on Intel
+Skylake and later server platforms that allows an OS or Hypervisor/VMM to
+slow misbehaving apps/VMs or create advanced closed-loop control system via
+exposing control over a credit-based throttling mechanism. To enforce bandwidth
+on a specific domain, just set throttling value (THRTL) into Class of Service
+(COS). MBA provides two THRTL mode. One is linear mode and the other is
+non-linear mode.
+
+In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
+not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
+to 10% delay applied).
+
+If linear values are not supported then input delay values are powers-of-two
+from zero to the THRTL_MAX value from CPUID. In this case any values not a power
+of two will be rounded down the next nearest power of two.
+
+For example, assuming a system with 8 portions and 2 domains:
+
+ * A THRTL of 0x0 for every domain means each domain can access the whole cache
+ without any delay. This is the default.
+
+ * Linear mode: Giving one domain a THRTL of 0xC and the other domain's 0 means
+ that the first domain gets 10% delay to access the cache and the other one
+ without any delay.
+
+ * Non-linear mode: Giving one domain a THRTL of 0xC and the other domain's 0
+ means that the first domain gets 8% delay to access the cache and the other
+ one without any delay.
+
+For more detailed information please refer to Intel SDM chapter
+"Introduction to Memory Bandwidth Allocation".
+
+In Xen's implementation, THRTL can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding THRTL is
+0, which means all the cache resource can be accessed without delay.
+
+### xl interfaces
+
+System MBA information such as maximum COS and maximum THRTL can be obtained by:
+
+`xl psr-hwinfo --mba`
+
+The simplest way to change a domain's THRTL from its default is running:
+
+`xl psr-mba-set [OPTIONS] <domid> <thrtl>`
+
+In a multi-socket system, the same thrtl will be set on each socket by default.
+Per socket thrtl can be specified with the `--socket SOCKET` option.
+
+Setting the THRTL may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting THRTL of all related domains to
+its default value(0).
+
+Per domain THRTL settings can be shown by:
+
+`xl psr-mba-show [OPTIONS] <domid>`
+
## Reference
[1] Intel SDM
--
1.9.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document.
2017-01-10 7:42 ` [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-02-23 20:46 ` Meng Xu
2017-02-24 5:07 ` Yi Sun
0 siblings, 1 reply; 21+ messages in thread
From: Meng Xu @ 2017-02-23 20:46 UTC (permalink / raw)
To: Yi Sun
Cc: Wei Liu, he.chen, Andrew Cooper, Ian Jackson, Jan Beulich,
Chao Peng, xen-devel
Hi Yi,
I have some quick comment about this document. Some minor points are
not very clear, IMHO.
> +
> + 2. `psr-mba-set [OPTIONS] domain-id throttling`:
> +
> + Set memory bandwidth throttling for domain.
> +
> + Options:
> + '-s': Specify the socket to process, otherwise all sockets are processed.
> +
> + Throttling value set in register implies memory bandwidth blocked, i.e.
> + higher throttling value results in lower bandwidth. The max throttling
> + value can be got through CPUID.
> +
> + The response of the throttling value could be linear mode or non-linear
> + mode.
> +
> + Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
> + if the MBA_MAX value is 90, the input precision is 10%. Values not an even
> + multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
> + delay applied) by HW automatically.
So MBA has a minimum allocation unit. What is the minimum bandwidth
allocation unit?
From the above example, I had the impression that the allocation unit is 10%.
As mentioned in the document later, the throttle value is set in the
COS register's Thrtl bit fields as shown in [Code_CBM, Data_CBM,
Thrtl]. I had the impression that the maximum number of bandwidth
units we can allocate is 2^number_of_bits_in_Thrtl.
Only one of my impression could be true, right? ;-)
In addition, since hardware will round down the partial bandwidth
value, why shouldn't we just allow system operators to configure the
"valid" bandwidth supported by the hardware.
For example, if the hardware only supports the bandwidth throttle
value in 10% units, then we should not allow users to input the
bandwidth throttle value as 12% or 13%. Otherwise, as a system
operator, I would be confused at why I increased the bandwidth
throttle value from 11% to 19%, I still see the same bandwidth
guarantee.
> +
> + Non-linear mode: input delay values are powers-of-two from zero to the
> + MBA_MAX value from CPUID. In this case any values not a power of two will
> + be rounded down the next nearest power of two by HW automatically.\
First question: Why is it the delay value instead of bandwidth value
in the non-linear mode? Does MBA really control memory access latency?
Second question: Does the hardware provide any guaranteed bandwidth in
the non-linear mode?
I saw the document patch in Linux at
http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1307176.html:
[Qutoe]
In nonlinear scale currently SDM specifies
+throttle values in 2^n values. However the h/w does not guarantee a
+specific curve for the amount of memory b/w that is actually throttled.
+But for any thrtl_by value x > y, its guaranteed that x would throttle
+more b/w than y. The info directory specifies the max thrtl_by value
+and thrtl_by granularity.
[/Qutoe]
It seems that the non-linear mode simply provide some throttling
relations but don't guarantee the actual throttle value.
Maybe it will be good to clearly state the capability and limitations
of the hardware.
> + System administrator can change PSR allocation policy at runtime by
> + tool stack. Since MBA shares COS with CAT/CDP, a COS corresponds to a
> + 2-tuple, like [CBM, Thrtl] with only-CAT enalbed, when CDP is enable,
> + the COS corresponds to a 3-tuple, like [Code_CBM, Data_CBM, Thrtl]. If
> + neither CAT nor CDP is enabled, things would be easier, one COS
> + corresponds to one Thrtl.
How many bits in Thrtl field?
Is it decided by the hardware type?
> +# References
> +
> +"INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES" [Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
> +
I checked the document. The CAT is in Chapter 17.17. However, there is
no description about the MBA? ;-)
Thanks,
Meng
-----------
Meng Xu
PhD Student in Computer and Information Science
University of Pennsylvania
http://www.cis.upenn.edu/~mengxu/
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document.
2017-02-23 20:46 ` Meng Xu
@ 2017-02-24 5:07 ` Yi Sun
2017-02-24 15:53 ` Meng Xu
0 siblings, 1 reply; 21+ messages in thread
From: Yi Sun @ 2017-02-24 5:07 UTC (permalink / raw)
To: Meng Xu
Cc: Wei Liu, he.chen, Andrew Cooper, Ian Jackson, Jan Beulich,
Chao Peng, xen-devel
On 17-02-23 15:46:36, Meng Xu wrote:
> Hi Yi,
>
> I have some quick comment about this document. Some minor points are
> not very clear, IMHO.
>
Thanks for your mail!
> > +
> > + 2. `psr-mba-set [OPTIONS] domain-id throttling`:
> > +
> > + Set memory bandwidth throttling for domain.
> > +
> > + Options:
> > + '-s': Specify the socket to process, otherwise all sockets are processed.
> > +
> > + Throttling value set in register implies memory bandwidth blocked, i.e.
> > + higher throttling value results in lower bandwidth. The max throttling
> > + value can be got through CPUID.
> > +
> > + The response of the throttling value could be linear mode or non-linear
> > + mode.
> > +
> > + Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
> > + if the MBA_MAX value is 90, the input precision is 10%. Values not an even
> > + multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
> > + delay applied) by HW automatically.
>
> So MBA has a minimum allocation unit. What is the minimum bandwidth
> allocation unit?
> >From the above example, I had the impression that the allocation unit is 10%.
> As mentioned in the document later, the throttle value is set in the
> COS register's Thrtl bit fields as shown in [Code_CBM, Data_CBM,
> Thrtl]. I had the impression that the maximum number of bandwidth
> units we can allocate is 2^number_of_bits_in_Thrtl.
> Only one of my impression could be true, right? ;-)
>
MBA supports two modes by design. One is linear mode which likes 10%. The other
is non-linear mode which is power of 2. So, it depends on the HW info to see
which mode is supported. :)
> In addition, since hardware will round down the partial bandwidth
> value, why shouldn't we just allow system operators to configure the
> "valid" bandwidth supported by the hardware.
> For example, if the hardware only supports the bandwidth throttle
> value in 10% units, then we should not allow users to input the
> bandwidth throttle value as 12% or 13%. Otherwise, as a system
> operator, I would be confused at why I increased the bandwidth
> throttle value from 11% to 19%, I still see the same bandwidth
> guarantee.
>
That is an option to implement libxl or even upper layer.
> > +
> > + Non-linear mode: input delay values are powers-of-two from zero to the
> > + MBA_MAX value from CPUID. In this case any values not a power of two will
> > + be rounded down the next nearest power of two by HW automatically.\
>
> First question: Why is it the delay value instead of bandwidth value
> in the non-linear mode? Does MBA really control memory access latency?
>
MBA directly controls the latency to indirectly control the bandwidth.
You can see the description in SDM:
"The Memory Bandwidth Allocation (MBA) feature provides indirect and
approximate control over memory band width available per-core"
> Second question: Does the hardware provide any guaranteed bandwidth in
> the non-linear mode?
Nope, as above mentions, "approximate control" is provided no matter linear
mode or non-linear mode.
> I saw the document patch in Linux at
> http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1307176.html:
> [Qutoe]
> In nonlinear scale currently SDM specifies
> +throttle values in 2^n values. However the h/w does not guarantee a
> +specific curve for the amount of memory b/w that is actually throttled.
> +But for any thrtl_by value x > y, its guaranteed that x would throttle
> +more b/w than y. The info directory specifies the max thrtl_by value
> +and thrtl_by granularity.
> [/Qutoe]
>
> It seems that the non-linear mode simply provide some throttling
> relations but don't guarantee the actual throttle value.
> Maybe it will be good to clearly state the capability and limitations
> of the hardware.
>
Sorry, there is no such info in SDM. But you can use MBM (Memory Bandwidth
Monitoring) feature to learn the MBA real status.
> > + System administrator can change PSR allocation policy at runtime by
> > + tool stack. Since MBA shares COS with CAT/CDP, a COS corresponds to a
> > + 2-tuple, like [CBM, Thrtl] with only-CAT enalbed, when CDP is enable,
> > + the COS corresponds to a 3-tuple, like [Code_CBM, Data_CBM, Thrtl]. If
> > + neither CAT nor CDP is enabled, things would be easier, one COS
> > + corresponds to one Thrtl.
>
> How many bits in Thrtl field?
> Is it decided by the hardware type?
>
This is defined in SDM.
"The definition for the MBA delay value MSRs is provided in Figure 17.39. The
lower 16 bits are used for MBA delay values, and values from zero to the maximum
from the CPUID MBA_MAX-1 value are supported."
Please note, MBA value is different with CBM. You do not need care the bits.
> > +# References
> > +
> > +"INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES" [Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
> > +
>
> I checked the document. The CAT is in Chapter 17.17. However, there is
> no description about the MBA? ;-)
Have you downloaded latest SDM? 17.18.7 is for MBA.
>
> Thanks,
>
> Meng
>
> -----------
> Meng Xu
> PhD Student in Computer and Information Science
> University of Pennsylvania
> http://www.cis.upenn.edu/~mengxu/
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document.
2017-02-24 5:07 ` Yi Sun
@ 2017-02-24 15:53 ` Meng Xu
2017-02-27 4:39 ` Yi Sun
0 siblings, 1 reply; 21+ messages in thread
From: Meng Xu @ 2017-02-24 15:53 UTC (permalink / raw)
To: Yi Sun
Cc: Wei Liu, he.chen, Andrew Cooper, Ian Jackson, Jan Beulich,
Chao Peng, xen-devel
>> > + System administrator can change PSR allocation policy at runtime by
>> > + tool stack. Since MBA shares COS with CAT/CDP, a COS corresponds to a
>> > + 2-tuple, like [CBM, Thrtl] with only-CAT enalbed, when CDP is enable,
>> > + the COS corresponds to a 3-tuple, like [Code_CBM, Data_CBM, Thrtl]. If
>> > + neither CAT nor CDP is enabled, things would be easier, one COS
>> > + corresponds to one Thrtl.
>>
>> How many bits in Thrtl field?
>> Is it decided by the hardware type?
>>
> This is defined in SDM.
> "The definition for the MBA delay value MSRs is provided in Figure 17.39. The
> lower 16 bits are used for MBA delay values, and values from zero to the maximum
> from the CPUID MBA_MAX-1 value are supported."
>
> Please note, MBA value is different with CBM. You do not need care the bits.
>
>> > +# References
>> > +
>> > +"INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES" [Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
>> > +
>>
>> I checked the document. The CAT is in Chapter 17.17. However, there is
>> no description about the MBA? ;-)
> Have you downloaded latest SDM? 17.18.7 is for MBA.
Ah-ha, I saw it now. I guess I downloaded the old version. :-)
I found this MBA feature is interesting. Is there any processor on the
market we can purchase?
We'd like to evaluate this feature. ;-)
Thanks,
Meng
-----------
Meng Xu
PhD Student in Computer and Information Science
University of Pennsylvania
http://www.cis.upenn.edu/~mengxu/
_______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document.
2017-02-24 15:53 ` Meng Xu
@ 2017-02-27 4:39 ` Yi Sun
0 siblings, 0 replies; 21+ messages in thread
From: Yi Sun @ 2017-02-27 4:39 UTC (permalink / raw)
To: Meng Xu
Cc: Wei Liu, he.chen, Andrew Cooper, Ian Jackson, Jan Beulich,
Chao Peng, xen-devel
On 17-02-24 10:53:16, Meng Xu wrote:
> >> > +# References
> >> > +
> >> > +"INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES" [Intel® 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
> >> > +
> >>
> >> I checked the document. The CAT is in Chapter 17.17. However, there is
> >> no description about the MBA? ;-)
> > Have you downloaded latest SDM? 17.18.7 is for MBA.
>
> Ah-ha, I saw it now. I guess I downloaded the old version. :-)
>
> I found this MBA feature is interesting. Is there any processor on the
> market we can purchase?
> We'd like to evaluate this feature. ;-)
>
Per my info, Skylake which enables the MBA will be released in the middle of
this year.
> Thanks,
>
> Meng
>
> -----------
> Meng Xu
> PhD Student in Computer and Information Science
> University of Pennsylvania
> http://www.cis.upenn.edu/~mengxu/
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-02-27 4:39 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-10 7:42 [RFC 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-01-10 7:42 ` [RFC 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-02-23 20:46 ` Meng Xu
2017-02-24 5:07 ` Yi Sun
2017-02-24 15:53 ` Meng Xu
2017-02-27 4:39 ` Yi Sun
2017-01-10 7:42 ` [RFC 02/16] Rename sysctl/domctl interface and xsm policy to make them general Yi Sun
2017-01-10 7:42 ` [RFC 03/16] x86: change 'cbm_type' to 'psr_val_type' to make it general Yi Sun
2017-01-10 7:42 ` [RFC 04/16] x86: implement data structure of MBA Yi Sun
2017-01-10 7:42 ` [RFC 05/16] x86: parse config parameters for MBA Yi Sun
2017-01-10 7:42 ` [RFC 06/16] x86: implement init flow " Yi Sun
2017-01-10 7:42 ` [RFC 07/16] x86: implement get hw info " Yi Sun
2017-01-10 7:42 ` [RFC 08/16] x86: implement get value " Yi Sun
2017-01-10 7:42 ` [RFC 09/16] x86: implement set " Yi Sun
2017-01-10 7:42 ` [RFC 10/16] tools: refactor codes to make get hw info interface be general Yi Sun
2017-01-10 7:42 ` [RFC 11/16] tools: refactor codes to make get val be more general Yi Sun
2017-01-10 7:42 ` [RFC 12/16] tools: refactor codes to make set " Yi Sun
2017-01-10 7:42 ` [RFC 13/16] tools: implemet get hw info flow for MBA Yi Sun
2017-01-10 7:42 ` [RFC 14/16] tools: implemet get value " Yi Sun
2017-01-10 7:42 ` [RFC 15/16] tools: implemet set " Yi Sun
2017-01-10 7:42 ` [RFC 16/16] docs: add MBA description in docs Yi Sun
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