* [PATCH v2 1/4] ntb_hw_amd: Style fixes: open code macros that just obfuscate code
2017-01-11 0:33 [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
@ 2017-01-11 0:33 ` Logan Gunthorpe
2017-03-08 16:41 ` Jon Mason
2017-01-11 0:33 ` [PATCH v2 2/4] ntb_hw_intel: " Logan Gunthorpe
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Logan Gunthorpe @ 2017-01-11 0:33 UTC (permalink / raw)
To: Xiangliang Yu, Jon Mason, Dave Jiang, Allen Hubbe, Joe Perches
Cc: Greg Kroah-Hartman, linux-ntb, linux-kernel, Logan Gunthorpe
As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should
be cleaned up. This makes it more clear what's actually going on when
reading the code.
[1] http://www.spinics.net/lists/linux-pci/msg56904.html
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 59 ++++++++++++++++++++++-------------------
drivers/ntb/hw/amd/ntb_hw_amd.h | 3 ---
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
index 019a158..0135fcf 100644
--- a/drivers/ntb/hw/amd/ntb_hw_amd.c
+++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
@@ -98,10 +98,10 @@ static int amd_ntb_mw_get_range(struct ntb_dev *ntb, int idx,
return bar;
if (base)
- *base = pci_resource_start(ndev->ntb.pdev, bar);
+ *base = pci_resource_start(ntb->pdev, bar);
if (size)
- *size = pci_resource_len(ndev->ntb.pdev, bar);
+ *size = pci_resource_len(ntb->pdev, bar);
if (align)
*align = SZ_4K;
@@ -126,7 +126,7 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
if (bar < 0)
return bar;
- mw_size = pci_resource_len(ndev->ntb.pdev, bar);
+ mw_size = pci_resource_len(ntb->pdev, bar);
/* make sure the range fits in the usable mw size */
if (size > mw_size)
@@ -135,7 +135,7 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
mmio = ndev->self_mmio;
peer_mmio = ndev->peer_mmio;
- base_addr = pci_resource_start(ndev->ntb.pdev, bar);
+ base_addr = pci_resource_start(ntb->pdev, bar);
if (bar != 1) {
xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);
@@ -225,7 +225,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
if (width)
*width = NTB_LNK_STA_WIDTH(ndev->lnk_sta);
- dev_dbg(ndev_dev(ndev), "link is up.\n");
+ dev_dbg(&ntb->pdev->dev, "link is up.\n");
ret = 1;
} else {
@@ -234,7 +234,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
if (width)
*width = NTB_WIDTH_NONE;
- dev_dbg(ndev_dev(ndev), "link is down.\n");
+ dev_dbg(&ntb->pdev->dev, "link is down.\n");
}
return ret;
@@ -254,7 +254,7 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(ndev_dev(ndev), "Enabling Link.\n");
+ dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
@@ -275,7 +275,7 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(ndev_dev(ndev), "Enabling Link.\n");
+ dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
@@ -466,18 +466,19 @@ static void amd_ack_smu(struct amd_ntb_dev *ndev, u32 bit)
static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
{
void __iomem *mmio = ndev->self_mmio;
+ struct device *dev = &ndev->ntb.pdev->dev;
u32 status;
status = readl(mmio + AMD_INTSTAT_OFFSET);
if (!(status & AMD_EVENT_INTMASK))
return;
- dev_dbg(ndev_dev(ndev), "status = 0x%x and vec = %d\n", status, vec);
+ dev_dbg(dev, "status = 0x%x and vec = %d\n", status, vec);
status &= AMD_EVENT_INTMASK;
switch (status) {
case AMD_PEER_FLUSH_EVENT:
- dev_info(ndev_dev(ndev), "Flush is done.\n");
+ dev_info(dev, "Flush is done.\n");
break;
case AMD_PEER_RESET_EVENT:
amd_ack_smu(ndev, AMD_PEER_RESET_EVENT);
@@ -503,7 +504,7 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
status = readl(mmio + AMD_PMESTAT_OFFSET);
/* check if this is WAKEUP event */
if (status & 0x1)
- dev_info(ndev_dev(ndev), "Wakeup is done.\n");
+ dev_info(dev, "Wakeup is done.\n");
amd_ack_smu(ndev, AMD_PEER_D0_EVENT);
@@ -512,14 +513,14 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
AMD_LINK_HB_TIMEOUT);
break;
default:
- dev_info(ndev_dev(ndev), "event status = 0x%x.\n", status);
+ dev_info(dev, "event status = 0x%x.\n", status);
break;
}
}
static irqreturn_t ndev_interrupt(struct amd_ntb_dev *ndev, int vec)
{
- dev_dbg(ndev_dev(ndev), "vec %d\n", vec);
+ dev_dbg(&ndev->ntb.pdev->dev, "vec %d\n", vec);
if (vec > (AMD_DB_CNT - 1) || (ndev->msix_vec_count == 1))
amd_handle_event(ndev, vec);
@@ -541,7 +542,7 @@ static irqreturn_t ndev_irq_isr(int irq, void *dev)
{
struct amd_ntb_dev *ndev = dev;
- return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq);
+ return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq);
}
static int ndev_init_isr(struct amd_ntb_dev *ndev,
@@ -550,7 +551,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
struct pci_dev *pdev;
int rc, i, msix_count, node;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
node = dev_to_node(&pdev->dev);
@@ -592,7 +593,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
goto err_msix_request;
}
- dev_dbg(ndev_dev(ndev), "Using msix interrupts\n");
+ dev_dbg(&pdev->dev, "Using msix interrupts\n");
ndev->db_count = msix_min;
ndev->msix_vec_count = msix_max;
return 0;
@@ -619,7 +620,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
if (rc)
goto err_msi_request;
- dev_dbg(ndev_dev(ndev), "Using msi interrupts\n");
+ dev_dbg(&pdev->dev, "Using msi interrupts\n");
ndev->db_count = 1;
ndev->msix_vec_count = 1;
return 0;
@@ -636,7 +637,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
if (rc)
goto err_intx_request;
- dev_dbg(ndev_dev(ndev), "Using intx interrupts\n");
+ dev_dbg(&pdev->dev, "Using intx interrupts\n");
ndev->db_count = 1;
ndev->msix_vec_count = 1;
return 0;
@@ -651,7 +652,7 @@ static void ndev_deinit_isr(struct amd_ntb_dev *ndev)
void __iomem *mmio = ndev->self_mmio;
int i;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
/* Mask all doorbell interrupts */
ndev->db_mask = ndev->db_valid_mask;
@@ -777,7 +778,8 @@ static void ndev_init_debugfs(struct amd_ntb_dev *ndev)
ndev->debugfs_info = NULL;
} else {
ndev->debugfs_dir =
- debugfs_create_dir(ndev_name(ndev), debugfs_dir);
+ debugfs_create_dir(pci_name(ndev->ntb.pdev),
+ debugfs_dir);
if (!ndev->debugfs_dir)
ndev->debugfs_info = NULL;
else
@@ -812,7 +814,7 @@ static int amd_poll_link(struct amd_ntb_dev *ndev)
reg = readl(mmio + AMD_SIDEINFO_OFFSET);
reg &= NTB_LIN_STA_ACTIVE_BIT;
- dev_dbg(ndev_dev(ndev), "%s: reg_val = 0x%x.\n", __func__, reg);
+ dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg);
if (reg == ndev->cntl_sta)
return 0;
@@ -894,7 +896,8 @@ static int amd_init_ntb(struct amd_ntb_dev *ndev)
break;
default:
- dev_err(ndev_dev(ndev), "AMD NTB does not support B2B mode.\n");
+ dev_err(&ndev->ntb.pdev->dev,
+ "AMD NTB does not support B2B mode.\n");
return -EINVAL;
}
@@ -923,10 +926,10 @@ static int amd_init_dev(struct amd_ntb_dev *ndev)
struct pci_dev *pdev;
int rc = 0;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
ndev->ntb.topo = amd_get_topo(ndev);
- dev_dbg(ndev_dev(ndev), "AMD NTB topo is %s\n",
+ dev_dbg(&pdev->dev, "AMD NTB topo is %s\n",
ntb_topo_string(ndev->ntb.topo));
rc = amd_init_ntb(ndev);
@@ -935,7 +938,7 @@ static int amd_init_dev(struct amd_ntb_dev *ndev)
rc = amd_init_isr(ndev);
if (rc) {
- dev_err(ndev_dev(ndev), "fail to init isr.\n");
+ dev_err(&pdev->dev, "fail to init isr.\n");
return rc;
}
@@ -973,7 +976,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc)
goto err_dma_mask;
- dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n");
+ dev_warn(&pdev->dev, "Cannot DMA highmem\n");
}
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
@@ -981,7 +984,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc)
goto err_dma_mask;
- dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n");
+ dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
}
ndev->self_mmio = pci_iomap(pdev, 0, 0);
@@ -1004,7 +1007,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
static void amd_ntb_deinit_pci(struct amd_ntb_dev *ndev)
{
- struct pci_dev *pdev = ndev_pdev(ndev);
+ struct pci_dev *pdev = ndev->ntb.pdev;
pci_iounmap(pdev, ndev->self_mmio);
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.h b/drivers/ntb/hw/amd/ntb_hw_amd.h
index 13d73ed..8f3617a 100644
--- a/drivers/ntb/hw/amd/ntb_hw_amd.h
+++ b/drivers/ntb/hw/amd/ntb_hw_amd.h
@@ -211,9 +211,6 @@ struct amd_ntb_dev {
struct dentry *debugfs_info;
};
-#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
-#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
-#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
#define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
#define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 1/4] ntb_hw_amd: Style fixes: open code macros that just obfuscate code
2017-01-11 0:33 ` [PATCH v2 1/4] ntb_hw_amd: Style fixes: open code macros that just obfuscate code Logan Gunthorpe
@ 2017-03-08 16:41 ` Jon Mason
0 siblings, 0 replies; 11+ messages in thread
From: Jon Mason @ 2017-03-08 16:41 UTC (permalink / raw)
To: Logan Gunthorpe
Cc: Xiangliang Yu, Dave Jiang, Allen Hubbe, Joe Perches,
Greg Kroah-Hartman, linux-ntb, linux-kernel
On Tue, Jan 10, 2017 at 05:33:36PM -0700, Logan Gunthorpe wrote:
> As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should
> be cleaned up. This makes it more clear what's actually going on when
> reading the code.
>
> [1] http://www.spinics.net/lists/linux-pci/msg56904.html
>
> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Applied to my ntb-next branch
Thanks,
Jon
> ---
> drivers/ntb/hw/amd/ntb_hw_amd.c | 59 ++++++++++++++++++++++-------------------
> drivers/ntb/hw/amd/ntb_hw_amd.h | 3 ---
> 2 files changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
> index 019a158..0135fcf 100644
> --- a/drivers/ntb/hw/amd/ntb_hw_amd.c
> +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
> @@ -98,10 +98,10 @@ static int amd_ntb_mw_get_range(struct ntb_dev *ntb, int idx,
> return bar;
>
> if (base)
> - *base = pci_resource_start(ndev->ntb.pdev, bar);
> + *base = pci_resource_start(ntb->pdev, bar);
>
> if (size)
> - *size = pci_resource_len(ndev->ntb.pdev, bar);
> + *size = pci_resource_len(ntb->pdev, bar);
>
> if (align)
> *align = SZ_4K;
> @@ -126,7 +126,7 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
> if (bar < 0)
> return bar;
>
> - mw_size = pci_resource_len(ndev->ntb.pdev, bar);
> + mw_size = pci_resource_len(ntb->pdev, bar);
>
> /* make sure the range fits in the usable mw size */
> if (size > mw_size)
> @@ -135,7 +135,7 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
> mmio = ndev->self_mmio;
> peer_mmio = ndev->peer_mmio;
>
> - base_addr = pci_resource_start(ndev->ntb.pdev, bar);
> + base_addr = pci_resource_start(ntb->pdev, bar);
>
> if (bar != 1) {
> xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);
> @@ -225,7 +225,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
> if (width)
> *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta);
>
> - dev_dbg(ndev_dev(ndev), "link is up.\n");
> + dev_dbg(&ntb->pdev->dev, "link is up.\n");
>
> ret = 1;
> } else {
> @@ -234,7 +234,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
> if (width)
> *width = NTB_WIDTH_NONE;
>
> - dev_dbg(ndev_dev(ndev), "link is down.\n");
> + dev_dbg(&ntb->pdev->dev, "link is down.\n");
> }
>
> return ret;
> @@ -254,7 +254,7 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
>
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
> - dev_dbg(ndev_dev(ndev), "Enabling Link.\n");
> + dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
>
> ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
> ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
> @@ -275,7 +275,7 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
>
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
> - dev_dbg(ndev_dev(ndev), "Enabling Link.\n");
> + dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
>
> ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
> ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
> @@ -466,18 +466,19 @@ static void amd_ack_smu(struct amd_ntb_dev *ndev, u32 bit)
> static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> {
> void __iomem *mmio = ndev->self_mmio;
> + struct device *dev = &ndev->ntb.pdev->dev;
> u32 status;
>
> status = readl(mmio + AMD_INTSTAT_OFFSET);
> if (!(status & AMD_EVENT_INTMASK))
> return;
>
> - dev_dbg(ndev_dev(ndev), "status = 0x%x and vec = %d\n", status, vec);
> + dev_dbg(dev, "status = 0x%x and vec = %d\n", status, vec);
>
> status &= AMD_EVENT_INTMASK;
> switch (status) {
> case AMD_PEER_FLUSH_EVENT:
> - dev_info(ndev_dev(ndev), "Flush is done.\n");
> + dev_info(dev, "Flush is done.\n");
> break;
> case AMD_PEER_RESET_EVENT:
> amd_ack_smu(ndev, AMD_PEER_RESET_EVENT);
> @@ -503,7 +504,7 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> status = readl(mmio + AMD_PMESTAT_OFFSET);
> /* check if this is WAKEUP event */
> if (status & 0x1)
> - dev_info(ndev_dev(ndev), "Wakeup is done.\n");
> + dev_info(dev, "Wakeup is done.\n");
>
> amd_ack_smu(ndev, AMD_PEER_D0_EVENT);
>
> @@ -512,14 +513,14 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> AMD_LINK_HB_TIMEOUT);
> break;
> default:
> - dev_info(ndev_dev(ndev), "event status = 0x%x.\n", status);
> + dev_info(dev, "event status = 0x%x.\n", status);
> break;
> }
> }
>
> static irqreturn_t ndev_interrupt(struct amd_ntb_dev *ndev, int vec)
> {
> - dev_dbg(ndev_dev(ndev), "vec %d\n", vec);
> + dev_dbg(&ndev->ntb.pdev->dev, "vec %d\n", vec);
>
> if (vec > (AMD_DB_CNT - 1) || (ndev->msix_vec_count == 1))
> amd_handle_event(ndev, vec);
> @@ -541,7 +542,7 @@ static irqreturn_t ndev_irq_isr(int irq, void *dev)
> {
> struct amd_ntb_dev *ndev = dev;
>
> - return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq);
> + return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq);
> }
>
> static int ndev_init_isr(struct amd_ntb_dev *ndev,
> @@ -550,7 +551,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
> struct pci_dev *pdev;
> int rc, i, msix_count, node;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> node = dev_to_node(&pdev->dev);
>
> @@ -592,7 +593,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
> goto err_msix_request;
> }
>
> - dev_dbg(ndev_dev(ndev), "Using msix interrupts\n");
> + dev_dbg(&pdev->dev, "Using msix interrupts\n");
> ndev->db_count = msix_min;
> ndev->msix_vec_count = msix_max;
> return 0;
> @@ -619,7 +620,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
> if (rc)
> goto err_msi_request;
>
> - dev_dbg(ndev_dev(ndev), "Using msi interrupts\n");
> + dev_dbg(&pdev->dev, "Using msi interrupts\n");
> ndev->db_count = 1;
> ndev->msix_vec_count = 1;
> return 0;
> @@ -636,7 +637,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev,
> if (rc)
> goto err_intx_request;
>
> - dev_dbg(ndev_dev(ndev), "Using intx interrupts\n");
> + dev_dbg(&pdev->dev, "Using intx interrupts\n");
> ndev->db_count = 1;
> ndev->msix_vec_count = 1;
> return 0;
> @@ -651,7 +652,7 @@ static void ndev_deinit_isr(struct amd_ntb_dev *ndev)
> void __iomem *mmio = ndev->self_mmio;
> int i;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> /* Mask all doorbell interrupts */
> ndev->db_mask = ndev->db_valid_mask;
> @@ -777,7 +778,8 @@ static void ndev_init_debugfs(struct amd_ntb_dev *ndev)
> ndev->debugfs_info = NULL;
> } else {
> ndev->debugfs_dir =
> - debugfs_create_dir(ndev_name(ndev), debugfs_dir);
> + debugfs_create_dir(pci_name(ndev->ntb.pdev),
> + debugfs_dir);
> if (!ndev->debugfs_dir)
> ndev->debugfs_info = NULL;
> else
> @@ -812,7 +814,7 @@ static int amd_poll_link(struct amd_ntb_dev *ndev)
> reg = readl(mmio + AMD_SIDEINFO_OFFSET);
> reg &= NTB_LIN_STA_ACTIVE_BIT;
>
> - dev_dbg(ndev_dev(ndev), "%s: reg_val = 0x%x.\n", __func__, reg);
> + dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg);
>
> if (reg == ndev->cntl_sta)
> return 0;
> @@ -894,7 +896,8 @@ static int amd_init_ntb(struct amd_ntb_dev *ndev)
>
> break;
> default:
> - dev_err(ndev_dev(ndev), "AMD NTB does not support B2B mode.\n");
> + dev_err(&ndev->ntb.pdev->dev,
> + "AMD NTB does not support B2B mode.\n");
> return -EINVAL;
> }
>
> @@ -923,10 +926,10 @@ static int amd_init_dev(struct amd_ntb_dev *ndev)
> struct pci_dev *pdev;
> int rc = 0;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> ndev->ntb.topo = amd_get_topo(ndev);
> - dev_dbg(ndev_dev(ndev), "AMD NTB topo is %s\n",
> + dev_dbg(&pdev->dev, "AMD NTB topo is %s\n",
> ntb_topo_string(ndev->ntb.topo));
>
> rc = amd_init_ntb(ndev);
> @@ -935,7 +938,7 @@ static int amd_init_dev(struct amd_ntb_dev *ndev)
>
> rc = amd_init_isr(ndev);
> if (rc) {
> - dev_err(ndev_dev(ndev), "fail to init isr.\n");
> + dev_err(&pdev->dev, "fail to init isr.\n");
> return rc;
> }
>
> @@ -973,7 +976,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
> rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
> if (rc)
> goto err_dma_mask;
> - dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n");
> + dev_warn(&pdev->dev, "Cannot DMA highmem\n");
> }
>
> rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
> @@ -981,7 +984,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
> rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
> if (rc)
> goto err_dma_mask;
> - dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n");
> + dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
> }
>
> ndev->self_mmio = pci_iomap(pdev, 0, 0);
> @@ -1004,7 +1007,7 @@ static int amd_ntb_init_pci(struct amd_ntb_dev *ndev,
>
> static void amd_ntb_deinit_pci(struct amd_ntb_dev *ndev)
> {
> - struct pci_dev *pdev = ndev_pdev(ndev);
> + struct pci_dev *pdev = ndev->ntb.pdev;
>
> pci_iounmap(pdev, ndev->self_mmio);
>
> diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.h b/drivers/ntb/hw/amd/ntb_hw_amd.h
> index 13d73ed..8f3617a 100644
> --- a/drivers/ntb/hw/amd/ntb_hw_amd.h
> +++ b/drivers/ntb/hw/amd/ntb_hw_amd.h
> @@ -211,9 +211,6 @@ struct amd_ntb_dev {
> struct dentry *debugfs_info;
> };
>
> -#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
> -#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
> -#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
> #define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
> #define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/4] ntb_hw_intel: Style fixes: open code macros that just obfuscate code
2017-01-11 0:33 [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
2017-01-11 0:33 ` [PATCH v2 1/4] ntb_hw_amd: Style fixes: open code macros that just obfuscate code Logan Gunthorpe
@ 2017-01-11 0:33 ` Logan Gunthorpe
2017-03-08 16:41 ` Jon Mason
2017-01-11 0:33 ` [PATCH v2 3/4] ntb_hw_amd: Print kernel messages with the ntb device not the pci one Logan Gunthorpe
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Logan Gunthorpe @ 2017-01-11 0:33 UTC (permalink / raw)
To: Xiangliang Yu, Jon Mason, Dave Jiang, Allen Hubbe, Joe Perches
Cc: Greg Kroah-Hartman, linux-ntb, linux-kernel, Logan Gunthorpe
As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should
be cleaned up. This makes it more clear what's actually going on when
reading the code.
[1] http://www.spinics.net/lists/linux-pci/msg56904.html
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
---
drivers/ntb/hw/intel/ntb_hw_intel.c | 192 ++++++++++++++++++------------------
drivers/ntb/hw/intel/ntb_hw_intel.h | 3 -
2 files changed, 95 insertions(+), 100 deletions(-)
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c
index eca9688..6456f54 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.c
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
@@ -270,12 +270,12 @@ static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
if (db_addr) {
*db_addr = reg_addr + reg;
- dev_dbg(ndev_dev(ndev), "Peer db addr %llx\n", *db_addr);
+ dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx\n", *db_addr);
}
if (db_size) {
*db_size = ndev->reg->db_size;
- dev_dbg(ndev_dev(ndev), "Peer db size %llx\n", *db_size);
+ dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size);
}
return 0;
@@ -368,7 +368,8 @@ static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx,
if (spad_addr) {
*spad_addr = reg_addr + reg + (idx << 2);
- dev_dbg(ndev_dev(ndev), "Peer spad addr %llx\n", *spad_addr);
+ dev_dbg(&ndev->ntb.pdev->dev, "Peer spad addr %llx\n",
+ *spad_addr);
}
return 0;
@@ -409,7 +410,7 @@ static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec)
if ((ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) && (vec == 31))
vec_mask |= ndev->db_link_mask;
- dev_dbg(ndev_dev(ndev), "vec %d vec_mask %llx\n", vec, vec_mask);
+ dev_dbg(&ndev->ntb.pdev->dev, "vec %d vec_mask %llx\n", vec, vec_mask);
ndev->last_ts = jiffies;
@@ -428,7 +429,7 @@ static irqreturn_t ndev_vec_isr(int irq, void *dev)
{
struct intel_ntb_vec *nvec = dev;
- dev_dbg(ndev_dev(nvec->ndev), "irq: %d nvec->num: %d\n",
+ dev_dbg(&nvec->ndev->ntb.pdev->dev, "irq: %d nvec->num: %d\n",
irq, nvec->num);
return ndev_interrupt(nvec->ndev, nvec->num);
@@ -438,7 +439,7 @@ static irqreturn_t ndev_irq_isr(int irq, void *dev)
{
struct intel_ntb_dev *ndev = dev;
- return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq);
+ return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq);
}
static int ndev_init_isr(struct intel_ntb_dev *ndev,
@@ -448,7 +449,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
struct pci_dev *pdev;
int rc, i, msix_count, node;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
node = dev_to_node(&pdev->dev);
@@ -487,7 +488,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
goto err_msix_request;
}
- dev_dbg(ndev_dev(ndev), "Using %d msix interrupts\n", msix_count);
+ dev_dbg(&pdev->dev, "Using %d msix interrupts\n", msix_count);
ndev->db_vec_count = msix_count;
ndev->db_vec_shift = msix_shift;
return 0;
@@ -515,7 +516,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
if (rc)
goto err_msi_request;
- dev_dbg(ndev_dev(ndev), "Using msi interrupts\n");
+ dev_dbg(&pdev->dev, "Using msi interrupts\n");
ndev->db_vec_count = 1;
ndev->db_vec_shift = total_shift;
return 0;
@@ -533,7 +534,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
if (rc)
goto err_intx_request;
- dev_dbg(ndev_dev(ndev), "Using intx interrupts\n");
+ dev_dbg(&pdev->dev, "Using intx interrupts\n");
ndev->db_vec_count = 1;
ndev->db_vec_shift = total_shift;
return 0;
@@ -547,7 +548,7 @@ static void ndev_deinit_isr(struct intel_ntb_dev *ndev)
struct pci_dev *pdev;
int i;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
/* Mask all doorbell interrupts */
ndev->db_mask = ndev->db_valid_mask;
@@ -744,7 +745,7 @@ static ssize_t ndev_ntb_debugfs_read(struct file *filp, char __user *ubuf,
union { u64 v64; u32 v32; u16 v16; u8 v8; } u;
ndev = filp->private_data;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
mmio = ndev->self_mmio;
buf_size = min(count, 0x800ul);
@@ -1019,7 +1020,8 @@ static void ndev_init_debugfs(struct intel_ntb_dev *ndev)
ndev->debugfs_info = NULL;
} else {
ndev->debugfs_dir =
- debugfs_create_dir(ndev_name(ndev), debugfs_dir);
+ debugfs_create_dir(pci_name(ndev->ntb.pdev),
+ debugfs_dir);
if (!ndev->debugfs_dir)
ndev->debugfs_info = NULL;
else
@@ -1206,13 +1208,13 @@ static int intel_ntb_link_enable(struct ntb_dev *ntb,
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(ndev_dev(ndev),
+ dev_dbg(&ntb->pdev->dev,
"Enabling link with max_speed %d max_width %d\n",
max_speed, max_width);
if (max_speed != NTB_SPEED_AUTO)
- dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed);
+ dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
if (max_width != NTB_WIDTH_AUTO)
- dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width);
+ dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
@@ -1235,7 +1237,7 @@ static int intel_ntb_link_disable(struct ntb_dev *ntb)
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(ndev_dev(ndev), "Disabling link\n");
+ dev_dbg(&ntb->pdev->dev, "Disabling link\n");
/* Bring NTB link down */
ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
@@ -1442,30 +1444,33 @@ static int atom_link_is_err(struct intel_ntb_dev *ndev)
static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
{
+ struct device *dev = &ndev->ntb.pdev->dev;
+
switch (ppd & ATOM_PPD_TOPO_MASK) {
case ATOM_PPD_TOPO_B2B_USD:
- dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd);
+ dev_dbg(dev, "PPD %d B2B USD\n", ppd);
return NTB_TOPO_B2B_USD;
case ATOM_PPD_TOPO_B2B_DSD:
- dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd);
+ dev_dbg(dev, "PPD %d B2B DSD\n", ppd);
return NTB_TOPO_B2B_DSD;
case ATOM_PPD_TOPO_PRI_USD:
case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
case ATOM_PPD_TOPO_SEC_USD:
case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
- dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd);
+ dev_dbg(dev, "PPD %d non B2B disabled\n", ppd);
return NTB_TOPO_NONE;
}
- dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd);
+ dev_dbg(dev, "PPD %d invalid\n", ppd);
return NTB_TOPO_NONE;
}
static void atom_link_hb(struct work_struct *work)
{
struct intel_ntb_dev *ndev = hb_ndev(work);
+ struct device *dev = &ndev->ntb.pdev->dev;
unsigned long poll_ts;
void __iomem *mmio;
u32 status32;
@@ -1503,30 +1508,30 @@ static void atom_link_hb(struct work_struct *work)
/* Clear AER Errors, write to clear */
status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
- dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32);
+ dev_dbg(dev, "ERRCORSTS = %x\n", status32);
status32 &= PCI_ERR_COR_REP_ROLL;
iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
/* Clear unexpected electrical idle event in LTSSM, write to clear */
status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
- dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32);
+ dev_dbg(dev, "LTSSMERRSTS0 = %x\n", status32);
status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
/* Clear DeSkew Buffer error, write to clear */
status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
- dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32);
+ dev_dbg(dev, "DESKEWSTS = %x\n", status32);
status32 |= ATOM_DESKEWSTS_DBERR;
iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
- dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32);
+ dev_dbg(dev, "IBSTERRRCRVSTS0 = %x\n", status32);
status32 &= ATOM_IBIST_ERR_OFLOW;
iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
/* Releases the NTB state machine to allow the link to retrain */
status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
- dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32);
+ dev_dbg(dev, "LTSSMSTATEJMP = %x\n", status32);
status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
@@ -1677,11 +1682,11 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
int b2b_bar;
u8 bar_sz;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
mmio = ndev->self_mmio;
if (ndev->b2b_idx == UINT_MAX) {
- dev_dbg(ndev_dev(ndev), "not using b2b mw\n");
+ dev_dbg(&pdev->dev, "not using b2b mw\n");
b2b_bar = 0;
ndev->b2b_off = 0;
} else {
@@ -1689,24 +1694,21 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
if (b2b_bar < 0)
return -EIO;
- dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar);
+ dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
- dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
+ dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
if (b2b_mw_share && ((bar_size >> 1) >= XEON_B2B_MIN_SIZE)) {
- dev_dbg(ndev_dev(ndev),
- "b2b using first half of bar\n");
+ dev_dbg(&pdev->dev, "b2b using first half of bar\n");
ndev->b2b_off = bar_size >> 1;
} else if (bar_size >= XEON_B2B_MIN_SIZE) {
- dev_dbg(ndev_dev(ndev),
- "b2b using whole bar\n");
+ dev_dbg(&pdev->dev, "b2b using whole bar\n");
ndev->b2b_off = 0;
--ndev->mw_count;
} else {
- dev_dbg(ndev_dev(ndev),
- "b2b bar size is too small\n");
+ dev_dbg(&pdev->dev, "b2b bar size is too small\n");
return -EIO;
}
}
@@ -1716,7 +1718,7 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
* except disable or halve the size of the b2b secondary bar.
*/
pci_read_config_byte(pdev, SKX_IMBAR1SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "IMBAR1SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "IMBAR1SZ %#x\n", bar_sz);
if (b2b_bar == 1) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -1726,10 +1728,10 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
pci_write_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "EMBAR1SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "EMBAR1SZ %#x\n", bar_sz);
pci_read_config_byte(pdev, SKX_IMBAR2SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "IMBAR2SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "IMBAR2SZ %#x\n", bar_sz);
if (b2b_bar == 2) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -1739,7 +1741,7 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
pci_write_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "EMBAR2SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "EMBAR2SZ %#x\n", bar_sz);
/* SBAR01 hit by first part of the b2b bar */
if (b2b_bar == 0)
@@ -1755,12 +1757,12 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = addr->bar2_addr64 + (b2b_bar == 1 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET);
bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "IMBAR1XLMT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
bar_addr = addr->bar4_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET);
bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "IMBAR2XLMT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
/* zero incoming translation addrs */
iowrite64(0, mmio + SKX_IMBAR1XBASE_OFFSET);
@@ -1830,7 +1832,7 @@ static int skx_init_dev(struct intel_ntb_dev *ndev)
u8 ppd;
int rc;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
ndev->reg = &skx_reg;
@@ -1839,7 +1841,7 @@ static int skx_init_dev(struct intel_ntb_dev *ndev)
return -EIO;
ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
- dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
+ dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
ntb_topo_string(ndev->ntb.topo));
if (ndev->ntb.topo == NTB_TOPO_NONE)
return -EINVAL;
@@ -1863,14 +1865,14 @@ static int intel_ntb3_link_enable(struct ntb_dev *ntb,
ndev = container_of(ntb, struct intel_ntb_dev, ntb);
- dev_dbg(ndev_dev(ndev),
+ dev_dbg(&ntb->pdev->dev,
"Enabling link with max_speed %d max_width %d\n",
max_speed, max_width);
if (max_speed != NTB_SPEED_AUTO)
- dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed);
+ dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
if (max_width != NTB_WIDTH_AUTO)
- dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width);
+ dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
@@ -1931,7 +1933,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(ndev_dev(ndev), "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
/* set and verify setting the limit */
iowrite64(limit, mmio + limit_reg);
@@ -1942,7 +1944,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(ndev_dev(ndev), "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
/* setup the EP */
limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
@@ -1963,7 +1965,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(ndev_dev(ndev), "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
return 0;
}
@@ -2070,7 +2072,7 @@ static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)
static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)
{
if (ppd & XEON_PPD_SPLIT_BAR_MASK) {
- dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd);
+ dev_dbg(&ndev->ntb.pdev->dev, "PPD %d split bar\n", ppd);
return 1;
}
return 0;
@@ -2100,11 +2102,11 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
int b2b_bar;
u8 bar_sz;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
mmio = ndev->self_mmio;
if (ndev->b2b_idx == UINT_MAX) {
- dev_dbg(ndev_dev(ndev), "not using b2b mw\n");
+ dev_dbg(&pdev->dev, "not using b2b mw\n");
b2b_bar = 0;
ndev->b2b_off = 0;
} else {
@@ -2112,24 +2114,21 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
if (b2b_bar < 0)
return -EIO;
- dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar);
+ dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
- dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
+ dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) {
- dev_dbg(ndev_dev(ndev),
- "b2b using first half of bar\n");
+ dev_dbg(&pdev->dev, "b2b using first half of bar\n");
ndev->b2b_off = bar_size >> 1;
} else if (XEON_B2B_MIN_SIZE <= bar_size) {
- dev_dbg(ndev_dev(ndev),
- "b2b using whole bar\n");
+ dev_dbg(&pdev->dev, "b2b using whole bar\n");
ndev->b2b_off = 0;
--ndev->mw_count;
} else {
- dev_dbg(ndev_dev(ndev),
- "b2b bar size is too small\n");
+ dev_dbg(&pdev->dev, "b2b bar size is too small\n");
return -EIO;
}
}
@@ -2141,7 +2140,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
* offsets are not in a consistent order (bar5sz comes after ppd, odd).
*/
pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz);
if (b2b_bar == 2) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2150,11 +2149,11 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz);
if (!ndev->bar4_split) {
pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz);
if (b2b_bar == 4) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2163,10 +2162,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz);
} else {
pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz);
if (b2b_bar == 4) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2175,10 +2174,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz);
pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz);
if (b2b_bar == 5) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2187,7 +2186,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz);
- dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz);
+ dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz);
}
/* SBAR01 hit by first part of the b2b bar */
@@ -2204,7 +2203,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
else
return -EIO;
- dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR01 %#018llx\n", bar_addr);
iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET);
/* Other SBAR are normally hit by the PBAR xlat, except for b2b bar.
@@ -2215,26 +2214,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR23 %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = addr->bar4_addr64 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR45 %#018llx\n", bar_addr);
} else {
bar_addr = addr->bar4_addr32 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR4 %#010llx\n", bar_addr);
bar_addr = addr->bar5_addr32 +
(b2b_bar == 5 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR5 %#010llx\n", bar_addr);
}
/* setup incoming bar limits == base addrs (zero length windows) */
@@ -2242,26 +2241,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR23LMT %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = addr->bar4_addr64 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR45LMT %#018llx\n", bar_addr);
} else {
bar_addr = addr->bar4_addr32 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR4LMT %#010llx\n", bar_addr);
bar_addr = addr->bar5_addr32 +
(b2b_bar == 5 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);
- dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "SBAR5LMT %#05llx\n", bar_addr);
}
/* zero incoming translation addrs */
@@ -2287,23 +2286,23 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = peer_addr->bar2_addr64;
iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
- dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "PBAR23XLAT %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = peer_addr->bar4_addr64;
iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
- dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "PBAR45XLAT %#018llx\n", bar_addr);
} else {
bar_addr = peer_addr->bar4_addr32;
iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET);
bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
- dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "PBAR4XLAT %#010llx\n", bar_addr);
bar_addr = peer_addr->bar5_addr32;
iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET);
bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
- dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "PBAR5XLAT %#010llx\n", bar_addr);
}
/* set the translation offset for b2b registers */
@@ -2321,7 +2320,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
return -EIO;
/* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */
- dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr);
+ dev_dbg(&pdev->dev, "B2BXLAT %#018llx\n", bar_addr);
iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL);
iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU);
@@ -2340,6 +2339,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
static int xeon_init_ntb(struct intel_ntb_dev *ndev)
{
+ struct device *dev = &ndev->ntb.pdev->dev;
int rc;
u32 ntb_ctl;
@@ -2355,7 +2355,7 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
switch (ndev->ntb.topo) {
case NTB_TOPO_PRI:
if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
- dev_err(ndev_dev(ndev), "NTB Primary config disabled\n");
+ dev_err(dev, "NTB Primary config disabled\n");
return -EINVAL;
}
@@ -2373,7 +2373,7 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
case NTB_TOPO_SEC:
if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
- dev_err(ndev_dev(ndev), "NTB Secondary config disabled\n");
+ dev_err(dev, "NTB Secondary config disabled\n");
return -EINVAL;
}
/* use half the spads for the peer */
@@ -2398,18 +2398,17 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
ndev->b2b_idx = b2b_mw_idx;
if (ndev->b2b_idx >= ndev->mw_count) {
- dev_dbg(ndev_dev(ndev),
+ dev_dbg(dev,
"b2b_mw_idx %d invalid for mw_count %u\n",
b2b_mw_idx, ndev->mw_count);
return -EINVAL;
}
- dev_dbg(ndev_dev(ndev),
- "setting up b2b mw idx %d means %d\n",
+ dev_dbg(dev, "setting up b2b mw idx %d means %d\n",
b2b_mw_idx, ndev->b2b_idx);
} else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) {
- dev_warn(ndev_dev(ndev), "Reduce doorbell count by 1\n");
+ dev_warn(dev, "Reduce doorbell count by 1\n");
ndev->db_count -= 1;
}
@@ -2450,7 +2449,7 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
u8 ppd;
int rc, mem;
- pdev = ndev_pdev(ndev);
+ pdev = ndev->ntb.pdev;
switch (pdev->device) {
/* There is a Xeon hardware errata related to writes to SDOORBELL or
@@ -2526,14 +2525,14 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
return -EIO;
ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
- dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
+ dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
ntb_topo_string(ndev->ntb.topo));
if (ndev->ntb.topo == NTB_TOPO_NONE)
return -EINVAL;
if (ndev->ntb.topo != NTB_TOPO_SEC) {
ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd);
- dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n",
+ dev_dbg(&pdev->dev, "ppd %#x bar4_split %d\n",
ppd, ndev->bar4_split);
} else {
/* This is a way for transparent BAR to figure out if we are
@@ -2543,7 +2542,7 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
mem = pci_select_bars(pdev, IORESOURCE_MEM);
ndev->bar4_split = hweight32(mem) ==
HSX_SPLIT_BAR_MW_COUNT + 1;
- dev_dbg(ndev_dev(ndev), "mem %#x bar4_split %d\n",
+ dev_dbg(&pdev->dev, "mem %#x bar4_split %d\n",
mem, ndev->bar4_split);
}
@@ -2580,7 +2579,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc)
goto err_dma_mask;
- dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n");
+ dev_warn(&pdev->dev, "Cannot DMA highmem\n");
}
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
@@ -2588,7 +2587,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
if (rc)
goto err_dma_mask;
- dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n");
+ dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
}
ndev->self_mmio = pci_iomap(pdev, 0, 0);
@@ -2614,7 +2613,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
static void intel_ntb_deinit_pci(struct intel_ntb_dev *ndev)
{
- struct pci_dev *pdev = ndev_pdev(ndev);
+ struct pci_dev *pdev = ndev->ntb.pdev;
if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio)
pci_iounmap(pdev, ndev->peer_mmio);
@@ -2986,4 +2985,3 @@ static void __exit intel_ntb_pci_driver_exit(void)
debugfs_remove_recursive(debugfs_dir);
}
module_exit(intel_ntb_pci_driver_exit);
-
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index f2cf8a7..2d6c38a 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -382,9 +382,6 @@ struct intel_ntb_dev {
struct dentry *debugfs_info;
};
-#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
-#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
-#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
hb_timer.work)
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 2/4] ntb_hw_intel: Style fixes: open code macros that just obfuscate code
2017-01-11 0:33 ` [PATCH v2 2/4] ntb_hw_intel: " Logan Gunthorpe
@ 2017-03-08 16:41 ` Jon Mason
0 siblings, 0 replies; 11+ messages in thread
From: Jon Mason @ 2017-03-08 16:41 UTC (permalink / raw)
To: Logan Gunthorpe
Cc: Xiangliang Yu, Dave Jiang, Allen Hubbe, Joe Perches,
Greg Kroah-Hartman, linux-ntb, linux-kernel
On Tue, Jan 10, 2017 at 05:33:37PM -0700, Logan Gunthorpe wrote:
> As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should
> be cleaned up. This makes it more clear what's actually going on when
> reading the code.
>
> [1] http://www.spinics.net/lists/linux-pci/msg56904.html
>
> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
Applied to my ntb-next branch
Thanks,
Jon
> ---
> drivers/ntb/hw/intel/ntb_hw_intel.c | 192 ++++++++++++++++++------------------
> drivers/ntb/hw/intel/ntb_hw_intel.h | 3 -
> 2 files changed, 95 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c
> index eca9688..6456f54 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_intel.c
> +++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
> @@ -270,12 +270,12 @@ static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
>
> if (db_addr) {
> *db_addr = reg_addr + reg;
> - dev_dbg(ndev_dev(ndev), "Peer db addr %llx\n", *db_addr);
> + dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx\n", *db_addr);
> }
>
> if (db_size) {
> *db_size = ndev->reg->db_size;
> - dev_dbg(ndev_dev(ndev), "Peer db size %llx\n", *db_size);
> + dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size);
> }
>
> return 0;
> @@ -368,7 +368,8 @@ static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx,
>
> if (spad_addr) {
> *spad_addr = reg_addr + reg + (idx << 2);
> - dev_dbg(ndev_dev(ndev), "Peer spad addr %llx\n", *spad_addr);
> + dev_dbg(&ndev->ntb.pdev->dev, "Peer spad addr %llx\n",
> + *spad_addr);
> }
>
> return 0;
> @@ -409,7 +410,7 @@ static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec)
> if ((ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) && (vec == 31))
> vec_mask |= ndev->db_link_mask;
>
> - dev_dbg(ndev_dev(ndev), "vec %d vec_mask %llx\n", vec, vec_mask);
> + dev_dbg(&ndev->ntb.pdev->dev, "vec %d vec_mask %llx\n", vec, vec_mask);
>
> ndev->last_ts = jiffies;
>
> @@ -428,7 +429,7 @@ static irqreturn_t ndev_vec_isr(int irq, void *dev)
> {
> struct intel_ntb_vec *nvec = dev;
>
> - dev_dbg(ndev_dev(nvec->ndev), "irq: %d nvec->num: %d\n",
> + dev_dbg(&nvec->ndev->ntb.pdev->dev, "irq: %d nvec->num: %d\n",
> irq, nvec->num);
>
> return ndev_interrupt(nvec->ndev, nvec->num);
> @@ -438,7 +439,7 @@ static irqreturn_t ndev_irq_isr(int irq, void *dev)
> {
> struct intel_ntb_dev *ndev = dev;
>
> - return ndev_interrupt(ndev, irq - ndev_pdev(ndev)->irq);
> + return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq);
> }
>
> static int ndev_init_isr(struct intel_ntb_dev *ndev,
> @@ -448,7 +449,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
> struct pci_dev *pdev;
> int rc, i, msix_count, node;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> node = dev_to_node(&pdev->dev);
>
> @@ -487,7 +488,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
> goto err_msix_request;
> }
>
> - dev_dbg(ndev_dev(ndev), "Using %d msix interrupts\n", msix_count);
> + dev_dbg(&pdev->dev, "Using %d msix interrupts\n", msix_count);
> ndev->db_vec_count = msix_count;
> ndev->db_vec_shift = msix_shift;
> return 0;
> @@ -515,7 +516,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
> if (rc)
> goto err_msi_request;
>
> - dev_dbg(ndev_dev(ndev), "Using msi interrupts\n");
> + dev_dbg(&pdev->dev, "Using msi interrupts\n");
> ndev->db_vec_count = 1;
> ndev->db_vec_shift = total_shift;
> return 0;
> @@ -533,7 +534,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
> if (rc)
> goto err_intx_request;
>
> - dev_dbg(ndev_dev(ndev), "Using intx interrupts\n");
> + dev_dbg(&pdev->dev, "Using intx interrupts\n");
> ndev->db_vec_count = 1;
> ndev->db_vec_shift = total_shift;
> return 0;
> @@ -547,7 +548,7 @@ static void ndev_deinit_isr(struct intel_ntb_dev *ndev)
> struct pci_dev *pdev;
> int i;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> /* Mask all doorbell interrupts */
> ndev->db_mask = ndev->db_valid_mask;
> @@ -744,7 +745,7 @@ static ssize_t ndev_ntb_debugfs_read(struct file *filp, char __user *ubuf,
> union { u64 v64; u32 v32; u16 v16; u8 v8; } u;
>
> ndev = filp->private_data;
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
> mmio = ndev->self_mmio;
>
> buf_size = min(count, 0x800ul);
> @@ -1019,7 +1020,8 @@ static void ndev_init_debugfs(struct intel_ntb_dev *ndev)
> ndev->debugfs_info = NULL;
> } else {
> ndev->debugfs_dir =
> - debugfs_create_dir(ndev_name(ndev), debugfs_dir);
> + debugfs_create_dir(pci_name(ndev->ntb.pdev),
> + debugfs_dir);
> if (!ndev->debugfs_dir)
> ndev->debugfs_info = NULL;
> else
> @@ -1206,13 +1208,13 @@ static int intel_ntb_link_enable(struct ntb_dev *ntb,
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
>
> - dev_dbg(ndev_dev(ndev),
> + dev_dbg(&ntb->pdev->dev,
> "Enabling link with max_speed %d max_width %d\n",
> max_speed, max_width);
> if (max_speed != NTB_SPEED_AUTO)
> - dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed);
> + dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
> if (max_width != NTB_WIDTH_AUTO)
> - dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width);
> + dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
>
> ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
> ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
> @@ -1235,7 +1237,7 @@ static int intel_ntb_link_disable(struct ntb_dev *ntb)
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
>
> - dev_dbg(ndev_dev(ndev), "Disabling link\n");
> + dev_dbg(&ntb->pdev->dev, "Disabling link\n");
>
> /* Bring NTB link down */
> ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
> @@ -1442,30 +1444,33 @@ static int atom_link_is_err(struct intel_ntb_dev *ndev)
>
> static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
> {
> + struct device *dev = &ndev->ntb.pdev->dev;
> +
> switch (ppd & ATOM_PPD_TOPO_MASK) {
> case ATOM_PPD_TOPO_B2B_USD:
> - dev_dbg(ndev_dev(ndev), "PPD %d B2B USD\n", ppd);
> + dev_dbg(dev, "PPD %d B2B USD\n", ppd);
> return NTB_TOPO_B2B_USD;
>
> case ATOM_PPD_TOPO_B2B_DSD:
> - dev_dbg(ndev_dev(ndev), "PPD %d B2B DSD\n", ppd);
> + dev_dbg(dev, "PPD %d B2B DSD\n", ppd);
> return NTB_TOPO_B2B_DSD;
>
> case ATOM_PPD_TOPO_PRI_USD:
> case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
> case ATOM_PPD_TOPO_SEC_USD:
> case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
> - dev_dbg(ndev_dev(ndev), "PPD %d non B2B disabled\n", ppd);
> + dev_dbg(dev, "PPD %d non B2B disabled\n", ppd);
> return NTB_TOPO_NONE;
> }
>
> - dev_dbg(ndev_dev(ndev), "PPD %d invalid\n", ppd);
> + dev_dbg(dev, "PPD %d invalid\n", ppd);
> return NTB_TOPO_NONE;
> }
>
> static void atom_link_hb(struct work_struct *work)
> {
> struct intel_ntb_dev *ndev = hb_ndev(work);
> + struct device *dev = &ndev->ntb.pdev->dev;
> unsigned long poll_ts;
> void __iomem *mmio;
> u32 status32;
> @@ -1503,30 +1508,30 @@ static void atom_link_hb(struct work_struct *work)
>
> /* Clear AER Errors, write to clear */
> status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
> - dev_dbg(ndev_dev(ndev), "ERRCORSTS = %x\n", status32);
> + dev_dbg(dev, "ERRCORSTS = %x\n", status32);
> status32 &= PCI_ERR_COR_REP_ROLL;
> iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
>
> /* Clear unexpected electrical idle event in LTSSM, write to clear */
> status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
> - dev_dbg(ndev_dev(ndev), "LTSSMERRSTS0 = %x\n", status32);
> + dev_dbg(dev, "LTSSMERRSTS0 = %x\n", status32);
> status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
> iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
>
> /* Clear DeSkew Buffer error, write to clear */
> status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
> - dev_dbg(ndev_dev(ndev), "DESKEWSTS = %x\n", status32);
> + dev_dbg(dev, "DESKEWSTS = %x\n", status32);
> status32 |= ATOM_DESKEWSTS_DBERR;
> iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
>
> status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
> - dev_dbg(ndev_dev(ndev), "IBSTERRRCRVSTS0 = %x\n", status32);
> + dev_dbg(dev, "IBSTERRRCRVSTS0 = %x\n", status32);
> status32 &= ATOM_IBIST_ERR_OFLOW;
> iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
>
> /* Releases the NTB state machine to allow the link to retrain */
> status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
> - dev_dbg(ndev_dev(ndev), "LTSSMSTATEJMP = %x\n", status32);
> + dev_dbg(dev, "LTSSMSTATEJMP = %x\n", status32);
> status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
> iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
>
> @@ -1677,11 +1682,11 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
> int b2b_bar;
> u8 bar_sz;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
> mmio = ndev->self_mmio;
>
> if (ndev->b2b_idx == UINT_MAX) {
> - dev_dbg(ndev_dev(ndev), "not using b2b mw\n");
> + dev_dbg(&pdev->dev, "not using b2b mw\n");
> b2b_bar = 0;
> ndev->b2b_off = 0;
> } else {
> @@ -1689,24 +1694,21 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
> if (b2b_bar < 0)
> return -EIO;
>
> - dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar);
> + dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
>
> bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
>
> - dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
> + dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
>
> if (b2b_mw_share && ((bar_size >> 1) >= XEON_B2B_MIN_SIZE)) {
> - dev_dbg(ndev_dev(ndev),
> - "b2b using first half of bar\n");
> + dev_dbg(&pdev->dev, "b2b using first half of bar\n");
> ndev->b2b_off = bar_size >> 1;
> } else if (bar_size >= XEON_B2B_MIN_SIZE) {
> - dev_dbg(ndev_dev(ndev),
> - "b2b using whole bar\n");
> + dev_dbg(&pdev->dev, "b2b using whole bar\n");
> ndev->b2b_off = 0;
> --ndev->mw_count;
> } else {
> - dev_dbg(ndev_dev(ndev),
> - "b2b bar size is too small\n");
> + dev_dbg(&pdev->dev, "b2b bar size is too small\n");
> return -EIO;
> }
> }
> @@ -1716,7 +1718,7 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
> * except disable or halve the size of the b2b secondary bar.
> */
> pci_read_config_byte(pdev, SKX_IMBAR1SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "IMBAR1SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "IMBAR1SZ %#x\n", bar_sz);
> if (b2b_bar == 1) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -1726,10 +1728,10 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
>
> pci_write_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, SKX_EMBAR1SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "EMBAR1SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "EMBAR1SZ %#x\n", bar_sz);
>
> pci_read_config_byte(pdev, SKX_IMBAR2SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "IMBAR2SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "IMBAR2SZ %#x\n", bar_sz);
> if (b2b_bar == 2) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -1739,7 +1741,7 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
>
> pci_write_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, SKX_EMBAR2SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "EMBAR2SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "EMBAR2SZ %#x\n", bar_sz);
>
> /* SBAR01 hit by first part of the b2b bar */
> if (b2b_bar == 0)
> @@ -1755,12 +1757,12 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
> bar_addr = addr->bar2_addr64 + (b2b_bar == 1 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET);
> bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "IMBAR1XLMT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
>
> bar_addr = addr->bar4_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET);
> bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "IMBAR2XLMT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
>
> /* zero incoming translation addrs */
> iowrite64(0, mmio + SKX_IMBAR1XBASE_OFFSET);
> @@ -1830,7 +1832,7 @@ static int skx_init_dev(struct intel_ntb_dev *ndev)
> u8 ppd;
> int rc;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> ndev->reg = &skx_reg;
>
> @@ -1839,7 +1841,7 @@ static int skx_init_dev(struct intel_ntb_dev *ndev)
> return -EIO;
>
> ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
> - dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
> + dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
> ntb_topo_string(ndev->ntb.topo));
> if (ndev->ntb.topo == NTB_TOPO_NONE)
> return -EINVAL;
> @@ -1863,14 +1865,14 @@ static int intel_ntb3_link_enable(struct ntb_dev *ntb,
>
> ndev = container_of(ntb, struct intel_ntb_dev, ntb);
>
> - dev_dbg(ndev_dev(ndev),
> + dev_dbg(&ntb->pdev->dev,
> "Enabling link with max_speed %d max_width %d\n",
> max_speed, max_width);
>
> if (max_speed != NTB_SPEED_AUTO)
> - dev_dbg(ndev_dev(ndev), "ignoring max_speed %d\n", max_speed);
> + dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
> if (max_width != NTB_WIDTH_AUTO)
> - dev_dbg(ndev_dev(ndev), "ignoring max_width %d\n", max_width);
> + dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
>
> ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
> ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
> @@ -1931,7 +1933,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
> return -EIO;
> }
>
> - dev_dbg(ndev_dev(ndev), "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
> + dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
>
> /* set and verify setting the limit */
> iowrite64(limit, mmio + limit_reg);
> @@ -1942,7 +1944,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
> return -EIO;
> }
>
> - dev_dbg(ndev_dev(ndev), "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
> + dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
>
> /* setup the EP */
> limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
> @@ -1963,7 +1965,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
> return -EIO;
> }
>
> - dev_dbg(ndev_dev(ndev), "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
> + dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
>
> return 0;
> }
> @@ -2070,7 +2072,7 @@ static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)
> static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)
> {
> if (ppd & XEON_PPD_SPLIT_BAR_MASK) {
> - dev_dbg(ndev_dev(ndev), "PPD %d split bar\n", ppd);
> + dev_dbg(&ndev->ntb.pdev->dev, "PPD %d split bar\n", ppd);
> return 1;
> }
> return 0;
> @@ -2100,11 +2102,11 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> int b2b_bar;
> u8 bar_sz;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
> mmio = ndev->self_mmio;
>
> if (ndev->b2b_idx == UINT_MAX) {
> - dev_dbg(ndev_dev(ndev), "not using b2b mw\n");
> + dev_dbg(&pdev->dev, "not using b2b mw\n");
> b2b_bar = 0;
> ndev->b2b_off = 0;
> } else {
> @@ -2112,24 +2114,21 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> if (b2b_bar < 0)
> return -EIO;
>
> - dev_dbg(ndev_dev(ndev), "using b2b mw bar %d\n", b2b_bar);
> + dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
>
> bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
>
> - dev_dbg(ndev_dev(ndev), "b2b bar size %#llx\n", bar_size);
> + dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
>
> if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) {
> - dev_dbg(ndev_dev(ndev),
> - "b2b using first half of bar\n");
> + dev_dbg(&pdev->dev, "b2b using first half of bar\n");
> ndev->b2b_off = bar_size >> 1;
> } else if (XEON_B2B_MIN_SIZE <= bar_size) {
> - dev_dbg(ndev_dev(ndev),
> - "b2b using whole bar\n");
> + dev_dbg(&pdev->dev, "b2b using whole bar\n");
> ndev->b2b_off = 0;
> --ndev->mw_count;
> } else {
> - dev_dbg(ndev_dev(ndev),
> - "b2b bar size is too small\n");
> + dev_dbg(&pdev->dev, "b2b bar size is too small\n");
> return -EIO;
> }
> }
> @@ -2141,7 +2140,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> * offsets are not in a consistent order (bar5sz comes after ppd, odd).
> */
> pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "PBAR23SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz);
> if (b2b_bar == 2) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -2150,11 +2149,11 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> }
> pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "SBAR23SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz);
>
> if (!ndev->bar4_split) {
> pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "PBAR45SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz);
> if (b2b_bar == 4) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -2163,10 +2162,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> }
> pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "SBAR45SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz);
> } else {
> pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "PBAR4SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz);
> if (b2b_bar == 4) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -2175,10 +2174,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> }
> pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "SBAR4SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz);
>
> pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "PBAR5SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz);
> if (b2b_bar == 5) {
> if (ndev->b2b_off)
> bar_sz -= 1;
> @@ -2187,7 +2186,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> }
> pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz);
> pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz);
> - dev_dbg(ndev_dev(ndev), "SBAR5SZ %#x\n", bar_sz);
> + dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz);
> }
>
> /* SBAR01 hit by first part of the b2b bar */
> @@ -2204,7 +2203,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> else
> return -EIO;
>
> - dev_dbg(ndev_dev(ndev), "SBAR01 %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR01 %#018llx\n", bar_addr);
> iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET);
>
> /* Other SBAR are normally hit by the PBAR xlat, except for b2b bar.
> @@ -2215,26 +2214,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET);
> bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR23 %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR23 %#018llx\n", bar_addr);
>
> if (!ndev->bar4_split) {
> bar_addr = addr->bar4_addr64 +
> (b2b_bar == 4 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET);
> bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR45 %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR45 %#018llx\n", bar_addr);
> } else {
> bar_addr = addr->bar4_addr32 +
> (b2b_bar == 4 ? ndev->b2b_off : 0);
> iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET);
> bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR4 %#010llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR4 %#010llx\n", bar_addr);
>
> bar_addr = addr->bar5_addr32 +
> (b2b_bar == 5 ? ndev->b2b_off : 0);
> iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET);
> bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR5 %#010llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR5 %#010llx\n", bar_addr);
> }
>
> /* setup incoming bar limits == base addrs (zero length windows) */
> @@ -2242,26 +2241,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET);
> bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR23LMT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR23LMT %#018llx\n", bar_addr);
>
> if (!ndev->bar4_split) {
> bar_addr = addr->bar4_addr64 +
> (b2b_bar == 4 ? ndev->b2b_off : 0);
> iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET);
> bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR45LMT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR45LMT %#018llx\n", bar_addr);
> } else {
> bar_addr = addr->bar4_addr32 +
> (b2b_bar == 4 ? ndev->b2b_off : 0);
> iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET);
> bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR4LMT %#010llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR4LMT %#010llx\n", bar_addr);
>
> bar_addr = addr->bar5_addr32 +
> (b2b_bar == 5 ? ndev->b2b_off : 0);
> iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET);
> bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "SBAR5LMT %#05llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "SBAR5LMT %#05llx\n", bar_addr);
> }
>
> /* zero incoming translation addrs */
> @@ -2287,23 +2286,23 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> bar_addr = peer_addr->bar2_addr64;
> iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET);
> bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "PBAR23XLAT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "PBAR23XLAT %#018llx\n", bar_addr);
>
> if (!ndev->bar4_split) {
> bar_addr = peer_addr->bar4_addr64;
> iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET);
> bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "PBAR45XLAT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "PBAR45XLAT %#018llx\n", bar_addr);
> } else {
> bar_addr = peer_addr->bar4_addr32;
> iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET);
> bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "PBAR4XLAT %#010llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "PBAR4XLAT %#010llx\n", bar_addr);
>
> bar_addr = peer_addr->bar5_addr32;
> iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET);
> bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
> - dev_dbg(ndev_dev(ndev), "PBAR5XLAT %#010llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "PBAR5XLAT %#010llx\n", bar_addr);
> }
>
> /* set the translation offset for b2b registers */
> @@ -2321,7 +2320,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
> return -EIO;
>
> /* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */
> - dev_dbg(ndev_dev(ndev), "B2BXLAT %#018llx\n", bar_addr);
> + dev_dbg(&pdev->dev, "B2BXLAT %#018llx\n", bar_addr);
> iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL);
> iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU);
>
> @@ -2340,6 +2339,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
>
> static int xeon_init_ntb(struct intel_ntb_dev *ndev)
> {
> + struct device *dev = &ndev->ntb.pdev->dev;
> int rc;
> u32 ntb_ctl;
>
> @@ -2355,7 +2355,7 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
> switch (ndev->ntb.topo) {
> case NTB_TOPO_PRI:
> if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
> - dev_err(ndev_dev(ndev), "NTB Primary config disabled\n");
> + dev_err(dev, "NTB Primary config disabled\n");
> return -EINVAL;
> }
>
> @@ -2373,7 +2373,7 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
>
> case NTB_TOPO_SEC:
> if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
> - dev_err(ndev_dev(ndev), "NTB Secondary config disabled\n");
> + dev_err(dev, "NTB Secondary config disabled\n");
> return -EINVAL;
> }
> /* use half the spads for the peer */
> @@ -2398,18 +2398,17 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
> ndev->b2b_idx = b2b_mw_idx;
>
> if (ndev->b2b_idx >= ndev->mw_count) {
> - dev_dbg(ndev_dev(ndev),
> + dev_dbg(dev,
> "b2b_mw_idx %d invalid for mw_count %u\n",
> b2b_mw_idx, ndev->mw_count);
> return -EINVAL;
> }
>
> - dev_dbg(ndev_dev(ndev),
> - "setting up b2b mw idx %d means %d\n",
> + dev_dbg(dev, "setting up b2b mw idx %d means %d\n",
> b2b_mw_idx, ndev->b2b_idx);
>
> } else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) {
> - dev_warn(ndev_dev(ndev), "Reduce doorbell count by 1\n");
> + dev_warn(dev, "Reduce doorbell count by 1\n");
> ndev->db_count -= 1;
> }
>
> @@ -2450,7 +2449,7 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
> u8 ppd;
> int rc, mem;
>
> - pdev = ndev_pdev(ndev);
> + pdev = ndev->ntb.pdev;
>
> switch (pdev->device) {
> /* There is a Xeon hardware errata related to writes to SDOORBELL or
> @@ -2526,14 +2525,14 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
> return -EIO;
>
> ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
> - dev_dbg(ndev_dev(ndev), "ppd %#x topo %s\n", ppd,
> + dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
> ntb_topo_string(ndev->ntb.topo));
> if (ndev->ntb.topo == NTB_TOPO_NONE)
> return -EINVAL;
>
> if (ndev->ntb.topo != NTB_TOPO_SEC) {
> ndev->bar4_split = xeon_ppd_bar4_split(ndev, ppd);
> - dev_dbg(ndev_dev(ndev), "ppd %#x bar4_split %d\n",
> + dev_dbg(&pdev->dev, "ppd %#x bar4_split %d\n",
> ppd, ndev->bar4_split);
> } else {
> /* This is a way for transparent BAR to figure out if we are
> @@ -2543,7 +2542,7 @@ static int xeon_init_dev(struct intel_ntb_dev *ndev)
> mem = pci_select_bars(pdev, IORESOURCE_MEM);
> ndev->bar4_split = hweight32(mem) ==
> HSX_SPLIT_BAR_MW_COUNT + 1;
> - dev_dbg(ndev_dev(ndev), "mem %#x bar4_split %d\n",
> + dev_dbg(&pdev->dev, "mem %#x bar4_split %d\n",
> mem, ndev->bar4_split);
> }
>
> @@ -2580,7 +2579,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
> rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
> if (rc)
> goto err_dma_mask;
> - dev_warn(ndev_dev(ndev), "Cannot DMA highmem\n");
> + dev_warn(&pdev->dev, "Cannot DMA highmem\n");
> }
>
> rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
> @@ -2588,7 +2587,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
> rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
> if (rc)
> goto err_dma_mask;
> - dev_warn(ndev_dev(ndev), "Cannot DMA consistent highmem\n");
> + dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
> }
>
> ndev->self_mmio = pci_iomap(pdev, 0, 0);
> @@ -2614,7 +2613,7 @@ static int intel_ntb_init_pci(struct intel_ntb_dev *ndev, struct pci_dev *pdev)
>
> static void intel_ntb_deinit_pci(struct intel_ntb_dev *ndev)
> {
> - struct pci_dev *pdev = ndev_pdev(ndev);
> + struct pci_dev *pdev = ndev->ntb.pdev;
>
> if (ndev->peer_mmio && ndev->peer_mmio != ndev->self_mmio)
> pci_iounmap(pdev, ndev->peer_mmio);
> @@ -2986,4 +2985,3 @@ static void __exit intel_ntb_pci_driver_exit(void)
> debugfs_remove_recursive(debugfs_dir);
> }
> module_exit(intel_ntb_pci_driver_exit);
> -
> diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
> index f2cf8a7..2d6c38a 100644
> --- a/drivers/ntb/hw/intel/ntb_hw_intel.h
> +++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
> @@ -382,9 +382,6 @@ struct intel_ntb_dev {
> struct dentry *debugfs_info;
> };
>
> -#define ndev_pdev(ndev) ((ndev)->ntb.pdev)
> -#define ndev_name(ndev) pci_name(ndev_pdev(ndev))
> -#define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
> #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
> #define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
> hb_timer.work)
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/4] ntb_hw_amd: Print kernel messages with the ntb device not the pci one
2017-01-11 0:33 [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
2017-01-11 0:33 ` [PATCH v2 1/4] ntb_hw_amd: Style fixes: open code macros that just obfuscate code Logan Gunthorpe
2017-01-11 0:33 ` [PATCH v2 2/4] ntb_hw_intel: " Logan Gunthorpe
@ 2017-01-11 0:33 ` Logan Gunthorpe
2017-03-08 16:43 ` Jon Mason
2017-01-11 0:33 ` [PATCH v2 4/4] ntb_hw_intel: " Logan Gunthorpe
2017-01-26 20:00 ` [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
4 siblings, 1 reply; 11+ messages in thread
From: Logan Gunthorpe @ 2017-01-11 0:33 UTC (permalink / raw)
To: Xiangliang Yu, Jon Mason, Dave Jiang, Allen Hubbe, Joe Perches
Cc: Greg Kroah-Hartman, linux-ntb, linux-kernel, Logan Gunthorpe
Now that macros are open it's pretty clear that these should print
using the NTB struct device not the PCI one.
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
index 0135fcf..69b8c64 100644
--- a/drivers/ntb/hw/amd/ntb_hw_amd.c
+++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
@@ -225,7 +225,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
if (width)
*width = NTB_LNK_STA_WIDTH(ndev->lnk_sta);
- dev_dbg(&ntb->pdev->dev, "link is up.\n");
+ dev_dbg(&ntb->dev, "link is up.\n");
ret = 1;
} else {
@@ -234,7 +234,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
if (width)
*width = NTB_WIDTH_NONE;
- dev_dbg(&ntb->pdev->dev, "link is down.\n");
+ dev_dbg(&ntb->dev, "link is down.\n");
}
return ret;
@@ -254,7 +254,7 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
+ dev_dbg(&ntb->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
@@ -275,7 +275,7 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
+ dev_dbg(&ntb->dev, "Enabling Link.\n");
ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
@@ -466,19 +466,18 @@ static void amd_ack_smu(struct amd_ntb_dev *ndev, u32 bit)
static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
{
void __iomem *mmio = ndev->self_mmio;
- struct device *dev = &ndev->ntb.pdev->dev;
u32 status;
status = readl(mmio + AMD_INTSTAT_OFFSET);
if (!(status & AMD_EVENT_INTMASK))
return;
- dev_dbg(dev, "status = 0x%x and vec = %d\n", status, vec);
+ dev_dbg(&ndev->ntb.dev, "status = 0x%x and vec = %d\n", status, vec);
status &= AMD_EVENT_INTMASK;
switch (status) {
case AMD_PEER_FLUSH_EVENT:
- dev_info(dev, "Flush is done.\n");
+ dev_info(&ndev->ntb.dev, "Flush is done.\n");
break;
case AMD_PEER_RESET_EVENT:
amd_ack_smu(ndev, AMD_PEER_RESET_EVENT);
@@ -504,7 +503,7 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
status = readl(mmio + AMD_PMESTAT_OFFSET);
/* check if this is WAKEUP event */
if (status & 0x1)
- dev_info(dev, "Wakeup is done.\n");
+ dev_info(&ndev->ntb.dev, "Wakeup is done.\n");
amd_ack_smu(ndev, AMD_PEER_D0_EVENT);
@@ -513,14 +512,14 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
AMD_LINK_HB_TIMEOUT);
break;
default:
- dev_info(dev, "event status = 0x%x.\n", status);
+ dev_info(&ndev->ntb.dev, "event status = 0x%x.\n", status);
break;
}
}
static irqreturn_t ndev_interrupt(struct amd_ntb_dev *ndev, int vec)
{
- dev_dbg(&ndev->ntb.pdev->dev, "vec %d\n", vec);
+ dev_dbg(&ndev->ntb.dev, "vec %d\n", vec);
if (vec > (AMD_DB_CNT - 1) || (ndev->msix_vec_count == 1))
amd_handle_event(ndev, vec);
@@ -814,7 +813,7 @@ static int amd_poll_link(struct amd_ntb_dev *ndev)
reg = readl(mmio + AMD_SIDEINFO_OFFSET);
reg &= NTB_LIN_STA_ACTIVE_BIT;
- dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg);
+ dev_dbg(&ndev->ntb.dev, "%s: reg_val = 0x%x.\n", __func__, reg);
if (reg == ndev->cntl_sta)
return 0;
@@ -1052,7 +1051,7 @@ static int amd_ntb_pci_probe(struct pci_dev *pdev,
if (rc)
goto err_register;
- dev_info(&pdev->dev, "NTB device registered.\n");
+ dev_info(&ndev->ntb.dev, "NTB device registered.\n");
return 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/4] ntb_hw_amd: Print kernel messages with the ntb device not the pci one
2017-01-11 0:33 ` [PATCH v2 3/4] ntb_hw_amd: Print kernel messages with the ntb device not the pci one Logan Gunthorpe
@ 2017-03-08 16:43 ` Jon Mason
0 siblings, 0 replies; 11+ messages in thread
From: Jon Mason @ 2017-03-08 16:43 UTC (permalink / raw)
To: Logan Gunthorpe
Cc: Xiangliang Yu, Dave Jiang, Allen Hubbe, Joe Perches,
Greg Kroah-Hartman, linux-ntb, linux-kernel
On Tue, Jan 10, 2017 at 05:33:38PM -0700, Logan Gunthorpe wrote:
> Now that macros are open it's pretty clear that these should print
> using the NTB struct device not the PCI one.
>
> Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
I believe that using the PCI dev here makes it more debugable, as this
is more referring to possible issues with the HW. So, I'm not taking
this patch (or the one for Intel).
Thanks,
Jon
> ---
> drivers/ntb/hw/amd/ntb_hw_amd.c | 23 +++++++++++------------
> 1 file changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
> index 0135fcf..69b8c64 100644
> --- a/drivers/ntb/hw/amd/ntb_hw_amd.c
> +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
> @@ -225,7 +225,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
> if (width)
> *width = NTB_LNK_STA_WIDTH(ndev->lnk_sta);
>
> - dev_dbg(&ntb->pdev->dev, "link is up.\n");
> + dev_dbg(&ntb->dev, "link is up.\n");
>
> ret = 1;
> } else {
> @@ -234,7 +234,7 @@ static int amd_ntb_link_is_up(struct ntb_dev *ntb,
> if (width)
> *width = NTB_WIDTH_NONE;
>
> - dev_dbg(&ntb->pdev->dev, "link is down.\n");
> + dev_dbg(&ntb->dev, "link is down.\n");
> }
>
> return ret;
> @@ -254,7 +254,7 @@ static int amd_ntb_link_enable(struct ntb_dev *ntb,
>
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
> - dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
> + dev_dbg(&ntb->dev, "Enabling Link.\n");
>
> ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
> ntb_ctl |= (PMM_REG_CTL | SMM_REG_CTL);
> @@ -275,7 +275,7 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
>
> if (ndev->ntb.topo == NTB_TOPO_SEC)
> return -EINVAL;
> - dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
> + dev_dbg(&ntb->dev, "Enabling Link.\n");
>
> ntb_ctl = readl(mmio + AMD_CNTL_OFFSET);
> ntb_ctl &= ~(PMM_REG_CTL | SMM_REG_CTL);
> @@ -466,19 +466,18 @@ static void amd_ack_smu(struct amd_ntb_dev *ndev, u32 bit)
> static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> {
> void __iomem *mmio = ndev->self_mmio;
> - struct device *dev = &ndev->ntb.pdev->dev;
> u32 status;
>
> status = readl(mmio + AMD_INTSTAT_OFFSET);
> if (!(status & AMD_EVENT_INTMASK))
> return;
>
> - dev_dbg(dev, "status = 0x%x and vec = %d\n", status, vec);
> + dev_dbg(&ndev->ntb.dev, "status = 0x%x and vec = %d\n", status, vec);
>
> status &= AMD_EVENT_INTMASK;
> switch (status) {
> case AMD_PEER_FLUSH_EVENT:
> - dev_info(dev, "Flush is done.\n");
> + dev_info(&ndev->ntb.dev, "Flush is done.\n");
> break;
> case AMD_PEER_RESET_EVENT:
> amd_ack_smu(ndev, AMD_PEER_RESET_EVENT);
> @@ -504,7 +503,7 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> status = readl(mmio + AMD_PMESTAT_OFFSET);
> /* check if this is WAKEUP event */
> if (status & 0x1)
> - dev_info(dev, "Wakeup is done.\n");
> + dev_info(&ndev->ntb.dev, "Wakeup is done.\n");
>
> amd_ack_smu(ndev, AMD_PEER_D0_EVENT);
>
> @@ -513,14 +512,14 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec)
> AMD_LINK_HB_TIMEOUT);
> break;
> default:
> - dev_info(dev, "event status = 0x%x.\n", status);
> + dev_info(&ndev->ntb.dev, "event status = 0x%x.\n", status);
> break;
> }
> }
>
> static irqreturn_t ndev_interrupt(struct amd_ntb_dev *ndev, int vec)
> {
> - dev_dbg(&ndev->ntb.pdev->dev, "vec %d\n", vec);
> + dev_dbg(&ndev->ntb.dev, "vec %d\n", vec);
>
> if (vec > (AMD_DB_CNT - 1) || (ndev->msix_vec_count == 1))
> amd_handle_event(ndev, vec);
> @@ -814,7 +813,7 @@ static int amd_poll_link(struct amd_ntb_dev *ndev)
> reg = readl(mmio + AMD_SIDEINFO_OFFSET);
> reg &= NTB_LIN_STA_ACTIVE_BIT;
>
> - dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg);
> + dev_dbg(&ndev->ntb.dev, "%s: reg_val = 0x%x.\n", __func__, reg);
>
> if (reg == ndev->cntl_sta)
> return 0;
> @@ -1052,7 +1051,7 @@ static int amd_ntb_pci_probe(struct pci_dev *pdev,
> if (rc)
> goto err_register;
>
> - dev_info(&pdev->dev, "NTB device registered.\n");
> + dev_info(&ndev->ntb.dev, "NTB device registered.\n");
>
> return 0;
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 4/4] ntb_hw_intel: Print kernel messages with the ntb device not the pci one
2017-01-11 0:33 [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
` (2 preceding siblings ...)
2017-01-11 0:33 ` [PATCH v2 3/4] ntb_hw_amd: Print kernel messages with the ntb device not the pci one Logan Gunthorpe
@ 2017-01-11 0:33 ` Logan Gunthorpe
2017-01-26 20:00 ` [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
4 siblings, 0 replies; 11+ messages in thread
From: Logan Gunthorpe @ 2017-01-11 0:33 UTC (permalink / raw)
To: Xiangliang Yu, Jon Mason, Dave Jiang, Allen Hubbe, Joe Perches
Cc: Greg Kroah-Hartman, linux-ntb, linux-kernel, Logan Gunthorpe
Now that macros are open it's pretty clear that these should print
using the NTB struct device not the PCI one.
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
---
drivers/ntb/hw/intel/ntb_hw_intel.c | 132 +++++++++++++++++-------------------
1 file changed, 64 insertions(+), 68 deletions(-)
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c
index 6456f54..001c82d 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.c
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
@@ -270,12 +270,12 @@ static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
if (db_addr) {
*db_addr = reg_addr + reg;
- dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx\n", *db_addr);
+ dev_dbg(&ndev->ntb.dev, "Peer db addr %llx\n", *db_addr);
}
if (db_size) {
*db_size = ndev->reg->db_size;
- dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size);
+ dev_dbg(&ndev->ntb.dev, "Peer db size %llx\n", *db_size);
}
return 0;
@@ -368,8 +368,7 @@ static inline int ndev_spad_addr(struct intel_ntb_dev *ndev, int idx,
if (spad_addr) {
*spad_addr = reg_addr + reg + (idx << 2);
- dev_dbg(&ndev->ntb.pdev->dev, "Peer spad addr %llx\n",
- *spad_addr);
+ dev_dbg(&ndev->ntb.dev, "Peer spad addr %llx\n", *spad_addr);
}
return 0;
@@ -410,7 +409,7 @@ static irqreturn_t ndev_interrupt(struct intel_ntb_dev *ndev, int vec)
if ((ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) && (vec == 31))
vec_mask |= ndev->db_link_mask;
- dev_dbg(&ndev->ntb.pdev->dev, "vec %d vec_mask %llx\n", vec, vec_mask);
+ dev_dbg(&ndev->ntb.dev, "vec %d vec_mask %llx\n", vec, vec_mask);
ndev->last_ts = jiffies;
@@ -429,7 +428,7 @@ static irqreturn_t ndev_vec_isr(int irq, void *dev)
{
struct intel_ntb_vec *nvec = dev;
- dev_dbg(&nvec->ndev->ntb.pdev->dev, "irq: %d nvec->num: %d\n",
+ dev_dbg(&nvec->ndev->ntb.dev, "irq: %d nvec->num: %d\n",
irq, nvec->num);
return ndev_interrupt(nvec->ndev, nvec->num);
@@ -534,7 +533,7 @@ static int ndev_init_isr(struct intel_ntb_dev *ndev,
if (rc)
goto err_intx_request;
- dev_dbg(&pdev->dev, "Using intx interrupts\n");
+ dev_dbg(&ndev->ntb.dev, "Using intx interrupts\n");
ndev->db_vec_count = 1;
ndev->db_vec_shift = total_shift;
return 0;
@@ -1208,13 +1207,12 @@ static int intel_ntb_link_enable(struct ntb_dev *ntb,
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(&ntb->pdev->dev,
- "Enabling link with max_speed %d max_width %d\n",
+ dev_dbg(&ntb->dev, "Enabling link with max_speed %d max_width %d\n",
max_speed, max_width);
if (max_speed != NTB_SPEED_AUTO)
- dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
+ dev_dbg(&ntb->dev, "ignoring max_speed %d\n", max_speed);
if (max_width != NTB_WIDTH_AUTO)
- dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
+ dev_dbg(&ntb->dev, "ignoring max_width %d\n", max_width);
ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
@@ -1237,7 +1235,7 @@ static int intel_ntb_link_disable(struct ntb_dev *ntb)
if (ndev->ntb.topo == NTB_TOPO_SEC)
return -EINVAL;
- dev_dbg(&ntb->pdev->dev, "Disabling link\n");
+ dev_dbg(&ntb->dev, "Disabling link\n");
/* Bring NTB link down */
ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
@@ -1444,33 +1442,30 @@ static int atom_link_is_err(struct intel_ntb_dev *ndev)
static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
{
- struct device *dev = &ndev->ntb.pdev->dev;
-
switch (ppd & ATOM_PPD_TOPO_MASK) {
case ATOM_PPD_TOPO_B2B_USD:
- dev_dbg(dev, "PPD %d B2B USD\n", ppd);
+ dev_dbg(&ndev->ntb.dev, "PPD %d B2B USD\n", ppd);
return NTB_TOPO_B2B_USD;
case ATOM_PPD_TOPO_B2B_DSD:
- dev_dbg(dev, "PPD %d B2B DSD\n", ppd);
+ dev_dbg(&ndev->ntb.dev, "PPD %d B2B DSD\n", ppd);
return NTB_TOPO_B2B_DSD;
case ATOM_PPD_TOPO_PRI_USD:
case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
case ATOM_PPD_TOPO_SEC_USD:
case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
- dev_dbg(dev, "PPD %d non B2B disabled\n", ppd);
+ dev_dbg(&ndev->ntb.dev, "PPD %d non B2B disabled\n", ppd);
return NTB_TOPO_NONE;
}
- dev_dbg(dev, "PPD %d invalid\n", ppd);
+ dev_dbg(&ndev->ntb.dev, "PPD %d invalid\n", ppd);
return NTB_TOPO_NONE;
}
static void atom_link_hb(struct work_struct *work)
{
struct intel_ntb_dev *ndev = hb_ndev(work);
- struct device *dev = &ndev->ntb.pdev->dev;
unsigned long poll_ts;
void __iomem *mmio;
u32 status32;
@@ -1508,30 +1503,30 @@ static void atom_link_hb(struct work_struct *work)
/* Clear AER Errors, write to clear */
status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
- dev_dbg(dev, "ERRCORSTS = %x\n", status32);
+ dev_dbg(&ndev->ntb.dev, "ERRCORSTS = %x\n", status32);
status32 &= PCI_ERR_COR_REP_ROLL;
iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
/* Clear unexpected electrical idle event in LTSSM, write to clear */
status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
- dev_dbg(dev, "LTSSMERRSTS0 = %x\n", status32);
+ dev_dbg(&ndev->ntb.dev, "LTSSMERRSTS0 = %x\n", status32);
status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
/* Clear DeSkew Buffer error, write to clear */
status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
- dev_dbg(dev, "DESKEWSTS = %x\n", status32);
+ dev_dbg(&ndev->ntb.dev, "DESKEWSTS = %x\n", status32);
status32 |= ATOM_DESKEWSTS_DBERR;
iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
- dev_dbg(dev, "IBSTERRRCRVSTS0 = %x\n", status32);
+ dev_dbg(&ndev->ntb.dev, "IBSTERRRCRVSTS0 = %x\n", status32);
status32 &= ATOM_IBIST_ERR_OFLOW;
iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
/* Releases the NTB state machine to allow the link to retrain */
status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
- dev_dbg(dev, "LTSSMSTATEJMP = %x\n", status32);
+ dev_dbg(&ndev->ntb.dev, "LTSSMSTATEJMP = %x\n", status32);
status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
@@ -1718,7 +1713,7 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
* except disable or halve the size of the b2b secondary bar.
*/
pci_read_config_byte(pdev, SKX_IMBAR1SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "IMBAR1SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "IMBAR1SZ %#x\n", bar_sz);
if (b2b_bar == 1) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -1865,14 +1860,13 @@ static int intel_ntb3_link_enable(struct ntb_dev *ntb,
ndev = container_of(ntb, struct intel_ntb_dev, ntb);
- dev_dbg(&ntb->pdev->dev,
- "Enabling link with max_speed %d max_width %d\n",
+ dev_dbg(&ntb->dev, "Enabling link with max_speed %d max_width %d\n",
max_speed, max_width);
if (max_speed != NTB_SPEED_AUTO)
- dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);
+ dev_dbg(&ntb->dev, "ignoring max_speed %d\n", max_speed);
if (max_width != NTB_WIDTH_AUTO)
- dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);
+ dev_dbg(&ntb->dev, "ignoring max_width %d\n", max_width);
ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);
ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);
@@ -1933,7 +1927,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);
/* set and verify setting the limit */
iowrite64(limit, mmio + limit_reg);
@@ -1944,7 +1938,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);
/* setup the EP */
limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
@@ -1965,7 +1959,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int idx,
return -EIO;
}
- dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
+ dev_dbg(&ntb->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);
return 0;
}
@@ -2072,7 +2066,7 @@ static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)
static inline int xeon_ppd_bar4_split(struct intel_ntb_dev *ndev, u8 ppd)
{
if (ppd & XEON_PPD_SPLIT_BAR_MASK) {
- dev_dbg(&ndev->ntb.pdev->dev, "PPD %d split bar\n", ppd);
+ dev_dbg(&ndev->ntb.dev, "PPD %d split bar\n", ppd);
return 1;
}
return 0;
@@ -2106,7 +2100,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
mmio = ndev->self_mmio;
if (ndev->b2b_idx == UINT_MAX) {
- dev_dbg(&pdev->dev, "not using b2b mw\n");
+ dev_dbg(&ndev->ntb.dev, "not using b2b mw\n");
b2b_bar = 0;
ndev->b2b_off = 0;
} else {
@@ -2114,21 +2108,21 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
if (b2b_bar < 0)
return -EIO;
- dev_dbg(&pdev->dev, "using b2b mw bar %d\n", b2b_bar);
+ dev_dbg(&ndev->ntb.dev, "using b2b mw bar %d\n", b2b_bar);
bar_size = pci_resource_len(ndev->ntb.pdev, b2b_bar);
- dev_dbg(&pdev->dev, "b2b bar size %#llx\n", bar_size);
+ dev_dbg(&ndev->ntb.dev, "b2b bar size %#llx\n", bar_size);
if (b2b_mw_share && XEON_B2B_MIN_SIZE <= bar_size >> 1) {
- dev_dbg(&pdev->dev, "b2b using first half of bar\n");
+ dev_dbg(&ndev->ntb.dev, "b2b using first half of bar\n");
ndev->b2b_off = bar_size >> 1;
} else if (XEON_B2B_MIN_SIZE <= bar_size) {
- dev_dbg(&pdev->dev, "b2b using whole bar\n");
+ dev_dbg(&ndev->ntb.dev, "b2b using whole bar\n");
ndev->b2b_off = 0;
--ndev->mw_count;
} else {
- dev_dbg(&pdev->dev, "b2b bar size is too small\n");
+ dev_dbg(&ndev->ntb.dev, "b2b bar size is too small\n");
return -EIO;
}
}
@@ -2140,7 +2134,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
* offsets are not in a consistent order (bar5sz comes after ppd, odd).
*/
pci_read_config_byte(pdev, XEON_PBAR23SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "PBAR23SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "PBAR23SZ %#x\n", bar_sz);
if (b2b_bar == 2) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2149,11 +2143,11 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR23SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR23SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "SBAR23SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "SBAR23SZ %#x\n", bar_sz);
if (!ndev->bar4_split) {
pci_read_config_byte(pdev, XEON_PBAR45SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "PBAR45SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "PBAR45SZ %#x\n", bar_sz);
if (b2b_bar == 4) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2162,10 +2156,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR45SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR45SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "SBAR45SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "SBAR45SZ %#x\n", bar_sz);
} else {
pci_read_config_byte(pdev, XEON_PBAR4SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "PBAR4SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "PBAR4SZ %#x\n", bar_sz);
if (b2b_bar == 4) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2174,10 +2168,10 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR4SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR4SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "SBAR4SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "SBAR4SZ %#x\n", bar_sz);
pci_read_config_byte(pdev, XEON_PBAR5SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "PBAR5SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "PBAR5SZ %#x\n", bar_sz);
if (b2b_bar == 5) {
if (ndev->b2b_off)
bar_sz -= 1;
@@ -2186,7 +2180,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
}
pci_write_config_byte(pdev, XEON_SBAR5SZ_OFFSET, bar_sz);
pci_read_config_byte(pdev, XEON_SBAR5SZ_OFFSET, &bar_sz);
- dev_dbg(&pdev->dev, "SBAR5SZ %#x\n", bar_sz);
+ dev_dbg(&ndev->ntb.dev, "SBAR5SZ %#x\n", bar_sz);
}
/* SBAR01 hit by first part of the b2b bar */
@@ -2203,7 +2197,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
else
return -EIO;
- dev_dbg(&pdev->dev, "SBAR01 %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR01 %#018llx\n", bar_addr);
iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET);
/* Other SBAR are normally hit by the PBAR xlat, except for b2b bar.
@@ -2214,26 +2208,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR23BASE_OFFSET);
- dev_dbg(&pdev->dev, "SBAR23 %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR23 %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = addr->bar4_addr64 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45BASE_OFFSET);
- dev_dbg(&pdev->dev, "SBAR45 %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR45 %#018llx\n", bar_addr);
} else {
bar_addr = addr->bar4_addr32 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR4BASE_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR4BASE_OFFSET);
- dev_dbg(&pdev->dev, "SBAR4 %#010llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR4 %#010llx\n", bar_addr);
bar_addr = addr->bar5_addr32 +
(b2b_bar == 5 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR5BASE_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR5BASE_OFFSET);
- dev_dbg(&pdev->dev, "SBAR5 %#010llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR5 %#010llx\n", bar_addr);
}
/* setup incoming bar limits == base addrs (zero length windows) */
@@ -2241,26 +2235,26 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = addr->bar2_addr64 + (b2b_bar == 2 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR23LMT_OFFSET);
- dev_dbg(&pdev->dev, "SBAR23LMT %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR23LMT %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = addr->bar4_addr64 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET);
bar_addr = ioread64(mmio + XEON_SBAR45LMT_OFFSET);
- dev_dbg(&pdev->dev, "SBAR45LMT %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR45LMT %#018llx\n", bar_addr);
} else {
bar_addr = addr->bar4_addr32 +
(b2b_bar == 4 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR4LMT_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR4LMT_OFFSET);
- dev_dbg(&pdev->dev, "SBAR4LMT %#010llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR4LMT %#010llx\n", bar_addr);
bar_addr = addr->bar5_addr32 +
(b2b_bar == 5 ? ndev->b2b_off : 0);
iowrite32(bar_addr, mmio + XEON_SBAR5LMT_OFFSET);
bar_addr = ioread32(mmio + XEON_SBAR5LMT_OFFSET);
- dev_dbg(&pdev->dev, "SBAR5LMT %#05llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "SBAR5LMT %#05llx\n", bar_addr);
}
/* zero incoming translation addrs */
@@ -2286,23 +2280,23 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
bar_addr = peer_addr->bar2_addr64;
iowrite64(bar_addr, mmio + XEON_PBAR23XLAT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR23XLAT_OFFSET);
- dev_dbg(&pdev->dev, "PBAR23XLAT %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "PBAR23XLAT %#018llx\n", bar_addr);
if (!ndev->bar4_split) {
bar_addr = peer_addr->bar4_addr64;
iowrite64(bar_addr, mmio + XEON_PBAR45XLAT_OFFSET);
bar_addr = ioread64(mmio + XEON_PBAR45XLAT_OFFSET);
- dev_dbg(&pdev->dev, "PBAR45XLAT %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "PBAR45XLAT %#018llx\n", bar_addr);
} else {
bar_addr = peer_addr->bar4_addr32;
iowrite32(bar_addr, mmio + XEON_PBAR4XLAT_OFFSET);
bar_addr = ioread32(mmio + XEON_PBAR4XLAT_OFFSET);
- dev_dbg(&pdev->dev, "PBAR4XLAT %#010llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "PBAR4XLAT %#010llx\n", bar_addr);
bar_addr = peer_addr->bar5_addr32;
iowrite32(bar_addr, mmio + XEON_PBAR5XLAT_OFFSET);
bar_addr = ioread32(mmio + XEON_PBAR5XLAT_OFFSET);
- dev_dbg(&pdev->dev, "PBAR5XLAT %#010llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "PBAR5XLAT %#010llx\n", bar_addr);
}
/* set the translation offset for b2b registers */
@@ -2320,7 +2314,7 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
return -EIO;
/* B2B_XLAT_OFFSET is 64bit, but can only take 32bit writes */
- dev_dbg(&pdev->dev, "B2BXLAT %#018llx\n", bar_addr);
+ dev_dbg(&ndev->ntb.dev, "B2BXLAT %#018llx\n", bar_addr);
iowrite32(bar_addr, mmio + XEON_B2B_XLAT_OFFSETL);
iowrite32(bar_addr >> 32, mmio + XEON_B2B_XLAT_OFFSETU);
@@ -2339,7 +2333,6 @@ static int xeon_setup_b2b_mw(struct intel_ntb_dev *ndev,
static int xeon_init_ntb(struct intel_ntb_dev *ndev)
{
- struct device *dev = &ndev->ntb.pdev->dev;
int rc;
u32 ntb_ctl;
@@ -2355,7 +2348,8 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
switch (ndev->ntb.topo) {
case NTB_TOPO_PRI:
if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
- dev_err(dev, "NTB Primary config disabled\n");
+ dev_err(&ndev->ntb.dev,
+ "NTB Primary config disabled\n");
return -EINVAL;
}
@@ -2373,7 +2367,8 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
case NTB_TOPO_SEC:
if (ndev->hwerr_flags & NTB_HWERR_SDOORBELL_LOCKUP) {
- dev_err(dev, "NTB Secondary config disabled\n");
+ dev_err(&ndev->ntb.dev,
+ "NTB Secondary config disabled\n");
return -EINVAL;
}
/* use half the spads for the peer */
@@ -2398,17 +2393,18 @@ static int xeon_init_ntb(struct intel_ntb_dev *ndev)
ndev->b2b_idx = b2b_mw_idx;
if (ndev->b2b_idx >= ndev->mw_count) {
- dev_dbg(dev,
+ dev_dbg(&ndev->ntb.dev,
"b2b_mw_idx %d invalid for mw_count %u\n",
b2b_mw_idx, ndev->mw_count);
return -EINVAL;
}
- dev_dbg(dev, "setting up b2b mw idx %d means %d\n",
+ dev_dbg(&ndev->ntb.dev,
+ "setting up b2b mw idx %d means %d\n",
b2b_mw_idx, ndev->b2b_idx);
} else if (ndev->hwerr_flags & NTB_HWERR_B2BDOORBELL_BIT14) {
- dev_warn(dev, "Reduce doorbell count by 1\n");
+ dev_warn(&ndev->ntb.dev, "Reduce doorbell count by 1\n");
ndev->db_count -= 1;
}
@@ -2728,7 +2724,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
if (rc)
goto err_register;
- dev_info(&pdev->dev, "NTB device registered.\n");
+ dev_info(&ndev->ntb.dev, "NTB device registered.\n");
return 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 0/4] Style fixes: open code obfuscating macros
2017-01-11 0:33 [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
` (3 preceding siblings ...)
2017-01-11 0:33 ` [PATCH v2 4/4] ntb_hw_intel: " Logan Gunthorpe
@ 2017-01-26 20:00 ` Logan Gunthorpe
2017-02-01 20:08 ` Jon Mason
4 siblings, 1 reply; 11+ messages in thread
From: Logan Gunthorpe @ 2017-01-26 20:00 UTC (permalink / raw)
To: Xiangliang Yu, Jon Mason, Dave Jiang, Allen Hubbe, Joe Perches
Cc: Greg Kroah-Hartman, linux-ntb, linux-kernel
Hi,
It's been a couple weeks... Any thoughts on this?
Thanks,
Logan
On 10/01/17 05:33 PM, Logan Gunthorpe wrote:
> Hi,
>
> Here's an updated version of the style fixes patchset. The differences
> from v1 are:
>
> 1) Rebased onto Jon Mason's current NTB branch
>
> 2) Added two more patches to convert the print lines to use the ntb
> device and not the pci one. This seems more sane, shortens a bunch
> of lines and removes the need for temporaries.
>
> Note with (2): I've tried my best to ensure that statements that print
> before the ntb device is registered still use the PCI device. However,
> someone should probably review and test this as I don't have access
> to all types of hardware to do that.
>
> Thanks,
>
> Logan
>
>
>
> Logan Gunthorpe (4):
> ntb_hw_amd: Style fixes: open code macros that just obfuscate code
> ntb_hw_intel: Style fixes: open code macros that just obfuscate code
> ntb_hw_amd: Print kernel messages with the ntb device not the pci one
> ntb_hw_intel: Print kernel messages with the ntb device not the pci
> one
>
> drivers/ntb/hw/amd/ntb_hw_amd.c | 60 +++++------
> drivers/ntb/hw/amd/ntb_hw_amd.h | 3 -
> drivers/ntb/hw/intel/ntb_hw_intel.c | 192 +++++++++++++++++-------------------
> drivers/ntb/hw/intel/ntb_hw_intel.h | 3 -
> 4 files changed, 124 insertions(+), 134 deletions(-)
>
> --
> 2.1.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 0/4] Style fixes: open code obfuscating macros
2017-01-26 20:00 ` [PATCH v2 0/4] Style fixes: open code obfuscating macros Logan Gunthorpe
@ 2017-02-01 20:08 ` Jon Mason
2017-02-01 22:11 ` Logan Gunthorpe
0 siblings, 1 reply; 11+ messages in thread
From: Jon Mason @ 2017-02-01 20:08 UTC (permalink / raw)
To: Logan Gunthorpe
Cc: Xiangliang Yu, Dave Jiang, Allen Hubbe, Joe Perches,
Greg Kroah-Hartman, linux-ntb, linux-kernel
On Thu, Jan 26, 2017 at 3:00 PM, Logan Gunthorpe <logang@deltatee.com> wrote:
> Hi,
>
> It's been a couple weeks... Any thoughts on this?
My apologies for not responding sooner. A large rework of the core
NTB code was done prior to your patches (for IDT NTB support).
Unfortunately, after those changes this series does not apply cleanly.
I understand the changes being made, and will fix-up the patches to
make it apply cleanly on the updated code base.
Thanks,
Jon
>
> Thanks,
>
> Logan
>
> On 10/01/17 05:33 PM, Logan Gunthorpe wrote:
>> Hi,
>>
>> Here's an updated version of the style fixes patchset. The differences
>> from v1 are:
>>
>> 1) Rebased onto Jon Mason's current NTB branch
>>
>> 2) Added two more patches to convert the print lines to use the ntb
>> device and not the pci one. This seems more sane, shortens a bunch
>> of lines and removes the need for temporaries.
>>
>> Note with (2): I've tried my best to ensure that statements that print
>> before the ntb device is registered still use the PCI device. However,
>> someone should probably review and test this as I don't have access
>> to all types of hardware to do that.
>>
>> Thanks,
>>
>> Logan
>>
>>
>>
>> Logan Gunthorpe (4):
>> ntb_hw_amd: Style fixes: open code macros that just obfuscate code
>> ntb_hw_intel: Style fixes: open code macros that just obfuscate code
>> ntb_hw_amd: Print kernel messages with the ntb device not the pci one
>> ntb_hw_intel: Print kernel messages with the ntb device not the pci
>> one
>>
>> drivers/ntb/hw/amd/ntb_hw_amd.c | 60 +++++------
>> drivers/ntb/hw/amd/ntb_hw_amd.h | 3 -
>> drivers/ntb/hw/intel/ntb_hw_intel.c | 192 +++++++++++++++++-------------------
>> drivers/ntb/hw/intel/ntb_hw_intel.h | 3 -
>> 4 files changed, 124 insertions(+), 134 deletions(-)
>>
>> --
>> 2.1.4
>>
>
> --
> You received this message because you are subscribed to the Google Groups "linux-ntb" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-ntb+unsubscribe@googlegroups.com.
> To post to this group, send email to linux-ntb@googlegroups.com.
> To view this discussion on the web visit https://groups.google.com/d/msgid/linux-ntb/5ed3be6c-c94e-1ade-e4cd-a8e8293296cd%40deltatee.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/4] Style fixes: open code obfuscating macros
2017-02-01 20:08 ` Jon Mason
@ 2017-02-01 22:11 ` Logan Gunthorpe
0 siblings, 0 replies; 11+ messages in thread
From: Logan Gunthorpe @ 2017-02-01 22:11 UTC (permalink / raw)
To: Jon Mason
Cc: Xiangliang Yu, Dave Jiang, Allen Hubbe, Joe Perches,
Greg Kroah-Hartman, linux-ntb, linux-kernel
Cool, Thanks.
Let me know if you need anything from me.
Logan
On 01/02/17 01:08 PM, Jon Mason wrote:
> On Thu, Jan 26, 2017 at 3:00 PM, Logan Gunthorpe <logang@deltatee.com> wrote:
>> Hi,
>>
>> It's been a couple weeks... Any thoughts on this?
>
> My apologies for not responding sooner. A large rework of the core
> NTB code was done prior to your patches (for IDT NTB support).
> Unfortunately, after those changes this series does not apply cleanly.
> I understand the changes being made, and will fix-up the patches to
> make it apply cleanly on the updated code base.
>
> Thanks,
> Jon
>
>>
>> Thanks,
>>
>> Logan
>>
>> On 10/01/17 05:33 PM, Logan Gunthorpe wrote:
>>> Hi,
>>>
>>> Here's an updated version of the style fixes patchset. The differences
>>> from v1 are:
>>>
>>> 1) Rebased onto Jon Mason's current NTB branch
>>>
>>> 2) Added two more patches to convert the print lines to use the ntb
>>> device and not the pci one. This seems more sane, shortens a bunch
>>> of lines and removes the need for temporaries.
>>>
>>> Note with (2): I've tried my best to ensure that statements that print
>>> before the ntb device is registered still use the PCI device. However,
>>> someone should probably review and test this as I don't have access
>>> to all types of hardware to do that.
>>>
>>> Thanks,
>>>
>>> Logan
>>>
>>>
>>>
>>> Logan Gunthorpe (4):
>>> ntb_hw_amd: Style fixes: open code macros that just obfuscate code
>>> ntb_hw_intel: Style fixes: open code macros that just obfuscate code
>>> ntb_hw_amd: Print kernel messages with the ntb device not the pci one
>>> ntb_hw_intel: Print kernel messages with the ntb device not the pci
>>> one
>>>
>>> drivers/ntb/hw/amd/ntb_hw_amd.c | 60 +++++------
>>> drivers/ntb/hw/amd/ntb_hw_amd.h | 3 -
>>> drivers/ntb/hw/intel/ntb_hw_intel.c | 192 +++++++++++++++++-------------------
>>> drivers/ntb/hw/intel/ntb_hw_intel.h | 3 -
>>> 4 files changed, 124 insertions(+), 134 deletions(-)
>>>
>>> --
>>> 2.1.4
>>>
>>
>> --
>> You received this message because you are subscribed to the Google Groups "linux-ntb" group.
>> To unsubscribe from this group and stop receiving emails from it, send an email to linux-ntb+unsubscribe@googlegroups.com.
>> To post to this group, send email to linux-ntb@googlegroups.com.
>> To view this discussion on the web visit https://groups.google.com/d/msgid/linux-ntb/5ed3be6c-c94e-1ade-e4cd-a8e8293296cd%40deltatee.com.
>> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 11+ messages in thread