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* [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL
@ 2017-01-15 22:39 Lukasz Majewski
  2017-01-15 22:39 ` [U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration Lukasz Majewski
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Lukasz Majewski @ 2017-01-15 22:39 UTC (permalink / raw)
  To: u-boot

With this code only 19.2 HMz SYSCLK (input) frequency is supported on
dra7xx based SoCs.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
 arch/arm/cpu/armv7/omap5/hw_data.c | 12 ++++++++++++
 arch/arm/include/asm/omap_common.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 2192090..e16bd2c 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -257,6 +257,17 @@ static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
 	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
 };
 
+static const struct dpll_params pcie_dpll_params_1500mhz[NUM_SYS_CLKS] = {
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{625, 7, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
+};
+
+
 struct dplls omap5_dplls_es1 = {
 	.mpu = mpu_dpll_params_800mhz,
 	.core = core_dpll_params_2128mhz_ddr532,
@@ -294,6 +305,7 @@ struct dplls dra7xx_dplls = {
 	.usb = usb_dpll_params_1920mhz,
 	.ddr = ddr_dpll_params_2128mhz,
 	.gmac = gmac_dpll_params_2000mhz,
+	.pcie = pcie_dpll_params_1500mhz,
 };
 
 struct dplls dra72x_dplls = {
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 605c549..cc40ee9 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -526,6 +526,7 @@ struct dplls {
 	const struct dpll_params *usb;
 	const struct dpll_params *ddr;
 	const struct dpll_params *gmac;
+	const struct dpll_params *pcie;
 };
 
 struct pmic_data {
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration
  2017-01-15 22:39 [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lukasz Majewski
@ 2017-01-15 22:39 ` Lukasz Majewski
  2017-01-15 22:39 ` [U-Boot] [PATCH 3/3] CLK: OMAP: PCIE: Registers definitions necessary for PCIe clock generation Lukasz Majewski
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Lukasz Majewski @ 2017-01-15 22:39 UTC (permalink / raw)
  To: u-boot

New function - configure_pcie_dpll() - has been added to allow setting up
the PCIe DPLL clock (1500 MHz).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 22 ++++++++++++++++++++++
 arch/arm/include/asm/omap_common.h             |  2 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 9b97583..56476bf 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -208,6 +208,17 @@ static const struct dpll_params *get_gmac_dpll_params
 }
 #endif
 
+static const struct dpll_params *get_pcie_dpll_params
+			(struct dplls const *dpll_data)
+{
+	u32 sysclk_ind = get_sys_clk_index();
+
+	if (!dpll_data->pcie)
+		return NULL;
+
+	return &dpll_data->pcie[sysclk_ind];
+}
+
 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 				u8 lock, char *dpll)
 {
@@ -302,6 +313,17 @@ u32 omap_ddr_clk(void)
 	return ddr_clk;
 }
 
+void configure_pcie_dpll(void)
+{
+	const struct dpll_params *params;
+
+	params = get_pcie_dpll_params(*dplls_data);
+
+	do_setup_dpll((*prcm)->cm_clkmode_dpll_pcie_ref, params, DPLL_LOCK,
+		      "pcie");
+	debug("PCIE DPLL locked\n");
+}
+
 /*
  * Lock MPU dpll
  *
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index cc40ee9..bb74321 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -612,6 +612,8 @@ void enable_basic_uboot_clocks(void);
 void enable_usb_clocks(int index);
 void disable_usb_clocks(int index);
 
+void configure_pcie_dpll(void);
+
 void scale_vcores(struct vcores_data const *);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 3/3] CLK: OMAP: PCIE: Registers definitions necessary for PCIe clock generation
  2017-01-15 22:39 [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lukasz Majewski
  2017-01-15 22:39 ` [U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration Lukasz Majewski
@ 2017-01-15 22:39 ` Lukasz Majewski
  2017-01-16  3:44 ` [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lokesh Vutla
  2017-01-16 16:25 ` Roger Quadros
  3 siblings, 0 replies; 5+ messages in thread
From: Lukasz Majewski @ 2017-01-15 22:39 UTC (permalink / raw)
  To: u-boot

Those registers are necessary to generate and output the PCIe clock.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
 arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++
 arch/arm/include/asm/omap_common.h   | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b5f1d70..5a0c872 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -385,6 +385,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_phy_power_sata			= 0x4A002374,
 	.ctrl_core_sma_sw_0			= 0x4A0023FC,
 	.ctrl_core_sma_sw_1			= 0x4A002534,
+	.ctrl_core_sma_sw_6                     = 0x4A003C14,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -396,6 +397,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_core_mmr_lock5			= 0x4A002550,
 	.control_core_control_io1		= 0x4A002554,
 	.control_core_control_io2		= 0x4A002558,
+	.control_core_pcie_power_state          = 0x4A0026C0,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,
 	.control_smart1io_padconf_0		= 0x4A002DA8,
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index bb74321..2d8dbbd 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -393,6 +393,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_usbotghs_ctrl;
 	u32 control_phy_power_sata;
 	u32 control_padconf_core_base;
+	u32 control_core_pcie_power_state;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
 	u32 control_smart1io_padconf_0;
@@ -482,6 +483,7 @@ struct omap_sys_ctrl_regs {
 	u32 iodelay_config_base;
 	u32 ctrl_core_sma_sw_0;
 	u32 ctrl_core_sma_sw_1;
+	u32 ctrl_core_sma_sw_6;
 };
 
 struct dpll_params {
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL
  2017-01-15 22:39 [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lukasz Majewski
  2017-01-15 22:39 ` [U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration Lukasz Majewski
  2017-01-15 22:39 ` [U-Boot] [PATCH 3/3] CLK: OMAP: PCIE: Registers definitions necessary for PCIe clock generation Lukasz Majewski
@ 2017-01-16  3:44 ` Lokesh Vutla
  2017-01-16 16:25 ` Roger Quadros
  3 siblings, 0 replies; 5+ messages in thread
From: Lokesh Vutla @ 2017-01-16  3:44 UTC (permalink / raw)
  To: u-boot



On Monday 16 January 2017 04:09 AM, Lukasz Majewski wrote:
> With this code only 19.2 HMz SYSCLK (input) frequency is supported on
> dra7xx based SoCs.

This wold be breaking dra74x-evm which has 20MHz sysclk.
May I know what is intention for configuring PCIE dpll in u-boot?(you
want to use PCIE at u-boot or for kernel to depend on this configuration?)

Thanks and regards,
Lokesh

> 
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>  arch/arm/cpu/armv7/omap5/hw_data.c | 12 ++++++++++++
>  arch/arm/include/asm/omap_common.h |  1 +
>  2 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
> index 2192090..e16bd2c 100644
> --- a/arch/arm/cpu/armv7/omap5/hw_data.c
> +++ b/arch/arm/cpu/armv7/omap5/hw_data.c
> @@ -257,6 +257,17 @@ static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
>  	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
>  };
>  
> +static const struct dpll_params pcie_dpll_params_1500mhz[NUM_SYS_CLKS] = {
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
> +	{625, 7, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
> +};
> +
> +
>  struct dplls omap5_dplls_es1 = {
>  	.mpu = mpu_dpll_params_800mhz,
>  	.core = core_dpll_params_2128mhz_ddr532,
> @@ -294,6 +305,7 @@ struct dplls dra7xx_dplls = {
>  	.usb = usb_dpll_params_1920mhz,
>  	.ddr = ddr_dpll_params_2128mhz,
>  	.gmac = gmac_dpll_params_2000mhz,
> +	.pcie = pcie_dpll_params_1500mhz,
>  };
>  
>  struct dplls dra72x_dplls = {
> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
> index 605c549..cc40ee9 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -526,6 +526,7 @@ struct dplls {
>  	const struct dpll_params *usb;
>  	const struct dpll_params *ddr;
>  	const struct dpll_params *gmac;
> +	const struct dpll_params *pcie;
>  };
>  
>  struct pmic_data {
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL
  2017-01-15 22:39 [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lukasz Majewski
                   ` (2 preceding siblings ...)
  2017-01-16  3:44 ` [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lokesh Vutla
@ 2017-01-16 16:25 ` Roger Quadros
  3 siblings, 0 replies; 5+ messages in thread
From: Roger Quadros @ 2017-01-16 16:25 UTC (permalink / raw)
  To: u-boot

+Kishon

On 16/01/17 00:39, Lukasz Majewski wrote:
> With this code only 19.2 HMz SYSCLK (input) frequency is supported on
> dra7xx based SoCs.
> 
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
>  arch/arm/cpu/armv7/omap5/hw_data.c | 12 ++++++++++++
>  arch/arm/include/asm/omap_common.h |  1 +
>  2 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
> index 2192090..e16bd2c 100644
> --- a/arch/arm/cpu/armv7/omap5/hw_data.c
> +++ b/arch/arm/cpu/armv7/omap5/hw_data.c
> @@ -257,6 +257,17 @@ static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
>  	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
>  };
>  
> +static const struct dpll_params pcie_dpll_params_1500mhz[NUM_SYS_CLKS] = {
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
> +	{625, 7, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
> +	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
> +};
> +
> +
>  struct dplls omap5_dplls_es1 = {
>  	.mpu = mpu_dpll_params_800mhz,
>  	.core = core_dpll_params_2128mhz_ddr532,
> @@ -294,6 +305,7 @@ struct dplls dra7xx_dplls = {
>  	.usb = usb_dpll_params_1920mhz,
>  	.ddr = ddr_dpll_params_2128mhz,
>  	.gmac = gmac_dpll_params_2000mhz,
> +	.pcie = pcie_dpll_params_1500mhz,
>  };
>  
>  struct dplls dra72x_dplls = {
> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
> index 605c549..cc40ee9 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -526,6 +526,7 @@ struct dplls {
>  	const struct dpll_params *usb;
>  	const struct dpll_params *ddr;
>  	const struct dpll_params *gmac;
> +	const struct dpll_params *pcie;
>  };
>  
>  struct pmic_data {
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-01-16 16:25 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-15 22:39 [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lukasz Majewski
2017-01-15 22:39 ` [U-Boot] [PATCH 2/3] CLK: OMAP: PCIE: Provide support for PCIE DPLL configuration Lukasz Majewski
2017-01-15 22:39 ` [U-Boot] [PATCH 3/3] CLK: OMAP: PCIE: Registers definitions necessary for PCIe clock generation Lukasz Majewski
2017-01-16  3:44 ` [U-Boot] [PATCH 1/3] DRA7XX: HW_DATA: Provide dpll_params definitions for PCIe DPLL Lokesh Vutla
2017-01-16 16:25 ` Roger Quadros

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