* [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
This patch set support use cross type vCPU when using KVM on ARM and add
two new CPU types: generic and cortex-a72.
You can test this patch set with QEMU using
-cpu cortex-a53/cortex-a57/generic/cortex-a72
These patches can be fetched from:
https://git.linaro.org/people/shannon.zhao/qemu.git cross_vcpu_rfc
You corresponding KVM patches can be fetched from:
https://git.linaro.org/people/shannon.zhao/linux-mainline.git cross_vcpu_rfc
Shannon Zhao (6):
headers: update linux headers
target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
arm: kvm64: Check if kvm supports cross type vCPU
target: arm: Add a generic type cpu
arm: virt: Enable generic type CPU in virt machine
target-arm: cpu64: Add support for Cortex-A72
hw/arm/virt.c | 2 +
linux-headers/asm-arm64/kvm.h | 1 +
linux-headers/linux/kvm.h | 2 +
target/arm/cpu64.c | 110 +++++++++++++++++++++++++
target/arm/kvm-consts.h | 2 +
target/arm/kvm64.c | 182 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 299 insertions(+)
--
2.0.4
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
This patch set support use cross type vCPU when using KVM on ARM and add
two new CPU types: generic and cortex-a72.
You can test this patch set with QEMU using
-cpu cortex-a53/cortex-a57/generic/cortex-a72
These patches can be fetched from:
https://git.linaro.org/people/shannon.zhao/qemu.git cross_vcpu_rfc
You corresponding KVM patches can be fetched from:
https://git.linaro.org/people/shannon.zhao/linux-mainline.git cross_vcpu_rfc
Shannon Zhao (6):
headers: update linux headers
target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
arm: kvm64: Check if kvm supports cross type vCPU
target: arm: Add a generic type cpu
arm: virt: Enable generic type CPU in virt machine
target-arm: cpu64: Add support for Cortex-A72
hw/arm/virt.c | 2 +
linux-headers/asm-arm64/kvm.h | 1 +
linux-headers/linux/kvm.h | 2 +
target/arm/cpu64.c | 110 +++++++++++++++++++++++++
target/arm/kvm-consts.h | 2 +
target/arm/kvm64.c | 182 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 299 insertions(+)
--
2.0.4
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 1/6] headers: update linux headers
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:26 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
| 1 +
| 2 ++
2 files changed, 3 insertions(+)
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index fd5a276..f914eac 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -97,6 +97,7 @@ struct kvm_regs {
#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
+#define KVM_ARM_VCPU_CROSS 4 /* Support cross type vCPU */
struct kvm_vcpu_init {
__u32 target;
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index bb0ed71..ea9e288 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -870,6 +870,8 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_S390_USER_INSTR0 130
#define KVM_CAP_MSI_DEVID 131
#define KVM_CAP_PPC_HTM 132
+#define KVM_CAP_ARM_CROSS_VCPU 133
+#define KVM_CAP_ARM_HETEROGENEOUS 134
#ifdef KVM_CAP_IRQ_ROUTING
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 1/6] headers: update linux headers
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
| 1 +
| 2 ++
2 files changed, 3 insertions(+)
--git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
index fd5a276..f914eac 100644
--- a/linux-headers/asm-arm64/kvm.h
+++ b/linux-headers/asm-arm64/kvm.h
@@ -97,6 +97,7 @@ struct kvm_regs {
#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
+#define KVM_ARM_VCPU_CROSS 4 /* Support cross type vCPU */
struct kvm_vcpu_init {
__u32 target;
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index bb0ed71..ea9e288 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -870,6 +870,8 @@ struct kvm_ppc_smmu_info {
#define KVM_CAP_S390_USER_INSTR0 130
#define KVM_CAP_MSI_DEVID 131
#define KVM_CAP_PPC_HTM 132
+#define KVM_CAP_ARM_CROSS_VCPU 133
+#define KVM_CAP_ARM_HETEROGENEOUS 134
#ifdef KVM_CAP_IRQ_ROUTING
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 2/6] target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:26 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/kvm-consts.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index a2c9518..fc01ac5 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -128,6 +128,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
+#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5
/* There's no kernel define for this: sentinel value which
* matches no KVM target value for either 64 or 32 bit
@@ -140,6 +141,7 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8)
#else
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7)
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 2/6] target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/kvm-consts.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index a2c9518..fc01ac5 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -128,6 +128,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED)
#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
+#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5
/* There's no kernel define for this: sentinel value which
* matches no KVM target value for either 64 or 32 bit
@@ -140,6 +141,7 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8)
#else
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15)
MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7)
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:26 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
If user requests a specific type vCPU which is not same with the
physical ones and if kvm supports cross type vCPU, we set the
KVM_ARM_VCPU_CROSS bit and set the CPU ID registers.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/kvm64.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 6111109..70442ea 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -481,7 +481,151 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
return true;
}
+#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
+/* ID group 1 registers */
+#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
+#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
+
+/* ID group 2 registers */
+#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
+#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
+#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
+#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
+
+/* ID group 3 registers */
+#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
+#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
+#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
+#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
+#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
+#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
+#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
+#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
+#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
+#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
+#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
+#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
+#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
+#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
+#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
+#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
+#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
+#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
+#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
+#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
+#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
+#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
+#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
+#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
+#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
+#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
+#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
+#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
+#define ARM_CPU_ID_MAX 36
+
+static int kvm_arm_set_id_registers(CPUState *cs)
+{
+ int ret = 0;
+ uint32_t i;
+ ARMCPU *cpu = ARM_CPU(cs);
+ struct kvm_one_reg id_regitsers[ARM_CPU_ID_MAX];
+
+ memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
+
+ id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
+ id_regitsers[0].addr = (uintptr_t)&cpu->midr;
+
+ id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
+ id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
+
+ id_regitsers[2].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR0);
+ id_regitsers[2].addr = (uintptr_t)&cpu->mvfr0;
+
+ id_regitsers[3].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR1);
+ id_regitsers[3].addr = (uintptr_t)&cpu->mvfr1;
+
+ id_regitsers[4].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR2);
+ id_regitsers[4].addr = (uintptr_t)&cpu->mvfr2;
+
+ id_regitsers[5].id = ARM64_SYS_REG(ARM_CPU_ID_PFR0);
+ id_regitsers[5].addr = (uintptr_t)&cpu->id_pfr0;
+
+ id_regitsers[6].id = ARM64_SYS_REG(ARM_CPU_ID_PFR1);
+ id_regitsers[6].addr = (uintptr_t)&cpu->id_pfr1;
+
+ id_regitsers[7].id = ARM64_SYS_REG(ARM_CPU_ID_DFR0);
+ id_regitsers[7].addr = (uintptr_t)&cpu->id_dfr0;
+
+ id_regitsers[8].id = ARM64_SYS_REG(ARM_CPU_ID_AFR0);
+ id_regitsers[8].addr = (uintptr_t)&cpu->id_afr0;
+
+ id_regitsers[9].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR0);
+ id_regitsers[9].addr = (uintptr_t)&cpu->id_mmfr0;
+
+ id_regitsers[10].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR1);
+ id_regitsers[10].addr = (uintptr_t)&cpu->id_mmfr1;
+
+ id_regitsers[11].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR2);
+ id_regitsers[11].addr = (uintptr_t)&cpu->id_mmfr2;
+
+ id_regitsers[12].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR3);
+ id_regitsers[12].addr = (uintptr_t)&cpu->id_mmfr3;
+
+ id_regitsers[13].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR0);
+ id_regitsers[13].addr = (uintptr_t)&cpu->id_isar0;
+
+ id_regitsers[14].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR1);
+ id_regitsers[14].addr = (uintptr_t)&cpu->id_isar1;
+
+ id_regitsers[15].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR2);
+ id_regitsers[15].addr = (uintptr_t)&cpu->id_isar2;
+
+ id_regitsers[16].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR3);
+ id_regitsers[16].addr = (uintptr_t)&cpu->id_isar3;
+
+ id_regitsers[17].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR4);
+ id_regitsers[17].addr = (uintptr_t)&cpu->id_isar4;
+
+ id_regitsers[18].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR5);
+ id_regitsers[18].addr = (uintptr_t)&cpu->id_isar5;
+
+ id_regitsers[19].id = ARM64_SYS_REG(ARM_CPU_ID_AA64PFR0);
+ id_regitsers[19].addr = (uintptr_t)&cpu->id_aa64pfr0;
+
+ id_regitsers[20].id = ARM64_SYS_REG(ARM_CPU_ID_AA64DFR0);
+ id_regitsers[20].addr = (uintptr_t)&cpu->id_aa64dfr0;
+
+ id_regitsers[21].id = ARM64_SYS_REG(ARM_CPU_ID_AA64ISAR0);
+ id_regitsers[21].addr = (uintptr_t)&cpu->id_aa64isar0;
+
+ id_regitsers[22].id = ARM64_SYS_REG(ARM_CPU_ID_AA64MMFR0);
+ id_regitsers[22].addr = (uintptr_t)&cpu->id_aa64mmfr0;
+
+ id_regitsers[23].id = ARM64_SYS_REG(ARM_CPU_ID_CLIDR);
+ id_regitsers[23].addr = (uintptr_t)&cpu->clidr;
+
+ id_regitsers[24].id = ARM64_SYS_REG(ARM_CPU_ID_CTR);
+ id_regitsers[24].addr = (uintptr_t)&cpu->ctr;
+
+
+ for (i = 0; i < ARM_CPU_ID_MAX; i++) {
+ if(id_regitsers[i].id != 0) {
+ ret = kvm_set_one_reg(cs, id_regitsers[i].id,
+ (void *)id_regitsers[i].addr);
+ if (ret) {
+ fprintf(stderr, "set ID register 0x%llx failed\n",
+ id_regitsers[i].id);
+ return ret;
+ }
+ } else {
+ break;
+ }
+ }
+
+ /* TODO: Set CCSIDR */
+ return ret;
+}
int kvm_arch_init_vcpu(CPUState *cs)
{
@@ -489,6 +633,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
uint64_t mpidr;
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ bool heterogeneous = false, cross = false;
+ struct kvm_vcpu_init init;
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
@@ -518,12 +664,48 @@ int kvm_arch_init_vcpu(CPUState *cs)
unset_feature(&env->features, ARM_FEATURE_PMU);
}
+ /*
+ * Check if host is a heterogeneous system. It doesn't support -cpu host on
+ * heterogeneous system. If user requests a specific type VCPU, it should
+ * set the KVM_ARM_VCPU_CROSS bit to tell KVM that userspace want a specific
+ * vCPU. If KVM supports cross type vCPU, then set the ID registers.
+ */
+ if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_HETEROGENEOUS)) {
+ heterogeneous = true;
+ }
+
+ if (strcmp(object_get_typename(OBJECT(cpu)), TYPE_ARM_HOST_CPU) == 0) {
+ if (heterogeneous) {
+ fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
+ return -EINVAL;
+ }
+ } else if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_CROSS_VCPU)) {
+ init.features[0] = 1 << KVM_ARM_VCPU_CROSS;
+ if (kvm_vm_ioctl(cs->kvm_state, KVM_ARM_PREFERRED_TARGET, &init) < 0) {
+ return -EINVAL;
+ }
+
+ if (init.target != (cpu->midr & 0xFF00FFF0) || heterogeneous) {
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_CROSS;
+ cross = true;
+ }
+ }
+
/* Do KVM_ARM_VCPU_INIT ioctl */
ret = kvm_arm_vcpu_init(cs);
if (ret) {
return ret;
}
+ if (cross) {
+ ret = kvm_arm_set_id_registers(cs);
+ if (ret) {
+ fprintf(stderr, "set vcpu ID registers failed\n");
+ return ret;
+ }
+ }
+
/*
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
* Currently KVM has its own idea about MPIDR assignment, so we
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
If user requests a specific type vCPU which is not same with the
physical ones and if kvm supports cross type vCPU, we set the
KVM_ARM_VCPU_CROSS bit and set the CPU ID registers.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/kvm64.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 6111109..70442ea 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -481,7 +481,151 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
return true;
}
+#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
+/* ID group 1 registers */
+#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
+#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
+
+/* ID group 2 registers */
+#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
+#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
+#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
+#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
+
+/* ID group 3 registers */
+#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
+#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
+#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
+#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
+#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
+#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
+#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
+#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
+#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
+#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
+#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
+#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
+#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
+#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
+#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
+#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
+#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
+#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
+#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
+#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
+#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
+#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
+#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
+#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
+#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
+#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
+#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
+#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
+#define ARM_CPU_ID_MAX 36
+
+static int kvm_arm_set_id_registers(CPUState *cs)
+{
+ int ret = 0;
+ uint32_t i;
+ ARMCPU *cpu = ARM_CPU(cs);
+ struct kvm_one_reg id_regitsers[ARM_CPU_ID_MAX];
+
+ memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
+
+ id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
+ id_regitsers[0].addr = (uintptr_t)&cpu->midr;
+
+ id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
+ id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
+
+ id_regitsers[2].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR0);
+ id_regitsers[2].addr = (uintptr_t)&cpu->mvfr0;
+
+ id_regitsers[3].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR1);
+ id_regitsers[3].addr = (uintptr_t)&cpu->mvfr1;
+
+ id_regitsers[4].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR2);
+ id_regitsers[4].addr = (uintptr_t)&cpu->mvfr2;
+
+ id_regitsers[5].id = ARM64_SYS_REG(ARM_CPU_ID_PFR0);
+ id_regitsers[5].addr = (uintptr_t)&cpu->id_pfr0;
+
+ id_regitsers[6].id = ARM64_SYS_REG(ARM_CPU_ID_PFR1);
+ id_regitsers[6].addr = (uintptr_t)&cpu->id_pfr1;
+
+ id_regitsers[7].id = ARM64_SYS_REG(ARM_CPU_ID_DFR0);
+ id_regitsers[7].addr = (uintptr_t)&cpu->id_dfr0;
+
+ id_regitsers[8].id = ARM64_SYS_REG(ARM_CPU_ID_AFR0);
+ id_regitsers[8].addr = (uintptr_t)&cpu->id_afr0;
+
+ id_regitsers[9].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR0);
+ id_regitsers[9].addr = (uintptr_t)&cpu->id_mmfr0;
+
+ id_regitsers[10].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR1);
+ id_regitsers[10].addr = (uintptr_t)&cpu->id_mmfr1;
+
+ id_regitsers[11].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR2);
+ id_regitsers[11].addr = (uintptr_t)&cpu->id_mmfr2;
+
+ id_regitsers[12].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR3);
+ id_regitsers[12].addr = (uintptr_t)&cpu->id_mmfr3;
+
+ id_regitsers[13].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR0);
+ id_regitsers[13].addr = (uintptr_t)&cpu->id_isar0;
+
+ id_regitsers[14].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR1);
+ id_regitsers[14].addr = (uintptr_t)&cpu->id_isar1;
+
+ id_regitsers[15].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR2);
+ id_regitsers[15].addr = (uintptr_t)&cpu->id_isar2;
+
+ id_regitsers[16].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR3);
+ id_regitsers[16].addr = (uintptr_t)&cpu->id_isar3;
+
+ id_regitsers[17].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR4);
+ id_regitsers[17].addr = (uintptr_t)&cpu->id_isar4;
+
+ id_regitsers[18].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR5);
+ id_regitsers[18].addr = (uintptr_t)&cpu->id_isar5;
+
+ id_regitsers[19].id = ARM64_SYS_REG(ARM_CPU_ID_AA64PFR0);
+ id_regitsers[19].addr = (uintptr_t)&cpu->id_aa64pfr0;
+
+ id_regitsers[20].id = ARM64_SYS_REG(ARM_CPU_ID_AA64DFR0);
+ id_regitsers[20].addr = (uintptr_t)&cpu->id_aa64dfr0;
+
+ id_regitsers[21].id = ARM64_SYS_REG(ARM_CPU_ID_AA64ISAR0);
+ id_regitsers[21].addr = (uintptr_t)&cpu->id_aa64isar0;
+
+ id_regitsers[22].id = ARM64_SYS_REG(ARM_CPU_ID_AA64MMFR0);
+ id_regitsers[22].addr = (uintptr_t)&cpu->id_aa64mmfr0;
+
+ id_regitsers[23].id = ARM64_SYS_REG(ARM_CPU_ID_CLIDR);
+ id_regitsers[23].addr = (uintptr_t)&cpu->clidr;
+
+ id_regitsers[24].id = ARM64_SYS_REG(ARM_CPU_ID_CTR);
+ id_regitsers[24].addr = (uintptr_t)&cpu->ctr;
+
+
+ for (i = 0; i < ARM_CPU_ID_MAX; i++) {
+ if(id_regitsers[i].id != 0) {
+ ret = kvm_set_one_reg(cs, id_regitsers[i].id,
+ (void *)id_regitsers[i].addr);
+ if (ret) {
+ fprintf(stderr, "set ID register 0x%llx failed\n",
+ id_regitsers[i].id);
+ return ret;
+ }
+ } else {
+ break;
+ }
+ }
+
+ /* TODO: Set CCSIDR */
+ return ret;
+}
int kvm_arch_init_vcpu(CPUState *cs)
{
@@ -489,6 +633,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
uint64_t mpidr;
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
+ bool heterogeneous = false, cross = false;
+ struct kvm_vcpu_init init;
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
@@ -518,12 +664,48 @@ int kvm_arch_init_vcpu(CPUState *cs)
unset_feature(&env->features, ARM_FEATURE_PMU);
}
+ /*
+ * Check if host is a heterogeneous system. It doesn't support -cpu host on
+ * heterogeneous system. If user requests a specific type VCPU, it should
+ * set the KVM_ARM_VCPU_CROSS bit to tell KVM that userspace want a specific
+ * vCPU. If KVM supports cross type vCPU, then set the ID registers.
+ */
+ if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_HETEROGENEOUS)) {
+ heterogeneous = true;
+ }
+
+ if (strcmp(object_get_typename(OBJECT(cpu)), TYPE_ARM_HOST_CPU) == 0) {
+ if (heterogeneous) {
+ fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
+ return -EINVAL;
+ }
+ } else if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_CROSS_VCPU)) {
+ init.features[0] = 1 << KVM_ARM_VCPU_CROSS;
+ if (kvm_vm_ioctl(cs->kvm_state, KVM_ARM_PREFERRED_TARGET, &init) < 0) {
+ return -EINVAL;
+ }
+
+ if (init.target != (cpu->midr & 0xFF00FFF0) || heterogeneous) {
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_CROSS;
+ cross = true;
+ }
+ }
+
/* Do KVM_ARM_VCPU_INIT ioctl */
ret = kvm_arm_vcpu_init(cs);
if (ret) {
return ret;
}
+ if (cross) {
+ ret = kvm_arm_set_id_registers(cs);
+ if (ret) {
+ fprintf(stderr, "set vcpu ID registers failed\n");
+ return ret;
+ }
+ }
+
/*
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
* Currently KVM has its own idea about MPIDR assignment, so we
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:26 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
Add a generic type cpu, it's useful for migration when running on
different hardwares.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 549cb1e..223f31e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}
+static void aarch64_generic_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,armv8";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034070;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x12111111;
+ cpu->mvfr2 = 0x00000043;
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->id_pfr0 = 0x00000131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01260000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232042;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x00011142;
+ cpu->id_isar5 = 0x00011121;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->id_aa64isar0 = 0x00011120;
+ cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
+ cpu->dbgdidr = 0x3516d000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
+ cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
+}
+
#ifdef CONFIG_USER_ONLY
static void aarch64_any_initfn(Object *obj)
{
@@ -232,6 +285,7 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
+ { .name = "generic", .initfn = aarch64_generic_initfn },
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 4/6] target: arm: Add a generic type cpu
@ 2017-01-16 9:26 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:26 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
Add a generic type cpu, it's useful for migration when running on
different hardwares.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 549cb1e..223f31e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}
+static void aarch64_generic_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,armv8";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034070;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x12111111;
+ cpu->mvfr2 = 0x00000043;
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->id_pfr0 = 0x00000131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01260000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232042;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x00011142;
+ cpu->id_isar5 = 0x00011121;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->id_aa64isar0 = 0x00011120;
+ cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
+ cpu->dbgdidr = 0x3516d000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
+ cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
+}
+
#ifdef CONFIG_USER_ONLY
static void aarch64_any_initfn(Object *obj)
{
@@ -232,6 +285,7 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
+ { .name = "generic", .initfn = aarch64_generic_initfn },
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 5/6] arm: virt: Enable generic type CPU in virt machine
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:27 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:27 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b301c2..49b7b65 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -166,6 +166,7 @@ static const char *valid_cpus[] = {
"cortex-a15",
"cortex-a53",
"cortex-a57",
+ "generic",
"host",
NULL
};
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 5/6] arm: virt: Enable generic type CPU in virt machine
@ 2017-01-16 9:27 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:27 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4b301c2..49b7b65 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -166,6 +166,7 @@ static const char *valid_cpus[] = {
"cortex-a15",
"cortex-a53",
"cortex-a57",
+ "generic",
"host",
NULL
};
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH RFC 6/6] target-arm: cpu64: Add support for Cortex-A72
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:27 ` Shannon Zhao
-1 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:27 UTC (permalink / raw)
To: qemu-arm
Cc: qemu-devel, peter.maydell, wei, drjones, christoffer.dall,
kvmarm, zhaoshenglong, wu.wubin
From: Shannon Zhao <shannon.zhao@linaro.org>
Add the ARM Cortex-A72 processor definition. It's similar to A57.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 49b7b65..2ba93e3 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -166,6 +166,7 @@ static const char *valid_cpus[] = {
"cortex-a15",
"cortex-a53",
"cortex-a57",
+ "cortex-a72",
"generic",
"host",
NULL
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 223f31e..4f00ceb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -204,6 +204,61 @@ static void aarch64_a53_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}
+static void aarch64_a72_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a72";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->midr = 0x410fd081;
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034080;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x12111111;
+ cpu->mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->id_pfr0 = 0x00000131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10201105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01260000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232042;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x00011142;
+ cpu->id_isar5 = 0x00011121;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
+ cpu->id_aa64isar0 = 0x00011120;
+ cpu->id_aa64mmfr0 = 0x00001124;
+ cpu->dbgdidr = 0x3516d000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x71ffe07a; /* 4096KB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
+}
+
static void aarch64_generic_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -285,6 +340,7 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
+ { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "generic", .initfn = aarch64_generic_initfn },
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH RFC 6/6] target-arm: cpu64: Add support for Cortex-A72
@ 2017-01-16 9:27 ` Shannon Zhao
0 siblings, 0 replies; 26+ messages in thread
From: Shannon Zhao @ 2017-01-16 9:27 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, wu.wubin, kvmarm
From: Shannon Zhao <shannon.zhao@linaro.org>
Add the ARM Cortex-A72 processor definition. It's similar to A57.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 49b7b65..2ba93e3 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -166,6 +166,7 @@ static const char *valid_cpus[] = {
"cortex-a15",
"cortex-a53",
"cortex-a57",
+ "cortex-a72",
"generic",
"host",
NULL
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 223f31e..4f00ceb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -204,6 +204,61 @@ static void aarch64_a53_initfn(Object *obj)
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}
+static void aarch64_a72_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a72";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_V8_AES);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
+ set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
+ set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
+ set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
+ cpu->midr = 0x410fd081;
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034080;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x12111111;
+ cpu->mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->id_pfr0 = 0x00000131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10201105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01260000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232042;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x00011142;
+ cpu->id_isar5 = 0x00011121;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
+ cpu->id_aa64isar0 = 0x00011120;
+ cpu->id_aa64mmfr0 = 0x00001124;
+ cpu->dbgdidr = 0x3516d000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x71ffe07a; /* 4096KB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
+}
+
static void aarch64_generic_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -285,6 +340,7 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
+ { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "generic", .initfn = aarch64_generic_initfn },
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
--
2.0.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-16 9:42 ` no-reply
-1 siblings, 0 replies; 26+ messages in thread
From: no-reply @ 2017-01-16 9:42 UTC (permalink / raw)
To: zhaoshenglong
Cc: famz, qemu-arm, wei, peter.maydell, drjones, qemu-devel,
wu.wubin, kvmarm, christoffer.dall
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com
Subject: [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com -> patchew/1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com
Switched to a new branch 'test'
ad5e87b target-arm: cpu64: Add support for Cortex-A72
d4f6c86 arm: virt: Enable generic type CPU in virt machine
db2426e target: arm: Add a generic type cpu
042dff8 arm: kvm64: Check if kvm supports cross type vCPU
d8b8db1 target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
71eb07d headers: update linux headers
=== OUTPUT BEGIN ===
Checking PATCH 1/6: headers: update linux headers...
Checking PATCH 2/6: target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8...
Checking PATCH 3/6: arm: kvm64: Check if kvm supports cross type vCPU...
ERROR: Macros with complex values should be enclosed in parenthesis
#21: FILE: target/arm/kvm64.c:484:
+#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#24: FILE: target/arm/kvm64.c:487:
+#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#25: FILE: target/arm/kvm64.c:488:
+#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
ERROR: Macros with complex values should be enclosed in parenthesis
#28: FILE: target/arm/kvm64.c:491:
+#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#29: FILE: target/arm/kvm64.c:492:
+#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#30: FILE: target/arm/kvm64.c:493:
+#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#31: FILE: target/arm/kvm64.c:494:
+#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#34: FILE: target/arm/kvm64.c:497:
+#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#35: FILE: target/arm/kvm64.c:498:
+#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#36: FILE: target/arm/kvm64.c:499:
+#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#37: FILE: target/arm/kvm64.c:500:
+#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
ERROR: Macros with complex values should be enclosed in parenthesis
#38: FILE: target/arm/kvm64.c:501:
+#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#39: FILE: target/arm/kvm64.c:502:
+#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#40: FILE: target/arm/kvm64.c:503:
+#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#41: FILE: target/arm/kvm64.c:504:
+#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
ERROR: Macros with complex values should be enclosed in parenthesis
#42: FILE: target/arm/kvm64.c:505:
+#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#43: FILE: target/arm/kvm64.c:506:
+#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#44: FILE: target/arm/kvm64.c:507:
+#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#45: FILE: target/arm/kvm64.c:508:
+#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
ERROR: Macros with complex values should be enclosed in parenthesis
#46: FILE: target/arm/kvm64.c:509:
+#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#47: FILE: target/arm/kvm64.c:510:
+#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#48: FILE: target/arm/kvm64.c:511:
+#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#49: FILE: target/arm/kvm64.c:512:
+#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#50: FILE: target/arm/kvm64.c:513:
+#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#51: FILE: target/arm/kvm64.c:514:
+#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#52: FILE: target/arm/kvm64.c:515:
+#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#53: FILE: target/arm/kvm64.c:516:
+#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#54: FILE: target/arm/kvm64.c:517:
+#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#55: FILE: target/arm/kvm64.c:518:
+#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#56: FILE: target/arm/kvm64.c:519:
+#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#57: FILE: target/arm/kvm64.c:520:
+#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#58: FILE: target/arm/kvm64.c:521:
+#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#59: FILE: target/arm/kvm64.c:522:
+#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#60: FILE: target/arm/kvm64.c:523:
+#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#61: FILE: target/arm/kvm64.c:524:
+#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
ERROR: space required before the open parenthesis '('
#150: FILE: target/arm/kvm64.c:613:
+ if(id_regitsers[i].id != 0) {
WARNING: line over 80 characters
#194: FILE: target/arm/kvm64.c:679:
+ fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
total: 36 errors, 1 warnings, 207 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/6: target: arm: Add a generic type cpu...
WARNING: line over 80 characters
#63: FILE: target/arm/cpu64.c:250:
+ cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
total: 0 errors, 1 warnings, 66 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/6: arm: virt: Enable generic type CPU in virt machine...
Checking PATCH 6/6: target-arm: cpu64: Add support for Cortex-A72...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
@ 2017-01-16 9:42 ` no-reply
0 siblings, 0 replies; 26+ messages in thread
From: no-reply @ 2017-01-16 9:42 UTC (permalink / raw)
Cc: wei, peter.maydell, drjones, famz, qemu-devel, qemu-arm,
christoffer.dall, zhaoshenglong, kvmarm, wu.wubin
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com
Subject: [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com -> patchew/1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com
Switched to a new branch 'test'
ad5e87b target-arm: cpu64: Add support for Cortex-A72
d4f6c86 arm: virt: Enable generic type CPU in virt machine
db2426e target: arm: Add a generic type cpu
042dff8 arm: kvm64: Check if kvm supports cross type vCPU
d8b8db1 target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8
71eb07d headers: update linux headers
=== OUTPUT BEGIN ===
Checking PATCH 1/6: headers: update linux headers...
Checking PATCH 2/6: target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8...
Checking PATCH 3/6: arm: kvm64: Check if kvm supports cross type vCPU...
ERROR: Macros with complex values should be enclosed in parenthesis
#21: FILE: target/arm/kvm64.c:484:
+#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#24: FILE: target/arm/kvm64.c:487:
+#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#25: FILE: target/arm/kvm64.c:488:
+#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
ERROR: Macros with complex values should be enclosed in parenthesis
#28: FILE: target/arm/kvm64.c:491:
+#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#29: FILE: target/arm/kvm64.c:492:
+#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#30: FILE: target/arm/kvm64.c:493:
+#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#31: FILE: target/arm/kvm64.c:494:
+#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#34: FILE: target/arm/kvm64.c:497:
+#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#35: FILE: target/arm/kvm64.c:498:
+#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#36: FILE: target/arm/kvm64.c:499:
+#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#37: FILE: target/arm/kvm64.c:500:
+#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
ERROR: Macros with complex values should be enclosed in parenthesis
#38: FILE: target/arm/kvm64.c:501:
+#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#39: FILE: target/arm/kvm64.c:502:
+#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#40: FILE: target/arm/kvm64.c:503:
+#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#41: FILE: target/arm/kvm64.c:504:
+#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
ERROR: Macros with complex values should be enclosed in parenthesis
#42: FILE: target/arm/kvm64.c:505:
+#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#43: FILE: target/arm/kvm64.c:506:
+#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#44: FILE: target/arm/kvm64.c:507:
+#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#45: FILE: target/arm/kvm64.c:508:
+#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
ERROR: Macros with complex values should be enclosed in parenthesis
#46: FILE: target/arm/kvm64.c:509:
+#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#47: FILE: target/arm/kvm64.c:510:
+#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#48: FILE: target/arm/kvm64.c:511:
+#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
ERROR: Macros with complex values should be enclosed in parenthesis
#49: FILE: target/arm/kvm64.c:512:
+#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#50: FILE: target/arm/kvm64.c:513:
+#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#51: FILE: target/arm/kvm64.c:514:
+#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
ERROR: Macros with complex values should be enclosed in parenthesis
#52: FILE: target/arm/kvm64.c:515:
+#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#53: FILE: target/arm/kvm64.c:516:
+#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#54: FILE: target/arm/kvm64.c:517:
+#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#55: FILE: target/arm/kvm64.c:518:
+#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#56: FILE: target/arm/kvm64.c:519:
+#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
ERROR: Macros with complex values should be enclosed in parenthesis
#57: FILE: target/arm/kvm64.c:520:
+#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
ERROR: Macros with complex values should be enclosed in parenthesis
#58: FILE: target/arm/kvm64.c:521:
+#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#59: FILE: target/arm/kvm64.c:522:
+#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
ERROR: Macros with complex values should be enclosed in parenthesis
#60: FILE: target/arm/kvm64.c:523:
+#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
ERROR: Macros with complex values should be enclosed in parenthesis
#61: FILE: target/arm/kvm64.c:524:
+#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
ERROR: space required before the open parenthesis '('
#150: FILE: target/arm/kvm64.c:613:
+ if(id_regitsers[i].id != 0) {
WARNING: line over 80 characters
#194: FILE: target/arm/kvm64.c:679:
+ fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
total: 36 errors, 1 warnings, 207 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/6: target: arm: Add a generic type cpu...
WARNING: line over 80 characters
#63: FILE: target/arm/cpu64.c:250:
+ cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
total: 0 errors, 1 warnings, 66 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/6: arm: virt: Enable generic type CPU in virt machine...
Checking PATCH 6/6: target-arm: cpu64: Add support for Cortex-A72...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-29 11:53 ` Andrew Jones
-1 siblings, 0 replies; 26+ messages in thread
From: Andrew Jones @ 2017-01-29 11:53 UTC (permalink / raw)
To: Shannon Zhao
Cc: qemu-arm, wei, peter.maydell, qemu-devel, wu.wubin, kvmarm,
christoffer.dall
On Mon, Jan 16, 2017 at 05:26:58PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> If user requests a specific type vCPU which is not same with the
> physical ones and if kvm supports cross type vCPU, we set the
> KVM_ARM_VCPU_CROSS bit and set the CPU ID registers.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/kvm64.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 182 insertions(+)
>
> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
> index 6111109..70442ea 100644
> --- a/target/arm/kvm64.c
> +++ b/target/arm/kvm64.c
> @@ -481,7 +481,151 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
> return true;
> }
>
> +#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
> #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
> +/* ID group 1 registers */
> +#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
> +#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
> +
> +/* ID group 2 registers */
> +#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
> +#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
> +#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
> +#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
> +
> +/* ID group 3 registers */
> +#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
> +#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
> +#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
> +#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
> +#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
> +#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
> +#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
> +#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
> +#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
> +#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
> +#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
> +#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
> +#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
> +#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
> +#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
> +#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
> +#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
> +#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
> +#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
> +#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
> +#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
> +#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
> +#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
> +#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
> +#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
> +#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
> +#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
> +#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
> +#define ARM_CPU_ID_MAX 36
We don't need ARM_CPU_ID_MAX, I'll show you why below
> +
> +static int kvm_arm_set_id_registers(CPUState *cs)
> +{
> + int ret = 0;
> + uint32_t i;
> + ARMCPU *cpu = ARM_CPU(cs);
> + struct kvm_one_reg id_regitsers[ARM_CPU_ID_MAX];
> +
> + memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
> +
> + id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
> + id_regitsers[0].addr = (uintptr_t)&cpu->midr;
> +
> + id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
> + id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
> +
We can condense this nicely with list initialization
struct kvm_one_reg id_regitsers[] = {
{ ARM64_SYS_REG(ARM_CPU_ID_MIDR), (uintptr_t)&cpu->midr },
{ ARM64_SYS_REG(ARM_CPU_ID_REVIDR), (uintptr_t)&cpu->revidr },
...
{ 0, 0 }
};
...
> +
> + for (i = 0; i < ARM_CPU_ID_MAX; i++) {
> + if(id_regitsers[i].id != 0) {
Not sure why this check was here before, as there shouldn't have been
any zero ids in the list, but now we need the test, just not here.
The for loop should be written as
for (i = 0; id_regitsers[i].id; i++) {
> + ret = kvm_set_one_reg(cs, id_regitsers[i].id,
> + (void *)id_regitsers[i].addr);
> + if (ret) {
> + fprintf(stderr, "set ID register 0x%llx failed\n",
> + id_regitsers[i].id);
> + return ret;
> + }
> + } else {
> + break;
> + }
> + }
> +
> + /* TODO: Set CCSIDR */
> + return ret;
> +}
>
> int kvm_arch_init_vcpu(CPUState *cs)
> {
> @@ -489,6 +633,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
> uint64_t mpidr;
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> + bool heterogeneous = false, cross = false;
> + struct kvm_vcpu_init init;
>
> if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
> !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
> @@ -518,12 +664,48 @@ int kvm_arch_init_vcpu(CPUState *cs)
> unset_feature(&env->features, ARM_FEATURE_PMU);
> }
>
> + /*
> + * Check if host is a heterogeneous system. It doesn't support -cpu host on
> + * heterogeneous system. If user requests a specific type VCPU, it should
> + * set the KVM_ARM_VCPU_CROSS bit to tell KVM that userspace want a specific
> + * vCPU. If KVM supports cross type vCPU, then set the ID registers.
> + */
> + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_HETEROGENEOUS)) {
> + heterogeneous = true;
> + }
I don't think it should be necessary for qemu to check this. It should
just fail to create vcpus if it chooses the wrong type. Anyway, there
should be other ways for qemu to determine it's running on a
heterogeneous system without extending kvm's api.
> +
> + if (strcmp(object_get_typename(OBJECT(cpu)), TYPE_ARM_HOST_CPU) == 0) {
> + if (heterogeneous) {
> + fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
> + return -EINVAL;
> + }
IMO, we should leave this to higher levels. E.g. libvirt can determine if
a host is heterogeneous and then output errors when a user tries to
configure a guest to use cpu host. At the QEMU level an ioctl EINVAL on
vcpu create should be sufficient.
> + } else if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_CROSS_VCPU)) {
> + init.features[0] = 1 << KVM_ARM_VCPU_CROSS;
As I stated in the kvm series, I don't think this feature bit should be
necessary.
> + if (kvm_vm_ioctl(cs->kvm_state, KVM_ARM_PREFERRED_TARGET, &init) < 0) {
> + return -EINVAL;
> + }
> +
> + if (init.target != (cpu->midr & 0xFF00FFF0) || heterogeneous) {
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
Why force the target to be generic when we're cross? Not being possible
to do anything else, and that that's what we agreed on in Toronto is a
fair answer :-) I just don't recall right now what we said.
> + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_CROSS;
> + cross = true;
> + }
> + }
> +
> /* Do KVM_ARM_VCPU_INIT ioctl */
> ret = kvm_arm_vcpu_init(cs);
> if (ret) {
> return ret;
> }
>
> + if (cross) {
> + ret = kvm_arm_set_id_registers(cs);
> + if (ret) {
> + fprintf(stderr, "set vcpu ID registers failed\n");
You already have an fprintf(stderr, at the point of failure. We probably
don't need two, with this one having less information. I'd just return
ret here quietly.
> + return ret;
> + }
> + }
> +
> /*
> * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
> * Currently KVM has its own idea about MPIDR assignment, so we
> --
> 2.0.4
>
>
>
Thanks,
drew
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
@ 2017-01-29 11:53 ` Andrew Jones
0 siblings, 0 replies; 26+ messages in thread
From: Andrew Jones @ 2017-01-29 11:53 UTC (permalink / raw)
To: Shannon Zhao; +Cc: qemu-devel, qemu-arm, kvmarm, wu.wubin
On Mon, Jan 16, 2017 at 05:26:58PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> If user requests a specific type vCPU which is not same with the
> physical ones and if kvm supports cross type vCPU, we set the
> KVM_ARM_VCPU_CROSS bit and set the CPU ID registers.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/kvm64.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 182 insertions(+)
>
> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
> index 6111109..70442ea 100644
> --- a/target/arm/kvm64.c
> +++ b/target/arm/kvm64.c
> @@ -481,7 +481,151 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
> return true;
> }
>
> +#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0
> #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
> +/* ID group 1 registers */
> +#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6
> +#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7
> +
> +/* ID group 2 registers */
> +#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0
> +#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1
> +#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0
> +#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1
> +
> +/* ID group 3 registers */
> +#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0
> +#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1
> +#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2
> +#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3
> +#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4
> +#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5
> +#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6
> +#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7
> +#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0
> +#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1
> +#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2
> +#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3
> +#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4
> +#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5
> +#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6
> +#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0
> +#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1
> +#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2
> +#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0
> +#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1
> +#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0
> +#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1
> +#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4
> +#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5
> +#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0
> +#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1
> +#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0
> +#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1
> +#define ARM_CPU_ID_MAX 36
We don't need ARM_CPU_ID_MAX, I'll show you why below
> +
> +static int kvm_arm_set_id_registers(CPUState *cs)
> +{
> + int ret = 0;
> + uint32_t i;
> + ARMCPU *cpu = ARM_CPU(cs);
> + struct kvm_one_reg id_regitsers[ARM_CPU_ID_MAX];
> +
> + memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
> +
> + id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
> + id_regitsers[0].addr = (uintptr_t)&cpu->midr;
> +
> + id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
> + id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
> +
We can condense this nicely with list initialization
struct kvm_one_reg id_regitsers[] = {
{ ARM64_SYS_REG(ARM_CPU_ID_MIDR), (uintptr_t)&cpu->midr },
{ ARM64_SYS_REG(ARM_CPU_ID_REVIDR), (uintptr_t)&cpu->revidr },
...
{ 0, 0 }
};
...
> +
> + for (i = 0; i < ARM_CPU_ID_MAX; i++) {
> + if(id_regitsers[i].id != 0) {
Not sure why this check was here before, as there shouldn't have been
any zero ids in the list, but now we need the test, just not here.
The for loop should be written as
for (i = 0; id_regitsers[i].id; i++) {
> + ret = kvm_set_one_reg(cs, id_regitsers[i].id,
> + (void *)id_regitsers[i].addr);
> + if (ret) {
> + fprintf(stderr, "set ID register 0x%llx failed\n",
> + id_regitsers[i].id);
> + return ret;
> + }
> + } else {
> + break;
> + }
> + }
> +
> + /* TODO: Set CCSIDR */
> + return ret;
> +}
>
> int kvm_arch_init_vcpu(CPUState *cs)
> {
> @@ -489,6 +633,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
> uint64_t mpidr;
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> + bool heterogeneous = false, cross = false;
> + struct kvm_vcpu_init init;
>
> if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
> !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
> @@ -518,12 +664,48 @@ int kvm_arch_init_vcpu(CPUState *cs)
> unset_feature(&env->features, ARM_FEATURE_PMU);
> }
>
> + /*
> + * Check if host is a heterogeneous system. It doesn't support -cpu host on
> + * heterogeneous system. If user requests a specific type VCPU, it should
> + * set the KVM_ARM_VCPU_CROSS bit to tell KVM that userspace want a specific
> + * vCPU. If KVM supports cross type vCPU, then set the ID registers.
> + */
> + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_HETEROGENEOUS)) {
> + heterogeneous = true;
> + }
I don't think it should be necessary for qemu to check this. It should
just fail to create vcpus if it chooses the wrong type. Anyway, there
should be other ways for qemu to determine it's running on a
heterogeneous system without extending kvm's api.
> +
> + if (strcmp(object_get_typename(OBJECT(cpu)), TYPE_ARM_HOST_CPU) == 0) {
> + if (heterogeneous) {
> + fprintf(stderr, "heterogeneous system can't support host guest CPU type\n");
> + return -EINVAL;
> + }
IMO, we should leave this to higher levels. E.g. libvirt can determine if
a host is heterogeneous and then output errors when a user tries to
configure a guest to use cpu host. At the QEMU level an ioctl EINVAL on
vcpu create should be sufficient.
> + } else if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_CROSS_VCPU)) {
> + init.features[0] = 1 << KVM_ARM_VCPU_CROSS;
As I stated in the kvm series, I don't think this feature bit should be
necessary.
> + if (kvm_vm_ioctl(cs->kvm_state, KVM_ARM_PREFERRED_TARGET, &init) < 0) {
> + return -EINVAL;
> + }
> +
> + if (init.target != (cpu->midr & 0xFF00FFF0) || heterogeneous) {
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
Why force the target to be generic when we're cross? Not being possible
to do anything else, and that that's what we agreed on in Toronto is a
fair answer :-) I just don't recall right now what we said.
> + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_CROSS;
> + cross = true;
> + }
> + }
> +
> /* Do KVM_ARM_VCPU_INIT ioctl */
> ret = kvm_arm_vcpu_init(cs);
> if (ret) {
> return ret;
> }
>
> + if (cross) {
> + ret = kvm_arm_set_id_registers(cs);
> + if (ret) {
> + fprintf(stderr, "set vcpu ID registers failed\n");
You already have an fprintf(stderr, at the point of failure. We probably
don't need two, with this one having less information. I'd just return
ret here quietly.
> + return ret;
> + }
> + }
> +
> /*
> * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
> * Currently KVM has its own idea about MPIDR assignment, so we
> --
> 2.0.4
>
>
>
Thanks,
drew
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu
2017-01-16 9:26 ` Shannon Zhao
@ 2017-01-29 11:59 ` Andrew Jones
-1 siblings, 0 replies; 26+ messages in thread
From: Andrew Jones @ 2017-01-29 11:59 UTC (permalink / raw)
To: Shannon Zhao
Cc: qemu-arm, wei, peter.maydell, qemu-devel, wu.wubin, kvmarm,
christoffer.dall
On Mon, Jan 16, 2017 at 05:26:59PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add a generic type cpu, it's useful for migration when running on
> different hardwares.
How are the cpu parameters and features chosen for this generic
version? Shouldn't some of them, like id_aa64mmfr0, be configurable?
Or do we want to create multiple generic flavors?
Thanks,
drew
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 549cb1e..223f31e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> +static void aarch64_generic_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,armv8";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_V8_AES);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> + set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
> + cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
> + cpu->revidr = 0x00000000;
> + cpu->reset_fpsid = 0x41034070;
> + cpu->mvfr0 = 0x10110222;
> + cpu->mvfr1 = 0x12111111;
> + cpu->mvfr2 = 0x00000043;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->id_pfr0 = 0x00000131;
> + cpu->id_pfr1 = 0x00011011;
> + cpu->id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x10101105;
> + cpu->id_mmfr1 = 0x40000000;
> + cpu->id_mmfr2 = 0x01260000;
> + cpu->id_mmfr3 = 0x02102211;
> + cpu->id_isar0 = 0x02101110;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232042;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x00011142;
> + cpu->id_isar5 = 0x00011121;
> + cpu->id_aa64pfr0 = 0x00002222;
> + cpu->id_aa64dfr0 = 0x10305106;
> + cpu->id_aa64isar0 = 0x00011120;
> + cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
> + cpu->dbgdidr = 0x3516d000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
> + cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
> + cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> +}
> +
> #ifdef CONFIG_USER_ONLY
> static void aarch64_any_initfn(Object *obj)
> {
> @@ -232,6 +285,7 @@ typedef struct ARMCPUInfo {
> static const ARMCPUInfo aarch64_cpus[] = {
> { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
> { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
> + { .name = "generic", .initfn = aarch64_generic_initfn },
> #ifdef CONFIG_USER_ONLY
> { .name = "any", .initfn = aarch64_any_initfn },
> #endif
> --
> 2.0.4
>
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu
@ 2017-01-29 11:59 ` Andrew Jones
0 siblings, 0 replies; 26+ messages in thread
From: Andrew Jones @ 2017-01-29 11:59 UTC (permalink / raw)
To: Shannon Zhao; +Cc: qemu-devel, qemu-arm, kvmarm, wu.wubin
On Mon, Jan 16, 2017 at 05:26:59PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add a generic type cpu, it's useful for migration when running on
> different hardwares.
How are the cpu parameters and features chosen for this generic
version? Shouldn't some of them, like id_aa64mmfr0, be configurable?
Or do we want to create multiple generic flavors?
Thanks,
drew
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 549cb1e..223f31e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> +static void aarch64_generic_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,armv8";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_V8_AES);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> + set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
> + cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
> + cpu->revidr = 0x00000000;
> + cpu->reset_fpsid = 0x41034070;
> + cpu->mvfr0 = 0x10110222;
> + cpu->mvfr1 = 0x12111111;
> + cpu->mvfr2 = 0x00000043;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->id_pfr0 = 0x00000131;
> + cpu->id_pfr1 = 0x00011011;
> + cpu->id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x10101105;
> + cpu->id_mmfr1 = 0x40000000;
> + cpu->id_mmfr2 = 0x01260000;
> + cpu->id_mmfr3 = 0x02102211;
> + cpu->id_isar0 = 0x02101110;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232042;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x00011142;
> + cpu->id_isar5 = 0x00011121;
> + cpu->id_aa64pfr0 = 0x00002222;
> + cpu->id_aa64dfr0 = 0x10305106;
> + cpu->id_aa64isar0 = 0x00011120;
> + cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
> + cpu->dbgdidr = 0x3516d000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
> + cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
> + cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> +}
> +
> #ifdef CONFIG_USER_ONLY
> static void aarch64_any_initfn(Object *obj)
> {
> @@ -232,6 +285,7 @@ typedef struct ARMCPUInfo {
> static const ARMCPUInfo aarch64_cpus[] = {
> { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
> { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
> + { .name = "generic", .initfn = aarch64_generic_initfn },
> #ifdef CONFIG_USER_ONLY
> { .name = "any", .initfn = aarch64_any_initfn },
> #endif
> --
> 2.0.4
>
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
2017-01-29 11:53 ` Andrew Jones
@ 2017-01-29 20:42 ` Peter Maydell
-1 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-01-29 20:42 UTC (permalink / raw)
To: Andrew Jones
Cc: Shannon Zhao, qemu-arm, Wei Huang, QEMU Developers, wu.wubin,
kvmarm, Christoffer Dall
On 29 January 2017 at 11:53, Andrew Jones <drjones@redhat.com> wrote:
> On Mon, Jan 16, 2017 at 05:26:58PM +0800, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>> + memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
>> +
>> + id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
>> + id_regitsers[0].addr = (uintptr_t)&cpu->midr;
>> +
>> + id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
>> + id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
>> +
>
> We can condense this nicely with list initialization
>
> struct kvm_one_reg id_regitsers[] = {
> { ARM64_SYS_REG(ARM_CPU_ID_MIDR), (uintptr_t)&cpu->midr },
> { ARM64_SYS_REG(ARM_CPU_ID_REVIDR), (uintptr_t)&cpu->revidr },
> ...
> { 0, 0 }
"registers", please :-)
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU
@ 2017-01-29 20:42 ` Peter Maydell
0 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-01-29 20:42 UTC (permalink / raw)
To: Andrew Jones; +Cc: QEMU Developers, qemu-arm, kvmarm, wu.wubin
On 29 January 2017 at 11:53, Andrew Jones <drjones@redhat.com> wrote:
> On Mon, Jan 16, 2017 at 05:26:58PM +0800, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>> + memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg));
>> +
>> + id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR);
>> + id_regitsers[0].addr = (uintptr_t)&cpu->midr;
>> +
>> + id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR);
>> + id_regitsers[1].addr = (uintptr_t)&cpu->revidr;
>> +
>
> We can condense this nicely with list initialization
>
> struct kvm_one_reg id_regitsers[] = {
> { ARM64_SYS_REG(ARM_CPU_ID_MIDR), (uintptr_t)&cpu->midr },
> { ARM64_SYS_REG(ARM_CPU_ID_REVIDR), (uintptr_t)&cpu->revidr },
> ...
> { 0, 0 }
"registers", please :-)
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu
2017-01-16 9:26 ` Shannon Zhao
@ 2017-02-07 15:39 ` Peter Maydell
-1 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-02-07 15:39 UTC (permalink / raw)
To: Shannon Zhao
Cc: qemu-arm, QEMU Developers, Wei Huang, Andrew Jones,
Christoffer Dall, kvmarm, wu.wubin
On 16 January 2017 at 09:26, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add a generic type cpu, it's useful for migration when running on
> different hardwares.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 549cb1e..223f31e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> +static void aarch64_generic_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,armv8";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_V8_AES);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> + set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
> + cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
> + cpu->revidr = 0x00000000;
> + cpu->reset_fpsid = 0x41034070;
> + cpu->mvfr0 = 0x10110222;
> + cpu->mvfr1 = 0x12111111;
> + cpu->mvfr2 = 0x00000043;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->id_pfr0 = 0x00000131;
> + cpu->id_pfr1 = 0x00011011;
> + cpu->id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x10101105;
> + cpu->id_mmfr1 = 0x40000000;
> + cpu->id_mmfr2 = 0x01260000;
> + cpu->id_mmfr3 = 0x02102211;
> + cpu->id_isar0 = 0x02101110;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232042;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x00011142;
> + cpu->id_isar5 = 0x00011121;
> + cpu->id_aa64pfr0 = 0x00002222;
> + cpu->id_aa64dfr0 = 0x10305106;
> + cpu->id_aa64isar0 = 0x00011120;
> + cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
Not 64K as well? That seems rather limiting.
> + cpu->dbgdidr = 0x3516d000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
> + cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
> + cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> +}
What's the general principle behind the values we're using
here for the various ID and feature registers?
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH RFC 4/6] target: arm: Add a generic type cpu
@ 2017-02-07 15:39 ` Peter Maydell
0 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-02-07 15:39 UTC (permalink / raw)
To: Shannon Zhao; +Cc: QEMU Developers, qemu-arm, wu.wubin, kvmarm
On 16 January 2017 at 09:26, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add a generic type cpu, it's useful for migration when running on
> different hardwares.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 549cb1e..223f31e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> +static void aarch64_generic_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,armv8";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_V8_AES);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> + set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
> + cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */
> + cpu->revidr = 0x00000000;
> + cpu->reset_fpsid = 0x41034070;
> + cpu->mvfr0 = 0x10110222;
> + cpu->mvfr1 = 0x12111111;
> + cpu->mvfr2 = 0x00000043;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->id_pfr0 = 0x00000131;
> + cpu->id_pfr1 = 0x00011011;
> + cpu->id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x10101105;
> + cpu->id_mmfr1 = 0x40000000;
> + cpu->id_mmfr2 = 0x01260000;
> + cpu->id_mmfr3 = 0x02102211;
> + cpu->id_isar0 = 0x02101110;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232042;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x00011142;
> + cpu->id_isar5 = 0x00011121;
> + cpu->id_aa64pfr0 = 0x00002222;
> + cpu->id_aa64dfr0 = 0x10305106;
> + cpu->id_aa64isar0 = 0x00011120;
> + cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */
Not 64K as well? That seems rather limiting.
> + cpu->dbgdidr = 0x3516d000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */
> + cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */
> + cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> +}
What's the general principle behind the values we're using
here for the various ID and feature registers?
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
2017-01-16 9:26 ` Shannon Zhao
@ 2017-02-07 15:45 ` Peter Maydell
-1 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-02-07 15:45 UTC (permalink / raw)
To: Shannon Zhao
Cc: qemu-arm, QEMU Developers, Wei Huang, Andrew Jones,
Christoffer Dall, kvmarm, wu.wubin
On 16 January 2017 at 09:26, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patch set support use cross type vCPU when using KVM on ARM and add
> two new CPU types: generic and cortex-a72.
>
> You can test this patch set with QEMU using
> -cpu cortex-a53/cortex-a57/generic/cortex-a72
>
> These patches can be fetched from:
> https://git.linaro.org/people/shannon.zhao/qemu.git cross_vcpu_rfc
>
> You corresponding KVM patches can be fetched from:
> https://git.linaro.org/people/shannon.zhao/linux-mainline.git cross_vcpu_rfc
We should really document the "generic" option for -cpu somewhere
and what it means. Unfortunately I'm not entirely sure where
that should be :-( Suggestions welcomed but this isn't a blocker
for this series.
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support
@ 2017-02-07 15:45 ` Peter Maydell
0 siblings, 0 replies; 26+ messages in thread
From: Peter Maydell @ 2017-02-07 15:45 UTC (permalink / raw)
To: Shannon Zhao; +Cc: QEMU Developers, qemu-arm, wu.wubin, kvmarm
On 16 January 2017 at 09:26, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> This patch set support use cross type vCPU when using KVM on ARM and add
> two new CPU types: generic and cortex-a72.
>
> You can test this patch set with QEMU using
> -cpu cortex-a53/cortex-a57/generic/cortex-a72
>
> These patches can be fetched from:
> https://git.linaro.org/people/shannon.zhao/qemu.git cross_vcpu_rfc
>
> You corresponding KVM patches can be fetched from:
> https://git.linaro.org/people/shannon.zhao/linux-mainline.git cross_vcpu_rfc
We should really document the "generic" option for -cpu somewhere
and what it means. Unfortunately I'm not entirely sure where
that should be :-( Suggestions welcomed but this isn't a blocker
for this series.
thanks
-- PMM
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2017-02-07 15:45 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-16 9:26 [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support Shannon Zhao
2017-01-16 9:26 ` Shannon Zhao
2017-01-16 9:26 ` [Qemu-devel] [PATCH RFC 1/6] headers: update linux headers Shannon Zhao
2017-01-16 9:26 ` Shannon Zhao
2017-01-16 9:26 ` [Qemu-devel] [PATCH RFC 2/6] target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8 Shannon Zhao
2017-01-16 9:26 ` Shannon Zhao
2017-01-16 9:26 ` [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU Shannon Zhao
2017-01-16 9:26 ` Shannon Zhao
2017-01-29 11:53 ` [Qemu-devel] " Andrew Jones
2017-01-29 11:53 ` Andrew Jones
2017-01-29 20:42 ` Peter Maydell
2017-01-29 20:42 ` Peter Maydell
2017-01-16 9:26 ` [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu Shannon Zhao
2017-01-16 9:26 ` Shannon Zhao
2017-01-29 11:59 ` [Qemu-devel] " Andrew Jones
2017-01-29 11:59 ` Andrew Jones
2017-02-07 15:39 ` Peter Maydell
2017-02-07 15:39 ` Peter Maydell
2017-01-16 9:27 ` [Qemu-devel] [PATCH RFC 5/6] arm: virt: Enable generic type CPU in virt machine Shannon Zhao
2017-01-16 9:27 ` Shannon Zhao
2017-01-16 9:27 ` [Qemu-devel] [PATCH RFC 6/6] target-arm: cpu64: Add support for Cortex-A72 Shannon Zhao
2017-01-16 9:27 ` Shannon Zhao
2017-01-16 9:42 ` [Qemu-devel] [PATCH RFC 0/6] target-arm: KVM64: Cross type vCPU support no-reply
2017-01-16 9:42 ` no-reply
2017-02-07 15:45 ` [Qemu-devel] " Peter Maydell
2017-02-07 15:45 ` Peter Maydell
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