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From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: wei.liu2@citrix.com, konrad.wilk@oracle.com,
	andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
	he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
	Yi Sun <yi.y.sun@linux.intel.com>,
	mengxu@cis.upenn.edu, jbeulich@suse.com,
	chao.p.peng@linux.intel.com
Subject: [PATCH v5 23/24] tools: L2 CAT: support set cbm for L2 CAT.
Date: Wed, 18 Jan 2017 10:02:46 +0800	[thread overview]
Message-ID: <1484704967-5609-24-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1484704967-5609-1-git-send-email-yi.y.sun@linux.intel.com>

This patch implements the xl/xc changes to support set CBM
for L2 CAT.

The new level option is introduced to original CAT setting
command in order to set CBM for specified level CAT.
- 'xl psr-cat-cbm-set' is updated to set cache capacity
  bitmasks(CBM) for a domain according to input cache level.

root@:~$ xl psr-cat-cbm-set -l2 1 0x7f

root@:~$ xl psr-cat-show -l2 1
Socket ID       : 0
Default CBM     : 0xff
   ID                     NAME             CBM
    1                 ubuntu14            0x7f

Signed-off-by: He Chen <he.chen@linux.intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
 tools/libxc/xc_psr.c      |  3 +++
 tools/libxl/xl_cmdimpl.c  | 31 ++++++++++++++++++++-----------
 tools/libxl/xl_cmdtable.c |  1 +
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index f0aed2d..67556bb 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -266,6 +266,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
     case XC_PSR_CAT_L3_CBM_DATA:
         cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA;
         break;
+    case XC_PSR_CAT_L2_CBM:
+        cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
+        break;
     default:
         errno = EINVAL;
         return -1;
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index cdcee5f..a32438c 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -9523,19 +9523,21 @@ int main_psr_cat_cbm_set(int argc, char **argv)
     char *value;
     libxl_string_list socket_list;
     unsigned long start, end;
-    int i, j, len;
+    unsigned int i, j, len;
+    unsigned int lvl = 3;
 
     static struct option opts[] = {
         {"socket", 1, 0, 's'},
         {"data", 0, 0, 'd'},
         {"code", 0, 0, 'c'},
+        {"level", 1, 0, 'l'},
         COMMON_LONG_OPTS
     };
 
     libxl_socket_bitmap_alloc(ctx, &target_map, 0);
     libxl_bitmap_set_none(&target_map);
 
-    SWITCH_FOREACH_OPT(opt, "s:cd", opts, "psr-cat-cbm-set", 2) {
+    SWITCH_FOREACH_OPT(opt, "s:l:cd", opts, "psr-cat-cbm-set", 2) {
     case 's':
         trim(isspace, optarg, &value);
         split_string_into_string_list(value, ",", &socket_list);
@@ -9555,17 +9557,24 @@ int main_psr_cat_cbm_set(int argc, char **argv)
     case 'c':
         opt_code = 1;
         break;
+    case 'l':
+        lvl = atoi(optarg);
+        break;
     }
 
-    if (opt_data && opt_code) {
-        fprintf(stderr, "Cannot handle -c and -d at the same time\n");
-        return -1;
-    } else if (opt_data) {
-        type = LIBXL_PSR_CBM_TYPE_L3_CBM_DATA;
-    } else if (opt_code) {
-        type = LIBXL_PSR_CBM_TYPE_L3_CBM_CODE;
-    } else {
-        type = LIBXL_PSR_CBM_TYPE_L3_CBM;
+    if (lvl == 2)
+        type = LIBXL_PSR_CBM_TYPE_L2_CBM;
+    else if (lvl == 3) {
+        if (opt_data && opt_code) {
+            fprintf(stderr, "Cannot handle -c and -d at the same time\n");
+            return ERROR_FAIL;
+        } else if (opt_data) {
+            type = LIBXL_PSR_CBM_TYPE_L3_CBM_DATA;
+        } else if (opt_code) {
+            type = LIBXL_PSR_CBM_TYPE_L3_CBM_CODE;
+        } else {
+            type = LIBXL_PSR_CBM_TYPE_L3_CBM;
+        }
     }
 
     if (libxl_bitmap_is_empty(&target_map))
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index c5fbad4..32c3ee5 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -550,6 +550,7 @@ struct cmd_spec cmd_table[] = {
       "Set cache capacity bitmasks(CBM) for a domain",
       "[options] <Domain> <CBM>",
       "-s <socket>       Specify the socket to process, otherwise all sockets are processed\n"
+      "-l <level>        Specify the cache level to process, otherwise L3 cache is processed\n"
       "-c                Set code CBM if CDP is supported\n"
       "-d                Set data CBM if CDP is supported\n"
     },
-- 
1.9.1


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  parent reply	other threads:[~2017-01-18  2:04 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-18  2:02 [PATCH v5 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-01-18  2:02 ` [PATCH v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document Yi Sun
2017-01-18  9:11   ` Dario Faggioli
2017-01-18  9:37     ` Yi Sun
2017-01-19  6:11     ` Yi Sun
2017-01-18  2:02 ` [PATCH v5 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-01-18  2:02 ` [PATCH v5 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-01-18  2:02 ` [PATCH v5 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-01-18  2:02 ` [PATCH v5 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-01-18  2:02 ` [PATCH v5 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-01-18  2:02 ` [PATCH v5 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-01-18  2:02 ` [PATCH v5 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-01-18  2:02 ` [PATCH v5 15/24] x86: refactor psr: implement get value " Yi Sun
2017-01-18  2:02 ` [PATCH v5 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-01-18  2:02 ` [PATCH v5 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-01-18  2:02 ` [PATCH v5 20/24] x86: L2 CAT: implement set " Yi Sun
2017-01-18  2:02 ` [PATCH v5 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-01-18  8:33   ` Dario Faggioli
2017-01-18  2:02 ` [PATCH v5 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-01-18  2:02 ` Yi Sun [this message]
2017-01-18  8:51   ` [PATCH v5 23/24] tools: L2 CAT: support set " Dario Faggioli
2017-01-18  2:02 ` [PATCH v5 24/24] docs: add L2 CAT description in docs Yi Sun

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