* [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround
@ 2017-01-12 11:47 Ander Conselvan de Oliveira
2017-01-12 11:47 ` [PATCH 2/3] drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 Ander Conselvan de Oliveira
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-01-12 11:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The workaround added in commit d965e7ac7a19 ("drm/i915/bxt: backlight
clock gating workaround") is listed in the workaround database with the
name WaDisablePWMClockGating, pointing to the same hsd as the nameless
entry in the display workarounds bspec page.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 249623d..148cd1e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -96,7 +96,8 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/*
- * Wa: Backlight PWM may stop in the asserted state, causing backlight
+ * WaDisablePWMClockGating:bxt
+ * Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
--
2.5.5
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/3] drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira @ 2017-01-12 11:47 ` Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too Ander Conselvan de Oliveira ` (3 subsequent siblings) 4 siblings, 0 replies; 14+ messages in thread From: Ander Conselvan de Oliveira @ 2017-01-12 11:47 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira The workaround WaSetHdcUnitClockGatingDisableInUcgctl6 applies only until BXT B0 according to bspec. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 148cd1e..b257343 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -89,11 +89,13 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* + * WaSetHdcUnitClockGatingDisableInUcgctl6:bxt * FIXME: * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. */ - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | - GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) + I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | + GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); /* * WaDisablePWMClockGating:bxt -- 2.5.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 2/3] drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 Ander Conselvan de Oliveira @ 2017-01-12 11:47 ` Ander Conselvan de Oliveira 2017-01-20 16:04 ` Rodrigo Vivi 2017-01-24 12:39 ` David Weinehall 2017-01-12 15:53 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Patchwork ` (2 subsequent siblings) 4 siblings, 2 replies; 14+ messages in thread From: Ander Conselvan de Oliveira @ 2017-01-12 11:47 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira Apply workarounds to Geminilake, and annoatate those that are applied uncondionally when they apply to GLK based on the workaround database. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- 5 files changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0ed99adf..7024144 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2167,14 +2167,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ if (IS_BROADWELL(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); else if (IS_SKYLAKE(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); - else if (IS_BROXTON(dev_priv)) + else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index db714dc..7bb3d0a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1126,13 +1126,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); if (ret < 0) return ret; index = ret; - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( @@ -1156,7 +1156,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, 0); } - /* WaMediaPoolStateCmdInWABB:bxt */ + /* WaMediaPoolStateCmdInWABB:bxt,glk */ if (HAS_POOLED_EU(engine->i915)) { /* * EU pool configuration is setup along with golden context diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index c787fc4..9c67534 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, "Platform that should have a MOCS table does not.\n"); } - /* WaDisableSkipCaching:skl,bxt,kbl */ + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ if (IS_GEN9(dev_priv)) { int i; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b257343..c8ebf1d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); - /* WaEnableChickenDCPR:skl,bxt,kbl */ + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ - /* WaFbcWakeMemOn:skl,bxt,kbl */ + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE); @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) PWM1_GATING_DIS | PWM2_GATING_DIS); } +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen9_init_clock_gating(dev_priv); + + /* + * WaDisablePWMClockGating:glk + * Backlight PWM may stop in the asserted state, causing backlight + * to stay fully on. + */ + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | + PWM1_GATING_DIS | PWM2_GATING_DIS); +} + static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl + * WaWmMemoryReadLatency:skl,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = skylake_init_clock_gating; else if (IS_KABYLAKE(dev_priv)) dev_priv->display.init_clock_gating = kabylake_init_clock_gating; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_BROXTON(dev_priv)) dev_priv->display.init_clock_gating = bxt_init_clock_gating; + else if (IS_GEMINILAKE(dev_priv)) + dev_priv->display.init_clock_gating = glk_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = broadwell_init_clock_gating; else if (IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ab83fc2..e17f339 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int ret; - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | ECOCHK_DIS_TLB); - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_GPGPU_PREEMPTION); - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ /* WaDisablePartialResolveInVc:skl,bxt,kbl */ WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); /* WaOCLCoherentLineFlush:skl,bxt,kbl */ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); if (ret) return ret; @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); if (ret) return ret; @@ -1128,6 +1128,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) return 0; } +static int glk_init_workarounds(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + int ret; + + ret = gen9_init_workarounds(engine); + if (ret) + return ret; + + /* WaToEnableHwFixForPushConstHWBug:glk */ + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); + + return 0; +} + int init_workarounds_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1152,6 +1168,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) if (IS_KABYLAKE(dev_priv)) return kbl_init_workarounds(engine); + if (IS_GEMINILAKE(dev_priv)) + return glk_init_workarounds(engine); + return 0; } -- 2.5.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-12 11:47 ` [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too Ander Conselvan de Oliveira @ 2017-01-20 16:04 ` Rodrigo Vivi 2017-01-23 7:49 ` Ander Conselvan De Oliveira 2017-01-24 12:39 ` David Weinehall 1 sibling, 1 reply; 14+ messages in thread From: Rodrigo Vivi @ 2017-01-20 16:04 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx On Thu, Jan 12, 2017 at 3:47 AM, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote: > Apply workarounds to Geminilake, and annoatate those that are applied > uncondionally when they apply to GLK based on the workaround database. > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- > 5 files changed, 53 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 0ed99adf..7024144 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2167,14 +2167,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > * called on driver load and after a GPU reset, so you can place > * workarounds here even if they get overwritten by GPU reset. > */ > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ > if (IS_BROADWELL(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > else if (IS_SKYLAKE(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > - else if (IS_BROXTON(dev_priv)) > + else if (IS_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > } > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index db714dc..7bb3d0a 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1126,13 +1126,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) > wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); > > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); > if (ret < 0) > return ret; > index = ret; > > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > @@ -1156,7 +1156,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > wa_ctx_emit(batch, index, 0); > } > > - /* WaMediaPoolStateCmdInWABB:bxt */ > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ > if (HAS_POOLED_EU(engine->i915)) { > /* > * EU pool configuration is setup along with golden context > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index c787fc4..9c67534 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > "Platform that should have a MOCS table does not.\n"); > } > > - /* WaDisableSkipCaching:skl,bxt,kbl */ > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > if (IS_GEN9(dev_priv)) { > int i; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b257343..c8ebf1d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(GEN8_CONFIG0, > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > - /* WaEnableChickenDCPR:skl,bxt,kbl */ > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > I915_WRITE(GEN8_CHICKEN_DCPR_1, > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > - /* WaFbcWakeMemOn:skl,bxt,kbl */ > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS | > DISP_FBC_MEMORY_WAKE); > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) > PWM1_GATING_DIS | PWM2_GATING_DIS); > } > > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > +{ > + gen9_init_clock_gating(dev_priv); > + > + /* > + * WaDisablePWMClockGating:glk > + * Backlight PWM may stop in the asserted state, causing backlight > + * to stay fully on. > + */ > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > + PWM1_GATING_DIS | PWM2_GATING_DIS); > +} > + > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > { > u32 tmp; > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, > } > > /* > - * WaWmMemoryReadLatency:skl > + * WaWmMemoryReadLatency:skl,glk > * > * punit doesn't take into account the read latency so we need > * to add 2us to the various latency levels we retrieve from the > @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = skylake_init_clock_gating; > else if (IS_KABYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = kabylake_init_clock_gating; > - else if (IS_GEN9_LP(dev_priv)) > + else if (IS_BROXTON(dev_priv)) > dev_priv->display.init_clock_gating = bxt_init_clock_gating; > + else if (IS_GEMINILAKE(dev_priv)) > + dev_priv->display.init_clock_gating = glk_init_clock_gating; > else if (IS_BROADWELL(dev_priv)) > dev_priv->display.init_clock_gating = broadwell_init_clock_gating; > else if (IS_CHERRYVIEW(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index ab83fc2..e17f339 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > struct drm_i915_private *dev_priv = engine->i915; > int ret; > > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > ECOCHK_DIS_TLB); > > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > FLOW_CONTROL_ENABLE | > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, > GEN9_ENABLE_GPGPU_PREEMPTION); > > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); > > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > GEN9_CCS_TLB_PREFETCH_ENABLE); > > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > GEN8_SAMPLER_POWER_BYPASS_DIS); > > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > if (ret) > return ret; > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > if (ret) > return ret; > @@ -1128,6 +1128,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) > return 0; > } > > +static int glk_init_workarounds(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *dev_priv = engine->i915; > + int ret; > + > + ret = gen9_init_workarounds(engine); > + if (ret) > + return ret; > + > + /* WaToEnableHwFixForPushConstHWBug:glk */ My first thought on this was wondering if we should have that for KBL and BXT... but then I noticed it is only up to C0 there while here is forever.... > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); But also how did you come up with these bit? Resolution I see there tells to reset some counter with invalidate or something like inserting 2 zero length push PS at some update... not sure, but noting that pointed me to this bit here.. > + > + return 0; > +} > + > int init_workarounds_ring(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > @@ -1152,6 +1168,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) > if (IS_KABYLAKE(dev_priv)) > return kbl_init_workarounds(engine); > > + if (IS_GEMINILAKE(dev_priv)) > + return glk_init_workarounds(engine); > + > return 0; > } > > -- > 2.5.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-20 16:04 ` Rodrigo Vivi @ 2017-01-23 7:49 ` Ander Conselvan De Oliveira 2017-01-23 9:19 ` Matthew Auld 0 siblings, 1 reply; 14+ messages in thread From: Ander Conselvan De Oliveira @ 2017-01-23 7:49 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Auld, Matthew On Fri, 2017-01-20 at 08:04 -0800, Rodrigo Vivi wrote: > On Thu, Jan 12, 2017 at 3:47 AM, Ander Conselvan de Oliveira > <ander.conselvan.de.oliveira@intel.com> wrote: > > > > Apply workarounds to Geminilake, and annoatate those that are applied > > uncondionally when they apply to GLK based on the workaround database. > > > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte > > l.com> > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- > > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++----- > > --- > > 5 files changed, 53 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 0ed99adf..7024144 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -2167,14 +2167,14 @@ static void gtt_write_workarounds(struct > > drm_i915_private *dev_priv) > > * called on driver load and after a GPU reset, so you can place > > * workarounds here even if they get overwritten by GPU reset. > > */ > > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ > > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ > > if (IS_BROADWELL(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > > else if (IS_CHERRYVIEW(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > > else if (IS_SKYLAKE(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > > - else if (IS_BROXTON(dev_priv)) > > + else if (IS_GEN9_LP(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > > } > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > > b/drivers/gpu/drm/i915/intel_lrc.c > > index db714dc..7bb3d0a 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1126,13 +1126,13 @@ static int gen9_init_indirectctx_bb(struct > > intel_engine_cs *engine, > > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) > > wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); > > > > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ > > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ > > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); > > if (ret < 0) > > return ret; > > index = ret; > > > > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ > > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > > @@ -1156,7 +1156,7 @@ static int gen9_init_indirectctx_bb(struct > > intel_engine_cs *engine, > > wa_ctx_emit(batch, index, 0); > > } > > > > - /* WaMediaPoolStateCmdInWABB:bxt */ > > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ > > if (HAS_POOLED_EU(engine->i915)) { > > /* > > * EU pool configuration is setup along with golden context > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c > > b/drivers/gpu/drm/i915/intel_mocs.c > > index c787fc4..9c67534 100644 > > --- a/drivers/gpu/drm/i915/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/intel_mocs.c > > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private > > *dev_priv, > > "Platform that should have a MOCS table does > > not.\n"); > > } > > > > - /* WaDisableSkipCaching:skl,bxt,kbl */ > > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > > if (IS_GEN9(dev_priv)) { > > int i; > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index b257343..c8ebf1d 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct > > drm_i915_private *dev_priv) > > I915_WRITE(GEN8_CONFIG0, > > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > > > - /* WaEnableChickenDCPR:skl,bxt,kbl */ > > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > > I915_WRITE(GEN8_CHICKEN_DCPR_1, > > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > > > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > > - /* WaFbcWakeMemOn:skl,bxt,kbl */ > > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > > DISP_FBC_WM_DIS | > > DISP_FBC_MEMORY_WAKE); > > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct > > drm_i915_private *dev_priv) > > PWM1_GATING_DIS | PWM2_GATING_DIS); > > } > > > > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > > +{ > > + gen9_init_clock_gating(dev_priv); > > + > > + /* > > + * WaDisablePWMClockGating:glk > > + * Backlight PWM may stop in the asserted state, causing backlight > > + * to stay fully on. > > + */ > > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > > + PWM1_GATING_DIS | PWM2_GATING_DIS); > > +} > > + > > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > > { > > u32 tmp; > > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct > > drm_i915_private *dev_priv, > > } > > > > /* > > - * WaWmMemoryReadLatency:skl > > + * WaWmMemoryReadLatency:skl,glk > > * > > * punit doesn't take into account the read latency so we > > need > > * to add 2us to the various latency levels we retrieve from > > the > > @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct > > drm_i915_private *dev_priv) > > dev_priv->display.init_clock_gating = > > skylake_init_clock_gating; > > else if (IS_KABYLAKE(dev_priv)) > > dev_priv->display.init_clock_gating = > > kabylake_init_clock_gating; > > - else if (IS_GEN9_LP(dev_priv)) > > + else if (IS_BROXTON(dev_priv)) > > dev_priv->display.init_clock_gating = bxt_init_clock_gating; > > + else if (IS_GEMINILAKE(dev_priv)) > > + dev_priv->display.init_clock_gating = glk_init_clock_gating; > > else if (IS_BROADWELL(dev_priv)) > > dev_priv->display.init_clock_gating = > > broadwell_init_clock_gating; > > else if (IS_CHERRYVIEW(dev_priv)) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index ab83fc2..e17f339 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > struct drm_i915_private *dev_priv = engine->i915; > > int ret; > > > > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ > > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, > > _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > > > > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ > > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ > > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > > > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs > > *engine) > > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > > ECOCHK_DIS_TLB); > > > > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ > > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ > > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ > > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ > > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > > FLOW_CONTROL_ENABLE | > > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, > > GEN9_ENABLE_GPGPU_PREEMPTION); > > > > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ > > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ > > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ > > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | > > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE) > > ); > > > > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ > > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > > GEN9_CCS_TLB_PREFETCH_ENABLE); > > > > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > > GEN8_SAMPLER_POWER_BYPASS_DIS); > > > > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ > > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > > > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ > > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > > > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ > > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > > if (ret) > > return ret; > > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs > > *engine) > > if (ret) > > return ret; > > > > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ > > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ > > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > > if (ret) > > return ret; > > @@ -1128,6 +1128,22 @@ static int kbl_init_workarounds(struct > > intel_engine_cs *engine) > > return 0; > > } > > > > +static int glk_init_workarounds(struct intel_engine_cs *engine) > > +{ > > + struct drm_i915_private *dev_priv = engine->i915; > > + int ret; > > + > > + ret = gen9_init_workarounds(engine); > > + if (ret) > > + return ret; > > + > > + /* WaToEnableHwFixForPushConstHWBug:glk */ > My first thought on this was wondering if we should have that for KBL and > BXT... > but then I noticed it is only up to C0 there while here is forever.... > > > > > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > But also how did you come up with these bit? > Resolution I see there tells to reset some counter with invalidate > or something like inserting 2 zero length push PS at some update... > not sure, but noting that pointed me to this bit here.. If I understood correctly, WaInsertDummyPushConstPs is the dummy push workaround. That is fixed in GKL, BXT C0 and KBL C0, but requires this bit to enable the fix. Enabling the fix is called WaToEnableHwFixForPushConstHWBug. Is this correct Matthew? Thanks, Ander > > + > > + return 0; > > +} > > + > > int init_workarounds_ring(struct intel_engine_cs *engine) > > { > > struct drm_i915_private *dev_priv = engine->i915; > > @@ -1152,6 +1168,9 @@ int init_workarounds_ring(struct intel_engine_cs > > *engine) > > if (IS_KABYLAKE(dev_priv)) > > return kbl_init_workarounds(engine); > > > > + if (IS_GEMINILAKE(dev_priv)) > > + return glk_init_workarounds(engine); > > + > > return 0; > > } > > > > -- > > 2.5.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-23 7:49 ` Ander Conselvan De Oliveira @ 2017-01-23 9:19 ` Matthew Auld 0 siblings, 0 replies; 14+ messages in thread From: Matthew Auld @ 2017-01-23 9:19 UTC (permalink / raw) To: Ander Conselvan De Oliveira; +Cc: intel-gfx, Auld, Matthew On 23 January 2017 at 07:49, Ander Conselvan De Oliveira <conselvan2@gmail.com> wrote: > On Fri, 2017-01-20 at 08:04 -0800, Rodrigo Vivi wrote: >> On Thu, Jan 12, 2017 at 3:47 AM, Ander Conselvan de Oliveira >> <ander.conselvan.de.oliveira@intel.com> wrote: >> > >> > Apply workarounds to Geminilake, and annoatate those that are applied >> > uncondionally when they apply to GLK based on the workaround database. >> > >> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte >> > l.com> >> > --- >> > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- >> > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- >> > drivers/gpu/drm/i915/intel_mocs.c | 2 +- >> > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- >> > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++----- >> > --- >> > 5 files changed, 53 insertions(+), 19 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c >> > b/drivers/gpu/drm/i915/i915_gem_gtt.c >> > index 0ed99adf..7024144 100644 >> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c >> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c >> > @@ -2167,14 +2167,14 @@ static void gtt_write_workarounds(struct >> > drm_i915_private *dev_priv) >> > * called on driver load and after a GPU reset, so you can place >> > * workarounds here even if they get overwritten by GPU reset. >> > */ >> > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ >> > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ >> > if (IS_BROADWELL(dev_priv)) >> > I915_WRITE(GEN8_L3_LRA_1_GPGPU, >> > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); >> > else if (IS_CHERRYVIEW(dev_priv)) >> > I915_WRITE(GEN8_L3_LRA_1_GPGPU, >> > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); >> > else if (IS_SKYLAKE(dev_priv)) >> > I915_WRITE(GEN8_L3_LRA_1_GPGPU, >> > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); >> > - else if (IS_BROXTON(dev_priv)) >> > + else if (IS_GEN9_LP(dev_priv)) >> > I915_WRITE(GEN8_L3_LRA_1_GPGPU, >> > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); >> > } >> > >> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c >> > b/drivers/gpu/drm/i915/intel_lrc.c >> > index db714dc..7bb3d0a 100644 >> > --- a/drivers/gpu/drm/i915/intel_lrc.c >> > +++ b/drivers/gpu/drm/i915/intel_lrc.c >> > @@ -1126,13 +1126,13 @@ static int gen9_init_indirectctx_bb(struct >> > intel_engine_cs *engine, >> > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) >> > wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); >> > >> > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ >> > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ >> > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); >> > if (ret < 0) >> > return ret; >> > index = ret; >> > >> > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ >> > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ >> > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); >> > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); >> > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( >> > @@ -1156,7 +1156,7 @@ static int gen9_init_indirectctx_bb(struct >> > intel_engine_cs *engine, >> > wa_ctx_emit(batch, index, 0); >> > } >> > >> > - /* WaMediaPoolStateCmdInWABB:bxt */ >> > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ >> > if (HAS_POOLED_EU(engine->i915)) { >> > /* >> > * EU pool configuration is setup along with golden context >> > diff --git a/drivers/gpu/drm/i915/intel_mocs.c >> > b/drivers/gpu/drm/i915/intel_mocs.c >> > index c787fc4..9c67534 100644 >> > --- a/drivers/gpu/drm/i915/intel_mocs.c >> > +++ b/drivers/gpu/drm/i915/intel_mocs.c >> > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private >> > *dev_priv, >> > "Platform that should have a MOCS table does >> > not.\n"); >> > } >> > >> > - /* WaDisableSkipCaching:skl,bxt,kbl */ >> > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ >> > if (IS_GEN9(dev_priv)) { >> > int i; >> > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c >> > b/drivers/gpu/drm/i915/intel_pm.c >> > index b257343..c8ebf1d 100644 >> > --- a/drivers/gpu/drm/i915/intel_pm.c >> > +++ b/drivers/gpu/drm/i915/intel_pm.c >> > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct >> > drm_i915_private *dev_priv) >> > I915_WRITE(GEN8_CONFIG0, >> > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); >> > >> > - /* WaEnableChickenDCPR:skl,bxt,kbl */ >> > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ >> > I915_WRITE(GEN8_CHICKEN_DCPR_1, >> > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); >> > >> > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ >> > - /* WaFbcWakeMemOn:skl,bxt,kbl */ >> > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ >> > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | >> > DISP_FBC_WM_DIS | >> > DISP_FBC_MEMORY_WAKE); >> > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct >> > drm_i915_private *dev_priv) >> > PWM1_GATING_DIS | PWM2_GATING_DIS); >> > } >> > >> > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) >> > +{ >> > + gen9_init_clock_gating(dev_priv); >> > + >> > + /* >> > + * WaDisablePWMClockGating:glk >> > + * Backlight PWM may stop in the asserted state, causing backlight >> > + * to stay fully on. >> > + */ >> > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | >> > + PWM1_GATING_DIS | PWM2_GATING_DIS); >> > +} >> > + >> > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) >> > { >> > u32 tmp; >> > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct >> > drm_i915_private *dev_priv, >> > } >> > >> > /* >> > - * WaWmMemoryReadLatency:skl >> > + * WaWmMemoryReadLatency:skl,glk >> > * >> > * punit doesn't take into account the read latency so we >> > need >> > * to add 2us to the various latency levels we retrieve from >> > the >> > @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct >> > drm_i915_private *dev_priv) >> > dev_priv->display.init_clock_gating = >> > skylake_init_clock_gating; >> > else if (IS_KABYLAKE(dev_priv)) >> > dev_priv->display.init_clock_gating = >> > kabylake_init_clock_gating; >> > - else if (IS_GEN9_LP(dev_priv)) >> > + else if (IS_BROXTON(dev_priv)) >> > dev_priv->display.init_clock_gating = bxt_init_clock_gating; >> > + else if (IS_GEMINILAKE(dev_priv)) >> > + dev_priv->display.init_clock_gating = glk_init_clock_gating; >> > else if (IS_BROADWELL(dev_priv)) >> > dev_priv->display.init_clock_gating = >> > broadwell_init_clock_gating; >> > else if (IS_CHERRYVIEW(dev_priv)) >> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c >> > b/drivers/gpu/drm/i915/intel_ringbuffer.c >> > index ab83fc2..e17f339 100644 >> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct >> > intel_engine_cs *engine) >> > struct drm_i915_private *dev_priv = engine->i915; >> > int ret; >> > >> > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ >> > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ >> > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, >> > _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); >> > >> > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ >> > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ >> > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | >> > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); >> > >> > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs >> > *engine) >> > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | >> > ECOCHK_DIS_TLB); >> > >> > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ >> > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ >> > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ >> > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ >> > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, >> > FLOW_CONTROL_ENABLE | >> > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); >> > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct >> > intel_engine_cs *engine) >> > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, >> > GEN9_ENABLE_GPGPU_PREEMPTION); >> > >> > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ >> > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ >> > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ >> > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | >> > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE) >> > ); >> > >> > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ >> > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ >> > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, >> > GEN9_CCS_TLB_PREFETCH_ENABLE); >> > >> > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct >> > intel_engine_cs *engine) >> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, >> > GEN8_SAMPLER_POWER_BYPASS_DIS); >> > >> > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ >> > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ >> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); >> > >> > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ >> > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | >> > GEN8_LQSC_FLUSH_COHERENT_LINES)); >> > >> > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ >> > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ >> > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); >> > if (ret) >> > return ret; >> > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs >> > *engine) >> > if (ret) >> > return ret; >> > >> > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ >> > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ >> > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); >> > if (ret) >> > return ret; >> > @@ -1128,6 +1128,22 @@ static int kbl_init_workarounds(struct >> > intel_engine_cs *engine) >> > return 0; >> > } >> > >> > +static int glk_init_workarounds(struct intel_engine_cs *engine) >> > +{ >> > + struct drm_i915_private *dev_priv = engine->i915; >> > + int ret; >> > + >> > + ret = gen9_init_workarounds(engine); >> > + if (ret) >> > + return ret; >> > + >> > + /* WaToEnableHwFixForPushConstHWBug:glk */ >> My first thought on this was wondering if we should have that for KBL and >> BXT... >> but then I noticed it is only up to C0 there while here is forever.... >> >> > >> > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, >> > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); >> But also how did you come up with these bit? >> Resolution I see there tells to reset some counter with invalidate >> or something like inserting 2 zero length push PS at some update... >> not sure, but noting that pointed me to this bit here.. > > If I understood correctly, WaInsertDummyPushConstPs is the dummy push > workaround. That is fixed in GKL, BXT C0 and KBL C0, but requires this bit to > enable the fix. Enabling the fix is called WaToEnableHwFixForPushConstHWBug. > > Is this correct Matthew? Yes, that's how I understood it. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-12 11:47 ` [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too Ander Conselvan de Oliveira 2017-01-20 16:04 ` Rodrigo Vivi @ 2017-01-24 12:39 ` David Weinehall 2017-01-26 8:57 ` [PATCH v2] " Ander Conselvan de Oliveira 1 sibling, 1 reply; 14+ messages in thread From: David Weinehall @ 2017-01-24 12:39 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx On Thu, Jan 12, 2017 at 01:47:37PM +0200, Ander Conselvan de Oliveira wrote: > Apply workarounds to Geminilake, and annoatate those that are applied annotate > uncondionally when they apply to GLK based on the workaround database. unconditionally > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- > 5 files changed, 53 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 0ed99adf..7024144 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2167,14 +2167,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > * called on driver load and after a GPU reset, so you can place > * workarounds here even if they get overwritten by GPU reset. > */ > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ > if (IS_BROADWELL(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > else if (IS_SKYLAKE(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > - else if (IS_BROXTON(dev_priv)) > + else if (IS_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > } > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index db714dc..7bb3d0a 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1126,13 +1126,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) > wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); > > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); > if (ret < 0) > return ret; > index = ret; > > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > @@ -1156,7 +1156,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > wa_ctx_emit(batch, index, 0); > } > > - /* WaMediaPoolStateCmdInWABB:bxt */ > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ > if (HAS_POOLED_EU(engine->i915)) { > /* > * EU pool configuration is setup along with golden context > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index c787fc4..9c67534 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > "Platform that should have a MOCS table does not.\n"); > } > > - /* WaDisableSkipCaching:skl,bxt,kbl */ > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > if (IS_GEN9(dev_priv)) { > int i; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b257343..c8ebf1d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(GEN8_CONFIG0, > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > - /* WaEnableChickenDCPR:skl,bxt,kbl */ > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > I915_WRITE(GEN8_CHICKEN_DCPR_1, > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > - /* WaFbcWakeMemOn:skl,bxt,kbl */ > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS | > DISP_FBC_MEMORY_WAKE); > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) > PWM1_GATING_DIS | PWM2_GATING_DIS); > } > > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > +{ > + gen9_init_clock_gating(dev_priv); > + > + /* > + * WaDisablePWMClockGating:glk > + * Backlight PWM may stop in the asserted state, causing backlight > + * to stay fully on. > + */ > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > + PWM1_GATING_DIS | PWM2_GATING_DIS); > +} > + > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > { > u32 tmp; > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, > } > > /* > - * WaWmMemoryReadLatency:skl > + * WaWmMemoryReadLatency:skl,glk > * > * punit doesn't take into account the read latency so we need > * to add 2us to the various latency levels we retrieve from the > @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = skylake_init_clock_gating; > else if (IS_KABYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = kabylake_init_clock_gating; > - else if (IS_GEN9_LP(dev_priv)) > + else if (IS_BROXTON(dev_priv)) > dev_priv->display.init_clock_gating = bxt_init_clock_gating; > + else if (IS_GEMINILAKE(dev_priv)) > + dev_priv->display.init_clock_gating = glk_init_clock_gating; > else if (IS_BROADWELL(dev_priv)) > dev_priv->display.init_clock_gating = broadwell_init_clock_gating; > else if (IS_CHERRYVIEW(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index ab83fc2..e17f339 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > struct drm_i915_private *dev_priv = engine->i915; > int ret; > > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > ECOCHK_DIS_TLB); > > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > FLOW_CONTROL_ENABLE | > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, > GEN9_ENABLE_GPGPU_PREEMPTION); > > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); > > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > GEN9_CCS_TLB_PREFETCH_ENABLE); > > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > GEN8_SAMPLER_POWER_BYPASS_DIS); > > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > if (ret) > return ret; > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > if (ret) > return ret; > @@ -1128,6 +1128,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) > return 0; > } > > +static int glk_init_workarounds(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *dev_priv = engine->i915; > + int ret; > + > + ret = gen9_init_workarounds(engine); > + if (ret) > + return ret; > + > + /* WaToEnableHwFixForPushConstHWBug:glk */ > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > + > + return 0; > +} > + > int init_workarounds_ring(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > @@ -1152,6 +1168,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) > if (IS_KABYLAKE(dev_priv)) > return kbl_init_workarounds(engine); > > + if (IS_GEMINILAKE(dev_priv)) > + return glk_init_workarounds(engine); > + > return 0; > } > > -- > 2.5.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-24 12:39 ` David Weinehall @ 2017-01-26 8:57 ` Ander Conselvan de Oliveira 2017-01-26 9:16 ` [PATCH v3] " Ander Conselvan de Oliveira 0 siblings, 1 reply; 14+ messages in thread From: Ander Conselvan de Oliveira @ 2017-01-26 8:57 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira Apply workarounds to Geminilake, and annotate those that are applied unconditionally when they apply to GLK based on the workaround database. v2: Fix commit message typos. (David) Cc: David Weinehall <david.weinehall@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- 5 files changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index e808aad..bf1e79b 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2184,14 +2184,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,glk */ if (IS_BROADWELL(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); else if (IS_SKYLAKE(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); - else if (IS_BROXTON(dev_priv)) + else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 32096d1..1ec293e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1102,13 +1102,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, struct drm_i915_private *dev_priv = engine->i915; uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); if (ret < 0) return ret; index = ret; - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( @@ -1132,7 +1132,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, 0); } - /* WaMediaPoolStateCmdInWABB:bxt */ + /* WaMediaPoolStateCmdInWABB:bxt,glk */ if (HAS_POOLED_EU(engine->i915)) { /* * EU pool configuration is setup along with golden context diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index c787fc4..9c67534 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, "Platform that should have a MOCS table does not.\n"); } - /* WaDisableSkipCaching:skl,bxt,kbl */ + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ if (IS_GEN9(dev_priv)) { int i; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b257343..c8ebf1d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); - /* WaEnableChickenDCPR:skl,bxt,kbl */ + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ - /* WaFbcWakeMemOn:skl,bxt,kbl */ + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE); @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) PWM1_GATING_DIS | PWM2_GATING_DIS); } +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen9_init_clock_gating(dev_priv); + + /* + * WaDisablePWMClockGating:glk + * Backlight PWM may stop in the asserted state, causing backlight + * to stay fully on. + */ + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | + PWM1_GATING_DIS | PWM2_GATING_DIS); +} + static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl + * WaWmMemoryReadLatency:skl,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -7659,8 +7672,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = skylake_init_clock_gating; else if (IS_KABYLAKE(dev_priv)) dev_priv->display.init_clock_gating = kabylake_init_clock_gating; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_BROXTON(dev_priv)) dev_priv->display.init_clock_gating = bxt_init_clock_gating; + else if (IS_GEMINILAKE(dev_priv)) + dev_priv->display.init_clock_gating = glk_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = broadwell_init_clock_gating; else if (IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 69035e4..d32cbba 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int ret; - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | ECOCHK_DIS_TLB); - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_GPGPU_PREEMPTION); - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ /* WaDisablePartialResolveInVc:skl,bxt,kbl */ WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); /* WaOCLCoherentLineFlush:skl,bxt,kbl */ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); if (ret) return ret; @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); if (ret) return ret; @@ -1120,6 +1120,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) return 0; } +static int glk_init_workarounds(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + int ret; + + ret = gen9_init_workarounds(engine); + if (ret) + return ret; + + /* WaToEnableHwFixForPushConstHWBug:glk */ + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); + + return 0; +} + int init_workarounds_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1144,6 +1160,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) if (IS_KABYLAKE(dev_priv)) return kbl_init_workarounds(engine); + if (IS_GEMINILAKE(dev_priv)) + return glk_init_workarounds(engine); + return 0; } -- 2.5.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-26 8:57 ` [PATCH v2] " Ander Conselvan de Oliveira @ 2017-01-26 9:16 ` Ander Conselvan de Oliveira 2017-01-26 12:06 ` David Weinehall 0 siblings, 1 reply; 14+ messages in thread From: Ander Conselvan de Oliveira @ 2017-01-26 9:16 UTC (permalink / raw) To: intel-gfx; +Cc: Ander Conselvan de Oliveira Apply workarounds to Geminilake, and annotate those that are applied unconditionally when they apply to GLK based on the workaround database. v2: Fix commit message typos. (David) v3: Rebase. Cc: David Weinehall <david.weinehall@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- 5 files changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 40685c6..048040e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2184,14 +2184,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl */ + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ if (IS_BROADWELL(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); else if (IS_GEN9_BC(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); - else if (IS_BROXTON(dev_priv)) + else if (IS_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index bee9d56..0e7b950 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1101,13 +1101,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, struct drm_i915_private *dev_priv = engine->i915; uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); if (ret < 0) return ret; index = ret; - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( @@ -1131,7 +1131,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, 0); } - /* WaMediaPoolStateCmdInWABB:bxt */ + /* WaMediaPoolStateCmdInWABB:bxt,glk */ if (HAS_POOLED_EU(engine->i915)) { /* * EU pool configuration is setup along with golden context diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 8f98fc7..773e362 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, "Platform that should have a MOCS table does not.\n"); } - /* WaDisableSkipCaching:skl,bxt,kbl */ + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ if (IS_GEN9(dev_priv)) { int i; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 08548a4..8fc1e89f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); - /* WaEnableChickenDCPR:skl,bxt,kbl */ + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ - /* WaFbcWakeMemOn:skl,bxt,kbl */ + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE); @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) PWM1_GATING_DIS | PWM2_GATING_DIS); } +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen9_init_clock_gating(dev_priv); + + /* + * WaDisablePWMClockGating:glk + * Backlight PWM may stop in the asserted state, causing backlight + * to stay fully on. + */ + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | + PWM1_GATING_DIS | PWM2_GATING_DIS); +} + static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl + * WaWmMemoryReadLatency:skl,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -7658,8 +7671,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = skylake_init_clock_gating; else if (IS_KABYLAKE(dev_priv)) dev_priv->display.init_clock_gating = kabylake_init_clock_gating; - else if (IS_GEN9_LP(dev_priv)) + else if (IS_BROXTON(dev_priv)) dev_priv->display.init_clock_gating = bxt_init_clock_gating; + else if (IS_GEMINILAKE(dev_priv)) + dev_priv->display.init_clock_gating = glk_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = broadwell_init_clock_gating; else if (IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 69035e4..d32cbba 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; int ret; - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | ECOCHK_DIS_TLB); - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_GPGPU_PREEMPTION); - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ /* WaDisablePartialResolveInVc:skl,bxt,kbl */ WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE); @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); /* WaOCLCoherentLineFlush:skl,bxt,kbl */ I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); if (ret) return ret; @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) if (ret) return ret; - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); if (ret) return ret; @@ -1120,6 +1120,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) return 0; } +static int glk_init_workarounds(struct intel_engine_cs *engine) +{ + struct drm_i915_private *dev_priv = engine->i915; + int ret; + + ret = gen9_init_workarounds(engine); + if (ret) + return ret; + + /* WaToEnableHwFixForPushConstHWBug:glk */ + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); + + return 0; +} + int init_workarounds_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1144,6 +1160,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) if (IS_KABYLAKE(dev_priv)) return kbl_init_workarounds(engine); + if (IS_GEMINILAKE(dev_priv)) + return glk_init_workarounds(engine); + return 0; } -- 2.5.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-26 9:16 ` [PATCH v3] " Ander Conselvan de Oliveira @ 2017-01-26 12:06 ` David Weinehall 2017-01-30 8:37 ` Ander Conselvan De Oliveira 0 siblings, 1 reply; 14+ messages in thread From: David Weinehall @ 2017-01-26 12:06 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx On Thu, Jan 26, 2017 at 11:16:58AM +0200, Ander Conselvan de Oliveira wrote: > Apply workarounds to Geminilake, and annotate those that are applied > unconditionally when they apply to GLK based on the workaround database. > > v2: Fix commit message typos. (David) > v3: Rebase. > Cc: David Weinehall <david.weinehall@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++-------- > 5 files changed, 53 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 40685c6..048040e 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2184,14 +2184,14 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > * called on driver load and after a GPU reset, so you can place > * workarounds here even if they get overwritten by GPU reset. > */ > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl */ > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ > if (IS_BROADWELL(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > else if (IS_GEN9_BC(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > - else if (IS_BROXTON(dev_priv)) > + else if (IS_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > } > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index bee9d56..0e7b950 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1101,13 +1101,13 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > struct drm_i915_private *dev_priv = engine->i915; > uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); > > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); > if (ret < 0) > return ret; > index = ret; > > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > @@ -1131,7 +1131,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, > wa_ctx_emit(batch, index, 0); > } > > - /* WaMediaPoolStateCmdInWABB:bxt */ > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ > if (HAS_POOLED_EU(engine->i915)) { > /* > * EU pool configuration is setup along with golden context > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 8f98fc7..773e362 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > "Platform that should have a MOCS table does not.\n"); > } > > - /* WaDisableSkipCaching:skl,bxt,kbl */ > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > if (IS_GEN9(dev_priv)) { > int i; > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 08548a4..8fc1e89f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(GEN8_CONFIG0, > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > - /* WaEnableChickenDCPR:skl,bxt,kbl */ > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > I915_WRITE(GEN8_CHICKEN_DCPR_1, > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > - /* WaFbcWakeMemOn:skl,bxt,kbl */ > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_FBC_WM_DIS | > DISP_FBC_MEMORY_WAKE); > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) > PWM1_GATING_DIS | PWM2_GATING_DIS); > } > > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > +{ > + gen9_init_clock_gating(dev_priv); > + > + /* > + * WaDisablePWMClockGating:glk > + * Backlight PWM may stop in the asserted state, causing backlight > + * to stay fully on. > + */ > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > + PWM1_GATING_DIS | PWM2_GATING_DIS); > +} > + > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > { > u32 tmp; > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, > } > > /* > - * WaWmMemoryReadLatency:skl > + * WaWmMemoryReadLatency:skl,glk > * > * punit doesn't take into account the read latency so we need > * to add 2us to the various latency levels we retrieve from the > @@ -7658,8 +7671,10 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = skylake_init_clock_gating; > else if (IS_KABYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = kabylake_init_clock_gating; > - else if (IS_GEN9_LP(dev_priv)) > + else if (IS_BROXTON(dev_priv)) > dev_priv->display.init_clock_gating = bxt_init_clock_gating; > + else if (IS_GEMINILAKE(dev_priv)) > + dev_priv->display.init_clock_gating = glk_init_clock_gating; > else if (IS_BROADWELL(dev_priv)) > dev_priv->display.init_clock_gating = broadwell_init_clock_gating; > else if (IS_CHERRYVIEW(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 69035e4..d32cbba 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > struct drm_i915_private *dev_priv = engine->i915; > int ret; > > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > ECOCHK_DIS_TLB); > > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > FLOW_CONTROL_ENABLE | > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, > GEN9_ENABLE_GPGPU_PREEMPTION); > > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); > > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > GEN9_CCS_TLB_PREFETCH_ENABLE); > > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > GEN8_SAMPLER_POWER_BYPASS_DIS); > > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > if (ret) > return ret; > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > if (ret) > return ret; > > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > if (ret) > return ret; > @@ -1120,6 +1120,22 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) > return 0; > } > > +static int glk_init_workarounds(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *dev_priv = engine->i915; > + int ret; > + > + ret = gen9_init_workarounds(engine); > + if (ret) > + return ret; > + > + /* WaToEnableHwFixForPushConstHWBug:glk */ > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > + > + return 0; > +} > + > int init_workarounds_ring(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > @@ -1144,6 +1160,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine) > if (IS_KABYLAKE(dev_priv)) > return kbl_init_workarounds(engine); > > + if (IS_GEMINILAKE(dev_priv)) > + return glk_init_workarounds(engine); > + > return 0; > } > > -- > 2.5.5 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3] drm/i915/glk: Turn on workarounds that apply to Geminilake too 2017-01-26 12:06 ` David Weinehall @ 2017-01-30 8:37 ` Ander Conselvan De Oliveira 0 siblings, 0 replies; 14+ messages in thread From: Ander Conselvan De Oliveira @ 2017-01-30 8:37 UTC (permalink / raw) To: David Weinehall; +Cc: intel-gfx On Thu, 2017-01-26 at 14:06 +0200, David Weinehall wrote: > On Thu, Jan 26, 2017 at 11:16:58AM +0200, Ander Conselvan de Oliveira wrote: > > Apply workarounds to Geminilake, and annotate those that are applied > > unconditionally when they apply to GLK based on the workaround database. > > > > v2: Fix commit message typos. (David) > > v3: Rebase. > > Cc: David Weinehall <david.weinehall@linux.intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Thanks. I pushed this one. Ander > > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- > > drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- > > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++---- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++++++++----- > > --- > > 5 files changed, 53 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 40685c6..048040e 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -2184,14 +2184,14 @@ static void gtt_write_workarounds(struct > > drm_i915_private *dev_priv) > > * called on driver load and after a GPU reset, so you can place > > * workarounds here even if they get overwritten by GPU reset. > > */ > > - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl */ > > + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */ > > if (IS_BROADWELL(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > > else if (IS_CHERRYVIEW(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > > else if (IS_GEN9_BC(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > > - else if (IS_BROXTON(dev_priv)) > > + else if (IS_GEN9_LP(dev_priv)) > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > > } > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > > b/drivers/gpu/drm/i915/intel_lrc.c > > index bee9d56..0e7b950 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1101,13 +1101,13 @@ static int gen9_init_indirectctx_bb(struct > > intel_engine_cs *engine, > > struct drm_i915_private *dev_priv = engine->i915; > > uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); > > > > - /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ > > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ > > ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); > > if (ret < 0) > > return ret; > > index = ret; > > > > - /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ > > wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > > wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > > wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > > @@ -1131,7 +1131,7 @@ static int gen9_init_indirectctx_bb(struct > > intel_engine_cs *engine, > > wa_ctx_emit(batch, index, 0); > > } > > > > - /* WaMediaPoolStateCmdInWABB:bxt */ > > + /* WaMediaPoolStateCmdInWABB:bxt,glk */ > > if (HAS_POOLED_EU(engine->i915)) { > > /* > > * EU pool configuration is setup along with golden context > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c > > b/drivers/gpu/drm/i915/intel_mocs.c > > index 8f98fc7..773e362 100644 > > --- a/drivers/gpu/drm/i915/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/intel_mocs.c > > @@ -191,7 +191,7 @@ static bool get_mocs_settings(struct drm_i915_private > > *dev_priv, > > "Platform that should have a MOCS table does > > not.\n"); > > } > > > > - /* WaDisableSkipCaching:skl,bxt,kbl */ > > + /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > > if (IS_GEN9(dev_priv)) { > > int i; > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 08548a4..8fc1e89f 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -65,12 +65,12 @@ static void gen9_init_clock_gating(struct > > drm_i915_private *dev_priv) > > I915_WRITE(GEN8_CONFIG0, > > I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); > > > > - /* WaEnableChickenDCPR:skl,bxt,kbl */ > > + /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ > > I915_WRITE(GEN8_CHICKEN_DCPR_1, > > I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); > > > > /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ > > - /* WaFbcWakeMemOn:skl,bxt,kbl */ > > + /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ > > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > > DISP_FBC_WM_DIS | > > DISP_FBC_MEMORY_WAKE); > > @@ -107,6 +107,19 @@ static void bxt_init_clock_gating(struct > > drm_i915_private *dev_priv) > > PWM1_GATING_DIS | PWM2_GATING_DIS); > > } > > > > +static void glk_init_clock_gating(struct drm_i915_private *dev_priv) > > +{ > > + gen9_init_clock_gating(dev_priv); > > + > > + /* > > + * WaDisablePWMClockGating:glk > > + * Backlight PWM may stop in the asserted state, causing backlight > > + * to stay fully on. > > + */ > > + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | > > + PWM1_GATING_DIS | PWM2_GATING_DIS); > > +} > > + > > static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) > > { > > u32 tmp; > > @@ -2176,7 +2189,7 @@ static void intel_read_wm_latency(struct > > drm_i915_private *dev_priv, > > } > > > > /* > > - * WaWmMemoryReadLatency:skl > > + * WaWmMemoryReadLatency:skl,glk > > * > > * punit doesn't take into account the read latency so we > > need > > * to add 2us to the various latency levels we retrieve > > from the > > @@ -7658,8 +7671,10 @@ void intel_init_clock_gating_hooks(struct > > drm_i915_private *dev_priv) > > dev_priv->display.init_clock_gating = > > skylake_init_clock_gating; > > else if (IS_KABYLAKE(dev_priv)) > > dev_priv->display.init_clock_gating = > > kabylake_init_clock_gating; > > - else if (IS_GEN9_LP(dev_priv)) > > + else if (IS_BROXTON(dev_priv)) > > dev_priv->display.init_clock_gating = > > bxt_init_clock_gating; > > + else if (IS_GEMINILAKE(dev_priv)) > > + dev_priv->display.init_clock_gating = > > glk_init_clock_gating; > > else if (IS_BROADWELL(dev_priv)) > > dev_priv->display.init_clock_gating = > > broadwell_init_clock_gating; > > else if (IS_CHERRYVIEW(dev_priv)) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 69035e4..d32cbba 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -812,10 +812,10 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > struct drm_i915_private *dev_priv = engine->i915; > > int ret; > > > > - /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ > > + /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ > > I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, > > _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); > > > > - /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ > > + /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ > > I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | > > GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); > > > > @@ -823,8 +823,8 @@ static int gen9_init_workarounds(struct intel_engine_cs > > *engine) > > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > > ECOCHK_DIS_TLB); > > > > - /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ > > - /* WaDisablePartialInstShootdown:skl,bxt,kbl */ > > + /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ > > + /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ > > WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, > > FLOW_CONTROL_ENABLE | > > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > > @@ -853,12 +853,12 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, > > GEN9_ENABLE_GPGPU_PREEMPTION); > > > > - /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ > > + /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ > > /* WaDisablePartialResolveInVc:skl,bxt,kbl */ > > WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE > > | > > GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE > > )); > > > > - /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ > > + /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ > > WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > > GEN9_CCS_TLB_PREFETCH_ENABLE); > > > > @@ -900,14 +900,14 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *engine) > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > > GEN8_SAMPLER_POWER_BYPASS_DIS); > > > > - /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ > > + /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > > > /* WaOCLCoherentLineFlush:skl,bxt,kbl */ > > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > > > - /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ > > ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > > if (ret) > > return ret; > > @@ -917,7 +917,7 @@ static int gen9_init_workarounds(struct intel_engine_cs > > *engine) > > if (ret) > > return ret; > > > > - /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ > > + /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ > > ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); > > if (ret) > > return ret; > > @@ -1120,6 +1120,22 @@ static int kbl_init_workarounds(struct > > intel_engine_cs *engine) > > return 0; > > } > > > > +static int glk_init_workarounds(struct intel_engine_cs *engine) > > +{ > > + struct drm_i915_private *dev_priv = engine->i915; > > + int ret; > > + > > + ret = gen9_init_workarounds(engine); > > + if (ret) > > + return ret; > > + > > + /* WaToEnableHwFixForPushConstHWBug:glk */ > > + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > > + GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > > + > > + return 0; > > +} > > + > > int init_workarounds_ring(struct intel_engine_cs *engine) > > { > > struct drm_i915_private *dev_priv = engine->i915; > > @@ -1144,6 +1160,9 @@ int init_workarounds_ring(struct intel_engine_cs > > *engine) > > if (IS_KABYLAKE(dev_priv)) > > return kbl_init_workarounds(engine); > > > > + if (IS_GEMINILAKE(dev_priv)) > > + return glk_init_workarounds(engine); > > + > > return 0; > > } > > > > -- > > 2.5.5 > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 2/3] drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too Ander Conselvan de Oliveira @ 2017-01-12 15:53 ` Patchwork 2017-01-26 9:02 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev2) Patchwork 2017-01-26 11:54 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev3) Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2017-01-12 15:53 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround URL : https://patchwork.freedesktop.org/series/17904/ State : success == Summary == Series 17904v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17904/revisions/1/mbox/ fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 beb34e26b0349bb8190f6c51d534ba5bf4611cf0 drm-tip: 2017y-01m-12d-14h-11m-49s UTC integration manifest 6f38f83 drm/i915/glk: Turn on workarounds that apply to Geminilake too 3b5b7a08 drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 0205597 drm/i915: Add name for WaDisablePWMClockGating workaround == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3501/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev2) 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira ` (2 preceding siblings ...) 2017-01-12 15:53 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Patchwork @ 2017-01-26 9:02 ` Patchwork 2017-01-26 11:54 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev3) Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2017-01-26 9:02 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev2) URL : https://patchwork.freedesktop.org/series/17904/ State : failure == Summary == CC [M] drivers/gpu/drm/i915/gvt/cfg_space.o CC [M] drivers/gpu/drm/i915/gvt/opregion.o CC [M] drivers/gpu/drm/i915/gvt/display.o CC [M] drivers/gpu/drm/i915/gvt/mmio.o CC [M] drivers/gpu/drm/i915/gvt/edid.o CC [M] drivers/gpu/drm/i915/gvt/execlist.o CC [M] drivers/gpu/drm/i915/gvt/scheduler.o CC [M] drivers/gpu/drm/i915/gvt/sched_policy.o CC [M] drivers/gpu/drm/i915/gvt/render.o CC [M] drivers/gpu/drm/i915/gvt/cmd_parser.o LD [M] drivers/mmc/core/mmc_block.o LD drivers/mmc/built-in.o LD drivers/thermal/thermal_sys.o LD lib/raid6/raid6_pq.o LD drivers/thermal/built-in.o LD lib/raid6/built-in.o LD drivers/usb/storage/usb-storage.o LD drivers/usb/storage/built-in.o LD drivers/acpi/acpica/acpi.o LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o LD drivers/pci/built-in.o LD drivers/tty/serial/8250/8250.o LD net/xfrm/built-in.o LD drivers/acpi/acpica/built-in.o LD [M] drivers/usb/serial/usbserial.o LD drivers/scsi/scsi_mod.o LD net/packet/built-in.o LD drivers/acpi/built-in.o LD drivers/video/fbdev/core/fb.o LD drivers/video/fbdev/core/built-in.o LD drivers/spi/built-in.o LD drivers/usb/gadget/libcomposite.o drivers/gpu/drm/i915/i915_gem_gtt.c: In function ‘gtt_write_workarounds’: drivers/gpu/drm/i915/i915_gem_gtt.c:2187:1: error: expected expression before ‘<<’ token <<<<<<< 6d30d0b2f432fa451dccfb4db6bd159e59aca5c8 ^ drivers/gpu/drm/i915/i915_gem_gtt.c:2187:9: error: invalid suffix "d30d0b2f432fa451dccfb4db6bd159e59aca5c8" on integer constant <<<<<<< 6d30d0b2f432fa451dccfb4db6bd159e59aca5c8 ^ drivers/gpu/drm/i915/i915_gem_gtt.c:2194:2: error: ‘else’ without a previous ‘if’ else if (IS_CHERRYVIEW(dev_priv)) ^ LD drivers/iommu/built-in.o AR lib/lib.a LD drivers/gpu/drm/drm.o EXPORTS lib/lib-ksyms.o scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/i915_gem_gtt.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_gem_gtt.o] Error 1 make[4]: *** Waiting for unfinished jobs.... LD lib/built-in.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o LD drivers/usb/gadget/udc/udc-core.o LD drivers/usb/gadget/udc/built-in.o LD drivers/usb/gadget/built-in.o LD [M] sound/pci/hda/snd-hda-codec-generic.o LD sound/pci/built-in.o LD drivers/video/fbdev/built-in.o LD net/ipv6/ipv6.o LD sound/built-in.o LD drivers/scsi/sd_mod.o LD net/ipv6/built-in.o LD drivers/scsi/built-in.o LD drivers/tty/serial/8250/8250_base.o LD fs/btrfs/btrfs.o LD drivers/tty/serial/8250/built-in.o LD drivers/tty/serial/built-in.o LD fs/btrfs/built-in.o LD drivers/usb/core/usbcore.o LD drivers/video/console/built-in.o LD drivers/usb/core/built-in.o LD drivers/video/built-in.o CC arch/x86/kernel/cpu/capflags.o LD arch/x86/kernel/cpu/built-in.o LD arch/x86/kernel/built-in.o LD drivers/usb/host/xhci-hcd.o LD [M] drivers/net/ethernet/intel/igb/igb.o LD arch/x86/built-in.o LD drivers/tty/vt/built-in.o LD drivers/tty/built-in.o LD drivers/md/md-mod.o LD drivers/md/built-in.o LD drivers/usb/host/built-in.o LD net/core/built-in.o LD drivers/usb/built-in.o LD net/ipv4/built-in.o LD fs/ext4/ext4.o LD net/built-in.o LD fs/ext4/built-in.o LD fs/built-in.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o LD drivers/net/ethernet/built-in.o LD drivers/net/built-in.o scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:988: recipe for target 'drivers' failed make: *** [drivers] Error 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev3) 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira ` (3 preceding siblings ...) 2017-01-26 9:02 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev2) Patchwork @ 2017-01-26 11:54 ` Patchwork 4 siblings, 0 replies; 14+ messages in thread From: Patchwork @ 2017-01-26 11:54 UTC (permalink / raw) To: Ander Conselvan de Oliveira; +Cc: intel-gfx == Series Details == Series: series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev3) URL : https://patchwork.freedesktop.org/series/17904/ State : success == Summary == Series 17904v3 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17904/revisions/3/mbox/ fi-bdw-5557u total:247 pass:233 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:247 pass:208 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:247 pass:225 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:79 pass:66 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:247 pass:228 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:247 pass:226 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hq total:247 pass:227 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:247 pass:222 dwarn:4 dfail:0 fail:0 skip:21 fi-skl-6770hq total:247 pass:234 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:247 pass:216 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:247 pass:215 dwarn:0 dfail:0 fail:0 skip:32 3778ca36c6b4e894b581d4f56abe6bbafe927e96 drm-tip: 2017y-01m-26d-10h-11m-00s UTC integration manifest 32a8520 drm/i915/glk: Turn on workarounds that apply to Geminilake too f68f575 drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 4ff866c drm/i915: Add name for WaDisablePWMClockGating workaround == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3609/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2017-01-30 8:37 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-01-12 11:47 [PATCH 1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 2/3] drm/i915: Apply WaSetHdcUnitClockGatingDisableInUcgctl6 only until B0 Ander Conselvan de Oliveira 2017-01-12 11:47 ` [PATCH 3/3] drm/i915/glk: Turn on workarounds that apply to Geminilake too Ander Conselvan de Oliveira 2017-01-20 16:04 ` Rodrigo Vivi 2017-01-23 7:49 ` Ander Conselvan De Oliveira 2017-01-23 9:19 ` Matthew Auld 2017-01-24 12:39 ` David Weinehall 2017-01-26 8:57 ` [PATCH v2] " Ander Conselvan de Oliveira 2017-01-26 9:16 ` [PATCH v3] " Ander Conselvan de Oliveira 2017-01-26 12:06 ` David Weinehall 2017-01-30 8:37 ` Ander Conselvan De Oliveira 2017-01-12 15:53 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround Patchwork 2017-01-26 9:02 ` ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev2) Patchwork 2017-01-26 11:54 ` ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Add name for WaDisablePWMClockGating workaround (rev3) Patchwork
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