* [PATCH v2 0/3] Exynos5433/TM2: add clocks configuration for display subsystem
[not found] <CGME20170126123805eucas1p23881b01fa3f9719e2bfea9cd5cf1b429@eucas1p2.samsung.com>
@ 2017-01-26 12:37 ` Marek Szyprowski
[not found] ` <CGME20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4@eucas1p2.samsung.com>
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-26 12:37 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Hello,
This patchset is a next step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for initial clocks
configuration on TM2/TM2e boards. Till now display subsystem worked only
because the clock hierarchy has been configured by the bootloader.
However when power domains are added, such configuration might be lost
if the display power domain get turned off before display clock
controller's probe.
Patches have been generated on top of linux-next from 25th January 2017.
This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs and TM2/TM2e boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Changelog:
v2:
- corrected DISP PLL rate from 266MHz to 250MHz (TM2) and 278MHz (TM2e)
- added a patch with PLL data for 250MHZ and 278MHz rates
v1:
- initial version
Patch summary:
Marek Szyprowski (3):
clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
arm64: dts: exynos: Add initial configuration for DISP clocks for
TM2/TM2e
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ---------
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++
drivers/clk/samsung/clk-exynos5433.c | 8 ++++--
include/dt-bindings/clock/exynos5433.h | 5 +++-
5 files changed, 68 insertions(+), 15 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/3] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
[not found] ` <CGME20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4@eucas1p2.samsung.com>
@ 2017-01-26 12:37 ` Marek Szyprowski
0 siblings, 0 replies; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-26 12:37 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsugn.com>
---
drivers/clk/samsung/clk-exynos5433.c | 6 ++++--
include/dt-bindings/clock/exynos5433.h | 5 ++++-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 8fd7f6e88e3c..6ee91ae875c3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)
FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
/* PHY clocks from MIPI_DPHY0 */
- FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
- FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+ FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
+ NULL, 0, 188000000),
+ FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
+ NULL, 0, 100000000),
/* PHY clocks from HDMI_PHY */
FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
NULL, 0, 300000000),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4fa6bb2136e3..be39d23e6a32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -771,7 +771,10 @@
#define CLK_PCLK_DECON 113
-#define DISP_NR_CLK 114
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
+
+#define DISP_NR_CLK 116
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
[not found] ` <CGME20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc@eucas1p2.samsung.com>
@ 2017-01-26 12:37 ` Marek Szyprowski
2017-01-26 14:33 ` Chanwoo Choi
0 siblings, 1 reply; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-26 12:37 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such
configuration for those boards with 'assigned-clocks*' properties,
parameters for those two additional rates are needed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-exynos5433.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 6ee91ae875c3..11343a597093 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@
PLL_35XX_RATE(350000000U, 350, 6, 2),
PLL_35XX_RATE(333000000U, 222, 4, 2),
PLL_35XX_RATE(300000000U, 500, 5, 3),
+ PLL_35XX_RATE(278000000U, 556, 6, 3),
PLL_35XX_RATE(266000000U, 532, 6, 3),
+ PLL_35XX_RATE(250000000U, 500, 6, 3),
PLL_35XX_RATE(200000000U, 400, 6, 3),
PLL_35XX_RATE(166000000U, 332, 6, 3),
PLL_35XX_RATE(160000000U, 320, 6, 3),
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
[not found] ` <CGME20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb@eucas1p2.samsung.com>
@ 2017-01-26 12:37 ` Marek Szyprowski
2017-01-26 14:49 ` Chanwoo Choi
0 siblings, 1 reply; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-26 12:37 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Add initial clock configuration for display subsystem for Exynos5433
based TM2/TM2e boards in device tree in order to avoid dependency on the
configuration left by the bootloader. This initial configuration is also
needed to ensure that display subsystem is operational if display power
domain gets turned off before clock controller is probed and the inital
clock configuration left by the bootloader saved.
TM2 and TM2e uses different rate for DISP PLL clock, but for better
maintainability all 'assigned-clocks-*' properties for DISP CMU are
defines in each board dts instead of redefining the rates property.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ---------
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++
3 files changed, 58 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 5c207575ed0a..1c1c03142e6d 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,18 +217,6 @@
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
};
-&cmu_disp {
- assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
- <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
- assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
- <0>,
- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
- assigned-clock-rates = <0>, <400000000>;
-};
-
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index ddba2f889326..b8bb053495af 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -18,6 +18,35 @@
compatible = "samsung,tm2", "samsung,exynos5433";
};
+&cmu_disp {
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <250000000>, <400000000>;
+};
+
&hsi2c_9 {
status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index d8bca75a1afe..c27500b7d8b5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -18,6 +18,35 @@
compatible = "samsung,tm2e", "samsung,exynos5433";
};
+&cmu_disp {
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <278000000>, <400000000>;
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
2017-01-26 12:37 ` [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates Marek Szyprowski
@ 2017-01-26 14:33 ` Chanwoo Choi
0 siblings, 0 replies; 13+ messages in thread
From: Chanwoo Choi @ 2017-01-26 14:33 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Hi Marek,
2017-01-26 21:37 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> Default clock configuration applied by the bootloader for TM2 and TM2e
> boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such
> configuration for those boards with 'assigned-clocks*' properties,
> parameters for those two additional rates are needed.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5433.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 6ee91ae875c3..11343a597093 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -739,7 +739,9 @@
> PLL_35XX_RATE(350000000U, 350, 6, 2),
> PLL_35XX_RATE(333000000U, 222, 4, 2),
> PLL_35XX_RATE(300000000U, 500, 5, 3),
> + PLL_35XX_RATE(278000000U, 556, 6, 3),
> PLL_35XX_RATE(266000000U, 532, 6, 3),
> + PLL_35XX_RATE(250000000U, 500, 6, 3),
> PLL_35XX_RATE(200000000U, 400, 6, 3),
> PLL_35XX_RATE(166000000U, 332, 6, 3),
> PLL_35XX_RATE(160000000U, 320, 6, 3),
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-26 12:37 ` [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Marek Szyprowski
@ 2017-01-26 14:49 ` Chanwoo Choi
2017-01-26 15:20 ` Andrzej Hajda
0 siblings, 1 reply; 13+ messages in thread
From: Chanwoo Choi @ 2017-01-26 14:49 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
Hi Marek
2017-01-26 21:37 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
> Add initial clock configuration for display subsystem for Exynos5433
> based TM2/TM2e boards in device tree in order to avoid dependency on the
> configuration left by the bootloader. This initial configuration is also
> needed to ensure that display subsystem is operational if display power
> domain gets turned off before clock controller is probed and the inital
> clock configuration left by the bootloader saved.
>
> TM2 and TM2e uses different rate for DISP PLL clock, but for better
> maintainability all 'assigned-clocks-*' properties for DISP CMU are
> defines in each board dts instead of redefining the rates property.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ---------
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++
> 3 files changed, 58 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 5c207575ed0a..1c1c03142e6d 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -217,18 +217,6 @@
> assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> };
>
> -&cmu_disp {
> - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> - <0>,
> - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> - assigned-clock-rates = <0>, <400000000>;
> -};
> -
> &cmu_fsys {
> assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index ddba2f889326..b8bb053495af 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -18,6 +18,35 @@
> compatible = "samsung,tm2", "samsung,exynos5433";
> };
>
> +&cmu_disp {
> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> + <&cmu_disp CLK_MOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> + assigned-clock-parents = <0>, <0>,
> + <&cmu_mif CLK_ACLK_DISP_333>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> + <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> + assigned-clock-rates = <250000000>, <400000000>;
> +};
> +
> &hsi2c_9 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index d8bca75a1afe..c27500b7d8b5 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -18,6 +18,35 @@
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> +&cmu_disp {
> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> + <&cmu_disp CLK_MOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> + assigned-clock-parents = <0>, <0>,
> + <&cmu_mif CLK_ACLK_DISP_333>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> + <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> + assigned-clock-rates = <278000000>, <400000000>;
Except for setting the assigned-clock-rate for CLK_FOUT_DISP_PLL,
tm2.dts and tm2e.dts has the same dt node of cmu_disp.
If there is same value between tm2 and tm2e, you should keep the same value
in exynos5433-tm2-common.dtsi.
So, I think that exynos5433-tm2-common.dtsi include the relationships
between clocks and parent clocks as following without assigning the clocks.
And then, each tm2 and tm2e.dts can assign the clock rate for CLK_FOUT_DISP_PLL
and CLK_DIV_SCLK_DECON_TV_ECLK.
For example,
In exynos5433-tm2-common.dtsi
&cmu_disp {
assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
<&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
<&cmu_disp CLK_MOUT_SCLK_DSIM0>,
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
<&cmu_disp CLK_MOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
assigned-clock-parents = <0>, <0>,
<&cmu_mif CLK_ACLK_DISP_333>,
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
<&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
};
In exynos5433-tm2.dts
&cmu_disp {
assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
assigned-clock-rates = <250000000>, <400000000>;
};
In exynos5433-tm2e.dts
&cmu_disp {
assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
assigned-clock-rates = <278000000>, <400000000>;
};
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-26 14:49 ` Chanwoo Choi
@ 2017-01-26 15:20 ` Andrzej Hajda
2017-01-26 19:35 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Andrzej Hajda @ 2017-01-26 15:20 UTC (permalink / raw)
To: cwchoi00, Marek Szyprowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi
On 26.01.2017 15:49, Chanwoo Choi wrote:
> Hi Marek
>
> 2017-01-26 21:37 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>:
>> Add initial clock configuration for display subsystem for Exynos5433
>> based TM2/TM2e boards in device tree in order to avoid dependency on the
>> configuration left by the bootloader. This initial configuration is also
>> needed to ensure that display subsystem is operational if display power
>> domain gets turned off before clock controller is probed and the inital
>> clock configuration left by the bootloader saved.
>>
>> TM2 and TM2e uses different rate for DISP PLL clock, but for better
>> maintainability all 'assigned-clocks-*' properties for DISP CMU are
>> defines in each board dts instead of redefining the rates property.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ---------
>> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++
>> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++
>> 3 files changed, 58 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> index 5c207575ed0a..1c1c03142e6d 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> @@ -217,18 +217,6 @@
>> assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
>> };
>>
>> -&cmu_disp {
>> - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>> - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
>> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
>> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
>> - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>> - <0>,
>> - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
>> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
>> - assigned-clock-rates = <0>, <400000000>;
>> -};
>> -
>> &cmu_fsys {
>> assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
>> <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index ddba2f889326..b8bb053495af 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -18,6 +18,35 @@
>> compatible = "samsung,tm2", "samsung,exynos5433";
>> };
>>
>> +&cmu_disp {
>> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
>> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
>> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
>> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
>> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
>> + <&cmu_disp CLK_MOUT_DISP_PLL>,
>> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
>> + assigned-clock-parents = <0>, <0>,
>> + <&cmu_mif CLK_ACLK_DISP_333>,
>> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
>> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
>> + <&cmu_disp CLK_FOUT_DISP_PLL>,
>> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
>> + assigned-clock-rates = <250000000>, <400000000>;
>> +};
>> +
>> &hsi2c_9 {
>> status = "okay";
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> index d8bca75a1afe..c27500b7d8b5 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> @@ -18,6 +18,35 @@
>> compatible = "samsung,tm2e", "samsung,exynos5433";
>> };
>>
>> +&cmu_disp {
>> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
>> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
>> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
>> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
>> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
>> + <&cmu_disp CLK_MOUT_DISP_PLL>,
>> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
>> + assigned-clock-parents = <0>, <0>,
>> + <&cmu_mif CLK_ACLK_DISP_333>,
>> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
>> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
>> + <&cmu_disp CLK_FOUT_DISP_PLL>,
>> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
>> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
>> + assigned-clock-rates = <278000000>, <400000000>;
> Except for setting the assigned-clock-rate for CLK_FOUT_DISP_PLL,
> tm2.dts and tm2e.dts has the same dt node of cmu_disp.
> If there is same value between tm2 and tm2e, you should keep the same value
> in exynos5433-tm2-common.dtsi.
>
> So, I think that exynos5433-tm2-common.dtsi include the relationships
> between clocks and parent clocks as following without assigning the clocks.
>
> And then, each tm2 and tm2e.dts can assign the clock rate for CLK_FOUT_DISP_PLL
> and CLK_DIV_SCLK_DECON_TV_ECLK.
>
> For example,
> In exynos5433-tm2-common.dtsi
>
> &cmu_disp {
> assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> <&cmu_disp CLK_MOUT_DISP_PLL>,
> <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> assigned-clock-parents = <0>, <0>,
> <&cmu_mif CLK_ACLK_DISP_333>,
> <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> <&cmu_disp CLK_FOUT_DISP_PLL>,
> <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> };
>
>
> In exynos5433-tm2.dts
> &cmu_disp {
> assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
> assigned-clock-rates = <250000000>, <400000000>;
> };
>
>
> In exynos5433-tm2e.dts
> &cmu_disp {
> assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
> assigned-clock-rates = <278000000>, <400000000>;
> };
>
I guess in such case common properties will be overwritten.
If one really want to put as much as possible into common part it could
be done this way:
exynos5433-tm2.dts before '#include "exynos5433-tm2-common.dtsi"':
#define CLK_FOUT_DISP_PLL_RATE 250000000
exynos5433-tm2e.dts before '#include "exynos5433-tm2-common.dtsi"':
#define CLK_FOUT_DISP_PLL_RATE 278000000
and in exynos5433-tm2-common.dtsi:
+&cmu_disp {
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <CLK_FOUT_DISP_PLL_RATE>, <400000000>;
+};
+
The question is if such macro games will be accepted? :)
Regards
Andrzej
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-26 15:20 ` Andrzej Hajda
@ 2017-01-26 19:35 ` Krzysztof Kozlowski
[not found] ` <CGME20170127112056eucas1p15ced94a57821f980445c86f1393d5a94@eucas1p1.samsung.com>
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2017-01-26 19:35 UTC (permalink / raw)
To: Andrzej Hajda
Cc: cwchoi00, Marek Szyprowski, linux-samsung-soc,
Sylwester Nawrocki, Bartlomiej Zolnierkiewicz, Chanwoo Choi
On Thu, Jan 26, 2017 at 04:20:22PM +0100, Andrzej Hajda wrote:
> On 26.01.2017 15:49, Chanwoo Choi wrote:
> > Hi Marek
> >
(...)
> >> + assigned-clock-rates = <278000000>, <400000000>;
> > Except for setting the assigned-clock-rate for CLK_FOUT_DISP_PLL,
> > tm2.dts and tm2e.dts has the same dt node of cmu_disp.
> > If there is same value between tm2 and tm2e, you should keep the same value
> > in exynos5433-tm2-common.dtsi.
> >
> > So, I think that exynos5433-tm2-common.dtsi include the relationships
> > between clocks and parent clocks as following without assigning the clocks.
> >
> > And then, each tm2 and tm2e.dts can assign the clock rate for CLK_FOUT_DISP_PLL
> > and CLK_DIV_SCLK_DECON_TV_ECLK.
> >
> > For example,
> > In exynos5433-tm2-common.dtsi
> >
> > &cmu_disp {
> > assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> > <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> > <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> > <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> > <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> > <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> > <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> > <&cmu_disp CLK_MOUT_DISP_PLL>,
> > <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> > assigned-clock-parents = <0>, <0>,
> > <&cmu_mif CLK_ACLK_DISP_333>,
> > <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> > <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> > <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> > <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> > <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> > <&cmu_disp CLK_FOUT_DISP_PLL>,
> > <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> > <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> > <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> > };
> >
> >
> > In exynos5433-tm2.dts
> > &cmu_disp {
> > assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> > <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
> > assigned-clock-rates = <250000000>, <400000000>;
> > };
> >
> >
> > In exynos5433-tm2e.dts
> > &cmu_disp {
> > assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> > <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>;
> > assigned-clock-rates = <278000000>, <400000000>;
> > };
> >
> I guess in such case common properties will be overwritten.
>
Indeed.
> If one really want to put as much as possible into common part it could
> be done this way:
>
> exynos5433-tm2.dts before '#include "exynos5433-tm2-common.dtsi"':
>
> #define CLK_FOUT_DISP_PLL_RATE 250000000
>
> exynos5433-tm2e.dts before '#include "exynos5433-tm2-common.dtsi"':
>
> #define CLK_FOUT_DISP_PLL_RATE 278000000
>
> and in exynos5433-tm2-common.dtsi:
>
> +&cmu_disp {
> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> + <&cmu_disp CLK_MOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> + assigned-clock-parents = <0>, <0>,
> + <&cmu_mif CLK_ACLK_DISP_333>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> + <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> + assigned-clock-rates = <CLK_FOUT_DISP_PLL_RATE>, <400000000>;
> +};
> +
>
> The question is if such macro games will be accepted? :)
Interesting idea... The DTSI would look nice but the real problem is
hidden by a dependency on #define. In the same time one would have two
definitions of this value - when looking at DTSI, one would have to
look at DTS as well. This would be rather a new way of overriding
things (reading DTSI and then jumping to DTS) and I prefer
consistency...
assigned-clocks and assigned-clock-parents are the same, right? Only
assigned-clock-rates differ?
Ideas:
1. Make common assigned-clocks+assigned-clock-parents in DTSI and customize
only the rates in DTS.
Mention the reason behind the split for assigned-* properties in a
comment in all files (common + boards). Anyone looking at final DTS
will find that assigned-clocks/parents are somewhere else (and
vice-versa). Also anyone looking at DTSI will see a comment that one
part is missing - rates are somewhere else.
2. Duplicate the nodes like it is in Marek's patch but please mention in
a comment that assigned-clocks+assigned-clock-parents are expected to be
the same between boards.
The goal behind the comment is to make reader's life easier:
- no need to figure out why this is duplicated,
- if there would be a mistake (difference between boards), then
easily understand that this was a mistake, not a feature.
The benefit of Andrzej's approach is that there will be compile time
dependency - missing define causes build failure. In my approach, there
will be only comments. Anyway in all cases the reader have to look at
both DTSI and DTS to find the final answer.
What do you think?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
[not found] ` <CGME20170127112056eucas1p15ced94a57821f980445c86f1393d5a94@eucas1p1.samsung.com>
@ 2017-01-27 11:20 ` Marek Szyprowski
2017-01-28 15:28 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-27 11:20 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi, Andrzej Hajda
Add initial clock configuration for display subsystem for Exynos5433
based TM2/TM2e boards in device tree in order to avoid dependency on the
configuration left by the bootloader. This initial configuration is also
needed to ensure that display subsystem is operational if display power
domain gets turned off before clock controller is probed and the inital
clock configuration left by the bootloader saved.
TM2 and TM2e uses different rate for DISP PLL clock, but for better
maintainability all 'assigned-clocks-*' properties for DISP CMU are
defines in each board dts instead of redefining the rates property.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
Changelog:
v3:
- added comment about DISP CMU clocks configuration on TM2 and TM2e
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++
3 files changed, 68 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 53fd0683d400..098ad557fee3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,18 +217,6 @@
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
};
-&cmu_disp {
- assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
- <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
- assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
- <0>,
- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
- assigned-clock-rates = <0>, <400000000>;
-};
-
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 6d362f964b3a..db3fed27728b 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -18,6 +18,40 @@
compatible = "samsung,tm2", "samsung,exynos5433";
};
+&cmu_disp {
+ /*
+ * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
+ * clocks properties for DISP CMU for each board to keep them together
+ * for easier review and maintenance.
+ */
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <250000000>, <400000000>;
+};
+
&dsi {
panel@0 {
compatible = "samsung,s6e3ha2";
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 2fbf3a860316..7891a31adc17 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -18,6 +18,40 @@
compatible = "samsung,tm2e", "samsung,exynos5433";
};
+&cmu_disp {
+ /*
+ * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
+ * clocks properties for DISP CMU for each board to keep them together
+ * for easier review and maintenance.
+ */
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <278000000>, <400000000>;
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-27 11:20 ` [PATCH v3 " Marek Szyprowski
@ 2017-01-28 15:28 ` Krzysztof Kozlowski
[not found] ` <CGME20170130105746eucas1p1232fb56b92e5939beb7ee65670422860@eucas1p1.samsung.com>
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2017-01-28 15:28 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Bartlomiej Zolnierkiewicz,
Chanwoo Choi, Andrzej Hajda
On Fri, Jan 27, 2017 at 12:20:42PM +0100, Marek Szyprowski wrote:
> Add initial clock configuration for display subsystem for Exynos5433
> based TM2/TM2e boards in device tree in order to avoid dependency on the
> configuration left by the bootloader. This initial configuration is also
> needed to ensure that display subsystem is operational if display power
> domain gets turned off before clock controller is probed and the inital
> clock configuration left by the bootloader saved.
>
> TM2 and TM2e uses different rate for DISP PLL clock, but for better
> maintainability all 'assigned-clocks-*' properties for DISP CMU are
> defines in each board dts instead of redefining the rates property.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> Changelog:
> v3:
> - added comment about DISP CMU clocks configuration on TM2 and TM2e
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++
> 3 files changed, 68 insertions(+), 12 deletions(-)
>
Does not apply. Are you sure that you generated it on linux-next?
error: patch failed: arch/arm64/boot/dts/exynos/exynos5433-tm2.dts:18
error: arch/arm64/boot/dts/exynos/exynos5433-tm2.dts: patch does not apply
Patch failed at 0001 arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v3 3/3 REBASED] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
[not found] ` <CGME20170130105746eucas1p1232fb56b92e5939beb7ee65670422860@eucas1p1.samsung.com>
@ 2017-01-30 10:57 ` Marek Szyprowski
2017-01-31 0:39 ` Chanwoo Choi
0 siblings, 1 reply; 13+ messages in thread
From: Marek Szyprowski @ 2017-01-30 10:57 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Chanwoo Choi, Andrzej Hajda
Add initial clock configuration for display subsystem for Exynos5433
based TM2/TM2e boards in device tree in order to avoid dependency on the
configuration left by the bootloader. This initial configuration is also
needed to ensure that display subsystem is operational if display power
domain gets turned off before clock controller is probed and the inital
clock configuration left by the bootloader saved.
TM2 and TM2e uses different rate for DISP PLL clock, but for better
maintainability all 'assigned-clocks-*' properties for DISP CMU are
defines in each board dts instead of redefining the rates property.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
Changelog:
v3 resend:
- rebased onto Linux next-20170130
v3:
- added comment about DISP CMU clocks configuration on TM2 and TM2e
---
.../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++
3 files changed, 68 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 53fd0683d400..098ad557fee3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,18 +217,6 @@
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
};
-&cmu_disp {
- assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
- <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
- assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
- <0>,
- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
- <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
- assigned-clock-rates = <0>, <400000000>;
-};
-
&cmu_fsys {
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index ddba2f889326..dea0a6f5bc18 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -18,6 +18,40 @@
compatible = "samsung,tm2", "samsung,exynos5433";
};
+&cmu_disp {
+ /*
+ * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
+ * clocks properties for DISP CMU for each board to keep them together
+ * for easier review and maintenance.
+ */
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <250000000>, <400000000>;
+};
+
&hsi2c_9 {
status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 2fbf3a860316..7891a31adc17 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -18,6 +18,40 @@
compatible = "samsung,tm2e", "samsung,exynos5433";
};
+&cmu_disp {
+ /*
+ * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
+ * clocks properties for DISP CMU for each board to keep them together
+ * for easier review and maintenance.
+ */
+ assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+ <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+ <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+ <&cmu_disp CLK_MOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+ assigned-clock-parents = <0>, <0>,
+ <&cmu_mif CLK_ACLK_DISP_333>,
+ <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+ <&cmu_disp CLK_FOUT_DISP_PLL>,
+ <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+ <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+ <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+ assigned-clock-rates = <278000000>, <400000000>;
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/3 REBASED] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-30 10:57 ` [PATCH v3 3/3 REBASED] " Marek Szyprowski
@ 2017-01-31 0:39 ` Chanwoo Choi
2017-01-31 19:42 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Chanwoo Choi @ 2017-01-31 0:39 UTC (permalink / raw)
To: Marek Szyprowski, linux-samsung-soc
Cc: Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz, Andrzej Hajda
Hi Marek,
On 2017년 01월 30일 19:57, Marek Szyprowski wrote:
> Add initial clock configuration for display subsystem for Exynos5433
> based TM2/TM2e boards in device tree in order to avoid dependency on the
> configuration left by the bootloader. This initial configuration is also
> needed to ensure that display subsystem is operational if display power
> domain gets turned off before clock controller is probed and the inital
> clock configuration left by the bootloader saved.
>
> TM2 and TM2e uses different rate for DISP PLL clock, but for better
> maintainability all 'assigned-clocks-*' properties for DISP CMU are
> defines in each board dts instead of redefining the rates property.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> Changelog:
> v3 resend:
> - rebased onto Linux next-20170130
>
> v3:
> - added comment about DISP CMU clocks configuration on TM2 and TM2e
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++
> 3 files changed, 68 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 53fd0683d400..098ad557fee3 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -217,18 +217,6 @@
> assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> };
>
> -&cmu_disp {
> - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> - <0>,
> - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> - assigned-clock-rates = <0>, <400000000>;
> -};
> -
> &cmu_fsys {
> assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index ddba2f889326..dea0a6f5bc18 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -18,6 +18,40 @@
> compatible = "samsung,tm2", "samsung,exynos5433";
> };
>
> +&cmu_disp {
> + /*
> + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
> + * clocks properties for DISP CMU for each board to keep them together
> + * for easier review and maintenance.
> + */
> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> + <&cmu_disp CLK_MOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> + assigned-clock-parents = <0>, <0>,
> + <&cmu_mif CLK_ACLK_DISP_333>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> + <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> + assigned-clock-rates = <250000000>, <400000000>;
> +};
> +
> &hsi2c_9 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 2fbf3a860316..7891a31adc17 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -18,6 +18,40 @@
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> +&cmu_disp {
> + /*
> + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
> + * clocks properties for DISP CMU for each board to keep them together
> + * for easier review and maintenance.
> + */
> + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> + <&cmu_disp CLK_MOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> + assigned-clock-parents = <0>, <0>,
> + <&cmu_mif CLK_ACLK_DISP_333>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> + <&cmu_disp CLK_FOUT_DISP_PLL>,
> + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> + assigned-clock-rates = <278000000>, <400000000>;
> +};
> +
> &ldo31_reg {
> regulator-name = "TSP_VDD_1.8V_AP";
> regulator-min-microvolt = <1800000>;
>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v3 3/3 REBASED] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e
2017-01-31 0:39 ` Chanwoo Choi
@ 2017-01-31 19:42 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2017-01-31 19:42 UTC (permalink / raw)
To: Chanwoo Choi
Cc: Marek Szyprowski, linux-samsung-soc, Sylwester Nawrocki,
Bartlomiej Zolnierkiewicz, Andrzej Hajda
On Tue, Jan 31, 2017 at 09:39:49AM +0900, Chanwoo Choi wrote:
> Hi Marek,
>
> On 2017년 01월 30일 19:57, Marek Szyprowski wrote:
> > Add initial clock configuration for display subsystem for Exynos5433
> > based TM2/TM2e boards in device tree in order to avoid dependency on the
> > configuration left by the bootloader. This initial configuration is also
> > needed to ensure that display subsystem is operational if display power
> > domain gets turned off before clock controller is probed and the inital
> > clock configuration left by the bootloader saved.
> >
> > TM2 and TM2e uses different rate for DISP PLL clock, but for better
> > maintainability all 'assigned-clocks-*' properties for DISP CMU are
> > defines in each board dts instead of redefining the rates property.
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > ---
> > Changelog:
> > v3 resend:
> > - rebased onto Linux next-20170130
> >
> > v3:
> > - added comment about DISP CMU clocks configuration on TM2 and TM2e
> > ---
> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------
> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++
> > 3 files changed, 68 insertions(+), 12 deletions(-)
> >
Thanks, applied.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-01-31 19:48 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20170126123805eucas1p23881b01fa3f9719e2bfea9cd5cf1b429@eucas1p2.samsung.com>
2017-01-26 12:37 ` [PATCH v2 0/3] Exynos5433/TM2: add clocks configuration for display subsystem Marek Szyprowski
[not found] ` <CGME20170126123805eucas1p2fd873698f59addae8aab7ac3ad0f6de4@eucas1p2.samsung.com>
2017-01-26 12:37 ` [PATCH v2 1/3] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks Marek Szyprowski
[not found] ` <CGME20170126123805eucas1p2b95ab23660b7a6631ab7f639ebaff0fc@eucas1p2.samsung.com>
2017-01-26 12:37 ` [PATCH v2 2/3] clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates Marek Szyprowski
2017-01-26 14:33 ` Chanwoo Choi
[not found] ` <CGME20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb@eucas1p2.samsung.com>
2017-01-26 12:37 ` [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Marek Szyprowski
2017-01-26 14:49 ` Chanwoo Choi
2017-01-26 15:20 ` Andrzej Hajda
2017-01-26 19:35 ` Krzysztof Kozlowski
[not found] ` <CGME20170127112056eucas1p15ced94a57821f980445c86f1393d5a94@eucas1p1.samsung.com>
2017-01-27 11:20 ` [PATCH v3 " Marek Szyprowski
2017-01-28 15:28 ` Krzysztof Kozlowski
[not found] ` <CGME20170130105746eucas1p1232fb56b92e5939beb7ee65670422860@eucas1p1.samsung.com>
2017-01-30 10:57 ` [PATCH v3 3/3 REBASED] " Marek Szyprowski
2017-01-31 0:39 ` Chanwoo Choi
2017-01-31 19:42 ` Krzysztof Kozlowski
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