PRT support for amdgpu v2

PRT support for amdgpu v2

[Christian König]

Hi guys,

a bunch of bug fixes, but still completely untested since I'm on sick leave.

Bas maybe you could give it a try with radv.

Regards,
Christian.

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[PATCH 1/6] drm/amdgpu: add support for BO_VAs without BO v2

[Christian König]

From: Christian König <christian.koenig@amd.com>

For PRT support we need mappings which aren't backed by any memory.

v2: fix parameter checking

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8e6030d..64f04c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1117,7 +1117,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 	struct fence *exclusive;
 	int r;
 
-	if (clear) {
+	if (clear || !bo_va->bo) {
 		mem = NULL;
 		nodes = NULL;
 		exclusive = NULL;
@@ -1134,9 +1134,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 		exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
 	}
 
-	flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
-	gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-		adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? flags : 0;
+	if (bo_va->bo) {
+		flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+		gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
+			adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+			flags : 0;
+	} else {
+		flags = 0x0;
+		gtt_flags = ~0x0;
+	}
 
 	spin_lock(&vm->status_lock);
 	if (!list_empty(&bo_va->vm_status))
@@ -1271,7 +1277,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
 	INIT_LIST_HEAD(&bo_va->invalids);
 	INIT_LIST_HEAD(&bo_va->vm_status);
 
-	list_add_tail(&bo_va->bo_list, &bo->va);
+	if (bo)
+		list_add_tail(&bo_va->bo_list, &bo->va);
 
 	return bo_va;
 }
@@ -1309,7 +1316,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 
 	/* make sure object fit at this offset */
 	eaddr = saddr + size - 1;
-	if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
+	if (saddr >= eaddr ||
+	    (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
 		return -EINVAL;
 
 	last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
-- 
2.5.0

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[PATCH 2/6] drm/amdgpu: add basic PRT support

[Christian König]

From: Christian König <christian.koenig@amd.com>

Future hardware generations can handle PRT flags on a per page basis,
but current hardware can only turn it on globally.

Add the basic handling for both, a global callback to enable/disable
triggered by setting a per mapping flag.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 101 +++++++++++++++++++++++++++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   6 ++
 3 files changed, 98 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 402a895..34a971a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -296,6 +296,8 @@ struct amdgpu_gart_funcs {
 			   uint32_t gpu_page_idx, /* pte/pde to update */
 			   uint64_t addr, /* addr to write into pte/pde */
 			   uint32_t flags); /* access flags */
+	/* enable/disable PRT support */
+	void (*set_prt)(struct amdgpu_device *adev, bool enable);
 };
 
 /* provided by the ih block */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 64f04c7..bc32239 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -69,6 +69,12 @@ struct amdgpu_pte_update_params {
 	bool shadow;
 };
 
+/* Helper to disable partial resident texture feature from a fence callback */
+struct amdgpu_prt_cb {
+	struct amdgpu_device *adev;
+	struct fence_cb cb;
+};
+
 /**
  * amdgpu_vm_num_pde - return the number of page directory entries
  *
@@ -989,11 +995,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 		goto error_free;
 
 	amdgpu_bo_fence(vm->page_directory, f, true);
-	if (fence) {
-		fence_put(*fence);
-		*fence = fence_get(f);
-	}
-	fence_put(f);
+	fence_put(*fence);
+	*fence = f;
 	return 0;
 
 error_free:
@@ -1177,6 +1180,61 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 }
 
 /**
+ * amdgpu_vm_update_prt_state - update the global PRT state
+ */
+static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
+{
+	unsigned long flags;
+	bool enable;
+
+	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
+	enable = !!atomic_read(&adev->vm_manager.num_prt_mappings);
+	adev->gart.gart_funcs->set_prt(adev, enable);
+	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
+}
+
+/**
+ * amdgpu_vm_prt - callback for updating the PRT status
+ */
+static void amdgpu_vm_prt_cb(struct fence *fence, struct fence_cb *_cb)
+{
+	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
+
+	amdgpu_vm_update_prt_state(cb->adev);
+	kfree(cb);
+}
+
+/**
+ * amdgpu_vm_free_mapping - free a mapping
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requested vm
+ * @mapping: mapping to be freed
+ * @fence: fence of the unmap operation
+ *
+ * Free a mapping and make sure we decrease the PRT usage count if applicable.
+ */
+static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
+				   struct amdgpu_vm *vm,
+				   struct amdgpu_bo_va_mapping *mapping,
+				   struct fence *fence)
+{
+	if ((mapping->flags & AMDGPU_PTE_PRT) &&
+	    atomic_dec_return(&adev->vm_manager.num_prt_mappings) == 0) {
+		struct amdgpu_prt_cb *cb = kmalloc(sizeof(struct amdgpu_prt_cb),
+						   GFP_KERNEL);
+
+		cb->adev = adev;
+		if (!fence || fence_add_callback(fence, &cb->cb,
+						 amdgpu_vm_prt_cb)) {
+			amdgpu_vm_update_prt_state(adev);
+			kfree(cb);
+		}
+	}
+	kfree(mapping);
+}
+
+/**
  * amdgpu_vm_clear_freed - clear freed BOs in the PT
  *
  * @adev: amdgpu_device pointer
@@ -1191,6 +1249,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 			  struct amdgpu_vm *vm)
 {
 	struct amdgpu_bo_va_mapping *mapping;
+	struct fence *fence = NULL;
 	int r;
 
 	while (!list_empty(&vm->freed)) {
@@ -1199,12 +1258,15 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 		list_del(&mapping->list);
 
 		r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
-					       0, 0, NULL);
-		kfree(mapping);
-		if (r)
+					       0, 0, &fence);
+		amdgpu_vm_free_mapping(adev, vm, mapping, fence);
+		if (r) {
+			fence_put(fence);
 			return r;
+		}
 
 	}
+	fence_put(fence);
 	return 0;
 
 }
@@ -1314,6 +1376,15 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
 		return -EINVAL;
 
+	if (flags & AMDGPU_PTE_PRT) {
+		/* Check if we have PRT hardware support */
+		if (!adev->gart.gart_funcs->set_prt)
+			return -EINVAL;
+
+		if (atomic_inc_return(&adev->vm_manager.num_prt_mappings) == 1)
+			amdgpu_vm_update_prt_state(adev);
+	}
+
 	/* make sure object fit at this offset */
 	eaddr = saddr + size - 1;
 	if (saddr >= eaddr ||
@@ -1400,7 +1471,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
 	list_del(&mapping->list);
 	interval_tree_remove(&mapping->it, &vm->va);
 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
-	kfree(mapping);
+	amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
 
 error:
 	return r;
@@ -1452,7 +1523,8 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
 	if (valid)
 		list_add(&mapping->list, &vm->freed);
 	else
-		kfree(mapping);
+		amdgpu_vm_free_mapping(adev, vm, mapping,
+				       bo_va->last_pt_update);
 
 	return 0;
 }
@@ -1488,7 +1560,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
 		list_del(&mapping->list);
 		interval_tree_remove(&mapping->it, &vm->va);
-		kfree(mapping);
+		amdgpu_vm_free_mapping(adev, vm, mapping,
+				       bo_va->last_pt_update);
 	}
 
 	fence_put(bo_va->last_pt_update);
@@ -1625,9 +1698,13 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 		kfree(mapping);
 	}
 	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
+		if (mapping->flags & AMDGPU_PTE_PRT)
+			continue;
+
 		list_del(&mapping->list);
 		kfree(mapping);
 	}
+	amdgpu_vm_clear_freed(adev, vm);
 
 	for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
 		struct amdgpu_bo *pt = vm->page_tables[i].bo;
@@ -1672,6 +1749,8 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
 
 	atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
 	atomic64_set(&adev->vm_manager.client_counter, 0);
+	spin_lock_init(&adev->vm_manager.prt_lock);
+	atomic_set(&adev->vm_manager.num_prt_mappings, 0);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1f99715..4d26e9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -65,6 +65,8 @@ struct amdgpu_bo_list_entry;
 
 #define AMDGPU_PTE_FRAG(x)	((x & 0x1f) << 7)
 
+#define AMDGPU_PTE_PRT		(1UL << 63)
+
 /* How to programm VM fault handling */
 #define AMDGPU_VM_FAULT_STOP_NEVER	0
 #define AMDGPU_VM_FAULT_STOP_FIRST	1
@@ -159,6 +161,10 @@ struct amdgpu_vm_manager {
 	atomic_t				vm_pte_next_ring;
 	/* client id counter */
 	atomic64_t				client_counter;
+
+	/* partial resident texture handling */
+	spinlock_t				prt_lock;
+	atomic_t				num_prt_mappings;
 };
 
 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
-- 
2.5.0

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[PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Christian König]

From: Junwei Zhang <Jerry.Zhang@amd.com>

Till GFX8 we can only enable PRT support globally, but with the next hardware
generation we can do this on a per page basis.

Keep the interface consistent by adding PRT mappings and enable
support globally on current hardware when the first mapping is made.

v2: disable PRT support delayed and on all error paths
v3: PRT and other permissions are mutal exclusive,
    PRT mappings don't need a BO.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62 ++++++++++++++++++++-------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++
 include/uapi/drm/amdgpu_drm.h           |  2 ++
 4 files changed, 51 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 34a971a..99ca5e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
 
 struct amdgpu_fpriv {
 	struct amdgpu_vm	vm;
+	struct amdgpu_bo_va	*prt_va;
 	struct mutex		bo_list_lock;
 	struct idr		bo_list_handles;
 	struct amdgpu_ctx_mgr	ctx_mgr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 1dc59aa..f3e9051 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *filp)
 {
+	const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
+		AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+		AMDGPU_VM_PAGE_EXECUTABLE;
+	const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
+		AMDGPU_VM_PAGE_PRT;
+
 	struct drm_amdgpu_gem_va *args = data;
 	struct drm_gem_object *gobj;
 	struct amdgpu_device *adev = dev->dev_private;
@@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	struct ttm_validate_buffer tv;
 	struct ww_acquire_ctx ticket;
 	struct list_head list;
-	uint32_t invalid_flags, va_flags = 0;
+	uint32_t va_flags = 0;
 	int r = 0;
 
 	if (!adev->vm_manager.enabled)
@@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
-	invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
-			AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
-	if ((args->flags & invalid_flags)) {
-		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
-			args->flags, invalid_flags);
+	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
+		dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
+			args->flags);
 		return -EINVAL;
 	}
 
@@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
-	gobj = drm_gem_object_lookup(filp, args->handle);
-	if (gobj == NULL)
-		return -ENOENT;
-	abo = gem_to_amdgpu_bo(gobj);
 	INIT_LIST_HEAD(&list);
-	tv.bo = &abo->tbo;
-	tv.shared = false;
-	list_add(&tv.head, &list);
+	if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
+		gobj = drm_gem_object_lookup(filp, args->handle);
+		if (gobj == NULL)
+			return -ENOENT;
+		abo = gem_to_amdgpu_bo(gobj);
+		tv.bo = &abo->tbo;
+		tv.shared = false;
+		list_add(&tv.head, &list);
+	} else {
+		gobj = NULL;
+		abo = NULL;
+	}
 
 	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
 
 	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
-	if (r) {
-		drm_gem_object_unreference_unlocked(gobj);
-		return r;
-	}
+	if (r)
+		goto error_unref;
 
-	bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
-	if (!bo_va) {
-		ttm_eu_backoff_reservation(&ticket, &list);
-		drm_gem_object_unreference_unlocked(gobj);
-		return -ENOENT;
+	if (abo) {
+		bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
+		if (!bo_va) {
+			r = -ENOENT;
+			goto error_backoff;
+		}
+	} else {
+		bo_va = fpriv->prt_va;
 	}
 
 	switch (args->operation) {
@@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 			va_flags |= AMDGPU_PTE_WRITEABLE;
 		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
 			va_flags |= AMDGPU_PTE_EXECUTABLE;
+		if (args->flags & AMDGPU_VM_PAGE_PRT)
+			va_flags |= AMDGPU_PTE_PRT;
 		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 				     args->offset_in_bo, args->map_size,
 				     va_flags);
@@ -624,11 +636,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	default:
 		break;
 	}
-	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
-	    !amdgpu_vm_debug)
+	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
 		amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
+
+error_backoff:
 	ttm_eu_backoff_reservation(&ticket, &list);
 
+error_unref:
 	drm_gem_object_unreference_unlocked(gobj);
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 215f73b..d5f9d6a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -656,6 +656,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 		goto out_suspend;
 	}
 
+	fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
+	if (!fpriv->prt_va) {
+		r = -ENOMEM;
+		amdgpu_vm_fini(adev, &fpriv->vm);
+		kfree(fpriv);
+		goto out_suspend;
+	}
+
 	if (amdgpu_sriov_vf(adev)) {
 		r = amdgpu_map_static_csa(adev, &fpriv->vm);
 		if (r)
@@ -700,6 +708,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
 	amdgpu_uvd_free_handles(adev, file_priv);
 	amdgpu_vce_free_handles(adev, file_priv);
 
+	amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
+
 	if (amdgpu_sriov_vf(adev)) {
 		/* TODO: how to handle reserve failure */
 		BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 2cf8df8..07e3710 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -363,6 +363,8 @@ struct drm_amdgpu_gem_op {
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
+/* partially resident texture */
+#define AMDGPU_VM_PAGE_PRT		(1 << 4)
 
 struct drm_amdgpu_gem_va {
 	/** GEM object handle */
-- 
2.5.0

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[PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2

[Christian König]

From: Christian König <christian.koenig@amd.com>

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: write to the correct register, adjust bits to that hw generation

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 55 +++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index e2b0b16..b9b5c24 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -398,6 +398,60 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 	WREG32(mmVM_CONTEXT1_CNTL, tmp);
 }
 
+ /**
+   + * gmc_v8_0_set_prt - set PRT VM fault
+   + *
+   + * @adev: amdgpu_device pointer
+   + * @enable: enable/disable VM fault handling for PRT
+   +*/
+static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+	u32 tmp;
+
+	if (enable && !adev->mc.prt_warning) {
+		dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
+		adev->mc.prt_warning = true;
+	}
+
+	tmp = RREG32(mmVM_PRT_CNTL);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
+			    enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
+			    enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L2_CACHE_STORE_INVALID_ENTRIES,
+			    enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L1_TLB_STORE_INVALID_ENTRIES,
+			    enable);
+	WREG32(mmVM_PRT_CNTL, tmp);
+
+	if (enable) {
+		uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+		uint32_t high = adev->vm_manager.max_pfn;
+
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+	} else {
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+	}
+}
+
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
 	int r, i;
@@ -1080,6 +1134,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
+	.set_prt = gmc_v6_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
-- 
2.5.0

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[PATCH 5/6] drm/amdgpu: implement PRT for GFX7 v2

[Christian König]

From: Christian König <christian.koenig@amd.com>

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: set correct register

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 57 +++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 99ca5e8..d8516dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -571,6 +571,7 @@ struct amdgpu_mc {
 	uint32_t		vram_type;
 	uint32_t                srbm_soft_reset;
 	struct amdgpu_mode_mc_save save;
+	bool			prt_warning;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 8d05e0c..4b38d06 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -481,6 +481,62 @@ static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 }
 
 /**
+ * gmc_v7_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+ */
+static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+	uint32_t tmp;
+
+	if (enable && !adev->mc.prt_warning) {
+		dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
+		adev->mc.prt_warning = true;
+	}
+
+	tmp = RREG32(mmVM_PRT_CNTL);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L2_CACHE_STORE_INVALID_ENTRIES, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L1_TLB_STORE_INVALID_ENTRIES, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    MASK_PDE0_FAULT, enable);
+	WREG32(mmVM_PRT_CNTL, tmp);
+
+	if (enable) {
+		uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+		uint32_t high = adev->vm_manager.max_pfn;
+
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+	} else {
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+	}
+}
+
+/**
  * gmc_v7_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1259,6 +1315,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
+	.set_prt = gmc_v7_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
-- 
2.5.0

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[PATCH 6/6] drm/amdgpu: implement PRT for GFX8 v2

[Christian König]

From: Christian König <christian.koenig@amd.com>

Enable/disable the handling globally for now and
print a warning when we enable it for the first time.

v2: set correct register

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 57 +++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 7669b32..a68b850 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -595,6 +595,62 @@ static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 }
 
 /**
+ * gmc_v8_0_set_prt - set PRT VM fault
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable VM fault handling for PRT
+*/
+static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
+{
+	u32 tmp;
+
+	if (enable && !adev->mc.prt_warning) {
+		dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
+		adev->mc.prt_warning = true;
+	}
+
+	tmp = RREG32(mmVM_PRT_CNTL);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L2_CACHE_STORE_INVALID_ENTRIES, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    L1_TLB_STORE_INVALID_ENTRIES, enable);
+	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
+			    MASK_PDE0_FAULT, enable);
+	WREG32(mmVM_PRT_CNTL, tmp);
+
+	if (enable) {
+		uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
+		uint32_t high = adev->vm_manager.max_pfn;
+
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
+	} else {
+		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
+		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
+		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
+	}
+}
+
+/**
  * gmc_v8_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -1485,6 +1541,7 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
+	.set_prt = gmc_v8_0_set_prt,
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
-- 
2.5.0

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Re: PRT support for amdgpu v2

[Bas Nieuwenhuizen]

What branch is this based on? It fails to apply for me on
drm-next-4.11-wip of Alex' git repo.

On Thu, Feb 2, 2017, at 11:25, Christian König wrote:
> Hi guys,
> 
> a bunch of bug fixes, but still completely untested since I'm on sick
> leave.
> 
> Bas maybe you could give it a try with radv.
> 
> Regards,
> Christian.
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: PRT support for amdgpu v2

[Alex Deucher]

On Thu, Feb 2, 2017 at 4:05 PM, Bas Nieuwenhuizen
<bas@basnieuwenhuizen.nl> wrote:
> What branch is this based on? It fails to apply for me on
> drm-next-4.11-wip of Alex' git repo.

Probably amd-staging-4.9

Alex

>
> On Thu, Feb 2, 2017, at 11:25, Christian König wrote:
>> Hi guys,
>>
>> a bunch of bug fixes, but still completely untested since I'm on sick
>> leave.
>>
>> Bas maybe you could give it a try with radv.
>>
>> Regards,
>> Christian.
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Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2

[Nicolai Hähnle]

On 02.02.2017 11:25, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Enable/disable the handling globally for now and
> print a warning when we enable it for the first time.
>
> v2: write to the correct register, adjust bits to that hw generation
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 55 +++++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index e2b0b16..b9b5c24 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -398,6 +398,60 @@ static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
>  	WREG32(mmVM_CONTEXT1_CNTL, tmp);
>  }
>
> + /**
> +   + * gmc_v8_0_set_prt - set PRT VM fault
> +   + *
> +   + * @adev: amdgpu_device pointer
> +   + * @enable: enable/disable VM fault handling for PRT
> +   +*/
> +static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
> +{
> +	u32 tmp;
> +
> +	if (enable && !adev->mc.prt_warning) {
> +		dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
> +		adev->mc.prt_warning = true;
> +	}
> +
> +	tmp = RREG32(mmVM_PRT_CNTL);
> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> +			    CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
> +			    enable);

I get:

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c: In function ‘gmc_v6_0_set_prt’:
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c:419:27: error: 
‘VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK’ undeclared 
(first use in this function)
   tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
                            ^
and similar compiler errors here. The other patches compile fine.

Nicolai

> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> +			    TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
> +			    enable);
> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> +			    L2_CACHE_STORE_INVALID_ENTRIES,
> +			    enable);
> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> +			    L1_TLB_STORE_INVALID_ENTRIES,
> +			    enable);
> +	WREG32(mmVM_PRT_CNTL, tmp);
> +
> +	if (enable) {
> +		uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
> +		uint32_t high = adev->vm_manager.max_pfn;
> +
> +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
> +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
> +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
> +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
> +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
> +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
> +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
> +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
> +	} else {
> +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
> +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
> +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
> +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
> +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
> +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
> +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
> +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
> +	}
> +}
> +
>  static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
>  {
>  	int r, i;
> @@ -1080,6 +1134,7 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
>  static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
>  	.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
>  	.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
> +	.set_prt = gmc_v6_0_set_prt,
>  };
>
>  static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
>
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Re: [PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Bas Nieuwenhuizen]

I get an error when trying to map a PRT region:

[   41.588224] BUG: unable to handle kernel NULL pointer dereference at
00000000000001e8
[   41.589899] IP: [<ffffffffa0578fa6>]
ttm_eu_reserve_buffers+0x136/0x370 [ttm]
[   41.590424] PGD 0 

[   41.590943] Oops: 0000 [#1] PREEMPT SMP
[   41.591468] Modules linked in: uvcvideo videobuf2_vmalloc
videobuf2_memops videobuf2_v4l2 videobuf2_core snd_usb_audio videodev
snd_usbmidi_lib snd_rawmidi media snd_seq_device nct6775 hwmon_vid
cdc_acm ext4 crc16 jbd2 fscrypto mbcache nls_iso8859_1 intel_rapl
x86_pkg_temp_thermal nls_cp437 intel_powerclamp vfat coretemp fat
kvm_intel kvm irqbypass iTCO_wdt crct10dif_pclmul amdkfd crc32_pclmul
ghash_clmulni_intel amd_iommu_v2 iTCO_vendor_support amdgpu radeon
mei_wdt aesni_intel aes_x86_64 lrw gf128mul glue_helper ablk_helper
cryptd ttm drm_kms_helper intel_cstate intel_rapl_perf psmouse pcspkr
drm syscopyarea sysfillrect input_leds sysimgblt i2c_i801 evdev alx
joydev led_class mousedev fb_sys_fops lpc_ich i2c_smbus mac_hid mdio
i2c_algo_bit snd_hda_codec_realtek snd_hda_codec_generic
snd_hda_codec_hdmi
[   41.593415]  battery snd_hda_intel fjes nuvoton_cir snd_hda_codec
rc_core video soc_button_array snd_hda_core snd_hwdep mei_me button
snd_pcm mei snd_timer snd tpm_tis shpchp tpm_tis_core soundcore tpm
sch_fq_codel fuse ip_tables x_tables btrfs xor raid6_pq hid_generic
usbhid hid sd_mod serio_raw atkbd libps2 xhci_pci ahci libahci ehci_pci
xhci_hcd ehci_hcd libata crc32c_intel scsi_mod usbcore usb_common i8042
serio
[   41.595473] CPU: 1 PID: 469 Comm: deqp-vk Not tainted 4.9.0-amdgpu+
#2
[   41.596148] Hardware name: To Be Filled By O.E.M. To Be Filled By
O.E.M./B85 Killer, BIOS P1.50 07/11/2014
[   41.596829] task: ffff880429280000 task.stack: ffffc9000a5cc000
[   41.597517] RIP: 0010:[<ffffffffa0578fa6>]  [<ffffffffa0578fa6>]
ttm_eu_reserve_buffers+0x136/0x370 [ttm]
[   41.598220] RSP: 0018:ffffc9000a5cfb00  EFLAGS: 00010286
[   41.598978] RAX: 0000000000000000 RBX: ffffc9000a5cfb68 RCX:
ffffc9000a5cfb78
[   41.599760] RDX: ffff88040c415d00 RSI: ffffc9000a5cfb88 RDI:
0000000000000000
[   41.600558] RBP: ffffc9000a5cfb50 R08: 0000000000000004 R09:
00000000001000a0
[   41.601348] R10: 00000000fffffff2 R11: ffff880429280000 R12:
0000000000000000
[   41.602154] R13: 0000000000000058 R14: ffff880410ee76c0 R15:
ffffc9000a5cfba0
[   41.602926] FS:  00007f75deecb780(0000) GS:ffff88043dc80000(0000)
knlGS:0000000000000000
[   41.603690] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   41.604447] CR2: 00000000000001e8 CR3: 000000040e64a000 CR4:
00000000001406e0
[   41.605205] Stack:
[   41.605972]  ffff88042982a600 ffffc9000a5cfb78 01000000fffffe00
ffffc9000a5cfba0
[   41.606766]  ffffc9000a5cfb88 ffff88041d1f0000 0000000000000001
ffffc9000a5cfb68
[   41.607582]  ffff880410ee76c0 ffffc9000a5cfb78 ffffc9000a5cfc40
ffffffffa0808e38
[   41.608408] Call Trace:
[   41.609248]  [<ffffffffa0808e38>] amdgpu_gem_va_update_vm+0xb8/0x1c0
[amdgpu]
[   41.610091]  [<ffffffff8135c701>] ? interval_tree_iter_next+0x21/0x70
[   41.610946]  [<ffffffffa080a1b7>] amdgpu_gem_va_ioctl+0x2b7/0x350
[amdgpu]
[   41.611773]  [<ffffffff8136b67b>] ?
__percpu_counter_compare+0x3b/0x90
[   41.612578]  [<ffffffffa021ce01>] ?
__btrfs_btree_balance_dirty+0x41/0x80 [btrfs]
[   41.613409]  [<ffffffffa04b4277>] drm_ioctl+0x227/0x4c0 [drm]
[   41.614342]  [<ffffffffa0809f00>] ?
amdgpu_gem_metadata_ioctl+0x1e0/0x1e0 [amdgpu]
[   41.615166]  [<ffffffffa02403ff>] ? btrfs_file_write_iter+0x1df/0x560
[btrfs]
[   41.615989]  [<ffffffff814446df>] ? tty_write+0x1df/0x300
[   41.616862]  [<ffffffffa07ed062>] amdgpu_drm_ioctl+0x62/0xa0 [amdgpu]
[   41.617738]  [<ffffffff8124b612>] do_vfs_ioctl+0xb2/0x600
[   41.618601]  [<ffffffff812370cb>] ? vfs_write+0x14b/0x1b0
[   41.619448]  [<ffffffff8124bbe8>] SyS_ioctl+0x88/0xa0
[   41.620311]  [<ffffffff81679cb7>] entry_SYSCALL_64_fastpath+0x1a/0xa9
[   41.621212] Code: 0a 48 89 71 08 49 89 0f 49 89 57 08 48 89 32 49 89
c7 4d 8b 3f 4c 39 fb 4c 89 7d c8 0f 84 67 01 00 00 48 83 7d d0 00 4d 8b
6f 10 <49> 8b bd 90 01 00 00 0f 84 a7 00 00 00 80 7d c7 00 48 8b 75 d0 
[   41.622165] RIP  [<ffffffffa0578fa6>]
ttm_eu_reserve_buffers+0x136/0x370 [ttm]
[   41.623138]  RSP <ffffc9000a5cfb00>
[   41.624017] CR2: 00000000000001e8
[   41.630632] ---[ end trace f1fc48bc614df131 ]---

However, when I specify AMDGPU_VM_DELAY_UPDATE too, it is gone, and
seems to work.

(side note: when is that flag useful and when not? I was under the
impression that map/unmap operations always waited until the last CS
submitted before the op was complete. In what case would it be useful to
map/unmap earlier than next CS?)

- Bas

On Thu, Feb 2, 2017, at 11:25, Christian König wrote:
> From: Junwei Zhang <Jerry.Zhang@amd.com>
> 
> Till GFX8 we can only enable PRT support globally, but with the next
> hardware
> generation we can do this on a per page basis.
> 
> Keep the interface consistent by adding PRT mappings and enable
> support globally on current hardware when the first mapping is made.
> 
> v2: disable PRT support delayed and on all error paths
> v3: PRT and other permissions are mutal exclusive,
>     PRT mappings don't need a BO.
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62
>  ++++++++++++++++++++-------------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++
>  include/uapi/drm/amdgpu_drm.h           |  2 ++
>  4 files changed, 51 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 34a971a..99ca5e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
>  
>  struct amdgpu_fpriv {
>  	struct amdgpu_vm	vm;
> +       struct amdgpu_bo_va     *prt_va;
>  	struct mutex		bo_list_lock;
>  	struct idr		bo_list_handles;
>  	struct amdgpu_ctx_mgr	ctx_mgr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 1dc59aa..f3e9051 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct
> amdgpu_device *adev,
>  int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>  			  struct drm_file *filp)
>  {
> +       const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
> +               AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
> +               AMDGPU_VM_PAGE_EXECUTABLE;
> +       const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
> +               AMDGPU_VM_PAGE_PRT;
> +
>  	struct drm_amdgpu_gem_va *args = data;
>  	struct drm_gem_object *gobj;
>  	struct amdgpu_device *adev = dev->dev_private;
> @@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  	struct ttm_validate_buffer tv;
>  	struct ww_acquire_ctx ticket;
>  	struct list_head list;
> -       uint32_t invalid_flags, va_flags = 0;
> +       uint32_t va_flags = 0;
>  	int r = 0;
>  
>  	if (!adev->vm_manager.enabled)
> @@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  		return -EINVAL;
>  	}
>  
> -       invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE |
> AMDGPU_VM_PAGE_READABLE |
> -                       AMDGPU_VM_PAGE_WRITEABLE |
> AMDGPU_VM_PAGE_EXECUTABLE);
> -       if ((args->flags & invalid_flags)) {
> -               dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs
> 0x%08X\n",
> -                       args->flags, invalid_flags);
> +       if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
> +               dev_err(&dev->pdev->dev, "invalid flags combination
> 0x%08X\n",
> +                       args->flags);
>  		return -EINVAL;
>  	}
>  
> @@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> void *data,
>  		return -EINVAL;
>  	}
>  
> -       gobj = drm_gem_object_lookup(filp, args->handle);
> -       if (gobj == NULL)
> -               return -ENOENT;
> -       abo = gem_to_amdgpu_bo(gobj);
>  	INIT_LIST_HEAD(&list);
> -       tv.bo = &abo->tbo;
> -       tv.shared = false;
> -       list_add(&tv.head, &list);
> +       if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
> +               gobj = drm_gem_object_lookup(filp, args->handle);
> +               if (gobj == NULL)
> +                       return -ENOENT;
> +               abo = gem_to_amdgpu_bo(gobj);
> +               tv.bo = &abo->tbo;
> +               tv.shared = false;
> +               list_add(&tv.head, &list);
> +       } else {
> +               gobj = NULL;
> +               abo = NULL;
> +       }
>  
>  	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
>  
>  	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
> -       if (r) {
> -               drm_gem_object_unreference_unlocked(gobj);
> -               return r;
> -       }
> +       if (r)
> +               goto error_unref;
>  
> -       bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> -       if (!bo_va) {
> -               ttm_eu_backoff_reservation(&ticket, &list);
> -               drm_gem_object_unreference_unlocked(gobj);
> -               return -ENOENT;
> +       if (abo) {
> +               bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> +               if (!bo_va) {
> +                       r = -ENOENT;
> +                       goto error_backoff;
> +               }
> +       } else {
> +               bo_va = fpriv->prt_va;
>  	}
>  
>  	switch (args->operation) {
> @@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  			va_flags |= AMDGPU_PTE_WRITEABLE;
>  		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
>  			va_flags |= AMDGPU_PTE_EXECUTABLE;
> +               if (args->flags & AMDGPU_VM_PAGE_PRT)
> +                       va_flags |= AMDGPU_PTE_PRT;
>  		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
>  				     args->offset_in_bo, args->map_size,
>  				     va_flags);
> @@ -624,11 +636,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> void *data,
>  	default:
>  		break;
>  	}
> -       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
> -           !amdgpu_vm_debug)
> +       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
> !amdgpu_vm_debug)
>  		amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
> +
> +error_backoff:
>  	ttm_eu_backoff_reservation(&ticket, &list);
>  
> +error_unref:
>  	drm_gem_object_unreference_unlocked(gobj);
>  	return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 215f73b..d5f9d6a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -656,6 +656,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev,
> struct drm_file *file_priv)
>  		goto out_suspend;
>  	}
>  
> +       fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
> +       if (!fpriv->prt_va) {
> +               r = -ENOMEM;
> +               amdgpu_vm_fini(adev, &fpriv->vm);
> +               kfree(fpriv);
> +               goto out_suspend;
> +       }
> +
>  	if (amdgpu_sriov_vf(adev)) {
>  		r = amdgpu_map_static_csa(adev, &fpriv->vm);
>  		if (r)
> @@ -700,6 +708,8 @@ void amdgpu_driver_postclose_kms(struct drm_device
> *dev,
>  	amdgpu_uvd_free_handles(adev, file_priv);
>  	amdgpu_vce_free_handles(adev, file_priv);
>  
> +       amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
> +
>  	if (amdgpu_sriov_vf(adev)) {
>  		/* TODO: how to handle reserve failure */
>  		BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
> diff --git a/include/uapi/drm/amdgpu_drm.h
> b/include/uapi/drm/amdgpu_drm.h
> index 2cf8df8..07e3710 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -363,6 +363,8 @@ struct drm_amdgpu_gem_op {
>  #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
>  /* executable mapping, new for VI */
>  #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
> +/* partially resident texture */
> +#define AMDGPU_VM_PAGE_PRT             (1 << 4)
>  
>  struct drm_amdgpu_gem_va {
>  	/** GEM object handle */
> -- 
> 2.5.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Bas Nieuwenhuizen]

On Sat, Feb 4, 2017, at 20:14, Bas Nieuwenhuizen wrote:
> I get an error when trying to map a PRT region:
> 
> [   41.588224] BUG: unable to handle kernel NULL pointer dereference at
> 00000000000001e8
> [   41.589899] IP: [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]
> [   41.590424] PGD 0 
> 
> [   41.590943] Oops: 0000 [#1] PREEMPT SMP
> [   41.591468] Modules linked in: uvcvideo videobuf2_vmalloc
> videobuf2_memops videobuf2_v4l2 videobuf2_core snd_usb_audio videodev
> snd_usbmidi_lib snd_rawmidi media snd_seq_device nct6775 hwmon_vid
> cdc_acm ext4 crc16 jbd2 fscrypto mbcache nls_iso8859_1 intel_rapl
> x86_pkg_temp_thermal nls_cp437 intel_powerclamp vfat coretemp fat
> kvm_intel kvm irqbypass iTCO_wdt crct10dif_pclmul amdkfd crc32_pclmul
> ghash_clmulni_intel amd_iommu_v2 iTCO_vendor_support amdgpu radeon
> mei_wdt aesni_intel aes_x86_64 lrw gf128mul glue_helper ablk_helper
> cryptd ttm drm_kms_helper intel_cstate intel_rapl_perf psmouse pcspkr
> drm syscopyarea sysfillrect input_leds sysimgblt i2c_i801 evdev alx
> joydev led_class mousedev fb_sys_fops lpc_ich i2c_smbus mac_hid mdio
> i2c_algo_bit snd_hda_codec_realtek snd_hda_codec_generic
> snd_hda_codec_hdmi
> [   41.593415]  battery snd_hda_intel fjes nuvoton_cir snd_hda_codec
> rc_core video soc_button_array snd_hda_core snd_hwdep mei_me button
> snd_pcm mei snd_timer snd tpm_tis shpchp tpm_tis_core soundcore tpm
> sch_fq_codel fuse ip_tables x_tables btrfs xor raid6_pq hid_generic
> usbhid hid sd_mod serio_raw atkbd libps2 xhci_pci ahci libahci ehci_pci
> xhci_hcd ehci_hcd libata crc32c_intel scsi_mod usbcore usb_common i8042
> serio
> [   41.595473] CPU: 1 PID: 469 Comm: deqp-vk Not tainted 4.9.0-amdgpu+
> #2
> [   41.596148] Hardware name: To Be Filled By O.E.M. To Be Filled By
> O.E.M./B85 Killer, BIOS P1.50 07/11/2014
> [   41.596829] task: ffff880429280000 task.stack: ffffc9000a5cc000
> [   41.597517] RIP: 0010:[<ffffffffa0578fa6>]  [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]
> [   41.598220] RSP: 0018:ffffc9000a5cfb00  EFLAGS: 00010286
> [   41.598978] RAX: 0000000000000000 RBX: ffffc9000a5cfb68 RCX:
> ffffc9000a5cfb78
> [   41.599760] RDX: ffff88040c415d00 RSI: ffffc9000a5cfb88 RDI:
> 0000000000000000
> [   41.600558] RBP: ffffc9000a5cfb50 R08: 0000000000000004 R09:
> 00000000001000a0
> [   41.601348] R10: 00000000fffffff2 R11: ffff880429280000 R12:
> 0000000000000000
> [   41.602154] R13: 0000000000000058 R14: ffff880410ee76c0 R15:
> ffffc9000a5cfba0
> [   41.602926] FS:  00007f75deecb780(0000) GS:ffff88043dc80000(0000)
> knlGS:0000000000000000
> [   41.603690] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [   41.604447] CR2: 00000000000001e8 CR3: 000000040e64a000 CR4:
> 00000000001406e0
> [   41.605205] Stack:
> [   41.605972]  ffff88042982a600 ffffc9000a5cfb78 01000000fffffe00
> ffffc9000a5cfba0
> [   41.606766]  ffffc9000a5cfb88 ffff88041d1f0000 0000000000000001
> ffffc9000a5cfb68
> [   41.607582]  ffff880410ee76c0 ffffc9000a5cfb78 ffffc9000a5cfc40
> ffffffffa0808e38
> [   41.608408] Call Trace:
> [   41.609248]  [<ffffffffa0808e38>] amdgpu_gem_va_update_vm+0xb8/0x1c0
> [amdgpu]
> [   41.610091]  [<ffffffff8135c701>] ? interval_tree_iter_next+0x21/0x70
> [   41.610946]  [<ffffffffa080a1b7>] amdgpu_gem_va_ioctl+0x2b7/0x350
> [amdgpu]
> [   41.611773]  [<ffffffff8136b67b>] ?
> __percpu_counter_compare+0x3b/0x90
> [   41.612578]  [<ffffffffa021ce01>] ?
> __btrfs_btree_balance_dirty+0x41/0x80 [btrfs]
> [   41.613409]  [<ffffffffa04b4277>] drm_ioctl+0x227/0x4c0 [drm]
> [   41.614342]  [<ffffffffa0809f00>] ?
> amdgpu_gem_metadata_ioctl+0x1e0/0x1e0 [amdgpu]
> [   41.615166]  [<ffffffffa02403ff>] ? btrfs_file_write_iter+0x1df/0x560
> [btrfs]
> [   41.615989]  [<ffffffff814446df>] ? tty_write+0x1df/0x300
> [   41.616862]  [<ffffffffa07ed062>] amdgpu_drm_ioctl+0x62/0xa0 [amdgpu]
> [   41.617738]  [<ffffffff8124b612>] do_vfs_ioctl+0xb2/0x600
> [   41.618601]  [<ffffffff812370cb>] ? vfs_write+0x14b/0x1b0
> [   41.619448]  [<ffffffff8124bbe8>] SyS_ioctl+0x88/0xa0
> [   41.620311]  [<ffffffff81679cb7>] entry_SYSCALL_64_fastpath+0x1a/0xa9
> [   41.621212] Code: 0a 48 89 71 08 49 89 0f 49 89 57 08 48 89 32 49 89
> c7 4d 8b 3f 4c 39 fb 4c 89 7d c8 0f 84 67 01 00 00 48 83 7d d0 00 4d 8b
> 6f 10 <49> 8b bd 90 01 00 00 0f 84 a7 00 00 00 80 7d c7 00 48 8b 75 d0 
> [   41.622165] RIP  [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]
> [   41.623138]  RSP <ffffc9000a5cfb00>
> [   41.624017] CR2: 00000000000001e8
> [   41.630632] ---[ end trace f1fc48bc614df131 ]---
> 
> However, when I specify AMDGPU_VM_DELAY_UPDATE too, it is gone, and
> seems to work.

Scratch that, using AMDGPU_VM_DELAY_UPDATE I get a VM fault, and the
warning from gmc_v8_0_set_prt is never printed. 

> 
> (side note: when is that flag useful and when not? I was under the
> impression that map/unmap operations always waited until the last CS
> submitted before the op was complete. In what case would it be useful to
> map/unmap earlier than next CS?)
> 
> - Bas
> 
> On Thu, Feb 2, 2017, at 11:25, Christian König wrote:
> > From: Junwei Zhang <Jerry.Zhang@amd.com>
> > 
> > Till GFX8 we can only enable PRT support globally, but with the next
> > hardware
> > generation we can do this on a per page basis.
> > 
> > Keep the interface consistent by adding PRT mappings and enable
> > support globally on current hardware when the first mapping is made.
> > 
> > v2: disable PRT support delayed and on all error paths
> > v3: PRT and other permissions are mutal exclusive,
> >     PRT mappings don't need a BO.
> > 
> > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> > Signed-off-by: Christian König <christian.koenig@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62
> >  ++++++++++++++++++++-------------
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++
> >  include/uapi/drm/amdgpu_drm.h           |  2 ++
> >  4 files changed, 51 insertions(+), 24 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 34a971a..99ca5e8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
> >  
> >  struct amdgpu_fpriv {
> >  	struct amdgpu_vm	vm;
> > +       struct amdgpu_bo_va     *prt_va;
> >  	struct mutex		bo_list_lock;
> >  	struct idr		bo_list_handles;
> >  	struct amdgpu_ctx_mgr	ctx_mgr;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > index 1dc59aa..f3e9051 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> > @@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct
> > amdgpu_device *adev,
> >  int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
> >  			  struct drm_file *filp)
> >  {
> > +       const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
> > +               AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
> > +               AMDGPU_VM_PAGE_EXECUTABLE;
> > +       const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
> > +               AMDGPU_VM_PAGE_PRT;
> > +
> >  	struct drm_amdgpu_gem_va *args = data;
> >  	struct drm_gem_object *gobj;
> >  	struct amdgpu_device *adev = dev->dev_private;
> > @@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> > *data,
> >  	struct ttm_validate_buffer tv;
> >  	struct ww_acquire_ctx ticket;
> >  	struct list_head list;
> > -       uint32_t invalid_flags, va_flags = 0;
> > +       uint32_t va_flags = 0;
> >  	int r = 0;
> >  
> >  	if (!adev->vm_manager.enabled)
> > @@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> > *data,
> >  		return -EINVAL;
> >  	}
> >  
> > -       invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE |
> > AMDGPU_VM_PAGE_READABLE |
> > -                       AMDGPU_VM_PAGE_WRITEABLE |
> > AMDGPU_VM_PAGE_EXECUTABLE);
> > -       if ((args->flags & invalid_flags)) {
> > -               dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs
> > 0x%08X\n",
> > -                       args->flags, invalid_flags);
> > +       if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
> > +               dev_err(&dev->pdev->dev, "invalid flags combination
> > 0x%08X\n",
> > +                       args->flags);
> >  		return -EINVAL;
> >  	}
> >  
> > @@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> > void *data,
> >  		return -EINVAL;
> >  	}
> >  
> > -       gobj = drm_gem_object_lookup(filp, args->handle);
> > -       if (gobj == NULL)
> > -               return -ENOENT;
> > -       abo = gem_to_amdgpu_bo(gobj);
> >  	INIT_LIST_HEAD(&list);
> > -       tv.bo = &abo->tbo;
> > -       tv.shared = false;
> > -       list_add(&tv.head, &list);
> > +       if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
> > +               gobj = drm_gem_object_lookup(filp, args->handle);
> > +               if (gobj == NULL)
> > +                       return -ENOENT;
> > +               abo = gem_to_amdgpu_bo(gobj);
> > +               tv.bo = &abo->tbo;
> > +               tv.shared = false;
> > +               list_add(&tv.head, &list);
> > +       } else {
> > +               gobj = NULL;
> > +               abo = NULL;
> > +       }
> >  
> >  	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
> >  
> >  	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
> > -       if (r) {
> > -               drm_gem_object_unreference_unlocked(gobj);
> > -               return r;
> > -       }
> > +       if (r)
> > +               goto error_unref;
> >  
> > -       bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> > -       if (!bo_va) {
> > -               ttm_eu_backoff_reservation(&ticket, &list);
> > -               drm_gem_object_unreference_unlocked(gobj);
> > -               return -ENOENT;
> > +       if (abo) {
> > +               bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> > +               if (!bo_va) {
> > +                       r = -ENOENT;
> > +                       goto error_backoff;
> > +               }
> > +       } else {
> > +               bo_va = fpriv->prt_va;
> >  	}
> >  
> >  	switch (args->operation) {
> > @@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> > *data,
> >  			va_flags |= AMDGPU_PTE_WRITEABLE;
> >  		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
> >  			va_flags |= AMDGPU_PTE_EXECUTABLE;
> > +               if (args->flags & AMDGPU_VM_PAGE_PRT)
> > +                       va_flags |= AMDGPU_PTE_PRT;
> >  		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
> >  				     args->offset_in_bo, args->map_size,
> >  				     va_flags);
> > @@ -624,11 +636,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> > void *data,
> >  	default:
> >  		break;
> >  	}
> > -       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
> > -           !amdgpu_vm_debug)
> > +       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
> > !amdgpu_vm_debug)
> >  		amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
> > +
> > +error_backoff:
> >  	ttm_eu_backoff_reservation(&ticket, &list);
> >  
> > +error_unref:
> >  	drm_gem_object_unreference_unlocked(gobj);
> >  	return r;
> >  }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 215f73b..d5f9d6a4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -656,6 +656,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev,
> > struct drm_file *file_priv)
> >  		goto out_suspend;
> >  	}
> >  
> > +       fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
> > +       if (!fpriv->prt_va) {
> > +               r = -ENOMEM;
> > +               amdgpu_vm_fini(adev, &fpriv->vm);
> > +               kfree(fpriv);
> > +               goto out_suspend;
> > +       }
> > +
> >  	if (amdgpu_sriov_vf(adev)) {
> >  		r = amdgpu_map_static_csa(adev, &fpriv->vm);
> >  		if (r)
> > @@ -700,6 +708,8 @@ void amdgpu_driver_postclose_kms(struct drm_device
> > *dev,
> >  	amdgpu_uvd_free_handles(adev, file_priv);
> >  	amdgpu_vce_free_handles(adev, file_priv);
> >  
> > +       amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
> > +
> >  	if (amdgpu_sriov_vf(adev)) {
> >  		/* TODO: how to handle reserve failure */
> >  		BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
> > diff --git a/include/uapi/drm/amdgpu_drm.h
> > b/include/uapi/drm/amdgpu_drm.h
> > index 2cf8df8..07e3710 100644
> > --- a/include/uapi/drm/amdgpu_drm.h
> > +++ b/include/uapi/drm/amdgpu_drm.h
> > @@ -363,6 +363,8 @@ struct drm_amdgpu_gem_op {
> >  #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
> >  /* executable mapping, new for VI */
> >  #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
> > +/* partially resident texture */
> > +#define AMDGPU_VM_PAGE_PRT             (1 << 4)
> >  
> >  struct drm_amdgpu_gem_va {
> >  	/** GEM object handle */
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Christian König]

Am 04.02.2017 um 20:14 schrieb Bas Nieuwenhuizen:
> I get an error when trying to map a PRT region:
>
> [   41.588224] BUG: unable to handle kernel NULL pointer dereference at
> 00000000000001e8
> [   41.589899] IP: [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]

Oh, yeah the bug is rather obvious when I look into the code, sorry for 
that.

I'm still on sick leave for the next week as well, but going to look 
into this as soon as I can.

Regards,
Christian.

> [   41.590424] PGD 0
>
> [   41.590943] Oops: 0000 [#1] PREEMPT SMP
> [   41.591468] Modules linked in: uvcvideo videobuf2_vmalloc
> videobuf2_memops videobuf2_v4l2 videobuf2_core snd_usb_audio videodev
> snd_usbmidi_lib snd_rawmidi media snd_seq_device nct6775 hwmon_vid
> cdc_acm ext4 crc16 jbd2 fscrypto mbcache nls_iso8859_1 intel_rapl
> x86_pkg_temp_thermal nls_cp437 intel_powerclamp vfat coretemp fat
> kvm_intel kvm irqbypass iTCO_wdt crct10dif_pclmul amdkfd crc32_pclmul
> ghash_clmulni_intel amd_iommu_v2 iTCO_vendor_support amdgpu radeon
> mei_wdt aesni_intel aes_x86_64 lrw gf128mul glue_helper ablk_helper
> cryptd ttm drm_kms_helper intel_cstate intel_rapl_perf psmouse pcspkr
> drm syscopyarea sysfillrect input_leds sysimgblt i2c_i801 evdev alx
> joydev led_class mousedev fb_sys_fops lpc_ich i2c_smbus mac_hid mdio
> i2c_algo_bit snd_hda_codec_realtek snd_hda_codec_generic
> snd_hda_codec_hdmi
> [   41.593415]  battery snd_hda_intel fjes nuvoton_cir snd_hda_codec
> rc_core video soc_button_array snd_hda_core snd_hwdep mei_me button
> snd_pcm mei snd_timer snd tpm_tis shpchp tpm_tis_core soundcore tpm
> sch_fq_codel fuse ip_tables x_tables btrfs xor raid6_pq hid_generic
> usbhid hid sd_mod serio_raw atkbd libps2 xhci_pci ahci libahci ehci_pci
> xhci_hcd ehci_hcd libata crc32c_intel scsi_mod usbcore usb_common i8042
> serio
> [   41.595473] CPU: 1 PID: 469 Comm: deqp-vk Not tainted 4.9.0-amdgpu+
> #2
> [   41.596148] Hardware name: To Be Filled By O.E.M. To Be Filled By
> O.E.M./B85 Killer, BIOS P1.50 07/11/2014
> [   41.596829] task: ffff880429280000 task.stack: ffffc9000a5cc000
> [   41.597517] RIP: 0010:[<ffffffffa0578fa6>]  [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]
> [   41.598220] RSP: 0018:ffffc9000a5cfb00  EFLAGS: 00010286
> [   41.598978] RAX: 0000000000000000 RBX: ffffc9000a5cfb68 RCX:
> ffffc9000a5cfb78
> [   41.599760] RDX: ffff88040c415d00 RSI: ffffc9000a5cfb88 RDI:
> 0000000000000000
> [   41.600558] RBP: ffffc9000a5cfb50 R08: 0000000000000004 R09:
> 00000000001000a0
> [   41.601348] R10: 00000000fffffff2 R11: ffff880429280000 R12:
> 0000000000000000
> [   41.602154] R13: 0000000000000058 R14: ffff880410ee76c0 R15:
> ffffc9000a5cfba0
> [   41.602926] FS:  00007f75deecb780(0000) GS:ffff88043dc80000(0000)
> knlGS:0000000000000000
> [   41.603690] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [   41.604447] CR2: 00000000000001e8 CR3: 000000040e64a000 CR4:
> 00000000001406e0
> [   41.605205] Stack:
> [   41.605972]  ffff88042982a600 ffffc9000a5cfb78 01000000fffffe00
> ffffc9000a5cfba0
> [   41.606766]  ffffc9000a5cfb88 ffff88041d1f0000 0000000000000001
> ffffc9000a5cfb68
> [   41.607582]  ffff880410ee76c0 ffffc9000a5cfb78 ffffc9000a5cfc40
> ffffffffa0808e38
> [   41.608408] Call Trace:
> [   41.609248]  [<ffffffffa0808e38>] amdgpu_gem_va_update_vm+0xb8/0x1c0
> [amdgpu]
> [   41.610091]  [<ffffffff8135c701>] ? interval_tree_iter_next+0x21/0x70
> [   41.610946]  [<ffffffffa080a1b7>] amdgpu_gem_va_ioctl+0x2b7/0x350
> [amdgpu]
> [   41.611773]  [<ffffffff8136b67b>] ?
> __percpu_counter_compare+0x3b/0x90
> [   41.612578]  [<ffffffffa021ce01>] ?
> __btrfs_btree_balance_dirty+0x41/0x80 [btrfs]
> [   41.613409]  [<ffffffffa04b4277>] drm_ioctl+0x227/0x4c0 [drm]
> [   41.614342]  [<ffffffffa0809f00>] ?
> amdgpu_gem_metadata_ioctl+0x1e0/0x1e0 [amdgpu]
> [   41.615166]  [<ffffffffa02403ff>] ? btrfs_file_write_iter+0x1df/0x560
> [btrfs]
> [   41.615989]  [<ffffffff814446df>] ? tty_write+0x1df/0x300
> [   41.616862]  [<ffffffffa07ed062>] amdgpu_drm_ioctl+0x62/0xa0 [amdgpu]
> [   41.617738]  [<ffffffff8124b612>] do_vfs_ioctl+0xb2/0x600
> [   41.618601]  [<ffffffff812370cb>] ? vfs_write+0x14b/0x1b0
> [   41.619448]  [<ffffffff8124bbe8>] SyS_ioctl+0x88/0xa0
> [   41.620311]  [<ffffffff81679cb7>] entry_SYSCALL_64_fastpath+0x1a/0xa9
> [   41.621212] Code: 0a 48 89 71 08 49 89 0f 49 89 57 08 48 89 32 49 89
> c7 4d 8b 3f 4c 39 fb 4c 89 7d c8 0f 84 67 01 00 00 48 83 7d d0 00 4d 8b
> 6f 10 <49> 8b bd 90 01 00 00 0f 84 a7 00 00 00 80 7d c7 00 48 8b 75 d0
> [   41.622165] RIP  [<ffffffffa0578fa6>]
> ttm_eu_reserve_buffers+0x136/0x370 [ttm]
> [   41.623138]  RSP <ffffc9000a5cfb00>
> [   41.624017] CR2: 00000000000001e8
> [   41.630632] ---[ end trace f1fc48bc614df131 ]---
>
> However, when I specify AMDGPU_VM_DELAY_UPDATE too, it is gone, and
> seems to work.
>
> (side note: when is that flag useful and when not? I was under the
> impression that map/unmap operations always waited until the last CS
> submitted before the op was complete. In what case would it be useful to
> map/unmap earlier than next CS?)
>
> - Bas
>
> On Thu, Feb 2, 2017, at 11:25, Christian König wrote:
>> From: Junwei Zhang <Jerry.Zhang@amd.com>
>>
>> Till GFX8 we can only enable PRT support globally, but with the next
>> hardware
>> generation we can do this on a per page basis.
>>
>> Keep the interface consistent by adding PRT mappings and enable
>> support globally on current hardware when the first mapping is made.
>>
>> v2: disable PRT support delayed and on all error paths
>> v3: PRT and other permissions are mutal exclusive,
>>      PRT mappings don't need a BO.
>>
>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62
>>   ++++++++++++++++++++-------------
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++
>>   include/uapi/drm/amdgpu_drm.h           |  2 ++
>>   4 files changed, 51 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 34a971a..99ca5e8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
>>   
>>   struct amdgpu_fpriv {
>>   	struct amdgpu_vm	vm;
>> +       struct amdgpu_bo_va     *prt_va;
>>   	struct mutex		bo_list_lock;
>>   	struct idr		bo_list_handles;
>>   	struct amdgpu_ctx_mgr	ctx_mgr;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index 1dc59aa..f3e9051 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct
>> amdgpu_device *adev,
>>   int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>   			  struct drm_file *filp)
>>   {
>> +       const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
>> +               AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
>> +               AMDGPU_VM_PAGE_EXECUTABLE;
>> +       const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
>> +               AMDGPU_VM_PAGE_PRT;
>> +
>>   	struct drm_amdgpu_gem_va *args = data;
>>   	struct drm_gem_object *gobj;
>>   	struct amdgpu_device *adev = dev->dev_private;
>> @@ -550,7 +556,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
>> *data,
>>   	struct ttm_validate_buffer tv;
>>   	struct ww_acquire_ctx ticket;
>>   	struct list_head list;
>> -       uint32_t invalid_flags, va_flags = 0;
>> +       uint32_t va_flags = 0;
>>   	int r = 0;
>>   
>>   	if (!adev->vm_manager.enabled)
>> @@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
>> *data,
>>   		return -EINVAL;
>>   	}
>>   
>> -       invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE |
>> AMDGPU_VM_PAGE_READABLE |
>> -                       AMDGPU_VM_PAGE_WRITEABLE |
>> AMDGPU_VM_PAGE_EXECUTABLE);
>> -       if ((args->flags & invalid_flags)) {
>> -               dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs
>> 0x%08X\n",
>> -                       args->flags, invalid_flags);
>> +       if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
>> +               dev_err(&dev->pdev->dev, "invalid flags combination
>> 0x%08X\n",
>> +                       args->flags);
>>   		return -EINVAL;
>>   	}
>>   
>> @@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
>> void *data,
>>   		return -EINVAL;
>>   	}
>>   
>> -       gobj = drm_gem_object_lookup(filp, args->handle);
>> -       if (gobj == NULL)
>> -               return -ENOENT;
>> -       abo = gem_to_amdgpu_bo(gobj);
>>   	INIT_LIST_HEAD(&list);
>> -       tv.bo = &abo->tbo;
>> -       tv.shared = false;
>> -       list_add(&tv.head, &list);
>> +       if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
>> +               gobj = drm_gem_object_lookup(filp, args->handle);
>> +               if (gobj == NULL)
>> +                       return -ENOENT;
>> +               abo = gem_to_amdgpu_bo(gobj);
>> +               tv.bo = &abo->tbo;
>> +               tv.shared = false;
>> +               list_add(&tv.head, &list);
>> +       } else {
>> +               gobj = NULL;
>> +               abo = NULL;
>> +       }
>>   
>>   	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
>>   
>>   	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
>> -       if (r) {
>> -               drm_gem_object_unreference_unlocked(gobj);
>> -               return r;
>> -       }
>> +       if (r)
>> +               goto error_unref;
>>   
>> -       bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
>> -       if (!bo_va) {
>> -               ttm_eu_backoff_reservation(&ticket, &list);
>> -               drm_gem_object_unreference_unlocked(gobj);
>> -               return -ENOENT;
>> +       if (abo) {
>> +               bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
>> +               if (!bo_va) {
>> +                       r = -ENOENT;
>> +                       goto error_backoff;
>> +               }
>> +       } else {
>> +               bo_va = fpriv->prt_va;
>>   	}
>>   
>>   	switch (args->operation) {
>> @@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
>> *data,
>>   			va_flags |= AMDGPU_PTE_WRITEABLE;
>>   		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
>>   			va_flags |= AMDGPU_PTE_EXECUTABLE;
>> +               if (args->flags & AMDGPU_VM_PAGE_PRT)
>> +                       va_flags |= AMDGPU_PTE_PRT;
>>   		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
>>   				     args->offset_in_bo, args->map_size,
>>   				     va_flags);
>> @@ -624,11 +636,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
>> void *data,
>>   	default:
>>   		break;
>>   	}
>> -       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
>> -           !amdgpu_vm_debug)
>> +       if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
>> !amdgpu_vm_debug)
>>   		amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
>> +
>> +error_backoff:
>>   	ttm_eu_backoff_reservation(&ticket, &list);
>>   
>> +error_unref:
>>   	drm_gem_object_unreference_unlocked(gobj);
>>   	return r;
>>   }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> index 215f73b..d5f9d6a4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>> @@ -656,6 +656,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev,
>> struct drm_file *file_priv)
>>   		goto out_suspend;
>>   	}
>>   
>> +       fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
>> +       if (!fpriv->prt_va) {
>> +               r = -ENOMEM;
>> +               amdgpu_vm_fini(adev, &fpriv->vm);
>> +               kfree(fpriv);
>> +               goto out_suspend;
>> +       }
>> +
>>   	if (amdgpu_sriov_vf(adev)) {
>>   		r = amdgpu_map_static_csa(adev, &fpriv->vm);
>>   		if (r)
>> @@ -700,6 +708,8 @@ void amdgpu_driver_postclose_kms(struct drm_device
>> *dev,
>>   	amdgpu_uvd_free_handles(adev, file_priv);
>>   	amdgpu_vce_free_handles(adev, file_priv);
>>   
>> +       amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
>> +
>>   	if (amdgpu_sriov_vf(adev)) {
>>   		/* TODO: how to handle reserve failure */
>>   		BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
>> diff --git a/include/uapi/drm/amdgpu_drm.h
>> b/include/uapi/drm/amdgpu_drm.h
>> index 2cf8df8..07e3710 100644
>> --- a/include/uapi/drm/amdgpu_drm.h
>> +++ b/include/uapi/drm/amdgpu_drm.h
>> @@ -363,6 +363,8 @@ struct drm_amdgpu_gem_op {
>>   #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
>>   /* executable mapping, new for VI */
>>   #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
>> +/* partially resident texture */
>> +#define AMDGPU_VM_PAGE_PRT             (1 << 4)
>>   
>>   struct drm_amdgpu_gem_va {
>>   	/** GEM object handle */
>> -- 
>> 2.5.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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RE: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2

[Zhang, Jerry]

Hi all,

We also need below for SI(gmc v6) support.

{{{
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/
index 0f6c6c8..7155312 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
@@ -11891,5 +11891,9 @@
 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003
 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L
 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002
+#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000001L
+#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000000
+#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000002L
+#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000001
}}}

Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_____________________________________


> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Nicolai H?hnle
> Sent: Friday, February 03, 2017 22:37
> To: Christian König; amd-gfx@lists.freedesktop.org
> Cc: bas@basnieuwenhuizen.nl
> Subject: Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2
> 
> On 02.02.2017 11:25, Christian König wrote:
> > From: Christian König <christian.koenig@amd.com>
> >
> > Enable/disable the handling globally for now and print a warning when
> > we enable it for the first time.
> >
> > v2: write to the correct register, adjust bits to that hw generation
> >
> > Signed-off-by: Christian König <christian.koenig@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 55
> > +++++++++++++++++++++++++++++++++++
> >  1 file changed, 55 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > index e2b0b16..b9b5c24 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> > @@ -398,6 +398,60 @@ static void gmc_v6_0_set_fault_enable_default(struct
> amdgpu_device *adev,
> >  	WREG32(mmVM_CONTEXT1_CNTL, tmp);
> >  }
> >
> > + /**
> > +   + * gmc_v8_0_set_prt - set PRT VM fault
> > +   + *
> > +   + * @adev: amdgpu_device pointer
> > +   + * @enable: enable/disable VM fault handling for PRT
> > +   +*/
> > +static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
> > +{
> > +	u32 tmp;
> > +
> > +	if (enable && !adev->mc.prt_warning) {
> > +		dev_warn(adev->dev, "Disabling VM faults because of PRT
> request!\n");
> > +		adev->mc.prt_warning = true;
> > +	}
> > +
> > +	tmp = RREG32(mmVM_PRT_CNTL);
> > +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> > +			    CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
> > +			    enable);
> 
> I get:
> 
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c: In function ‘gmc_v6_0_set_prt’:
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c:419:27: error:
> ‘VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK’
> undeclared (first use in this function)
>    tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>                             ^
> and similar compiler errors here. The other patches compile fine.
> 
> Nicolai
> 
> > +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> > +			    TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
> > +			    enable);
> > +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> > +			    L2_CACHE_STORE_INVALID_ENTRIES,
> > +			    enable);
> > +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
> > +			    L1_TLB_STORE_INVALID_ENTRIES,
> > +			    enable);
> > +	WREG32(mmVM_PRT_CNTL, tmp);
> > +
> > +	if (enable) {
> > +		uint32_t low = AMDGPU_VA_RESERVED_SIZE >>
> AMDGPU_GPU_PAGE_SHIFT;
> > +		uint32_t high = adev->vm_manager.max_pfn;
> > +
> > +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
> > +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
> > +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
> > +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
> > +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
> > +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
> > +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
> > +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
> > +	} else {
> > +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
> > +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
> > +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
> > +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
> > +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
> > +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
> > +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
> > +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
> > +	}
> > +}
> > +
> >  static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)  {
> >  	int r, i;
> > @@ -1080,6 +1134,7 @@ static const struct amd_ip_funcs
> > gmc_v6_0_ip_funcs = {  static const struct amdgpu_gart_funcs
> gmc_v6_0_gart_funcs = {
> >  	.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
> >  	.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
> > +	.set_prt = gmc_v6_0_set_prt,
> >  };
> >
> >  static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
> >
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2

[Christian König]

Hi Jerry,

thanks for the defines. I accidentally compiled the patch without SI 
support, so I didn't noted that they are missing.

Going to integrate them and send out the patch set once more.

Regards,
Christian.

Am 06.02.2017 um 09:51 schrieb Zhang, Jerry:
> Hi all,
>
> We also need below for SI(gmc v6) support.
>
> {{{
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/
> index 0f6c6c8..7155312 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h
> @@ -11891,5 +11891,9 @@
>   #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x00000003
>   #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x00000004L
>   #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x00000002
> +#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000001L
> +#define VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000000
> +#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x00000002L
> +#define VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x00000001
> }}}
>
> Regards,
> Jerry (Junwei Zhang)
>
> Linux Base Graphics
> SRDC Software Development
> _____________________________________
>
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
>> Nicolai H?hnle
>> Sent: Friday, February 03, 2017 22:37
>> To: Christian König; amd-gfx@lists.freedesktop.org
>> Cc: bas@basnieuwenhuizen.nl
>> Subject: Re: [PATCH 4/6] drm/amdgpu: implement PRT for GFX6 v2
>>
>> On 02.02.2017 11:25, Christian König wrote:
>>> From: Christian König <christian.koenig@amd.com>
>>>
>>> Enable/disable the handling globally for now and print a warning when
>>> we enable it for the first time.
>>>
>>> v2: write to the correct register, adjust bits to that hw generation
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 55
>>> +++++++++++++++++++++++++++++++++++
>>>   1 file changed, 55 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> index e2b0b16..b9b5c24 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> @@ -398,6 +398,60 @@ static void gmc_v6_0_set_fault_enable_default(struct
>> amdgpu_device *adev,
>>>   	WREG32(mmVM_CONTEXT1_CNTL, tmp);
>>>   }
>>>
>>> + /**
>>> +   + * gmc_v8_0_set_prt - set PRT VM fault
>>> +   + *
>>> +   + * @adev: amdgpu_device pointer
>>> +   + * @enable: enable/disable VM fault handling for PRT
>>> +   +*/
>>> +static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
>>> +{
>>> +	u32 tmp;
>>> +
>>> +	if (enable && !adev->mc.prt_warning) {
>>> +		dev_warn(adev->dev, "Disabling VM faults because of PRT
>> request!\n");
>>> +		adev->mc.prt_warning = true;
>>> +	}
>>> +
>>> +	tmp = RREG32(mmVM_PRT_CNTL);
>>> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>>> +			    CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
>>> +			    enable);
>> I get:
>>
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c: In function ‘gmc_v6_0_set_prt’:
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c:419:27: error:
>> ‘VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK’
>> undeclared (first use in this function)
>>     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>>                              ^
>> and similar compiler errors here. The other patches compile fine.
>>
>> Nicolai
>>
>>> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>>> +			    TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
>>> +			    enable);
>>> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>>> +			    L2_CACHE_STORE_INVALID_ENTRIES,
>>> +			    enable);
>>> +	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
>>> +			    L1_TLB_STORE_INVALID_ENTRIES,
>>> +			    enable);
>>> +	WREG32(mmVM_PRT_CNTL, tmp);
>>> +
>>> +	if (enable) {
>>> +		uint32_t low = AMDGPU_VA_RESERVED_SIZE >>
>> AMDGPU_GPU_PAGE_SHIFT;
>>> +		uint32_t high = adev->vm_manager.max_pfn;
>>> +
>>> +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
>>> +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
>>> +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
>>> +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
>>> +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
>>> +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
>>> +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
>>> +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
>>> +	} else {
>>> +		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
>>> +		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
>>> +		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
>>> +		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
>>> +		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
>>> +		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
>>> +		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
>>> +		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
>>> +	}
>>> +}
>>> +
>>>   static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)  {
>>>   	int r, i;
>>> @@ -1080,6 +1134,7 @@ static const struct amd_ip_funcs
>>> gmc_v6_0_ip_funcs = {  static const struct amdgpu_gart_funcs
>> gmc_v6_0_gart_funcs = {
>>>   	.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
>>>   	.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
>>> +	.set_prt = gmc_v6_0_set_prt,
>>>   };
>>>
>>>   static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
>>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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RE: [PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3

[Zhang, Jerry]

Hi Christian,

> +	fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
Maybe we cannot add NULL bo to a vm, as it will cause NULL dereference inside amdgpu_vm_bo_add()
by list_add_tail(&bo_va->bo_list, &bo->va);

Regards,
Jerry (Junwei Zhang)

Linux Base Graphics
SRDC Software Development
_____________________________________


> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Christian K?nig
> Sent: Thursday, February 02, 2017 18:25
> To: amd-gfx@lists.freedesktop.org
> Cc: bas@basnieuwenhuizen.nl
> Subject: [PATCH 3/6] drm/amdgpu: IOCTL interface for PRT support v3
> 
> From: Junwei Zhang <Jerry.Zhang@amd.com>
> 
> Till GFX8 we can only enable PRT support globally, but with the next hardware
> generation we can do this on a per page basis.
> 
> Keep the interface consistent by adding PRT mappings and enable support
> globally on current hardware when the first mapping is made.
> 
> v2: disable PRT support delayed and on all error paths
> v3: PRT and other permissions are mutal exclusive,
>     PRT mappings don't need a BO.
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 62 ++++++++++++++++++++--
> -----------  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++
>  include/uapi/drm/amdgpu_drm.h           |  2 ++
>  4 files changed, 51 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 34a971a..99ca5e8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -703,6 +703,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
> 
>  struct amdgpu_fpriv {
>  	struct amdgpu_vm	vm;
> +	struct amdgpu_bo_va	*prt_va;
>  	struct mutex		bo_list_lock;
>  	struct idr		bo_list_handles;
>  	struct amdgpu_ctx_mgr	ctx_mgr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 1dc59aa..f3e9051 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -540,6 +540,12 @@ static void amdgpu_gem_va_update_vm(struct
> amdgpu_device *adev,  int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  			  struct drm_file *filp)
>  {
> +	const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
> +		AMDGPU_VM_PAGE_READABLE |
> AMDGPU_VM_PAGE_WRITEABLE |
> +		AMDGPU_VM_PAGE_EXECUTABLE;
> +	const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
> +		AMDGPU_VM_PAGE_PRT;
> +
>  	struct drm_amdgpu_gem_va *args = data;
>  	struct drm_gem_object *gobj;
>  	struct amdgpu_device *adev = dev->dev_private; @@ -550,7 +556,7 @@
> int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>  	struct ttm_validate_buffer tv;
>  	struct ww_acquire_ctx ticket;
>  	struct list_head list;
> -	uint32_t invalid_flags, va_flags = 0;
> +	uint32_t va_flags = 0;
>  	int r = 0;
> 
>  	if (!adev->vm_manager.enabled)
> @@ -564,11 +570,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  		return -EINVAL;
>  	}
> 
> -	invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE |
> AMDGPU_VM_PAGE_READABLE |
> -			AMDGPU_VM_PAGE_WRITEABLE |
> AMDGPU_VM_PAGE_EXECUTABLE);
> -	if ((args->flags & invalid_flags)) {
> -		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
> -			args->flags, invalid_flags);
> +	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
> +		dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
> +			args->flags);
>  		return -EINVAL;
>  	}
> 
> @@ -582,28 +586,34 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> void *data,
>  		return -EINVAL;
>  	}
> 
> -	gobj = drm_gem_object_lookup(filp, args->handle);
> -	if (gobj == NULL)
> -		return -ENOENT;
> -	abo = gem_to_amdgpu_bo(gobj);
>  	INIT_LIST_HEAD(&list);
> -	tv.bo = &abo->tbo;
> -	tv.shared = false;
> -	list_add(&tv.head, &list);
> +	if (!(args->flags & AMDGPU_VM_PAGE_PRT)) {
> +		gobj = drm_gem_object_lookup(filp, args->handle);
> +		if (gobj == NULL)
> +			return -ENOENT;
> +		abo = gem_to_amdgpu_bo(gobj);
> +		tv.bo = &abo->tbo;
> +		tv.shared = false;
> +		list_add(&tv.head, &list);
> +	} else {
> +		gobj = NULL;
> +		abo = NULL;
> +	}
> 
>  	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
> 
>  	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
> -	if (r) {
> -		drm_gem_object_unreference_unlocked(gobj);
> -		return r;
> -	}
> +	if (r)
> +		goto error_unref;
> 
> -	bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> -	if (!bo_va) {
> -		ttm_eu_backoff_reservation(&ticket, &list);
> -		drm_gem_object_unreference_unlocked(gobj);
> -		return -ENOENT;
> +	if (abo) {
> +		bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
> +		if (!bo_va) {
> +			r = -ENOENT;
> +			goto error_backoff;
> +		}
> +	} else {
> +		bo_va = fpriv->prt_va;
>  	}
> 
>  	switch (args->operation) {
> @@ -614,6 +624,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void
> *data,
>  			va_flags |= AMDGPU_PTE_WRITEABLE;
>  		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
>  			va_flags |= AMDGPU_PTE_EXECUTABLE;
> +		if (args->flags & AMDGPU_VM_PAGE_PRT)
> +			va_flags |= AMDGPU_PTE_PRT;
>  		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
>  				     args->offset_in_bo, args->map_size,
>  				     va_flags);
> @@ -624,11 +636,13 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev,
> void *data,
>  	default:
>  		break;
>  	}
> -	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
> -	    !amdgpu_vm_debug)
> +	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)
> && !amdgpu_vm_debug)
>  		amdgpu_gem_va_update_vm(adev, bo_va, &list, args-
> >operation);
> +
> +error_backoff:
>  	ttm_eu_backoff_reservation(&ticket, &list);
> 
> +error_unref:
>  	drm_gem_object_unreference_unlocked(gobj);
>  	return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 215f73b..d5f9d6a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -656,6 +656,14 @@ int amdgpu_driver_open_kms(struct drm_device *dev,
> struct drm_file *file_priv)
>  		goto out_suspend;
>  	}
> 
> +	fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
> +	if (!fpriv->prt_va) {
> +		r = -ENOMEM;
> +		amdgpu_vm_fini(adev, &fpriv->vm);
> +		kfree(fpriv);
> +		goto out_suspend;
> +	}
> +
>  	if (amdgpu_sriov_vf(adev)) {
>  		r = amdgpu_map_static_csa(adev, &fpriv->vm);
>  		if (r)
> @@ -700,6 +708,8 @@ void amdgpu_driver_postclose_kms(struct drm_device
> *dev,
>  	amdgpu_uvd_free_handles(adev, file_priv);
>  	amdgpu_vce_free_handles(adev, file_priv);
> 
> +	amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
> +
>  	if (amdgpu_sriov_vf(adev)) {
>  		/* TODO: how to handle reserve failure */
>  		BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false)); diff --
> git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 2cf8df8..07e3710 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -363,6 +363,8 @@ struct drm_amdgpu_gem_op {
>  #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
>  /* executable mapping, new for VI */
>  #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
> +/* partially resident texture */
> +#define AMDGPU_VM_PAGE_PRT		(1 << 4)
> 
>  struct drm_amdgpu_gem_va {
>  	/** GEM object handle */
> --
> 2.5.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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