[Qemu-devel] [PATCH Risu 0/7] Risu PPC improvements

[Qemu-devel] [PATCH Risu 0/7] Risu PPC improvements

[Jose Ricardo Ziviani]

This patchset contains some fixes and improvements for ppc64le.

Jose Ricardo Ziviani (7):
  risu_ppc64le: improve xsrqpi[x] and xsrqpxp instructions
  risu_ppc64le: fix 32-bit mov immediate
  risu_ppc64le: implement sign extend for small neg constants
  risu_ppc64le: implement FP random data for test improvement
  risu_ppc64le: stop loading data to register 1 and 13
  risu_ppc64le: remove fancy shell character cont from messages
  risu_ppc64le: fix minor code style in assembly test code

 ppc64.risu             |  9 ++++++---
 risu_reginfo_ppc64le.c |  6 +++---
 risugen_ppc64.pm       | 48 +++++++++++++++++++++++++++++++++++++++++++-----
 test_ppc64le.s         | 20 +++++++++-----------
 4 files changed, 61 insertions(+), 22 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH Risu 1/7] risu_ppc64le: improve xsrqpi[x] and xsrqpxp instructions

[Jose Ricardo Ziviani]

New constraint added to the referred instructions in order to avoid
generation of reserved (not used today) rounding modes for floating
point operations.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 ppc64.risu | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 7b2bfe3..f7fa3f4 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -3019,12 +3019,15 @@ XSREDP PPC64LE 111100 t:5 00000 b:5 00101 1010 bx:1 tx:1
 XSRESP PPC64LE 111100 t:5 00000 b:5 00001 1010 bx:1 tx:1
 
 # format:Z23 book:I page:636 v3.0 xsrqpi[x] VSX Scalar Round QP to Integral
-XSRQPI PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 000001010
+XSRQPI PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 000001010 \
+!constraints { ($r == 0 && ($rmc != 1 && $rmc != 2)) || $r == 1; }
 # format:Z23 book:I page:636 v3.0 xsrqpi[x] VSX Scalar Round QP to Integral
-XSRQPIx PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 000001011
+XSRQPIx PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 000001011 \
+!constraints { ($r == 0 && ($rmc != 1 && $rmc != 2)) || $r == 1; }
 
 # format:Z23 book:I page:638 v3.0 xsrqpxp VSX Scalar Round QP to XP
-XSRQPXP PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 001001010
+XSRQPXP PPC64LE 111111 vrt:5 0000 r:1 vrb:5 rmc:2 001001010 \
+!constraints { ($r == 0 && ($rmc != 1 && $rmc != 2)) || $r == 1; }
 
 # format:XX2 book:I page:640 v2.07 xsrsp VSX Scalar Round DP to SP
 XSRSP PPC64LE 111100 t:5 00000 b:5 10001 1001 bx:1 tx:1
-- 
2.7.4

[Qemu-devel] [PATCH Risu 2/7] risu_ppc64le: fix 32-bit mov immediate

[Jose Ricardo Ziviani]

Two instructions are necessary but the high value should be written
first, shifted 16 bit left, and then or'ed the lower value. This commit
fixes the problem.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen_ppc64.pm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index ca052de..40f3d4f 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -61,8 +61,8 @@ sub write_mov_ri32($$)
 {
     my ($rd, $imm) = @_;
 
-    # li rd,immediate@h
-    write_mov_ri16($rd, ($imm >> 16) & 0xffff);
+    # lis rd,immediate@h
+    insn32(0xf << 26 | $rd << 21 | ($imm >> 16));
     # ori rd,rd,immediate@l
     insn32((0x18 << 26) | ($rd << 21) | ($rd << 16) | ($imm & 0xffff));
 }
-- 
2.7.4

[Qemu-devel] [PATCH Risu 3/7] risu_ppc64le: implement sign extend for small neg constants

[Jose Ricardo Ziviani]

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen_ppc64.pm | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 40f3d4f..561c17b 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -75,6 +75,13 @@ sub write_add_ri($$$)
     insn32((0xe << 26) | ($rt << 21) | ($ra << 16) | ($imm & 0xffff));
 }
 
+sub write_sxt32($$)
+{
+    my ($ra, $rs) = @_;
+
+    insn32((0x1f << 26) | ($rs << 21) | ($ra << 16) | 0x7b4);
+}
+
 sub write_mov_ri($$)
 {
     # We always use a MOVW/MOVT pair, for simplicity.
@@ -87,10 +94,10 @@ sub write_mov_ri($$)
         write_mov_ri16($rd, $imm);
     }
 
-    #if ($is_aarch64 && $imm < 0) {
+    if ($imm < 0) {
         # sign extend to allow small negative imm constants
-    #    write_sxt32($rd, $rd);
-    #}
+        write_sxt32($rd, $rd);
+    }
 }
 
 sub write_random_ppc64_fpdata()
-- 
2.7.4

[Qemu-devel] [PATCH Risu 4/7] risu_ppc64le: implement FP random data for test improvement

[Jose Ricardo Ziviani]

This commit replaces the simple FP data written for tests for a
randomically generated one. This functionality stores the same data in
FP register and VSX[VRB+32] registers.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen_ppc64.pm | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 561c17b..8e323a2 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -100,8 +100,39 @@ sub write_mov_ri($$)
     }
 }
 
+sub write_mov_ri64($$)
+{
+    my ($imh, $iml) = @_;
+
+    # number of bit to shift
+    write_mov_ri16(19, 31);
+    # load the highest 32 bits
+    write_mov_ri32(20, $iml);
+    # shift left 32 bits (sld r20, r20, r19
+    insn32((0x1f << 26) | (20 << 21) | (20 << 16) | (19 << 11) | 0x36);
+    # write the lowest 32bits
+    write_mov_ri32(21, $imh);
+    # or r20, r20, r21
+    insn32((0x1f << 26) | (20 << 21) | (20 << 16) | (21 << 11) | 0x378);
+
+    # std r20, 16(r1)
+    insn32((0x3e << 26) | (20 << 21) | (1 << 16) | 0x10);
+}
+
 sub write_random_ppc64_fpdata()
 {
+    for (my $i = 0; $i < 32; $i++) {
+        # load a random doubleword value at r0
+        write_mov_ri64(rand(0xfffff), rand(0xfffff));
+        # since the EA is r1+16, load such value in FP reg
+        insn32((0x32 << 26) | ($i << 21) | (0x1 << 16) | 0x10);
+        insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12);
+
+    }
+}
+
+sub write_random_ppc64_fpdata_i()
+{
     # get an space from the stack
     insn32(0x3ac10020); # addi r22, r1, 32
     insn32(0x3ee03ff0); # lis r23, 0x3ff0
-- 
2.7.4

[Qemu-devel] [PATCH Risu 5/7] risu_ppc64le: stop loading data to register 1 and 13

[Jose Ricardo Ziviani]

Register R1 is defined as the stack frame pointer and R13 is the thread
local storage by ABI. So, in order to let the program flows, they are
better to keep unchanged.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 test_ppc64le.s | 2 --
 1 file changed, 2 deletions(-)

diff --git a/test_ppc64le.s b/test_ppc64le.s
index 4321751..af23ea3 100644
--- a/test_ppc64le.s
+++ b/test_ppc64le.s
@@ -13,7 +13,6 @@
 
 /* Initialise the gp regs */
 li 0,0
-li 1,1
 li 2,2
 li 3,3
 li 4,4
@@ -25,7 +24,6 @@ li 9,9
 li 10, 10
 li 11, 11
 li 12, 12
-li 13, 13
 li 14, 14
 li 15, 15
 li 16, 16
-- 
2.7.4

[Qemu-devel] [PATCH Risu 6/7] risu_ppc64le: remove fancy shell character cont from messages

[Jose Ricardo Ziviani]

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risu_reginfo_ppc64le.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index 7a54eab..e6bc0e0 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -105,9 +105,9 @@ void reginfo_dump(struct reginfo *ri, int is_master)
 {
     int i;
     if (is_master) {
-        fprintf(stderr, "  faulting insn \e[1;101;37m0x%x\e[0m\n", ri->faulting_insn);
-        fprintf(stderr, "  prev insn     \e[1;101;37m0x%x\e[0m\n", ri->prev_insn);
-        fprintf(stderr, "  prev addr     \e[1;101;37m0x%" PRIx64 "\e[0m\n\n", ri->prev_addr);
+        fprintf(stderr, "  faulting insn 0x%x\n", ri->faulting_insn);
+        fprintf(stderr, "  prev insn     0x%x\n", ri->prev_insn);
+        fprintf(stderr, "  prev addr    0x%" PRIx64 "\n\n", ri->nip);
     }
 
     for (i = 0; i < 16; i++) {
-- 
2.7.4

[Qemu-devel] [PATCH Risu 7/7] risu_ppc64le: fix minor code style in assembly test code

[Jose Ricardo Ziviani]

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 test_ppc64le.s | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/test_ppc64le.s b/test_ppc64le.s
index af23ea3..4af770c 100644
--- a/test_ppc64le.s
+++ b/test_ppc64le.s
@@ -12,15 +12,15 @@
  *****************************************************************************/
 
 /* Initialise the gp regs */
-li 0,0
-li 2,2
-li 3,3
-li 4,4
-li 5,5
-li 6,6
-li 7,7
-li 8,8
-li 9,9
+li 0, 0
+li 2, 2
+li 3, 3
+li 4, 4
+li 5, 5
+li 6, 6
+li 7, 7
+li 8, 8
+li 9, 9
 li 10, 10
 li 11, 11
 li 12, 12
-- 
2.7.4

Re: [Qemu-devel] [PATCH Risu 0/7] Risu PPC improvements

[Peter Maydell]

On 4 February 2017 at 02:17, Jose Ricardo Ziviani
<joserz@linux.vnet.ibm.com> wrote:
> This patchset contains some fixes and improvements for ppc64le.
>
> Jose Ricardo Ziviani (7):
>   risu_ppc64le: improve xsrqpi[x] and xsrqpxp instructions
>   risu_ppc64le: fix 32-bit mov immediate
>   risu_ppc64le: implement sign extend for small neg constants
>   risu_ppc64le: implement FP random data for test improvement
>   risu_ppc64le: stop loading data to register 1 and 13
>   risu_ppc64le: remove fancy shell character cont from messages
>   risu_ppc64le: fix minor code style in assembly test code
>
>  ppc64.risu             |  9 ++++++---
>  risu_reginfo_ppc64le.c |  6 +++---
>  risugen_ppc64.pm       | 48 +++++++++++++++++++++++++++++++++++++++++++-----
>  test_ppc64le.s         | 20 +++++++++-----------
>  4 files changed, 61 insertions(+), 22 deletions(-)

Applied to risu master, thanks.

Regarding the FP random data, we should split out the
write_random_fpreg_var() from the ARM risugen code so
it can be used by any architecture. That produces a
more useful distribution of FP values for testing than a
simple evenly distributed random number does.

thanks
-- PMM