* [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14
@ 2017-02-06 10:29 Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction Nikunj A Dadhania
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-06 10:29 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
This series contains 8 new instructions for POWER9 ISA3.0
VSX Scalar Maximum DP
VSX Scalar Minimum DP
Load/Store Atomic instructions
Balamuruhan S (2):
target-ppc: implement load atomic instruction
target-ppc: implement store atomic instruction
Bharata B Rao (2):
target-ppc: Add xsmaxcdp and xsmincdp instructions
target-ppc: Add xsmaxjdp and xsminjdp instructions
target/ppc/fpu_helper.c | 93 +++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 4 ++
target/ppc/internal.h | 2 +
target/ppc/translate.c | 98 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 4 ++
target/ppc/translate/vsx-ops.inc.c | 4 ++
6 files changed, 205 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
@ 2017-02-06 10:29 ` Nikunj A Dadhania
2017-02-09 1:20 ` David Gibson
2017-02-06 10:29 ` [Qemu-devel] [PATCH 2/4] target-ppc: implement store " Nikunj A Dadhania
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-06 10:29 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, bharata, nikunj, Balamuruhan S, Harish S, Athira Rajeev
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
lwat: Load Word Atomic
ldat: Load Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ combine both lwat/ldat implementation using macro ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/internal.h | 2 ++
target/ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 5b5b180..1f441c6 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -133,6 +133,8 @@ EXTRACT_HELPER(UIMM4, 16, 4);
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
+/* lwat/stwat/ldat/lwat */
+EXTRACT_HELPER(FC, 11, 5);
/* Vector shift count */
EXTRACT_HELPER(VSH, 6, 4);
/* Mask start */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b48abae..f59184f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2976,6 +2976,54 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, DEF_MEMOP(MO_UL))
+#define LD_ATOMIC(name, memop, tp, op, eop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* Fetch and add */ \
+ tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* Fetch and xor */ \
+ tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Fetch and or */ \
+ tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* Fetch and 'and' */ \
+ tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 8: /* Swap */ \
+ tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ default: \
+ /* invoke data storage error handler */ \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ break; \
+ } \
+ tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
+#if defined(TARGET_PPC64)
+LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6230,10 +6278,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
+GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
+GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 2/4] target-ppc: implement store atomic instruction
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction Nikunj A Dadhania
@ 2017-02-06 10:29 ` Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 3/4] target-ppc: Add xsmaxcdp and xsmincdp instructions Nikunj A Dadhania
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-06 10:29 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, bharata, nikunj, Balamuruhan S, Harish S, Athira Rajeev
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
stwat: Store Word Atomic
stdat: Store Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ implement stdat, use macro and combine both implementation ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f59184f..eae85f0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3024,6 +3024,52 @@ LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
#endif
+#define ST_ATOMIC(name, memop, tp, op) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* add and Store */ \
+ tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* xor and Store */ \
+ tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Or and Store */ \
+ tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* 'and' and Store */ \
+ tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 8: /* Swap */ \
+ tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ default: /* invoke data storage error handler */ \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ break; \
+ } \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
+#if defined(TARGET_PPC64)
+ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6279,11 +6325,13 @@ GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 3/4] target-ppc: Add xsmaxcdp and xsmincdp instructions
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 2/4] target-ppc: implement store " Nikunj A Dadhania
@ 2017-02-06 10:29 ` Nikunj A Dadhania
2017-02-06 10:30 ` [Qemu-devel] [PATCH 4/4] target-ppc: Add xsmaxjdp and xsminjdp instructions Nikunj A Dadhania
2017-02-09 1:27 ` [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 David Gibson
4 siblings, 0 replies; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-06 10:29 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision
xsmincdp: VSX Scalar Minimum Type-C Double-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 44 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 48973a9..9d2688e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2679,6 +2679,44 @@ VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
+#define VSX_MAX_MINC(name, max) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ bool vxsnan_flag = false, vex_flag = false; \
+ \
+ getVSR(rA(opcode) + 32, &xa, env); \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
+ float64_is_any_nan(xb.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } else if ((max && \
+ !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
+ (!max && \
+ float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else { \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } \
+ \
+ vex_flag = fpscr_ve & vxsnan_flag; \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (!vex_flag) { \
+ putVSR(rD(opcode) + 32, &xt, env); \
+ } \
+} \
+
+VSX_MAX_MINC(xsmaxcdp, 1);
+VSX_MAX_MINC(xsmincdp, 0);
+
/* VSX_CMP - VSX floating point compare
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3956fd1..fe3267e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -431,6 +431,8 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xsmaxcdp, void, env, i32)
+DEF_HELPER_2(xsmincdp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index a062203..3251dca 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -808,6 +808,8 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 2202c0f..16a135f 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -200,6 +200,8 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
+GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
+GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 4/4] target-ppc: Add xsmaxjdp and xsminjdp instructions
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
` (2 preceding siblings ...)
2017-02-06 10:29 ` [Qemu-devel] [PATCH 3/4] target-ppc: Add xsmaxcdp and xsmincdp instructions Nikunj A Dadhania
@ 2017-02-06 10:30 ` Nikunj A Dadhania
2017-02-09 1:27 ` [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 David Gibson
4 siblings, 0 replies; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-06 10:30 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision
xsminjdp: VSX Scalar Minimum Type-J Double-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/fpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 61 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9d2688e..1b6cd3b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2717,6 +2717,61 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
VSX_MAX_MINC(xsmaxcdp, 1);
VSX_MAX_MINC(xsmincdp, 0);
+#define VSX_MAX_MINJ(name, max) \
+void helper_##name(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, xb; \
+ bool vxsnan_flag = false, vex_flag = false; \
+ \
+ getVSR(rA(opcode) + 32, &xa, env); \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ if (unlikely(float64_is_any_nan(xa.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else if (unlikely(float64_is_any_nan(xb.VsrD(0)))) { \
+ if (float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ } \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } else if (float64_is_zero(xa.VsrD(0)) && float64_is_zero(xb.VsrD(0))) { \
+ if (max) { \
+ if (!float64_is_neg(xa.VsrD(0)) || !float64_is_neg(xb.VsrD(0))) { \
+ xt.VsrD(0) = 0ULL; \
+ } else { \
+ xt.VsrD(0) = 0x8000000000000000ULL; \
+ } \
+ } else { \
+ if (float64_is_neg(xa.VsrD(0)) || float64_is_neg(xb.VsrD(0))) { \
+ xt.VsrD(0) = 0x8000000000000000ULL; \
+ } else { \
+ xt.VsrD(0) = 0ULL; \
+ } \
+ } \
+ } else if ((max && \
+ !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) || \
+ (!max && \
+ float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) { \
+ xt.VsrD(0) = xa.VsrD(0); \
+ } else { \
+ xt.VsrD(0) = xb.VsrD(0); \
+ } \
+ \
+ vex_flag = fpscr_ve & vxsnan_flag; \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (!vex_flag) { \
+ putVSR(rD(opcode) + 32, &xt, env); \
+ } \
+} \
+
+VSX_MAX_MINJ(xsmaxjdp, 1);
+VSX_MAX_MINJ(xsminjdp, 0);
+
/* VSX_CMP - VSX floating point compare
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fe3267e..cc81709 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -433,6 +433,8 @@ DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xsmaxcdp, void, env, i32)
DEF_HELPER_2(xsmincdp, void, env, i32)
+DEF_HELPER_2(xsmaxjdp, void, env, i32)
+DEF_HELPER_2(xsminjdp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 3251dca..8de8cd0 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -810,6 +810,8 @@ GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 16a135f..c1b71ad 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -202,6 +202,8 @@ GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
+GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
+GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction
2017-02-06 10:29 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction Nikunj A Dadhania
@ 2017-02-09 1:20 ` David Gibson
2017-02-09 5:05 ` Nikunj A Dadhania
0 siblings, 1 reply; 8+ messages in thread
From: David Gibson @ 2017-02-09 1:20 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, Balamuruhan S, Harish S,
Athira Rajeev
[-- Attachment #1: Type: text/plain, Size: 6414 bytes --]
On Mon, Feb 06, 2017 at 03:59:57PM +0530, Nikunj A Dadhania wrote:
> From: Balamuruhan S <bala24@linux.vnet.ibm.com>
>
> lwat: Load Word Atomic
> ldat: Load Doubleword Atomic
>
> The instruction includes as function code (5 bits) which gives a detail
> on the operation to be performed. The patch implements five such
> functions.
>
> Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
> Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
> [ combine both lwat/ldat implementation using macro ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target/ppc/internal.h | 2 ++
> target/ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 5b5b180..1f441c6 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -133,6 +133,8 @@ EXTRACT_HELPER(UIMM4, 16, 4);
> EXTRACT_HELPER(NB, 11, 5);
> /* Shift count */
> EXTRACT_HELPER(SH, 11, 5);
> +/* lwat/stwat/ldat/lwat */
> +EXTRACT_HELPER(FC, 11, 5);
> /* Vector shift count */
> EXTRACT_HELPER(VSH, 6, 4);
> /* Mask start */
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b48abae..f59184f 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -2976,6 +2976,54 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
> LARX(lharx, DEF_MEMOP(MO_UW))
> LARX(lwarx, DEF_MEMOP(MO_UL))
>
> +#define LD_ATOMIC(name, memop, tp, op, eop) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + int len = MEMOP_GET_SIZE(memop); \
> + uint32_t gpr_FC = FC(ctx->opcode); \
> + TCGv EA = tcg_temp_local_new(); \
> + TCGv_##tp t0, t1; \
> + \
> + gen_addr_register(ctx, EA); \
> + if (len > 1) { \
> + gen_check_align(ctx, EA, len - 1); \
> + } \
> + t0 = tcg_temp_new_##tp(); \
> + t1 = tcg_temp_new_##tp(); \
> + tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
> + \
> + switch (gpr_FC) { \
> + case 0: /* Fetch and add */ \
> + tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
> + break; \
> + case 1: /* Fetch and xor */ \
> + tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
> + break; \
> + case 2: /* Fetch and or */ \
> + tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
> + break; \
> + case 3: /* Fetch and 'and' */ \
> + tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
> + break; \
> + case 8: /* Swap */ \
> + tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
> + break; \
> + default: \
> + /* invoke data storage error handler */ \
> + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
Both your comment and the ISA say that an invalid FC will result in a
data storage (0x300) exception, but here you seem to be invoking an
invalid instruction exception (0x700). Which is correct?
> + break; \
> + } \
> + tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
> + tcg_temp_free_##tp(t0); \
> + tcg_temp_free_##tp(t1); \
> + tcg_temp_free(EA); \
> +}
> +
> +LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
> +#if defined(TARGET_PPC64)
> +LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
> +#endif
> +
> #if defined(CONFIG_USER_ONLY)
> static void gen_conditional_store(DisasContext *ctx, TCGv EA,
> int reg, int memop)
> @@ -6230,10 +6278,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
> +GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
> #if defined(TARGET_PPC64)
> +GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
> GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
> GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
` (3 preceding siblings ...)
2017-02-06 10:30 ` [Qemu-devel] [PATCH 4/4] target-ppc: Add xsmaxjdp and xsminjdp instructions Nikunj A Dadhania
@ 2017-02-09 1:27 ` David Gibson
4 siblings, 0 replies; 8+ messages in thread
From: David Gibson @ 2017-02-09 1:27 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]
On Mon, Feb 06, 2017 at 03:59:56PM +0530, Nikunj A Dadhania wrote:
> This series contains 8 new instructions for POWER9 ISA3.0
> VSX Scalar Maximum DP
> VSX Scalar Minimum DP
> Load/Store Atomic instructions
>
> Balamuruhan S (2):
> target-ppc: implement load atomic instruction
> target-ppc: implement store atomic instruction
>
> Bharata B Rao (2):
> target-ppc: Add xsmaxcdp and xsmincdp instructions
> target-ppc: Add xsmaxjdp and xsminjdp instructions
>
> target/ppc/fpu_helper.c | 93 +++++++++++++++++++++++++++++++++++
> target/ppc/helper.h | 4 ++
> target/ppc/internal.h | 2 +
> target/ppc/translate.c | 98 +++++++++++++++++++++++++++++++++++++
> target/ppc/translate/vsx-impl.inc.c | 4 ++
> target/ppc/translate/vsx-ops.inc.c | 4 ++
> 6 files changed, 205 insertions(+)
I've applied 3 & 4 to ppc-for-2.9. 1 & 2 I have a query about.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction
2017-02-09 1:20 ` David Gibson
@ 2017-02-09 5:05 ` Nikunj A Dadhania
0 siblings, 0 replies; 8+ messages in thread
From: Nikunj A Dadhania @ 2017-02-09 5:05 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, rth, qemu-devel, bharata, Balamuruhan S, Harish S,
Athira Rajeev
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Mon, Feb 06, 2017 at 03:59:57PM +0530, Nikunj A Dadhania wrote:
>> From: Balamuruhan S <bala24@linux.vnet.ibm.com>
>>
>> lwat: Load Word Atomic
>> ldat: Load Doubleword Atomic
>>
>> The instruction includes as function code (5 bits) which gives a detail
>> on the operation to be performed. The patch implements five such
>> functions.
>>
>> Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
>> Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>> [ combine both lwat/ldat implementation using macro ]
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target/ppc/internal.h | 2 ++
>> target/ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 52 insertions(+)
>>
>> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
>> index 5b5b180..1f441c6 100644
>> --- a/target/ppc/internal.h
>> +++ b/target/ppc/internal.h
>> @@ -133,6 +133,8 @@ EXTRACT_HELPER(UIMM4, 16, 4);
>> EXTRACT_HELPER(NB, 11, 5);
>> /* Shift count */
>> EXTRACT_HELPER(SH, 11, 5);
>> +/* lwat/stwat/ldat/lwat */
>> +EXTRACT_HELPER(FC, 11, 5);
>> /* Vector shift count */
>> EXTRACT_HELPER(VSH, 6, 4);
>> /* Mask start */
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index b48abae..f59184f 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -2976,6 +2976,54 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
>> LARX(lharx, DEF_MEMOP(MO_UW))
>> LARX(lwarx, DEF_MEMOP(MO_UL))
>>
>> +#define LD_ATOMIC(name, memop, tp, op, eop) \
>> +static void gen_##name(DisasContext *ctx) \
>> +{ \
>> + int len = MEMOP_GET_SIZE(memop); \
>> + uint32_t gpr_FC = FC(ctx->opcode); \
>> + TCGv EA = tcg_temp_local_new(); \
>> + TCGv_##tp t0, t1; \
>> + \
>> + gen_addr_register(ctx, EA); \
>> + if (len > 1) { \
>> + gen_check_align(ctx, EA, len - 1); \
>> + } \
>> + t0 = tcg_temp_new_##tp(); \
>> + t1 = tcg_temp_new_##tp(); \
>> + tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
>> + \
>> + switch (gpr_FC) { \
>> + case 0: /* Fetch and add */ \
>> + tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
>> + break; \
>> + case 1: /* Fetch and xor */ \
>> + tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
>> + break; \
>> + case 2: /* Fetch and or */ \
>> + tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
>> + break; \
>> + case 3: /* Fetch and 'and' */ \
>> + tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
>> + break; \
>> + case 8: /* Swap */ \
>> + tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
>> + break; \
>> + default: \
>> + /* invoke data storage error handler */ \
>> + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
>
> Both your comment and the ISA say that an invalid FC will result in a
> data storage (0x300) exception, but here you seem to be invoking an
> invalid instruction exception (0x700). Which is correct?
Ah ok, as there are other FC that is not implemented yet in this
version, it was set as INVALID. Let me separate it out as:
case 4:
case 5:
[...]
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
break;
default:
/* invoke data storage error handler */
gen_exception_err(ctx, POWERPC_EXCP_DSI, 0);
}
Will send updated patch.
Regards
Nikunj
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-02-09 5:06 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-06 10:29 [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 1/4] target-ppc: implement load atomic instruction Nikunj A Dadhania
2017-02-09 1:20 ` David Gibson
2017-02-09 5:05 ` Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 2/4] target-ppc: implement store " Nikunj A Dadhania
2017-02-06 10:29 ` [Qemu-devel] [PATCH 3/4] target-ppc: Add xsmaxcdp and xsmincdp instructions Nikunj A Dadhania
2017-02-06 10:30 ` [Qemu-devel] [PATCH 4/4] target-ppc: Add xsmaxjdp and xsminjdp instructions Nikunj A Dadhania
2017-02-09 1:27 ` [Qemu-devel] [PATCH 0/4] POWER9 TCG enablements - part14 David Gibson
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