* [Qemu-devel] [PATCH v3 1/8] hw/mips_cmgcr: allow GCR base to be moved
@ 2017-02-08 16:31 Yongbok Kim
2017-02-08 21:44 ` Eric Blake
0 siblings, 1 reply; 2+ messages in thread
From: Yongbok Kim @ 2017-02-08 16:31 UTC (permalink / raw)
To: qemu-devel; +Cc: paul.burton, aurelien
From: Paul Burton <paul.burton@imgtec.com>
Support moving the GCR base address & updating the CPU's CP0 CMGCRBase
register appropriately. This is required if a platform needs to move its
GCRs away from other memory, as the MIPS Boston development board does
to avoid its flash memory.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
hw/misc/mips_cmgcr.c | 17 +++++++++++++++++
include/hw/misc/mips_cmgcr.h | 3 +++
2 files changed, 20 insertions(+)
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index b3ba166..a1edb53 100644
--- a/hw/misc/mips_cmgcr.c
+++ b/hw/misc/mips_cmgcr.c
@@ -29,6 +29,20 @@ static inline bool is_gic_connected(MIPSGCRState *s)
return s->gic_mr != NULL;
}
+static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val)
+{
+ CPUState *cpu;
+ MIPSCPU *mips_cpu;
+
+ gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK;
+ memory_region_set_address(&gcr->iomem, gcr->gcr_base);
+
+ CPU_FOREACH(cpu) {
+ mips_cpu = MIPS_CPU(cpu);
+ mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4;
+ }
+}
+
static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
{
if (is_cpc_connected(gcr)) {
@@ -117,6 +131,9 @@ static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
switch (addr) {
+ case GCR_BASE_OFS:
+ update_gcr_base(gcr, data);
+ break;
case GCR_GIC_BASE_OFS:
update_gic_base(gcr, data);
break;
diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
index a209d91..c9dfcb4 100644
--- a/include/hw/misc/mips_cmgcr.h
+++ b/include/hw/misc/mips_cmgcr.h
@@ -41,6 +41,9 @@
#define GCR_L2_CONFIG_BYPASS_SHF 20
#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
+/* GCR_BASE register fields */
+#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL
+
/* GCR_GIC_BASE register fields */
#define GCR_GIC_BASE_GICEN_MSK 1
#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/8] hw/mips_cmgcr: allow GCR base to be moved
2017-02-08 16:31 [Qemu-devel] [PATCH v3 1/8] hw/mips_cmgcr: allow GCR base to be moved Yongbok Kim
@ 2017-02-08 21:44 ` Eric Blake
0 siblings, 0 replies; 2+ messages in thread
From: Eric Blake @ 2017-02-08 21:44 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: aurelien, paul.burton
[-- Attachment #1: Type: text/plain, Size: 805 bytes --]
On 02/08/2017 10:31 AM, Yongbok Kim wrote:
> From: Paul Burton <paul.burton@imgtec.com>
The 0/8 cover letter was sent with this header:
Message-ID: <1486571463-16183-1-git-send-email-yongbok.kim@imgtec.com>
but your individual patches were sent with no In-Reply-To: or
References: headers; therefore, each message appears as its own
top-level thread. When reposting, please make sure your series is
properly threaded.
>
> Support moving the GCR base address & updating the CPU's CP0 CMGCRBase
> register appropriately. This is required if a platform needs to move its
> GCRs away from other memory, as the MIPS Boston development board does
> to avoid its flash memory.
>
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
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