* [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14
@ 2017-02-09 5:33 Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction Nikunj A Dadhania
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Nikunj A Dadhania @ 2017-02-09 5:33 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
This series contains 4 new instructions for POWER9 ISA3.0
Load/Store Atomic instructions
Changelog:
v0:
Raise invalid execption for function codes that are not implemented,
and data storage execption for invalid function codes.
Balamuruhan S (2):
target-ppc: implement load atomic instruction
target-ppc: implement store atomic instruction
target/ppc/internal.h | 2 +
target/ppc/translate.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction
2017-02-09 5:33 [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 Nikunj A Dadhania
@ 2017-02-09 5:33 ` Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 2/2] target-ppc: implement store " Nikunj A Dadhania
2017-02-09 23:58 ` [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Nikunj A Dadhania @ 2017-02-09 5:33 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, bharata, nikunj, Balamuruhan S, Harish S, Athira Rajeev
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
lwat: Load Word Atomic
ldat: Load Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ combine both lwat/ldat implementation using macro ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/internal.h | 2 ++
target/ppc/translate.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 5b5b180..1f441c6 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -133,6 +133,8 @@ EXTRACT_HELPER(UIMM4, 16, 4);
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
+/* lwat/stwat/ldat/lwat */
+EXTRACT_HELPER(FC, 11, 5);
/* Vector shift count */
EXTRACT_HELPER(VSH, 6, 4);
/* Mask start */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b48abae..ea2ec44 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2976,6 +2976,63 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
LARX(lharx, DEF_MEMOP(MO_UW))
LARX(lwarx, DEF_MEMOP(MO_UL))
+#define LD_ATOMIC(name, memop, tp, op, eop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* Fetch and add */ \
+ tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* Fetch and xor */ \
+ tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Fetch and or */ \
+ tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* Fetch and 'and' */ \
+ tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 8: /* Swap */ \
+ tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 4: /* Fetch and max unsigned */ \
+ case 5: /* Fetch and max signed */ \
+ case 6: /* Fetch and min unsigned */ \
+ case 7: /* Fetch and min signed */ \
+ case 16: /* compare and swap not equal */ \
+ case 24: /* Fetch and increment bounded */ \
+ case 25: /* Fetch and increment equal */ \
+ case 28: /* Fetch and decrement bounded */ \
+ gen_invalid(ctx); \
+ break; \
+ default: \
+ /* invoke data storage error handler */ \
+ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
+ } \
+ tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
+#if defined(TARGET_PPC64)
+LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6230,10 +6287,12 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
+GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
+GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH v1 2/2] target-ppc: implement store atomic instruction
2017-02-09 5:33 [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction Nikunj A Dadhania
@ 2017-02-09 5:33 ` Nikunj A Dadhania
2017-02-09 23:58 ` [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Nikunj A Dadhania @ 2017-02-09 5:33 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, bharata, nikunj, Balamuruhan S, Harish S, Athira Rajeev
From: Balamuruhan S <bala24@linux.vnet.ibm.com>
stwat: Store Word Atomic
stdat: Store Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com>
Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com>
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[ implement stdat, use macro and combine both implementation ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target/ppc/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ea2ec44..255735a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3033,6 +3033,56 @@ LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
#endif
+#define ST_ATOMIC(name, memop, tp, op) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int len = MEMOP_GET_SIZE(memop); \
+ uint32_t gpr_FC = FC(ctx->opcode); \
+ TCGv EA = tcg_temp_local_new(); \
+ TCGv_##tp t0, t1; \
+ \
+ gen_addr_register(ctx, EA); \
+ if (len > 1) { \
+ gen_check_align(ctx, EA, len - 1); \
+ } \
+ t0 = tcg_temp_new_##tp(); \
+ t1 = tcg_temp_new_##tp(); \
+ tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
+ \
+ switch (gpr_FC) { \
+ case 0: /* add and Store */ \
+ tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 1: /* xor and Store */ \
+ tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 2: /* Or and Store */ \
+ tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 3: /* 'and' and Store */ \
+ tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
+ break; \
+ case 4: /* Store max unsigned */ \
+ case 5: /* Store max signed */ \
+ case 6: /* Store min unsigned */ \
+ case 7: /* Store min signed */ \
+ case 24: /* Store twin */ \
+ gen_invalid(ctx); \
+ break; \
+ default: \
+ /* invoke data storage error handler */ \
+ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
+ } \
+ tcg_temp_free_##tp(t0); \
+ tcg_temp_free_##tp(t1); \
+ tcg_temp_free(EA); \
+}
+
+ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
+#if defined(TARGET_PPC64)
+ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
+#endif
+
#if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int memop)
@@ -6288,11 +6338,13 @@ GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14
2017-02-09 5:33 [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 2/2] target-ppc: implement store " Nikunj A Dadhania
@ 2017-02-09 23:58 ` David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2017-02-09 23:58 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 842 bytes --]
On Thu, Feb 09, 2017 at 11:03:29AM +0530, Nikunj A Dadhania wrote:
> This series contains 4 new instructions for POWER9 ISA3.0
> Load/Store Atomic instructions
>
> Changelog:
> v0:
> Raise invalid execption for function codes that are not implemented,
> and data storage execption for invalid function codes.
>
> Balamuruhan S (2):
> target-ppc: implement load atomic instruction
> target-ppc: implement store atomic instruction
>
> target/ppc/internal.h | 2 +
> target/ppc/translate.c | 111 +++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 113 insertions(+)
Applied to ppc-for-2.9.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-02-10 0:39 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-09 5:33 [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 1/2] target-ppc: implement load atomic instruction Nikunj A Dadhania
2017-02-09 5:33 ` [Qemu-devel] [PATCH v1 2/2] target-ppc: implement store " Nikunj A Dadhania
2017-02-09 23:58 ` [Qemu-devel] [PATCH v1 0/2] POWER9 TCG enablements - part14 David Gibson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.