From: Leo Yan <leo.yan@linaro.org>
To: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Leo Yan <leo.yan@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: [PATCH v1 0/2] coresight: enable debug module
Date: Thu, 23 Feb 2017 09:57:45 +0800 [thread overview]
Message-ID: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> (raw)
ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
Sample-based Profiling Extension" has description for sampling
registers, we can utilize these registers to check program counter
value with combined CPU exception level, secure state, etc. So this is
helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
with IRQ disabled; the 'hang' CPU cannot switch context and handle any
interrupt, so it cannot handle SMP call for stack dump, etc.
This patch series is to enable coresight debug module with sample-based
registers and register call back notifier for PCSR register dumping
when panic happens, so we can see below dumping info for panic; and
this patch series has considered the conditions for access permission
for debug registers self, so this can avoid access debug registers when
CPU power domain is off; the driver also try to figure out the CPU is
in secure or non-secure state.
ARM external debug module:
CPU[0]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff00000808eb54>] handle_IPI+0xe4/0x150
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
CPU[1]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff0000087a64c0>] debug_notifier_call+0x108/0x288
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[...]
This patch series has been verified on 96boards Hikey.
Changes from RFC:
* According to Mike Leach suggestion, added check for EDPRSR to avoid
lockup; added supporting EDVIDSR and EDCIDSR registers;
* According to Mark Rutland and Mathieu Poirier suggestion, rewrote
the documentation for DT binding;
* According to Mark and Mathieu suggestion, refined debug driver;
Leo Yan (2):
coresight: bindings for debug module
coresight: add support for debug module
.../devicetree/bindings/arm/coresight-debug.txt | 39 ++
drivers/hwtracing/coresight/Kconfig | 10 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-debug.c | 396 +++++++++++++++++++++
4 files changed, 446 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt
create mode 100644 drivers/hwtracing/coresight/coresight-debug.c
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
To: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Mathieu Poirier
<mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
mike.leach-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org
Subject: [PATCH v1 0/2] coresight: enable debug module
Date: Thu, 23 Feb 2017 09:57:45 +0800 [thread overview]
Message-ID: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> (raw)
ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
Sample-based Profiling Extension" has description for sampling
registers, we can utilize these registers to check program counter
value with combined CPU exception level, secure state, etc. So this is
helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
with IRQ disabled; the 'hang' CPU cannot switch context and handle any
interrupt, so it cannot handle SMP call for stack dump, etc.
This patch series is to enable coresight debug module with sample-based
registers and register call back notifier for PCSR register dumping
when panic happens, so we can see below dumping info for panic; and
this patch series has considered the conditions for access permission
for debug registers self, so this can avoid access debug registers when
CPU power domain is off; the driver also try to figure out the CPU is
in secure or non-secure state.
ARM external debug module:
CPU[0]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff00000808eb54>] handle_IPI+0xe4/0x150
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
CPU[1]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff0000087a64c0>] debug_notifier_call+0x108/0x288
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[...]
This patch series has been verified on 96boards Hikey.
Changes from RFC:
* According to Mike Leach suggestion, added check for EDPRSR to avoid
lockup; added supporting EDVIDSR and EDCIDSR registers;
* According to Mark Rutland and Mathieu Poirier suggestion, rewrote
the documentation for DT binding;
* According to Mark and Mathieu suggestion, refined debug driver;
Leo Yan (2):
coresight: bindings for debug module
coresight: add support for debug module
.../devicetree/bindings/arm/coresight-debug.txt | 39 ++
drivers/hwtracing/coresight/Kconfig | 10 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-debug.c | 396 +++++++++++++++++++++
4 files changed, 446 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt
create mode 100644 drivers/hwtracing/coresight/coresight-debug.c
--
2.7.4
--
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WARNING: multiple messages have this Message-ID (diff)
From: leo.yan@linaro.org (Leo Yan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 0/2] coresight: enable debug module
Date: Thu, 23 Feb 2017 09:57:45 +0800 [thread overview]
Message-ID: <1487815067-27511-1-git-send-email-leo.yan@linaro.org> (raw)
ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
Sample-based Profiling Extension" has description for sampling
registers, we can utilize these registers to check program counter
value with combined CPU exception level, secure state, etc. So this is
helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
with IRQ disabled; the 'hang' CPU cannot switch context and handle any
interrupt, so it cannot handle SMP call for stack dump, etc.
This patch series is to enable coresight debug module with sample-based
registers and register call back notifier for PCSR register dumping
when panic happens, so we can see below dumping info for panic; and
this patch series has considered the conditions for access permission
for debug registers self, so this can avoid access debug registers when
CPU power domain is off; the driver also try to figure out the CPU is
in secure or non-secure state.
ARM external debug module:
CPU[0]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff00000808eb54>] handle_IPI+0xe4/0x150
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
CPU[1]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff0000087a64c0>] debug_notifier_call+0x108/0x288
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[...]
This patch series has been verified on 96boards Hikey.
Changes from RFC:
* According to Mike Leach suggestion, added check for EDPRSR to avoid
lockup; added supporting EDVIDSR and EDCIDSR registers;
* According to Mark Rutland and Mathieu Poirier suggestion, rewrote
the documentation for DT binding;
* According to Mark and Mathieu suggestion, refined debug driver;
Leo Yan (2):
coresight: bindings for debug module
coresight: add support for debug module
.../devicetree/bindings/arm/coresight-debug.txt | 39 ++
drivers/hwtracing/coresight/Kconfig | 10 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-debug.c | 396 +++++++++++++++++++++
4 files changed, 446 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt
create mode 100644 drivers/hwtracing/coresight/coresight-debug.c
--
2.7.4
next reply other threads:[~2017-02-23 1:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-23 1:57 Leo Yan [this message]
2017-02-23 1:57 ` [PATCH v1 0/2] coresight: enable debug module Leo Yan
2017-02-23 1:57 ` Leo Yan
2017-02-23 1:57 ` [PATCH v1 1/2] coresight: bindings for " Leo Yan
2017-02-23 1:57 ` Leo Yan
2017-02-23 1:57 ` Leo Yan
2017-02-27 12:37 ` Mike Leach
2017-02-27 12:37 ` Mike Leach
2017-02-27 12:37 ` Mike Leach
2017-02-27 15:34 ` Leo Yan
2017-02-27 15:34 ` Leo Yan
2017-02-23 1:57 ` [PATCH v1 2/2] coresight: add support " Leo Yan
2017-02-23 1:57 ` Leo Yan
2017-02-23 1:57 ` Leo Yan
2017-02-24 19:07 ` Mathieu Poirier
2017-02-24 19:07 ` Mathieu Poirier
2017-02-26 14:07 ` Leo Yan
2017-02-26 14:07 ` Leo Yan
2017-02-26 14:07 ` Leo Yan
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