* [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors
@ 2017-03-06 13:05 Andrew Rybchenko
2017-03-06 13:05 ` [PATCH 2/2] net/sfc: remove Tx DMA descriptor boundary crossing limit Andrew Rybchenko
2017-03-08 17:41 ` [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Ferruh Yigit
0 siblings, 2 replies; 3+ messages in thread
From: Andrew Rybchenko @ 2017-03-06 13:05 UTC (permalink / raw)
To: dev
Siena has limitation on maximum byte count and 4k boundary crosssing
(which is stricter than maximum byte count).
EF10 has limitation on maximum byte count only.
Fixes: f7dc06bf35f2 ("net/sfc/base: import 5xxx/6xxx family support")
Fixes: e7cd430c864f ("net/sfc/base: import SFN7xxx family support")
Fixes: 94190e3543bf ("net/sfc/base: import SFN8xxx family support")
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_tx.c | 9 +++++----
drivers/net/sfc/base/efx.h | 7 +++++++
drivers/net/sfc/base/efx_tx.c | 16 ++++++++++++----
drivers/net/sfc/base/hunt_nic.c | 4 ++++
drivers/net/sfc/base/medford_nic.c | 4 ++++
drivers/net/sfc/base/siena_nic.c | 4 ++++
6 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/net/sfc/base/ef10_tx.c b/drivers/net/sfc/base/ef10_tx.c
index aa19cce..0f48a6c 100644
--- a/drivers/net/sfc/base/ef10_tx.c
+++ b/drivers/net/sfc/base/ef10_tx.c
@@ -435,8 +435,9 @@ ef10_tx_qpost(
size_t offset;
efx_qword_t qword;
- /* Fragments must not span 4k boundaries. */
- EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
+ /* No limitations on boundary crossing */
+ EFSYS_ASSERT(size <=
+ etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
id = added++ & etp->et_mask;
offset = id * sizeof (efx_qword_t);
@@ -551,8 +552,8 @@ ef10_tx_qdesc_dma_create(
__in boolean_t eop,
__out efx_desc_t *edp)
{
- /* Fragments must not span 4k boundaries. */
- EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
+ /* No limitations on boundary crossing */
+ EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
efsys_dma_addr_t, addr,
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index 0815d7a..ac702f3 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1154,6 +1154,13 @@ typedef struct efx_nic_cfg_s {
uint32_t enc_rx_batch_max;
/* Number of rx descriptors the hardware requires for a push. */
uint32_t enc_rx_push_align;
+ /* Maximum amount of data in DMA descriptor */
+ uint32_t enc_tx_dma_desc_size_max;
+ /*
+ * Boundary which DMA descriptor data must not cross or 0 if no
+ * limitation.
+ */
+ uint32_t enc_tx_dma_desc_boundary;
/*
* Maximum number of bytes into the packet the TCP header can start for
* the hardware to apply TSO packet edits.
diff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c
index 0d47390..ceb2920 100644
--- a/drivers/net/sfc/base/efx_tx.c
+++ b/drivers/net/sfc/base/efx_tx.c
@@ -745,8 +745,12 @@ siena_tx_qpost(
size_t size = ebp->eb_size;
efsys_dma_addr_t end = start + size;
- /* Fragments must not span 4k boundaries. */
- EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end);
+ /*
+ * Fragments must not span 4k boundaries.
+ * Here it is a stricter requirement than the maximum length.
+ */
+ EFSYS_ASSERT(P2ROUNDUP(start + 1,
+ etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= end);
EFX_TX_DESC(etp, start, size, ebp->eb_eop, added);
}
@@ -1005,8 +1009,12 @@ siena_tx_qdesc_dma_create(
__in boolean_t eop,
__out efx_desc_t *edp)
{
- /* Fragments must not span 4k boundaries. */
- EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
+ /*
+ * Fragments must not span 4k boundaries.
+ * Here it is a stricter requirement than the maximum length.
+ */
+ EFSYS_ASSERT(P2ROUNDUP(addr + 1,
+ etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= addr + size);
EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
efsys_dma_addr_t, addr,
diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index c2c4d74..addbf1c 100644
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -301,6 +301,10 @@ hunt_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
+ encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
+ /* No boundary crossing limits */
+ encp->enc_tx_dma_desc_boundary = 0;
+
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 6ad68c6..07afac1 100644
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -298,6 +298,10 @@ medford_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
+ encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
+ /* No boundary crossing limits */
+ encp->enc_tx_dma_desc_boundary = 0;
+
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c
index 1f8c4e7..129b854 100644
--- a/drivers/net/sfc/base/siena_nic.c
+++ b/drivers/net/sfc/base/siena_nic.c
@@ -135,6 +135,10 @@ siena_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = 1;
+ encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
+ /* Fragments must not span 4k boundaries. */
+ encp->enc_tx_dma_desc_boundary = 4096;
+
/* Resource limits */
rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
if (rc != 0) {
--
2.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] net/sfc: remove Tx DMA descriptor boundary crossing limit
2017-03-06 13:05 [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Andrew Rybchenko
@ 2017-03-06 13:05 ` Andrew Rybchenko
2017-03-08 17:41 ` [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Ferruh Yigit
1 sibling, 0 replies; 3+ messages in thread
From: Andrew Rybchenko @ 2017-03-06 13:05 UTC (permalink / raw)
To: dev
EF10 supported by the PMD has no limitations on address boundary
crossing by Tx DMA descriptors.
Fixes: 428c7ddd2f16 ("net/sfc: send bursts of packets")
Fixes: fec33d5bb3eb ("net/sfc: support firmware-assisted TSO")
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/sfc_tso.c | 11 ++++-------
drivers/net/sfc/sfc_tx.c | 24 +++++++++++++++++++++---
drivers/net/sfc/sfc_tx.h | 7 +------
3 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/net/sfc/sfc_tso.c b/drivers/net/sfc/sfc_tso.c
index 68d84c9..d3398b1 100644
--- a/drivers/net/sfc/sfc_tso.c
+++ b/drivers/net/sfc/sfc_tso.c
@@ -50,7 +50,7 @@ sfc_tso_alloc_tsoh_objs(struct sfc_tx_sw_desc *sw_ring,
for (i = 0; i < txq_entries; ++i) {
sw_ring[i].tsoh = rte_malloc_socket("sfc-txq-tsoh-obj",
SFC_TSOH_STD_LEN,
- SFC_TX_SEG_BOUNDARY,
+ RTE_CACHE_LINE_SIZE,
socket_id);
if (sw_ring[i].tsoh == NULL)
goto fail_alloc_tsoh_objs;
@@ -116,7 +116,6 @@ sfc_tso_do(struct sfc_txq *txq, unsigned int idx, struct rte_mbuf **in_seg,
uint8_t *tsoh;
const struct tcp_hdr *th;
efsys_dma_addr_t header_paddr;
- efsys_dma_addr_t paddr_next_frag;
uint16_t packet_id;
uint32_t sent_seq;
struct rte_mbuf *m = *in_seg;
@@ -140,17 +139,15 @@ sfc_tso_do(struct sfc_txq *txq, unsigned int idx, struct rte_mbuf **in_seg,
return EMSGSIZE;
header_paddr = rte_pktmbuf_mtophys(m);
- paddr_next_frag = P2ROUNDUP(header_paddr + 1, SFC_TX_SEG_BOUNDARY);
/*
* Sometimes headers may be split across multiple mbufs. In such cases
* we need to glue those pieces and store them in some temporary place.
* Also, packet headers must be contiguous in memory, so that
- * they can be referred to with a single DMA descriptor. Hence, handle
- * the case where the original header crosses a 4K memory boundary
+ * they can be referred to with a single DMA descriptor. EF10 has no
+ * limitations on address boundaries crossing by DMA descriptor data.
*/
- if ((m->data_len < header_len) ||
- ((paddr_next_frag - header_paddr) < header_len)) {
+ if (m->data_len < header_len) {
sfc_tso_prepare_header(txq, in_seg, in_off, idx, header_len);
tsoh = txq->sw_ring[idx & txq->ptr_mask].tsoh;
diff --git a/drivers/net/sfc/sfc_tx.c b/drivers/net/sfc/sfc_tx.c
index 5a6282c..5bb31ad 100644
--- a/drivers/net/sfc/sfc_tx.c
+++ b/drivers/net/sfc/sfc_tx.c
@@ -137,6 +137,7 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
uint16_t nb_tx_desc, unsigned int socket_id,
const struct rte_eth_txconf *tx_conf)
{
+ const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
struct sfc_txq_info *txq_info;
struct sfc_evq *evq;
struct sfc_txq *txq;
@@ -195,6 +196,7 @@ sfc_tx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
txq->ptr_mask = txq_info->entries - 1;
txq->free_thresh = (tx_conf->tx_free_thresh) ? tx_conf->tx_free_thresh :
SFC_TX_DEFAULT_FREE_THRESH;
+ txq->dma_desc_size_max = encp->enc_tx_dma_desc_size_max;
txq->hw_index = sw_index;
txq->flags = tx_conf->txq_flags;
txq->evq = evq;
@@ -302,10 +304,21 @@ sfc_tx_check_mode(struct sfc_adapter *sa, const struct rte_eth_txmode *txmode)
int
sfc_tx_init(struct sfc_adapter *sa)
{
+ const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
const struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
unsigned int sw_index;
int rc = 0;
+ /*
+ * The datapath implementation assumes absence of boundary
+ * limits on Tx DMA descriptors. Addition of these checks on
+ * datapath would simply make the datapath slower.
+ */
+ if (encp->enc_tx_dma_desc_boundary != 0) {
+ rc = ENOTSUP;
+ goto fail_tx_dma_desc_boundary;
+ }
+
rc = sfc_tx_check_mode(sa, &dev_conf->txmode);
if (rc != 0)
goto fail_check_mode;
@@ -334,6 +347,7 @@ sfc_tx_init(struct sfc_adapter *sa)
sa->txq_count = 0;
fail_check_mode:
+fail_tx_dma_desc_boundary:
sfc_log_init(sa, "failed (rc = %d)", rc);
return rc;
}
@@ -704,9 +718,13 @@ sfc_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
efsys_dma_addr_t frag_addr = next_frag;
size_t frag_len;
- next_frag = RTE_ALIGN(frag_addr + 1,
- SFC_TX_SEG_BOUNDARY);
- frag_len = MIN(next_frag - frag_addr, seg_len);
+ /*
+ * It is assumed here that there is no
+ * limitation on address boundary
+ * crossing by DMA descriptor.
+ */
+ frag_len = MIN(seg_len, txq->dma_desc_size_max);
+ next_frag += frag_len;
seg_len -= frag_len;
pkt_len -= frag_len;
diff --git a/drivers/net/sfc/sfc_tx.h b/drivers/net/sfc/sfc_tx.h
index 39977a5..700e92b 100644
--- a/drivers/net/sfc/sfc_tx.h
+++ b/drivers/net/sfc/sfc_tx.h
@@ -39,12 +39,6 @@
extern "C" {
#endif
-/**
- * A segment must not cross 4K boundary
- * (this is a requirement of NIC TX descriptors)
- */
-#define SFC_TX_SEG_BOUNDARY 4096
-
struct sfc_adapter;
struct sfc_evq;
@@ -79,6 +73,7 @@ struct sfc_txq {
unsigned int completed;
unsigned int free_thresh;
uint16_t hw_vlan_tci;
+ uint16_t dma_desc_size_max;
unsigned int hw_index;
unsigned int flags;
--
2.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors
2017-03-06 13:05 [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Andrew Rybchenko
2017-03-06 13:05 ` [PATCH 2/2] net/sfc: remove Tx DMA descriptor boundary crossing limit Andrew Rybchenko
@ 2017-03-08 17:41 ` Ferruh Yigit
1 sibling, 0 replies; 3+ messages in thread
From: Ferruh Yigit @ 2017-03-08 17:41 UTC (permalink / raw)
To: Andrew Rybchenko, dev
On 3/6/2017 1:05 PM, Andrew Rybchenko wrote:
> Siena has limitation on maximum byte count and 4k boundary crosssing
> (which is stricter than maximum byte count).
> EF10 has limitation on maximum byte count only.
>
> Fixes: f7dc06bf35f2 ("net/sfc/base: import 5xxx/6xxx family support")
> Fixes: e7cd430c864f ("net/sfc/base: import SFN7xxx family support")
> Fixes: 94190e3543bf ("net/sfc/base: import SFN8xxx family support")
>
> Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Series applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-03-06 13:05 [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Andrew Rybchenko
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2017-03-08 17:41 ` [PATCH 1/2] net/sfc/base: separate limitations on Tx DMA descriptors Ferruh Yigit
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