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From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 03/20] arm: socfpga: Restructure reset manager driver
Date: Thu,  9 Mar 2017 08:26:41 +0800	[thread overview]
Message-ID: <1489019218-4071-4-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1489019218-4071-1-git-send-email-ley.foon.tan@intel.com>

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files. Minor update in socfpga_per_reset().
No functional change.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile                     |   2 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  42 +-------
 .../mach-socfpga/include/mach/reset_manager_gen5.h |  47 +++++++++
 arch/arm/mach-socfpga/reset_manager.c              |  93 +----------------
 arch/arm/mach-socfpga/reset_manager_gen5.c         | 113 +++++++++++++++++++++
 5 files changed, 168 insertions(+), 129 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
 create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b76de4c..97819ac 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5)	+= scan_manager.o wrap_pll_config.o \
-					   clock_manager_gen5.o
+					   clock_manager_gen5.o reset_manager_gen5.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
 			   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..9e253bf 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,27 +8,12 @@
 #define	_RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
 
 void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	ctrl;
-	u32	counts;
-	u32	padding1;
-	u32	mpu_mod_reset;
-	u32	per_mod_reset;
-	u32	per2_mod_reset;
-	u32	brg_mod_reset;
-	u32	misc_mod_reset;
-	u32	padding2[12];
-	u32	tstscratch;
-};
-
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
@@ -55,28 +40,11 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)			\
 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
-#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
-#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
-#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
-#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
-#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
-#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/reset_manager_gen5.h>
+#endif
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 0000000..028974a
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,47 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_RESET_MANAGER_GEN5_H_
+#define	_RESET_MANAGER_GEN5_H_
+
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	ctrl;
+	u32	counts;
+	u32	padding1;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+	u32	misc_mod_reset;
+	u32	padding2[12];
+	u32	tstscratch;
+};
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
+#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+
+#endif /* _RESET_MANAGER_GEN5_H_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..29438ed 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -7,53 +7,12 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/fpga_manager.h>
 #include <asm/arch/reset_manager.h>
-#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
-/* Assert or de-assert SoCFPGA reset manager reset. */
-void socfpga_per_reset(u32 reset, int set)
-{
-	const void *reg;
-
-	if (RSTMGR_BANK(reset) == 0)
-		reg = &reset_manager_base->mpu_mod_reset;
-	else if (RSTMGR_BANK(reset) == 1)
-		reg = &reset_manager_base->per_mod_reset;
-	else if (RSTMGR_BANK(reset) == 2)
-		reg = &reset_manager_base->per2_mod_reset;
-	else if (RSTMGR_BANK(reset) == 3)
-		reg = &reset_manager_base->brg_mod_reset;
-	else if (RSTMGR_BANK(reset) == 4)
-		reg = &reset_manager_base->misc_mod_reset;
-	else	/* Invalid reset register, do nothing */
-		return;
-
-	if (set)
-		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
-	else
-		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
-}
-
-/*
- * Assert reset on every peripheral but L4WD0.
- * Watchdog must be kept intact to prevent glitches
- * and/or hangs.
- */
-void socfpga_per_reset_all(void)
-{
-	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
-
-	writel(~l4wd0, &reset_manager_base->per_mod_reset);
-	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
-}
 
 /*
  * Write the reset manager register to cause reset
@@ -61,8 +20,8 @@ void socfpga_per_reset_all(void)
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
-	writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
-		&reset_manager_base->ctrl);
+	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
+	       &reset_manager_base->ctrl);
 	/*
 	 * infinite loop here as watchdog will trigger and reset
 	 * the processor
@@ -70,51 +29,3 @@ void reset_cpu(ulong addr)
 	while (1)
 		;
 }
-
-/*
- * Release peripherals from reset based on handoff
- */
-void reset_deassert_peripherals_handoff(void)
-{
-	writel(0, &reset_manager_base->per_mod_reset);
-}
-
-#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-void socfpga_bridges_reset(int enable)
-{
-	/* For SoCFPGA-VT, this is NOP. */
-}
-#else
-
-#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
-#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
-#define L3REGS_REMAP_OCRAM_MASK		0x01
-
-void socfpga_bridges_reset(int enable)
-{
-	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
-				L3REGS_REMAP_HPS2FPGA_MASK |
-				L3REGS_REMAP_OCRAM_MASK;
-
-	if (enable) {
-		/* brdmodrst */
-		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
-	} else {
-		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
-		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
-
-		/* Check signal from FPGA. */
-		if (!fpgamgr_test_fpga_ready()) {
-			/* FPGA not ready, do nothing. */
-			printf("%s: FPGA not ready, aborting.\n", __func__);
-			return;
-		}
-
-		/* brdmodrst */
-		writel(0, &reset_manager_base->brg_mod_reset);
-
-		/* Remap the bridges into memory map */
-		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
-	}
-}
-#endif
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
new file mode 100644
index 0000000..54c0578
--- /dev/null
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -0,0 +1,113 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+	const u32 *reg;
+	u32 rstmgr_bank = RSTMGR_BANK(reset);
+
+	switch (rstmgr_bank) {
+	case 0:
+		reg = &reset_manager_base->mpu_mod_reset;
+		break;
+	case 1:
+		reg = &reset_manager_base->per_mod_reset;
+		break;
+	case 2:
+		reg = &reset_manager_base->per2_mod_reset;
+		break;
+	case 3:
+		reg = &reset_manager_base->brg_mod_reset;
+		break;
+	case 4:
+		reg = &reset_manager_base->misc_mod_reset;
+		break;
+
+	default:
+		return;
+	}
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+	writel(~l4wd0, &reset_manager_base->per_mod_reset);
+	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+	writel(0, &reset_manager_base->per_mod_reset);
+}
+
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+	/* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
+#define L3REGS_REMAP_OCRAM_MASK		0x01
+
+void socfpga_bridges_reset(int enable)
+{
+	const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+				L3REGS_REMAP_HPS2FPGA_MASK |
+				L3REGS_REMAP_OCRAM_MASK;
+
+	if (enable) {
+		/* brdmodrst */
+		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+	} else {
+		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
+		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+
+		/* Check signal from FPGA. */
+		if (!fpgamgr_test_fpga_ready()) {
+			/* FPGA not ready, do nothing. */
+			printf("%s: FPGA not ready, aborting.\n", __func__);
+			return;
+		}
+
+		/* brdmodrst */
+		writel(0, &reset_manager_base->brg_mod_reset);
+
+		/* Remap the bridges into memory map */
+		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+	}
+}
+#endif
-- 
1.8.2.3

  parent reply	other threads:[~2017-03-09  0:26 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-09  0:26 [U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 01/20] arm: socfpga: Restructure clock manager driver Ley Foon Tan
2017-03-09 16:29   ` Dinh Nguyen
2017-03-21  7:26     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 02/20] arm: socfpga: Update clock for Gen5 Ley Foon Tan
2017-03-09 16:39   ` Dinh Nguyen
2017-03-09  0:26 ` Ley Foon Tan [this message]
2017-03-09  0:26 ` [U-Boot] [PATCH v2 04/20] arm: socfpga: Restructure misc driver Ley Foon Tan
2017-03-10  1:36   ` Marek Vasut
2017-03-21  7:44     ` Ley Foon Tan
2017-03-21  8:25       ` Marek Vasut
2017-03-22  8:16         ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 05/20] arm: socfpga: Restructure system manager Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 06/20] arm: socfpga: Add A10 defines Ley Foon Tan
2017-03-10  1:38   ` Marek Vasut
2017-03-21  8:05     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 07/20] arm: socfpga: Add reset driver support for Arria 10 Ley Foon Tan
2017-03-10  1:40   ` Marek Vasut
2017-03-23  5:55     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 08/20] arm: socfpga: Add clock driver " Ley Foon Tan
2017-03-10  1:47   ` Marek Vasut
2017-03-22  6:14     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 09/20] arm: socfpga: Add system manager " Ley Foon Tan
2017-03-10  1:47   ` Marek Vasut
2017-03-09  0:26 ` [U-Boot] [PATCH v2 10/20] arm: socfpga: Add sdram header file " Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 11/20] arm: socfpga: Add misc support " Ley Foon Tan
2017-03-10  1:49   ` Marek Vasut
2017-03-09  0:26 ` [U-Boot] [PATCH v2 12/20] arm: socfpga: Add pinmux " Ley Foon Tan
2017-03-10  1:50   ` Marek Vasut
2017-03-22  6:26     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 13/20] fdt: Add compatible strings " Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 14/20] arm: dts: Add dts and dtsi " Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 15/20] arm: socfpga: Add SPL support " Ley Foon Tan
2017-03-10  1:52   ` Marek Vasut
2017-03-22  8:28     ` Ley Foon Tan
2017-03-22  8:41       ` Marek Vasut
2017-03-22  9:21         ` Ley Foon Tan
2017-03-22 14:46           ` Marek Vasut
2017-03-09  0:26 ` [U-Boot] [PATCH v2 16/20] drivers: fpga: Add compile switch for Gen5 only registers Ley Foon Tan
2017-03-10  1:53   ` Marek Vasut
2017-03-22  8:30     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 17/20] arm: socfpga: Convert Altera ddr driver to use Kconfig Ley Foon Tan
2017-03-10  1:53   ` Marek Vasut
2017-03-22  9:45     ` Ley Foon Tan
2017-03-22 14:26       ` Marek Vasut
2017-03-23  5:36         ` Ley Foon Tan
2017-03-23  7:39           ` Marek Vasut
2017-03-23  9:54             ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 18/20] arm: socfpga: Add config and defconfig for Arria 10 Ley Foon Tan
2017-03-10  1:55   ` Marek Vasut
2017-03-22  8:39     ` Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 19/20] arm: socfpga: Add board files for the Arria10 Ley Foon Tan
2017-03-09  0:26 ` [U-Boot] [PATCH v2 20/20] arm: socfpga: Enable build for Arria 10 Ley Foon Tan
2017-03-09 21:32 ` [U-Boot] [PATCH v2 00/20] Add Intel Arria 10 SoC support Dinh Nguyen
2017-03-10  1:51   ` Marek Vasut
2017-03-16 21:56 ` Marek Vasut
2017-03-17 12:25   ` Ley Foon Tan
2017-03-17 12:28     ` Marek Vasut
2017-03-20  7:33       ` Ley Foon Tan
2017-03-21  8:26         ` Marek Vasut

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