[PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Chris Brandt]

At first this started out as a simple typo fix, until I realized
that the SDHI in the RZ/A1 has 2 clocks per channel and both need
to be turned on/off.

This patch series adds the ability to specify 2 clocks instead of
just 1, and does so for the RZ/A1 r7s72100.

This patch has been tested on an RZ/A1 RSK board. Card detect works
fine as well as bind/unbind.

v6:
* more detailed descritpion in tmio_mmc.txt

v5:
* Take implementation details out of DT documentation and put into
  the driver code.

v4:
* No code changes, only text udpates to explain why there are 2 clocks
  and why we need to treat them as 1 clock.

Chris Brandt (3):
  mmc: sh_mobile_sdhi: add support for 2 clocks
  mmc: sh_mobile_sdhi: explain clock bindings
  ARM: dts: r7s72100: update sdhi clock bindings

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 ++++++++++++
 arch/arm/boot/dts/r7s72100.dtsi                    | 17 +++++++++++-----
 drivers/mmc/host/sh_mobile_sdhi.c                  | 23 ++++++++++++++++++++++
 include/dt-bindings/clock/r7s72100-clock.h         |  6 ++++--
 4 files changed, 52 insertions(+), 7 deletions(-)

-- 
2.10.1

[PATCH v6 1/3] mmc: sh_mobile_sdhi: add support for 2 clocks

[Chris Brandt]

Some controllers have 2 clock sources instead of 1. The 2nd clock
is for the internal card detect logic and must be enabled/disabled
along with the main core clock for proper operation.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v5:
* call clk_disable_unprepare even if clk_cd is NULL
v4:
* add technical explanation within probe routine
v3:
* add more clarification to the commit log
v2:
* changed clk2 to clk_cd
* disable clk if clk_cd enable fails
* changed clock name from "carddetect" to "cd"
---
 drivers/mmc/host/sh_mobile_sdhi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index 59db14b..d964a0d 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -143,6 +143,7 @@ MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
 
 struct sh_mobile_sdhi {
 	struct clk *clk;
+	struct clk *clk_cd;
 	struct tmio_mmc_data mmc_data;
 	struct tmio_mmc_dma dma_priv;
 	struct pinctrl *pinctrl;
@@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(struct tmio_mmc_host *host)
 	if (ret < 0)
 		return ret;
 
+	ret = clk_prepare_enable(priv->clk_cd);
+	if (ret < 0) {
+		clk_disable_unprepare(priv->clk);
+		return ret;
+	}
+
 	/*
 	 * The clock driver may not know what maximum frequency
 	 * actually works, so it should be set with the max-frequency
@@ -255,6 +262,7 @@ static void sh_mobile_sdhi_clk_disable(struct tmio_mmc_host *host)
 	struct sh_mobile_sdhi *priv = host_to_priv(host);
 
 	clk_disable_unprepare(priv->clk);
+	clk_disable_unprepare(priv->clk_cd);
 }
 
 static int sh_mobile_sdhi_card_busy(struct mmc_host *mmc)
@@ -572,6 +580,21 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
 		goto eprobe;
 	}
 
+	/*
+	 * Some controllers provide a 2nd clock just to run the internal card
+	 * detection logic. Unfortunately, the existing driver architecture does
+	 * not support a separation of clocks for runtime PM usage. When
+	 * native hotplug is used, the tmio driver assumes that the core
+	 * must continue to run for card detect to stay active, so we cannot
+	 * disable it.
+	 * Additionally, it is prohibited to supply a clock to the core but not
+	 * to the card detect circuit. That leaves us with if separate clocks
+	 * are presented, we must treat them both as virtually 1 clock.
+	 */
+	priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
+	if (IS_ERR(priv->clk_cd))
+		priv->clk_cd = NULL;
+
 	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 	if (!IS_ERR(priv->pinctrl)) {
 		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
-- 
2.10.1

[PATCH v6 2/3] mmc: sh_mobile_sdhi: explain clock bindings

[Chris Brandt]

In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v5:
* add Reviewed-by: Geert Uytterhoeven
* list number of clocks for each SoC
* remove example because it already exists in mmc.txt
v4:
* just explain there might be 2 clocks, don't explain how
  we will use them in the driver
v3:
* add more clarification about why there are sometimes 2 clocks
  and what you should do with them.
* remove 'status = "disabled"' from example
v2:
* fix spelling and change wording
* changed clock name from "carddetect" to "cd"
---
 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index a1650ed..4fd8b7a 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -25,6 +25,19 @@ Required properties:
 		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
 		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
 
+- clocks: Most controllers only have 1 clock source per channel. However, on
+	  some variations of this controller, the internal card detection
+	  logic that exists in this controller is sectioned off to be run by a
+	  separate second clock source to allow the main core clock to be turned
+	  off to save power.
+	  If 2 clocks are specified by the hardware, you must name them as
+	  "core" and "cd". If the controller only has 1 clock, naming is not
+	  required.
+	  Below is the number clocks for each supported SoC:
+	   1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
+	      R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
+	   2: R7S72100
+
 Optional properties:
 - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
 - pinctrl-names: should be "default", "state_uhs"
-- 
2.10.1

[PATCH v6 3/3] ARM: dts: r7s72100: update sdhi clock bindings

[Chris Brandt]

The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
* add missing clock sources instead of just fixing typo
* changed clock name from "carddetect" to "cd"
---
 arch/arm/boot/dts/r7s72100.dtsi            | 17 ++++++++++++-----
 include/dt-bindings/clock/r7s72100-clock.h |  6 ++++--
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..9d0b8d0 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -153,9 +153,12 @@
 			#clock-cells = <1>;
 			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0xfcfe0444 4>;
-			clocks = <&p1_clk>, <&p1_clk>;
-			clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>;
-			clock-output-names = "sdhi1", "sdhi0";
+			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+			clock-indices = <
+				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
+				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
+			>;
+			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
 		};
 	};
 
@@ -478,7 +481,9 @@
 			      GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
 			      GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 
-		clocks = <&mstp12_clks R7S72100_CLK_SDHI0>;
+		clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
+			 <&mstp12_clks R7S72100_CLK_SDHI01>;
+		clock-names = "core", "cd";
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
@@ -491,7 +496,9 @@
 			      GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
 			      GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 
-		clocks = <&mstp12_clks R7S72100_CLK_SDHI1>;
+		clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
+			 <&mstp12_clks R7S72100_CLK_SDHI11>;
+		clock-names = "core", "cd";
 		cap-sd-highspeed;
 		cap-sdio-irq;
 		status = "disabled";
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
index 29e01ed..f2d8428 100644
--- a/include/dt-bindings/clock/r7s72100-clock.h
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -45,7 +45,9 @@
 #define R7S72100_CLK_SPI4	3
 
 /* MSTP12 */
-#define R7S72100_CLK_SDHI0	3
-#define R7S72100_CLK_SDHI1	2
+#define R7S72100_CLK_SDHI00	3
+#define R7S72100_CLK_SDHI01	2
+#define R7S72100_CLK_SDHI10	1
+#define R7S72100_CLK_SDHI11	0
 
 #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
-- 
2.10.1

Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Ulf Hansson]

On 25 January 2017 at 21:28, Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org> wrote:
> At first this started out as a simple typo fix, until I realized
> that the SDHI in the RZ/A1 has 2 clocks per channel and both need
> to be turned on/off.
>
> This patch series adds the ability to specify 2 clocks instead of
> just 1, and does so for the RZ/A1 r7s72100.
>
> This patch has been tested on an RZ/A1 RSK board. Card detect works
> fine as well as bind/unbind.
>
> v6:
> * more detailed descritpion in tmio_mmc.txt
>
> v5:
> * Take implementation details out of DT documentation and put into
>   the driver code.
>
> v4:
> * No code changes, only text udpates to explain why there are 2 clocks
>   and why we need to treat them as 1 clock.
>
> Chris Brandt (3):
>   mmc: sh_mobile_sdhi: add support for 2 clocks
>   mmc: sh_mobile_sdhi: explain clock bindings
>   ARM: dts: r7s72100: update sdhi clock bindings
>
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 ++++++++++++
>  arch/arm/boot/dts/r7s72100.dtsi                    | 17 +++++++++++-----
>  drivers/mmc/host/sh_mobile_sdhi.c                  | 23 ++++++++++++++++++++++
>  include/dt-bindings/clock/r7s72100-clock.h         |  6 ++++--
>  4 files changed, 52 insertions(+), 7 deletions(-)
>
> --
> 2.10.1
>
>

Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
guess!? (And I can add Rob's ack afterwards).

Kind regards
Uffe
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Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Ulf Hansson]

On 25 January 2017 at 21:28, Chris Brandt <chris.brandt@renesas.com> wrote:
> At first this started out as a simple typo fix, until I realized
> that the SDHI in the RZ/A1 has 2 clocks per channel and both need
> to be turned on/off.
>
> This patch series adds the ability to specify 2 clocks instead of
> just 1, and does so for the RZ/A1 r7s72100.
>
> This patch has been tested on an RZ/A1 RSK board. Card detect works
> fine as well as bind/unbind.
>
> v6:
> * more detailed descritpion in tmio_mmc.txt
>
> v5:
> * Take implementation details out of DT documentation and put into
>   the driver code.
>
> v4:
> * No code changes, only text udpates to explain why there are 2 clocks
>   and why we need to treat them as 1 clock.
>
> Chris Brandt (3):
>   mmc: sh_mobile_sdhi: add support for 2 clocks
>   mmc: sh_mobile_sdhi: explain clock bindings
>   ARM: dts: r7s72100: update sdhi clock bindings
>
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 ++++++++++++
>  arch/arm/boot/dts/r7s72100.dtsi                    | 17 +++++++++++-----
>  drivers/mmc/host/sh_mobile_sdhi.c                  | 23 ++++++++++++++++++++++
>  include/dt-bindings/clock/r7s72100-clock.h         |  6 ++++--
>  4 files changed, 52 insertions(+), 7 deletions(-)
>
> --
> 2.10.1
>
>

Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
guess!? (And I can add Rob's ack afterwards).

Kind regards
Uffe

Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 237 bytes --]


> Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> guess!? (And I can add Rob's ack afterwards).

Can you add my tags as well. They got dropped somehow:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Simon Horman]

On Thu, Jan 26, 2017 at 09:07:45AM +0100, Ulf Hansson wrote:
> On 25 January 2017 at 21:28, Chris Brandt <chris.brandt@renesas.com> wrote:
> > At first this started out as a simple typo fix, until I realized
> > that the SDHI in the RZ/A1 has 2 clocks per channel and both need
> > to be turned on/off.
> >
> > This patch series adds the ability to specify 2 clocks instead of
> > just 1, and does so for the RZ/A1 r7s72100.
> >
> > This patch has been tested on an RZ/A1 RSK board. Card detect works
> > fine as well as bind/unbind.
> >
> > v6:
> > * more detailed descritpion in tmio_mmc.txt
> >
> > v5:
> > * Take implementation details out of DT documentation and put into
> >   the driver code.
> >
> > v4:
> > * No code changes, only text udpates to explain why there are 2 clocks
> >   and why we need to treat them as 1 clock.
> >
> > Chris Brandt (3):
> >   mmc: sh_mobile_sdhi: add support for 2 clocks
> >   mmc: sh_mobile_sdhi: explain clock bindings
> >   ARM: dts: r7s72100: update sdhi clock bindings
> >
> >  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 ++++++++++++
> >  arch/arm/boot/dts/r7s72100.dtsi                    | 17 +++++++++++-----
> >  drivers/mmc/host/sh_mobile_sdhi.c                  | 23 ++++++++++++++++++++++
> >  include/dt-bindings/clock/r7s72100-clock.h         |  6 ++++--
> >  4 files changed, 52 insertions(+), 7 deletions(-)
> >
> > --
> > 2.10.1
> >
> >
> 
> Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> guess!? (And I can add Rob's ack afterwards).

Thanks, I will take care of the 3rd patch.

Chris, is it safe to apply the 3rd patch without the first 2 patches
present?

RE: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Chris Brandt]

On Thursday, January 26, 2017, Wolfram Sang wrote:
> Subject: Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100
> clocks
> 
> 
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
> 
> Can you add my tags as well. They got dropped somehow:
> 
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Sorry, that was my fault. It looks like you added that back on patch set
v3, but I forgot to add that when sending v4+.


Chris

RE: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Chris Brandt]

Hi Simon,

On Thursday, January 26, 2017, Simon Horman wrote:
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
> 
> Thanks, I will take care of the 3rd patch.
> 
> Chris, is it safe to apply the 3rd patch without the first 2 patches
> present?

Yes, it is safe.

Chris

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RE: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Chris Brandt]

Hi Simon,

On Thursday, January 26, 2017, Simon Horman wrote:
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
> 
> Thanks, I will take care of the 3rd patch.
> 
> Chris, is it safe to apply the 3rd patch without the first 2 patches
> present?

Yes, it is safe.

Chris

[PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Vladimir Barinov]

Hello,

This adds the folowing:
- R8A7796 SoC based M3ULCB board peripherals

Vladimir Barinov (4):
[1/4] arm64: dts: m3ulcb: enable I2C
[2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
[3/4] arm64: dts: m3ulcb: enable EthernetAVB
[4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

---
This patchset is against the 'kernel/git/horms/renesas.git' repo.

 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts     | 50 +++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

[PATCH 1/4] arm64: dts: m3ulcb: enable I2C

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This supports I2C2 bus on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index a9c296b..f35e96c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -120,6 +120,11 @@
 		function = "scif_clk";
 	};
 
+	i2c2_pins: i2c2 {
+		groups = "i2c2_a";
+		function = "i2c2";
+	};
+
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
@@ -183,6 +198,13 @@
 	status = "okay";
 };
 
+&i2c2 {
+	pinctrl-0 = <&i2c2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &wdt0 {
 	timeout-sec = <60>;
 	status = "okay";
-- 
1.9.1

[PATCH 2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This patch updates memory region:

  - After changes, the new map of the m3ulcb board on R8A7796 SoC
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
    Bank1: 1GiB RAM : 0x000600000000 -> 0x0063fffffff

  - Before changes, the old map looked like this:
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index f35e96c..38bde9d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -32,6 +32,11 @@
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x0 0x40000000>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-- 
1.9.1

[PATCH 3/4] arm64: dts: m3ulcb: enable EthernetAVB

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This supports Ethernet AVB on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 38bde9d..c7f40f8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -20,6 +20,7 @@
 
 	aliases {
 		serial0 = &scif2;
+		ethernet0 = &avb;
 	};
 
 	chosen {
@@ -115,6 +116,11 @@
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
 
+	avb_pins: avb {
+		groups = "avb_mdc";
+		function = "avb";
+	};
+
 	scif2_pins: scif2 {
 		groups = "scif2_data_a";
 		function = "scif2";
@@ -155,6 +161,32 @@
 	};
 };
 
+&avb {
+	pinctrl-0 = <&avb_pins>;
+	pinctrl-names = "default";
+	renesas,no-ether-link;
+	phy-handle = <&phy0>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <900>;
+		rxdv-skew-ps = <0>;
+		rxd0-skew-ps = <0>;
+		rxd1-skew-ps = <0>;
+		rxd2-skew-ps = <0>;
+		rxd3-skew-ps = <0>;
+		txc-skew-ps = <900>;
+		txen-skew-ps = <0>;
+		txd0-skew-ps = <0>;
+		txd1-skew-ps = <0>;
+		txd2-skew-ps = <0>;
+		txd3-skew-ps = <0>;
+		reg = <0>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
 	pinctrl-1 = <&sdhi0_pins_uhs>;
-- 
1.9.1

[PATCH 4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This supports HS200 mode for eMMC on M3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index c7f40f8..c3e0b9e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -209,6 +209,7 @@
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
+	mmc-hs200-1_8v;
 	non-removable;
 	status = "okay";
 };
-- 
1.9.1

[PATCH 0/2] arm64: renesas: enable H3ULCB board peripherals

[Vladimir Barinov]

Hello,

This adds the folowing:
- R8A7795 SoC based H3ULCB board peripherals

Vladimir Barinov (2):
[1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map
[2/2] arm64: dts: h3ulcb: enable HS200 for eMMC

---
This patchset is against the 'kernel/git/horms/renesas.git' repo.

 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts     | 16 +++++++++++++++++++++++++
 1 file changed, 16 insertions(+)
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[PATCH 0/2] arm64: renesas: enable H3ULCB board peripherals

[Vladimir Barinov]

Hello,

This adds the folowing:
- R8A7795 SoC based H3ULCB board peripherals

Vladimir Barinov (2):
[1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map
[2/2] arm64: dts: h3ulcb: enable HS200 for eMMC

---
This patchset is against the 'kernel/git/horms/renesas.git' repo.

 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts     | 16 +++++++++++++++++++++++++
 1 file changed, 16 insertions(+)

[PATCH 1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

This patch adds memory region:

  - After changes, the H3ULCB board has the following map:
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
    Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff
    Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
    Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff

  - Before changes, the old map looked like this:
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index b36c300..3edf966 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -33,6 +33,21 @@
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
+	memory@500000000 {
+		device_type = "memory";
+		reg = <0x5 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@700000000 {
+		device_type = "memory";
+		reg = <0x7 0x00000000 0x0 0x40000000>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-- 
1.9.1

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[PATCH 1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This patch adds memory region:

  - After changes, the H3ULCB board has the following map:
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
    Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff
    Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
    Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff

  - Before changes, the old map looked like this:
    Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index b36c300..3edf966 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -33,6 +33,21 @@
 		reg = <0x0 0x48000000 0x0 0x38000000>;
 	};
 
+	memory@500000000 {
+		device_type = "memory";
+		reg = <0x5 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x0 0x40000000>;
+	};
+
+	memory@700000000 {
+		device_type = "memory";
+		reg = <0x7 0x00000000 0x0 0x40000000>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-- 
1.9.1

[PATCH 2/2] arm64: dts: h3ulcb: enable HS200 for eMMC

[Vladimir Barinov]

From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

This supports HS200 mode for eMMC on H3ULCB board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 7a8986e..51ef8bb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -329,6 +329,7 @@
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
+	mmc-hs200-1_8v;
 	non-removable;
 	status = "okay";
 };
-- 
1.9.1

Re: [PATCH 2/2] arm64: dts: h3ulcb: enable HS200 for eMMC

[Simon Horman]

[CC Wolfram, linux-mmc]

On Thu, Jan 26, 2017 at 06:14:00PM +0300, Vladimir Barinov wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> 
> This supports HS200 mode for eMMC on H3ULCB board
> 
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Hi Vladimir,

Please resend this change once the relevant driver changes hit an rc
release.

I believe that means the following changes which are present in mmc/next.

8c81459fa8ad mmc: sh_mobile_sdhi: enable HS200
60f215caef3f mmc: sh_mobile_sdhi: remove superfluous check in SCC error check
f7c68068fb27 mmc: sh_mobile_sdhi: remove superfluous check in init_tuning
4cf3ecd2e097 mmc: sh_mobile_sdhi: remove superfluous check in hw_reset
bdba200138a9 mmc: sh_mobile_sdhi: improve prerequisites for tuning
a7f2c661cca9 mmc: sh_mobile_sdhi: improve prerequisite for hw_reset
59c21074b582 mmc: sh_mobile_sdhi: simplify accessing DT data

Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Simon Horman]

On Thu, Jan 26, 2017 at 11:12:11AM +0100, Wolfram Sang wrote:
> 
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
> 
> Can you add my tags as well. They got dropped somehow:
> 
> Reviewed-by: Wolfram Sang <wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/@public.gmane.org>

On Thu, Jan 26, 2017 at 12:53:10PM +0000, Chris Brandt wrote:
> Hi Simon,
> 
> On Thursday, January 26, 2017, Simon Horman wrote:
> > > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > > guess!? (And I can add Rob's ack afterwards).
> > 
> > Thanks, I will take care of the 3rd patch.
> > 
> > Chris, is it safe to apply the 3rd patch without the first 2 patches
> > present?
> 
> Yes, it is safe.

Thanks, I have queued this up for v4.12 with Wolfram's tag.
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Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Simon Horman]

On Thu, Jan 26, 2017 at 11:12:11AM +0100, Wolfram Sang wrote:
> 
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
> 
> Can you add my tags as well. They got dropped somehow:
> 
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

On Thu, Jan 26, 2017 at 12:53:10PM +0000, Chris Brandt wrote:
> Hi Simon,
> 
> On Thursday, January 26, 2017, Simon Horman wrote:
> > > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > > guess!? (And I can add Rob's ack afterwards).
> > 
> > Thanks, I will take care of the 3rd patch.
> > 
> > Chris, is it safe to apply the 3rd patch without the first 2 patches
> > present?
> 
> Yes, it is safe.

Thanks, I have queued this up for v4.12 with Wolfram's tag.

Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100 clocks

[Ulf Hansson]

On 26 January 2017 at 11:12, Wolfram Sang <wsa@the-dreams.de> wrote:
>
>> Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
>> guess!? (And I can add Rob's ack afterwards).
>
> Can you add my tags as well. They got dropped somehow:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>

Done, thanks!

Kind regards
Uffe

Re: [PATCH v6 2/3] mmc: sh_mobile_sdhi: explain clock bindings

[Rob Herring]

On Wed, Jan 25, 2017 at 03:28:09PM -0500, Chris Brandt wrote:
> In the case of a single clock source, you don't need names. However,
> if the controller has 2 clock sources, you need to name them correctly
> so the driver can find the 2nd one. The 2nd clock is for the internal
> card detect logic.
> 
> Signed-off-by: Chris Brandt <chris.brandt-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> ---
> v5:
> * add Reviewed-by: Geert Uytterhoeven
> * list number of clocks for each SoC
> * remove example because it already exists in mmc.txt
> v4:
> * just explain there might be 2 clocks, don't explain how
>   we will use them in the driver
> v3:
> * add more clarification about why there are sometimes 2 clocks
>   and what you should do with them.
> * remove 'status = "disabled"' from example
> v2:
> * fix spelling and change wording
> * changed clock name from "carddetect" to "cd"
> ---
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH v6 2/3] mmc: sh_mobile_sdhi: explain clock bindings

[Rob Herring]

On Wed, Jan 25, 2017 at 03:28:09PM -0500, Chris Brandt wrote:
> In the case of a single clock source, you don't need names. However,
> if the controller has 2 clock sources, you need to name them correctly
> so the driver can find the 2nd one. The 2nd clock is for the internal
> card detect logic.
> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v5:
> * add Reviewed-by: Geert Uytterhoeven
> * list number of clocks for each SoC
> * remove example because it already exists in mmc.txt
> v4:
> * just explain there might be 2 clocks, don't explain how
>   we will use them in the driver
> v3:
> * add more clarification about why there are sometimes 2 clocks
>   and what you should do with them.
> * remove 'status = "disabled"' from example
> v2:
> * fix spelling and change wording
> * changed clock name from "carddetect" to "cd"
> ---
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/4] arm64: dts: m3ulcb: enable I2C

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This supports I2C2 bus on M3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This patch updates memory region:
>
>   - After changes, the new map of the m3ulcb board on R8A7796 SoC
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>     Bank1: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
>
>   - Before changes, the old map looked like this:
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 4:13 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This patch adds memory region:
>
>   - After changes, the H3ULCB board has the following map:
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>     Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff
>     Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
>     Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff
>
>   - Before changes, the old map looked like this:
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
>
> This supports HS200 mode for eMMC on M3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Re: [PATCH 4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This supports HS200 mode for eMMC on M3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] arm64: dts: h3ulcb: enable HS200 for eMMC

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 4:14 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This supports HS200 mode for eMMC on H3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: m3ulcb: enable EthernetAVB

[Geert Uytterhoeven]

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This supports Ethernet AVB on M3ULCB board
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/2] arm64: dts: h3ulcb: Update memory node to 4 GiB map

[Simon Horman]

On Wed, Feb 01, 2017 at 01:40:08PM +0100, Geert Uytterhoeven wrote:
> On Thu, Jan 26, 2017 at 4:13 PM, Vladimir Barinov
> <vladimir.barinov@cogentembedded.com> wrote:
> > From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> >
> > This patch adds memory region:
> >
> >   - After changes, the H3ULCB board has the following map:
> >     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
> >     Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff
> >     Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
> >     Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff
> >
> >   - Before changes, the old map looked like this:
> >     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, I have queued this up.

Re: [PATCH 2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map

[Geert Uytterhoeven]

Hi Vladimir,

On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
<vladimir.barinov@cogentembedded.com> wrote:
> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>
> This patch updates memory region:
>
>   - After changes, the new map of the m3ulcb board on R8A7796 SoC
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>     Bank1: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
>
>   - Before changes, the old map looked like this:
>     Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff

BTW, this means M3ULCB has a different R-Car M3 SiP than Salvator-X,
with half the RAM?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map

[Vladimir Barinov]

Hi Geert,

On 02.02.2017 21:19, Geert Uytterhoeven wrote:
> Hi Vladimir,
>
> On Thu, Jan 26, 2017 at 3:54 PM, Vladimir Barinov
> <vladimir.barinov@cogentembedded.com> wrote:
>> From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
>>
>> This patch updates memory region:
>>
>>    - After changes, the new map of the m3ulcb board on R8A7796 SoC
>>      Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
>>      Bank1: 1GiB RAM : 0x000600000000 -> 0x0063fffffff
>>
>>    - Before changes, the old map looked like this:
>>      Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff
> BTW, this means M3ULCB has a different R-Car M3 SiP than Salvator-X,
> with half the RAM?
Yes,
http://elinux.org/R-Car/Boards/M3SK

Regards,
Vladimir

>
> Gr{oetje,eeting}s,
>
>                          Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                  -- Linus Torvalds

Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Sjoerd Simons]

On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> Hello,
> 
> This adds the folowing:
> - R8A7796 SoC based M3ULCB board peripherals
> 
> Vladimir Barinov (4):
> [1/4] arm64: dts: m3ulcb: enable I2C
> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

Seems these didn't hit -next just yet, for this series (tested on a
M3ULCB)

Tested-By: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>

-- 
Sjoerd Simons
Collabora Ltd.
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Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Sjoerd Simons]

On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> Hello,
> 
> This adds the folowing:
> - R8A7796 SoC based M3ULCB board peripherals
> 
> Vladimir Barinov (4):
> [1/4] arm64: dts: m3ulcb: enable I2C
> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

Seems these didn't hit -next just yet, for this series (tested on a
M3ULCB)

Tested-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk>

-- 
Sjoerd Simons
Collabora Ltd.

Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Geert Uytterhoeven]

Hi Simon,

On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
<sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org> wrote:
> On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
>> This adds the folowing:
>> - R8A7796 SoC based M3ULCB board peripherals
>>
>> Vladimir Barinov (4):
>> [1/4] arm64: dts: m3ulcb: enable I2C
>> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
>> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
>> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
>
> Seems these didn't hit -next just yet, for this series (tested on a
> M3ULCB)
>
> Tested-By: Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>

It seems this series is still pending? Any reason (not) to apply it?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Geert Uytterhoeven]

Hi Simon,

On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
<sjoerd.simons@collabora.co.uk> wrote:
> On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
>> This adds the folowing:
>> - R8A7796 SoC based M3ULCB board peripherals
>>
>> Vladimir Barinov (4):
>> [1/4] arm64: dts: m3ulcb: enable I2C
>> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
>> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
>> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
>
> Seems these didn't hit -next just yet, for this series (tested on a
> M3ULCB)
>
> Tested-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk>

It seems this series is still pending? Any reason (not) to apply it?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Simon Horman]

On Thu, Apr 06, 2017 at 11:53:45AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
> <sjoerd.simons@collabora.co.uk> wrote:
> > On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> >> This adds the folowing:
> >> - R8A7796 SoC based M3ULCB board peripherals
> >>
> >> Vladimir Barinov (4):
> >> [1/4] arm64: dts: m3ulcb: enable I2C
> >> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map

I have queued up the above two patches.
> >> [3/4] arm64: dts: m3ulcb: enable EthernetAVB

Please update the above patch to reflect the changes made in
ef3f08c83fd1 ("arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing")

> >> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC

I will look at queuing this up in the near future
with other HS200 enablement patches.

> > Seems these didn't hit -next just yet, for this series (tested on a
> > M3ULCB)
> >
> > Tested-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> 
> It seems this series is still pending? Any reason (not) to apply it?

Sorry for the extended delay.

Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Simon Horman]

On Fri, Apr 07, 2017 at 09:52:13AM -0400, Simon Horman wrote:
> On Thu, Apr 06, 2017 at 11:53:45AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon,
> > 
> > On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
> > <sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org> wrote:
> > > On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> > >> This adds the folowing:
> > >> - R8A7796 SoC based M3ULCB board peripherals
> > >>
> > >> Vladimir Barinov (4):
> > >> [1/4] arm64: dts: m3ulcb: enable I2C
> > >> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
> 
> I have queued up the above two patches.
> > >> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
> 
> Please update the above patch to reflect the changes made in
> ef3f08c83fd1 ("arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing")
> 
> > >> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
> 
> I will look at queuing this up in the near future
> with other HS200 enablement patches.

I have now done so; patches 1,2,4 are queued up for v4.13.
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Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Simon Horman]

On Fri, Apr 07, 2017 at 09:52:13AM -0400, Simon Horman wrote:
> On Thu, Apr 06, 2017 at 11:53:45AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon,
> > 
> > On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
> > <sjoerd.simons@collabora.co.uk> wrote:
> > > On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> > >> This adds the folowing:
> > >> - R8A7796 SoC based M3ULCB board peripherals
> > >>
> > >> Vladimir Barinov (4):
> > >> [1/4] arm64: dts: m3ulcb: enable I2C
> > >> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
> 
> I have queued up the above two patches.
> > >> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
> 
> Please update the above patch to reflect the changes made in
> ef3f08c83fd1 ("arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing")
> 
> > >> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
> 
> I will look at queuing this up in the near future
> with other HS200 enablement patches.

I have now done so; patches 1,2,4 are queued up for v4.13.

Re: [PATCH 0/4] arm64: renesas: enable M3ULCB board peripherals

[Simon Horman]

On Fri, Apr 07, 2017 at 09:52:13AM -0400, Simon Horman wrote:
> On Thu, Apr 06, 2017 at 11:53:45AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon,
> > 
> > On Fri, Mar 17, 2017 at 11:02 PM, Sjoerd Simons
> > <sjoerd.simons@collabora.co.uk> wrote:
> > > On Thu, 2017-01-26 at 17:53 +0300, Vladimir Barinov wrote:
> > >> This adds the folowing:
> > >> - R8A7796 SoC based M3ULCB board peripherals
> > >>
> > >> Vladimir Barinov (4):
> > >> [1/4] arm64: dts: m3ulcb: enable I2C
> > >> [2/4] arm64: dts: m3ulcb: Update memory node to 2 GiB map
> 
> I have queued up the above two patches.
> > >> [3/4] arm64: dts: m3ulcb: enable EthernetAVB
> 
> Please update the above patch to reflect the changes made in
> ef3f08c83fd1 ("arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing")

I have queued up the above patch anyway.
I will post an incremental patch to update the PHY timing values.

> 
> > >> [4/4] arm64: dts: m3ulcb: enable HS200 for eMMC
> 
> I will look at queuing this up in the near future
> with other HS200 enablement patches.
> 
> > > Seems these didn't hit -next just yet, for this series (tested on a
> > > M3ULCB)
> > >
> > > Tested-By: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> > 
> > It seems this series is still pending? Any reason (not) to apply it?
> 
> Sorry for the extended delay.
>