[PATCH libdrm 0/7] Vega10 bits for libdrm and more

[PATCH libdrm 0/7] Vega10 bits for libdrm and more

[Marek Olšák]

Hi,

These are mostly libdrm patches for Vega10. BTW, I do plan to push
these before the kernel support lands (including the amdgpu_drm.h
change), so that I can push the Mesa support.

Please review.

Marek
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[PATCH libdrm 1/7] amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

---
 include/drm/amdgpu_drm.h | 396 ++++++++++++++++++++++++++++++-----------------
 1 file changed, 251 insertions(+), 145 deletions(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d8f2497..5797283 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -43,103 +43,109 @@ extern "C" {
 #define DRM_AMDGPU_CTX			0x02
 #define DRM_AMDGPU_BO_LIST		0x03
 #define DRM_AMDGPU_CS			0x04
 #define DRM_AMDGPU_INFO			0x05
 #define DRM_AMDGPU_GEM_METADATA		0x06
 #define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
 #define DRM_AMDGPU_GEM_VA		0x08
 #define DRM_AMDGPU_WAIT_CS		0x09
 #define DRM_AMDGPU_GEM_OP		0x10
 #define DRM_AMDGPU_GEM_USERPTR		0x11
+#define DRM_AMDGPU_WAIT_FENCES		0x12
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
 #define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
 #define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
 #define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
 #define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
 #define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
 #define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
 #define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
 #define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
 #define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
+#define DRM_IOCTL_AMDGPU_WAIT_FENCES	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
 
 #define AMDGPU_GEM_DOMAIN_CPU		0x1
 #define AMDGPU_GEM_DOMAIN_GTT		0x2
 #define AMDGPU_GEM_DOMAIN_VRAM		0x4
 #define AMDGPU_GEM_DOMAIN_GDS		0x8
 #define AMDGPU_GEM_DOMAIN_GWS		0x10
 #define AMDGPU_GEM_DOMAIN_OA		0x20
 
 /* Flag that CPU access will be required for the case of VRAM domain */
 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
 /* Flag that CPU access will not work, this VRAM domain is invisible */
 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)
 /* Flag that USWC attributes should be used for GTT */
 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)
 /* Flag that the memory should be in VRAM and cleared */
 #define AMDGPU_GEM_CREATE_VRAM_CLEARED		(1 << 3)
+/* Flag that create shadow bo(GTT) while allocating vram bo */
+#define AMDGPU_GEM_CREATE_SHADOW		(1 << 4)
+/* Flag that allocating the BO should use linear VRAM */
+#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
 
 struct drm_amdgpu_gem_create_in  {
 	/** the requested memory size */
-	uint64_t bo_size;
+	__u64 bo_size;
 	/** physical start_addr alignment in bytes for some HW requirements */
-	uint64_t alignment;
+	__u64 alignment;
 	/** the requested memory domains */
-	uint64_t domains;
+	__u64 domains;
 	/** allocation flags */
-	uint64_t domain_flags;
+	__u64 domain_flags;
 };
 
 struct drm_amdgpu_gem_create_out  {
 	/** returned GEM object handle */
-	uint32_t handle;
-	uint32_t _pad;
+	__u32 handle;
+	__u32 _pad;
 };
 
 union drm_amdgpu_gem_create {
 	struct drm_amdgpu_gem_create_in		in;
 	struct drm_amdgpu_gem_create_out	out;
 };
 
 /** Opcode to create new residency list.  */
 #define AMDGPU_BO_LIST_OP_CREATE	0
 /** Opcode to destroy previously created residency list */
 #define AMDGPU_BO_LIST_OP_DESTROY	1
 /** Opcode to update resource information in the list */
 #define AMDGPU_BO_LIST_OP_UPDATE	2
 
 struct drm_amdgpu_bo_list_in {
 	/** Type of operation */
-	uint32_t operation;
+	__u32 operation;
 	/** Handle of list or 0 if we want to create one */
-	uint32_t list_handle;
+	__u32 list_handle;
 	/** Number of BOs in list  */
-	uint32_t bo_number;
+	__u32 bo_number;
 	/** Size of each element describing BO */
-	uint32_t bo_info_size;
+	__u32 bo_info_size;
 	/** Pointer to array describing BOs */
-	uint64_t bo_info_ptr;
+	__u64 bo_info_ptr;
 };
 
 struct drm_amdgpu_bo_list_entry {
 	/** Handle of BO */
-	uint32_t bo_handle;
+	__u32 bo_handle;
 	/** New (if specified) BO priority to be used during migration */
-	uint32_t bo_priority;
+	__u32 bo_priority;
 };
 
 struct drm_amdgpu_bo_list_out {
 	/** Handle of resource list  */
-	uint32_t list_handle;
-	uint32_t _pad;
+	__u32 list_handle;
+	__u32 _pad;
 };
 
 union drm_amdgpu_bo_list {
 	struct drm_amdgpu_bo_list_in in;
 	struct drm_amdgpu_bo_list_out out;
 };
 
 /* context related */
 #define AMDGPU_CTX_OP_ALLOC_CTX	1
 #define AMDGPU_CTX_OP_FREE_CTX	2
@@ -149,65 +155,65 @@ union drm_amdgpu_bo_list {
 #define AMDGPU_CTX_NO_RESET		0
 /* this the context caused it */
 #define AMDGPU_CTX_GUILTY_RESET		1
 /* some other context caused it */
 #define AMDGPU_CTX_INNOCENT_RESET	2
 /* unknown cause */
 #define AMDGPU_CTX_UNKNOWN_RESET	3
 
 struct drm_amdgpu_ctx_in {
 	/** AMDGPU_CTX_OP_* */
-	uint32_t	op;
+	__u32	op;
 	/** For future use, no flags defined so far */
-	uint32_t	flags;
-	uint32_t	ctx_id;
-	uint32_t	_pad;
+	__u32	flags;
+	__u32	ctx_id;
+	__u32	_pad;
 };
 
 union drm_amdgpu_ctx_out {
 		struct {
-			uint32_t	ctx_id;
-			uint32_t	_pad;
+			__u32	ctx_id;
+			__u32	_pad;
 		} alloc;
 
 		struct {
 			/** For future use, no flags defined so far */
-			uint64_t	flags;
+			__u64	flags;
 			/** Number of resets caused by this context so far. */
-			uint32_t	hangs;
+			__u32	hangs;
 			/** Reset status since the last call of the ioctl. */
-			uint32_t	reset_status;
+			__u32	reset_status;
 		} state;
 };
 
 union drm_amdgpu_ctx {
 	struct drm_amdgpu_ctx_in in;
 	union drm_amdgpu_ctx_out out;
 };
 
 /*
  * This is not a reliable API and you should expect it to fail for any
  * number of reasons and have fallback path that do not use userptr to
  * perform any operation.
  */
 #define AMDGPU_GEM_USERPTR_READONLY	(1 << 0)
 #define AMDGPU_GEM_USERPTR_ANONONLY	(1 << 1)
 #define AMDGPU_GEM_USERPTR_VALIDATE	(1 << 2)
 #define AMDGPU_GEM_USERPTR_REGISTER	(1 << 3)
 
 struct drm_amdgpu_gem_userptr {
-	uint64_t		addr;
-	uint64_t		size;
+	__u64		addr;
+	__u64		size;
 	/* AMDGPU_GEM_USERPTR_* */
-	uint32_t		flags;
+	__u32		flags;
 	/* Resulting GEM handle */
-	uint32_t		handle;
+	__u32		handle;
 };
 
 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 #define AMDGPU_TILING_ARRAY_MODE_SHIFT			0
 #define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT			4
 #define AMDGPU_TILING_PIPE_CONFIG_MASK			0x1f
 #define AMDGPU_TILING_TILE_SPLIT_SHIFT			9
 #define AMDGPU_TILING_TILE_SPLIT_MASK			0x7
 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT		12
@@ -225,222 +231,249 @@ struct drm_amdgpu_gem_userptr {
 	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
 	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 
 /** The same structure is shared for input/output */
 struct drm_amdgpu_gem_metadata {
 	/** GEM Object handle */
-	uint32_t	handle;
+	__u32	handle;
 	/** Do we want get or set metadata */
-	uint32_t	op;
+	__u32	op;
 	struct {
 		/** For future use, no flags defined so far */
-		uint64_t	flags;
+		__u64	flags;
 		/** family specific tiling info */
-		uint64_t	tiling_info;
-		uint32_t	data_size_bytes;
-		uint32_t	data[64];
+		__u64	tiling_info;
+		__u32	data_size_bytes;
+		__u32	data[64];
 	} data;
 };
 
 struct drm_amdgpu_gem_mmap_in {
 	/** the GEM object handle */
-	uint32_t handle;
-	uint32_t _pad;
+	__u32 handle;
+	__u32 _pad;
 };
 
 struct drm_amdgpu_gem_mmap_out {
 	/** mmap offset from the vma offset manager */
-	uint64_t addr_ptr;
+	__u64 addr_ptr;
 };
 
 union drm_amdgpu_gem_mmap {
 	struct drm_amdgpu_gem_mmap_in   in;
 	struct drm_amdgpu_gem_mmap_out out;
 };
 
 struct drm_amdgpu_gem_wait_idle_in {
 	/** GEM object handle */
-	uint32_t handle;
+	__u32 handle;
 	/** For future use, no flags defined so far */
-	uint32_t flags;
+	__u32 flags;
 	/** Absolute timeout to wait */
-	uint64_t timeout;
+	__u64 timeout;
 };
 
 struct drm_amdgpu_gem_wait_idle_out {
 	/** BO status:  0 - BO is idle, 1 - BO is busy */
-	uint32_t status;
+	__u32 status;
 	/** Returned current memory domain */
-	uint32_t domain;
+	__u32 domain;
 };
 
 union drm_amdgpu_gem_wait_idle {
 	struct drm_amdgpu_gem_wait_idle_in  in;
 	struct drm_amdgpu_gem_wait_idle_out out;
 };
 
 struct drm_amdgpu_wait_cs_in {
 	/** Command submission handle */
-	uint64_t handle;
+	__u64 handle;
 	/** Absolute timeout to wait */
-	uint64_t timeout;
-	uint32_t ip_type;
-	uint32_t ip_instance;
-	uint32_t ring;
-	uint32_t ctx_id;
+	__u64 timeout;
+	__u32 ip_type;
+	__u32 ip_instance;
+	__u32 ring;
+	__u32 ctx_id;
 };
 
 struct drm_amdgpu_wait_cs_out {
 	/** CS status:  0 - CS completed, 1 - CS still busy */
-	uint64_t status;
+	__u64 status;
 };
 
 union drm_amdgpu_wait_cs {
 	struct drm_amdgpu_wait_cs_in in;
 	struct drm_amdgpu_wait_cs_out out;
 };
 
+struct drm_amdgpu_fence {
+	__u32 ctx_id;
+	__u32 ip_type;
+	__u32 ip_instance;
+	__u32 ring;
+	__u64 seq_no;
+};
+
+struct drm_amdgpu_wait_fences_in {
+	/** This points to uint64_t * which points to fences */
+	__u64 fences;
+	__u32 fence_count;
+	__u32 wait_all;
+	__u64 timeout_ns;
+};
+
+struct drm_amdgpu_wait_fences_out {
+	__u32 status;
+	__u32 first_signaled;
+};
+
+union drm_amdgpu_wait_fences {
+	struct drm_amdgpu_wait_fences_in in;
+	struct drm_amdgpu_wait_fences_out out;
+};
+
 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO	0
 #define AMDGPU_GEM_OP_SET_PLACEMENT		1
 
 /* Sets or returns a value associated with a buffer. */
 struct drm_amdgpu_gem_op {
 	/** GEM object handle */
-	uint32_t	handle;
+	__u32	handle;
 	/** AMDGPU_GEM_OP_* */
-	uint32_t	op;
+	__u32	op;
 	/** Input or return value */
-	uint64_t	value;
+	__u64	value;
 };
 
 #define AMDGPU_VA_OP_MAP			1
 #define AMDGPU_VA_OP_UNMAP			2
 
 /* Delay the page table update till the next CS */
 #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
 
 /* Mapping flags */
 /* readable mapping */
 #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
 /* writable mapping */
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
 
 struct drm_amdgpu_gem_va {
 	/** GEM object handle */
-	uint32_t handle;
-	uint32_t _pad;
+	__u32 handle;
+	__u32 _pad;
 	/** AMDGPU_VA_OP_* */
-	uint32_t operation;
+	__u32 operation;
 	/** AMDGPU_VM_PAGE_* */
-	uint32_t flags;
+	__u32 flags;
 	/** va address to assign . Must be correctly aligned.*/
-	uint64_t va_address;
+	__u64 va_address;
 	/** Specify offset inside of BO to assign. Must be correctly aligned.*/
-	uint64_t offset_in_bo;
+	__u64 offset_in_bo;
 	/** Specify mapping size. Must be correctly aligned. */
-	uint64_t map_size;
+	__u64 map_size;
 };
 
 #define AMDGPU_HW_IP_GFX          0
 #define AMDGPU_HW_IP_COMPUTE      1
 #define AMDGPU_HW_IP_DMA          2
 #define AMDGPU_HW_IP_UVD          3
 #define AMDGPU_HW_IP_VCE          4
 #define AMDGPU_HW_IP_NUM          5
 
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 
 #define AMDGPU_CHUNK_ID_IB		0x01
 #define AMDGPU_CHUNK_ID_FENCE		0x02
 #define AMDGPU_CHUNK_ID_DEPENDENCIES	0x03
 
 struct drm_amdgpu_cs_chunk {
-	uint32_t		chunk_id;
-	uint32_t		length_dw;
-	uint64_t		chunk_data;
+	__u32		chunk_id;
+	__u32		length_dw;
+	__u64		chunk_data;
 };
 
 struct drm_amdgpu_cs_in {
 	/** Rendering context id */
-	uint32_t		ctx_id;
+	__u32		ctx_id;
 	/**  Handle of resource list associated with CS */
-	uint32_t		bo_list_handle;
-	uint32_t		num_chunks;
-	uint32_t		_pad;
-	/** this points to uint64_t * which point to cs chunks */
-	uint64_t		chunks;
+	__u32		bo_list_handle;
+	__u32		num_chunks;
+	__u32		_pad;
+	/** this points to __u64 * which point to cs chunks */
+	__u64		chunks;
 };
 
 struct drm_amdgpu_cs_out {
-	uint64_t handle;
+	__u64 handle;
 };
 
 union drm_amdgpu_cs {
 	struct drm_amdgpu_cs_in in;
 	struct drm_amdgpu_cs_out out;
 };
 
 /* Specify flags to be used for IB */
 
 /* This IB should be submitted to CE */
 #define AMDGPU_IB_FLAG_CE	(1<<0)
 
 /* CE Preamble */
 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 
 struct drm_amdgpu_cs_chunk_ib {
-	uint32_t _pad;
+	__u32 _pad;
 	/** AMDGPU_IB_FLAG_* */
-	uint32_t flags;
+	__u32 flags;
 	/** Virtual address to begin IB execution */
-	uint64_t va_start;
+	__u64 va_start;
 	/** Size of submission */
-	uint32_t ib_bytes;
+	__u32 ib_bytes;
 	/** HW IP to submit to */
-	uint32_t ip_type;
+	__u32 ip_type;
 	/** HW IP index of the same type to submit to  */
-	uint32_t ip_instance;
+	__u32 ip_instance;
 	/** Ring index to submit to */
-	uint32_t ring;
+	__u32 ring;
 };
 
 struct drm_amdgpu_cs_chunk_dep {
-	uint32_t ip_type;
-	uint32_t ip_instance;
-	uint32_t ring;
-	uint32_t ctx_id;
-	uint64_t handle;
+	__u32 ip_type;
+	__u32 ip_instance;
+	__u32 ring;
+	__u32 ctx_id;
+	__u64 handle;
 };
 
 struct drm_amdgpu_cs_chunk_fence {
-	uint32_t handle;
-	uint32_t offset;
+	__u32 handle;
+	__u32 offset;
 };
 
 struct drm_amdgpu_cs_chunk_data {
 	union {
 		struct drm_amdgpu_cs_chunk_ib		ib_data;
 		struct drm_amdgpu_cs_chunk_fence	fence_data;
 	};
 };
 
 /**
  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
  *
  */
 #define AMDGPU_IDS_FLAGS_FUSION         0x1
+#define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 
 /* indicate if acceleration can be working */
 #define AMDGPU_INFO_ACCEL_WORKING		0x00
 /* get the crtc_id from the mode object id? */
 #define AMDGPU_INFO_CRTC_FROM_ID		0x01
 /* query hw IP info */
 #define AMDGPU_INFO_HW_IP_INFO			0x02
 /* query hw IP instance count for the specified type */
 #define AMDGPU_INFO_HW_IP_COUNT			0x03
 /* timestamp for GL_ARB_timer_query */
@@ -476,182 +509,255 @@ struct drm_amdgpu_cs_chunk_data {
 /* Information about GDS, etc. resource configuration */
 #define AMDGPU_INFO_GDS_CONFIG			0x13
 /* Query information about VRAM and GTT domains */
 #define AMDGPU_INFO_VRAM_GTT			0x14
 /* Query information about register in MMR address space*/
 #define AMDGPU_INFO_READ_MMR_REG		0x15
 /* Query information about device: rev id, family, etc. */
 #define AMDGPU_INFO_DEV_INFO			0x16
 /* visible vram usage */
 #define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
+/* number of TTM buffer evictions */
+#define AMDGPU_INFO_NUM_EVICTIONS		0x18
+/* Query memory about VRAM and GTT domains */
+#define AMDGPU_INFO_MEMORY			0x19
+/* Query vce clock table */
+#define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
+/* Query vbios related information */
+#define AMDGPU_INFO_VBIOS			0x1B
+	/* Subquery id: Query vbios size */
+	#define AMDGPU_INFO_VBIOS_SIZE		0x1
+	/* Subquery id: Query vbios image */
+	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
+/* Query UVD handles */
+#define AMDGPU_INFO_NUM_HANDLES			0x1C
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
 
 struct drm_amdgpu_query_fw {
 	/** AMDGPU_INFO_FW_* */
-	uint32_t fw_type;
+	__u32 fw_type;
 	/**
 	 * Index of the IP if there are more IPs of
 	 * the same type.
 	 */
-	uint32_t ip_instance;
+	__u32 ip_instance;
 	/**
 	 * Index of the engine. Whether this is used depends
 	 * on the firmware type. (e.g. MEC, SDMA)
 	 */
-	uint32_t index;
-	uint32_t _pad;
+	__u32 index;
+	__u32 _pad;
 };
 
 /* Input structure for the INFO ioctl */
 struct drm_amdgpu_info {
 	/* Where the return value will be stored */
-	uint64_t return_pointer;
+	__u64 return_pointer;
 	/* The size of the return value. Just like "size" in "snprintf",
 	 * it limits how many bytes the kernel can write. */
-	uint32_t return_size;
+	__u32 return_size;
 	/* The query request id. */
-	uint32_t query;
+	__u32 query;
 
 	union {
 		struct {
-			uint32_t id;
-			uint32_t _pad;
+			__u32 id;
+			__u32 _pad;
 		} mode_crtc;
 
 		struct {
 			/** AMDGPU_HW_IP_* */
-			uint32_t type;
+			__u32 type;
 			/**
 			 * Index of the IP if there are more IPs of the same
 			 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 			 */
-			uint32_t ip_instance;
+			__u32 ip_instance;
 		} query_hw_ip;
 
 		struct {
-			uint32_t dword_offset;
+			__u32 dword_offset;
 			/** number of registers to read */
-			uint32_t count;
-			uint32_t instance;
+			__u32 count;
+			__u32 instance;
 			/** For future use, no flags defined so far */
-			uint32_t flags;
+			__u32 flags;
 		} read_mmr_reg;
 
 		struct drm_amdgpu_query_fw query_fw;
+
+		struct {
+			__u32 type;
+			__u32 offset;
+		} vbios_info;
 	};
 };
 
 struct drm_amdgpu_info_gds {
 	/** GDS GFX partition size */
-	uint32_t gds_gfx_partition_size;
+	__u32 gds_gfx_partition_size;
 	/** GDS compute partition size */
-	uint32_t compute_partition_size;
+	__u32 compute_partition_size;
 	/** total GDS memory size */
-	uint32_t gds_total_size;
+	__u32 gds_total_size;
 	/** GWS size per GFX partition */
-	uint32_t gws_per_gfx_partition;
+	__u32 gws_per_gfx_partition;
 	/** GSW size per compute partition */
-	uint32_t gws_per_compute_partition;
+	__u32 gws_per_compute_partition;
 	/** OA size per GFX partition */
-	uint32_t oa_per_gfx_partition;
+	__u32 oa_per_gfx_partition;
 	/** OA size per compute partition */
-	uint32_t oa_per_compute_partition;
-	uint32_t _pad;
+	__u32 oa_per_compute_partition;
+	__u32 _pad;
 };
 
 struct drm_amdgpu_info_vram_gtt {
-	uint64_t vram_size;
-	uint64_t vram_cpu_accessible_size;
-	uint64_t gtt_size;
+	__u64 vram_size;
+	__u64 vram_cpu_accessible_size;
+	__u64 gtt_size;
+};
+
+struct drm_amdgpu_heap_info {
+	/** max. physical memory */
+	__u64 total_heap_size;
+
+	/** Theoretical max. available memory in the given heap */
+	__u64 usable_heap_size;
+
+	/**
+	 * Number of bytes allocated in the heap. This includes all processes
+	 * and private allocations in the kernel. It changes when new buffers
+	 * are allocated, freed, and moved. It cannot be larger than
+	 * heap_size.
+	 */
+	__u64 heap_usage;
+
+	/**
+	 * Theoretical possible max. size of buffer which
+	 * could be allocated in the given heap
+	 */
+	__u64 max_allocation;
+};
+
+struct drm_amdgpu_memory_info {
+	struct drm_amdgpu_heap_info vram;
+	struct drm_amdgpu_heap_info cpu_accessible_vram;
+	struct drm_amdgpu_heap_info gtt;
 };
 
 struct drm_amdgpu_info_firmware {
-	uint32_t ver;
-	uint32_t feature;
+	__u32 ver;
+	__u32 feature;
 };
 
 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 #define AMDGPU_VRAM_TYPE_GDDR1 1
 #define AMDGPU_VRAM_TYPE_DDR2  2
 #define AMDGPU_VRAM_TYPE_GDDR3 3
 #define AMDGPU_VRAM_TYPE_GDDR4 4
 #define AMDGPU_VRAM_TYPE_GDDR5 5
 #define AMDGPU_VRAM_TYPE_HBM   6
 #define AMDGPU_VRAM_TYPE_DDR3  7
 
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
-	uint32_t device_id;
+	__u32 device_id;
 	/** Internal chip revision: A0, A1, etc.) */
-	uint32_t chip_rev;
-	uint32_t external_rev;
+	__u32 chip_rev;
+	__u32 external_rev;
 	/** Revision id in PCI Config space */
-	uint32_t pci_rev;
-	uint32_t family;
-	uint32_t num_shader_engines;
-	uint32_t num_shader_arrays_per_engine;
+	__u32 pci_rev;
+	__u32 family;
+	__u32 num_shader_engines;
+	__u32 num_shader_arrays_per_engine;
 	/* in KHz */
-	uint32_t gpu_counter_freq;
-	uint64_t max_engine_clock;
-	uint64_t max_memory_clock;
+	__u32 gpu_counter_freq;
+	__u64 max_engine_clock;
+	__u64 max_memory_clock;
 	/* cu information */
-	uint32_t cu_active_number;
-	uint32_t cu_ao_mask;
-	uint32_t cu_bitmap[4][4];
+	__u32 cu_active_number;
+	__u32 cu_ao_mask;
+	__u32 cu_bitmap[4][4];
 	/** Render backend pipe mask. One render backend is CB+DB. */
-	uint32_t enabled_rb_pipes_mask;
-	uint32_t num_rb_pipes;
-	uint32_t num_hw_gfx_contexts;
-	uint32_t _pad;
-	uint64_t ids_flags;
+	__u32 enabled_rb_pipes_mask;
+	__u32 num_rb_pipes;
+	__u32 num_hw_gfx_contexts;
+	__u32 _pad;
+	__u64 ids_flags;
 	/** Starting virtual address for UMDs. */
-	uint64_t virtual_address_offset;
+	__u64 virtual_address_offset;
 	/** The maximum virtual address */
-	uint64_t virtual_address_max;
+	__u64 virtual_address_max;
 	/** Required alignment of virtual addresses. */
-	uint32_t virtual_address_alignment;
+	__u32 virtual_address_alignment;
 	/** Page table entry - fragment size */
-	uint32_t pte_fragment_size;
-	uint32_t gart_page_size;
+	__u32 pte_fragment_size;
+	__u32 gart_page_size;
 	/** constant engine ram size*/
-	uint32_t ce_ram_size;
+	__u32 ce_ram_size;
 	/** video memory type info*/
-	uint32_t vram_type;
+	__u32 vram_type;
 	/** video memory bit width*/
-	uint32_t vram_bit_width;
+	__u32 vram_bit_width;
 	/* vce harvesting instance */
-	uint32_t vce_harvest_config;
+	__u32 vce_harvest_config;
 };
 
 struct drm_amdgpu_info_hw_ip {
 	/** Version of h/w IP */
-	uint32_t  hw_ip_version_major;
-	uint32_t  hw_ip_version_minor;
+	__u32  hw_ip_version_major;
+	__u32  hw_ip_version_minor;
 	/** Capabilities */
-	uint64_t  capabilities_flags;
+	__u64  capabilities_flags;
 	/** command buffer address start alignment*/
-	uint32_t  ib_start_alignment;
+	__u32  ib_start_alignment;
 	/** command buffer size alignment*/
-	uint32_t  ib_size_alignment;
+	__u32  ib_size_alignment;
 	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
-	uint32_t  available_rings;
-	uint32_t  _pad;
+	__u32  available_rings;
+	__u32  _pad;
+};
+
+struct drm_amdgpu_info_num_handles {
+	/** Max handles as supported by firmware for UVD */
+	__u32  uvd_max_handles;
+	/** Handles currently in use for UVD */
+	__u32  uvd_used_handles;
+};
+
+#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES		6
+
+struct drm_amdgpu_info_vce_clock_table_entry {
+	/** System clock */
+	__u32 sclk;
+	/** Memory clock */
+	__u32 mclk;
+	/** VCE clock */
+	__u32 eclk;
+	__u32 pad;
+};
+
+struct drm_amdgpu_info_vce_clock_table {
+	struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
+	__u32 num_valid_entries;
+	__u32 pad;
 };
 
 /*
  * Supported GPU families
  */
 #define AMDGPU_FAMILY_UNKNOWN			0
+#define AMDGPU_FAMILY_SI			110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
 #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
 #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
 #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
 
 #if defined(__cplusplus)
 }
 #endif
 
 #endif
-- 
2.7.4

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[PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Marek Olšák]

From: Marek Olšák <marek.olsak@amd.com>

---
 include/drm/amdgpu_drm.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 5797283..d702a95 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -202,42 +202,47 @@ union drm_amdgpu_ctx {
 
 struct drm_amdgpu_gem_userptr {
 	__u64		addr;
 	__u64		size;
 	/* AMDGPU_GEM_USERPTR_* */
 	__u32		flags;
 	/* Resulting GEM handle */
 	__u32		handle;
 };
 
+/* SI-CI-VI: */
 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 #define AMDGPU_TILING_ARRAY_MODE_SHIFT			0
 #define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT			4
 #define AMDGPU_TILING_PIPE_CONFIG_MASK			0x1f
 #define AMDGPU_TILING_TILE_SPLIT_SHIFT			9
 #define AMDGPU_TILING_TILE_SPLIT_MASK			0x7
 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT		12
 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK		0x7
 #define AMDGPU_TILING_BANK_WIDTH_SHIFT			15
 #define AMDGPU_TILING_BANK_WIDTH_MASK			0x3
 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT			17
 #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
 #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
 #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
 
+/* GFX9 and later: */
+#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
+#define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
+
 #define AMDGPU_TILING_SET(field, value) \
-	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
+	(((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 #define AMDGPU_TILING_GET(value, field) \
-	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
+	(((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 
 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 
 /** The same structure is shared for input/output */
 struct drm_amdgpu_gem_metadata {
 	/** GEM Object handle */
 	__u32	handle;
 	/** Do we want get or set metadata */
 	__u32	op;
@@ -748,16 +753,17 @@ struct drm_amdgpu_info_vce_clock_table {
 
 /*
  * Supported GPU families
  */
 #define AMDGPU_FAMILY_UNKNOWN			0
 #define AMDGPU_FAMILY_SI			110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
 #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
 #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
 #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
+#define AMDGPU_FAMILY_AI			141 /* Vega10 */
 
 #if defined(__cplusplus)
 }
 #endif
 
 #endif
-- 
2.7.4

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[PATCH libdrm 3/7] amdgpu: don't read registers not present on Vega10

[Marek Olšák]

From: Huang Rui <ray.huang@amd.com>

---
 amdgpu/amdgpu_gpu_info.c | 48 ++++++++++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 22 deletions(-)

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 66c7e0e..cd31e1b 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -175,54 +175,58 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 				     AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
 
 		r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
 					     &dev->info.backend_disable[i]);
 		if (r)
 			return r;
 		/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 		dev->info.backend_disable[i] =
 			(dev->info.backend_disable[i] >> 16) & 0xff;
 
-		r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
-					     &dev->info.pa_sc_raster_cfg[i]);
-		if (r)
-			return r;
-
-		if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
-			r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
-					     &dev->info.pa_sc_raster_cfg1[i]);
+		if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+			r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
+						     &dev->info.pa_sc_raster_cfg[i]);
 			if (r)
 				return r;
+
+			if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+				r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
+						     &dev->info.pa_sc_raster_cfg1[i]);
+				if (r)
+					return r;
+			}
 		}
 	}
 
-	r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
-				     dev->info.gb_tile_mode);
+	r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
+					     &dev->info.gb_addr_cfg);
 	if (r)
 		return r;
 
-	if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
-		r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
-					     dev->info.gb_macro_tile_mode);
+	if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+		r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
+					     dev->info.gb_tile_mode);
 		if (r)
 			return r;
-	}
 
-	r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
-				     &dev->info.gb_addr_cfg);
-	if (r)
-		return r;
+		if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+			r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
+						     dev->info.gb_macro_tile_mode);
+			if (r)
+				return r;
+		}
 
-	r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
-				     &dev->info.mc_arb_ramcfg);
-	if (r)
-		return r;
+		r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
+					     &dev->info.mc_arb_ramcfg);
+		if (r)
+			return r;
+	}
 
 	dev->info.cu_active_number = dev->dev_info.cu_active_number;
 	dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
 	memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
 
 	/* TODO: info->max_quad_shader_pipes is not set */
 	/* TODO: info->avail_quad_shader_pipes is not set */
 	/* TODO: info->cache_entries_per_quad_pipe is not set */
 	return 0;
 }
-- 
2.7.4

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[PATCH libdrm 4/7] tests/amdgpu: fix the count number for vega10

[Marek Olšák]

From: Huang Rui <ray.huang@amd.com>

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 tests/amdgpu/basic_tests.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index bfda21b..4dce67e 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -796,26 +796,30 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 128;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo_mc;
 	volatile uint32_t *bo_cpu;
 	int i, j, r, loop;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -841,21 +845,24 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
 
 		resources[0] = bo;
 
 		/* fulfill PM4: test DMA write-linear */
 		i = j = 0;
 		if (ip_type == AMDGPU_HW_IP_DMA) {
 			pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 					       SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 			pm4[i++] = 0xffffffff & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
-			pm4[i++] = sdma_write_length;
+			if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+				pm4[i++] = sdma_write_length - 1;
+			else
+				pm4[i++] = sdma_write_length;
 			while(j++ < sdma_write_length)
 				pm4[i++] = 0xdeadbeaf;
 		} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 			   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 			pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
 			pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 			pm4[i++] = 0xfffffffc & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
 			while(j++ < sdma_write_length)
 				pm4[i++] = 0xdeadbeaf;
@@ -897,26 +904,30 @@ static void amdgpu_command_submission_sdma_write_linear(void)
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 1024 * 1024;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo_mc;
 	volatile uint32_t *bo_cpu;
 	int i, j, r, loop;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -942,21 +953,24 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
 		resources[0] = bo;
 
 		/* fulfill PM4: test DMA const fill */
 		i = j = 0;
 		if (ip_type == AMDGPU_HW_IP_DMA) {
 			pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
 					       SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
 			pm4[i++] = 0xffffffff & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
 			pm4[i++] = 0xdeadbeaf;
-			pm4[i++] = sdma_write_length;
+			if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+				pm4[i++] = sdma_write_length - 1;
+			else
+				pm4[i++] = sdma_write_length;
 		} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 			   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 			pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
 			pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
 				PACKET3_DMA_DATA_DST_SEL(0) |
 				PACKET3_DMA_DATA_SRC_SEL(2) |
 				PACKET3_DMA_DATA_CP_SYNC;
 			pm4[i++] = 0xdeadbeaf;
 			pm4[i++] = 0;
 			pm4[i++] = 0xfffffffc & bo_mc;
@@ -1000,26 +1014,30 @@ static void amdgpu_command_submission_sdma_const_fill(void)
 static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 1024;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo1, bo2;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo1_mc, bo2_mc;
 	volatile unsigned char *bo1_cpu, *bo2_cpu;
 	int i, j, r, loop1, loop2;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle bo1_va_handle, bo2_va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -1057,21 +1075,24 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
 			/* clear bo2 */
 			memset((void*)bo2_cpu, 0, sdma_write_length);
 
 			resources[0] = bo1;
 			resources[1] = bo2;
 
 			/* fulfill PM4: test DMA copy linear */
 			i = j = 0;
 			if (ip_type == AMDGPU_HW_IP_DMA) {
 				pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
-				pm4[i++] = sdma_write_length;
+				if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+					pm4[i++] = sdma_write_length - 1;
+				else
+					pm4[i++] = sdma_write_length;
 				pm4[i++] = 0;
 				pm4[i++] = 0xffffffff & bo1_mc;
 				pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
 				pm4[i++] = 0xffffffff & bo2_mc;
 				pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
 			} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 				   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 				pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
 				pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
 					PACKET3_DMA_DATA_DST_SEL(0) |
-- 
2.7.4

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[PATCH libdrm 5/7] tests/amdgpu: add uvd unit test support for vega10

[Marek Olšák]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 tests/amdgpu/cs_tests.c | 37 +++++++++++++++++++++++--------------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 82c55aa..0885d97 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -168,25 +168,25 @@ static int submit(unsigned ndw, unsigned ip)
 					 AMDGPU_TIMEOUT_INFINITE,
 					 0, &expired);
 	if (r)
 		return r;
 
 	return 0;
 }
 
 static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx)
 {
-	ib_cpu[(*idx)++] = 0x3BC4;
+	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4;
 	ib_cpu[(*idx)++] = addr;
-	ib_cpu[(*idx)++] = 0x3BC5;
+	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5;
 	ib_cpu[(*idx)++] = addr >> 32;
-	ib_cpu[(*idx)++] = 0x3BC3;
+	ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3;
 	ib_cpu[(*idx)++] = cmd << 1;
 }
 
 static void amdgpu_cs_uvd_create(void)
 {
 	struct amdgpu_bo_alloc_request req = {0};
 	amdgpu_bo_handle buf_handle;
 	uint64_t va = 0;
 	amdgpu_va_handle va_handle;
 	void *msg;
@@ -204,24 +204,26 @@ static void amdgpu_cs_uvd_create(void)
 				  &va_handle, 0);
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP);
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_cpu_map(buf_handle, &msg);
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
+
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		((uint8_t*)msg)[0x10] = 7;
-		/* chip polaris 10/11 */
-		if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
+		/* chip beyond polaris 10/11 */
+		if ((family_id == AMDGPU_FAMILY_AI) ||
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
 			/* dpb size */
 			((uint8_t*)msg)[0x28] = 0x00;
 			((uint8_t*)msg)[0x29] = 0x94;
 			((uint8_t*)msg)[0x2A] = 0x6B;
 			((uint8_t*)msg)[0x2B] = 0x00;
 		}
 	}
 
 	r = amdgpu_bo_cpu_unmap(buf_handle);
 	CU_ASSERT_EQUAL(r, 0);
@@ -280,27 +282,29 @@ static void amdgpu_cs_uvd_decode(void)
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
 			    AMDGPU_VA_OP_MAP);
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr);
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
+
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		ptr[0x10] = 7;
 		ptr[0x98] = 0x00;
 		ptr[0x99] = 0x02;
-		/* chip polaris10/11 */
-		if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
-			/*dpb size */
+		/* chip beyond polaris10/11 */
+		if ((family_id == AMDGPU_FAMILY_AI) ||
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+			/* dpb size */
 			ptr[0x24] = 0x00;
 			ptr[0x25] = 0x94;
 			ptr[0x26] = 0x6B;
 			ptr[0x27] = 0x00;
 			/*ctx size */
 			ptr[0x2C] = 0x00;
 			ptr[0x2D] = 0xAF;
 			ptr[0x2E] = 0x50;
 			ptr[0x2F] = 0x00;
 		}
@@ -328,39 +332,44 @@ static void amdgpu_cs_uvd_decode(void)
 
 	msg_addr = va;
 	fb_addr = msg_addr + 4*1024;
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		it_addr = fb_addr + 4*1024;
 		bs_addr = it_addr + 4*1024;
 	} else
 		bs_addr = fb_addr + 4*1024;
 	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 
-	if ((family_id >= AMDGPU_FAMILY_VI) &&
-		(chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
-		ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
+	if (family_id >= AMDGPU_FAMILY_VI) {
+		if ((family_id == AMDGPU_FAMILY_AI) ||
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+			ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
+		}
 	}
 
 	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 
 	i = 0;
 	uvd_cmd(msg_addr, 0x0, &i);
 	uvd_cmd(dpb_addr, 0x1, &i);
 	uvd_cmd(dt_addr, 0x2, &i);
 	uvd_cmd(fb_addr, 0x3, &i);
 	uvd_cmd(bs_addr, 0x100, &i);
+
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		uvd_cmd(it_addr, 0x204, &i);
-		if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)
+		if ((family_id == AMDGPU_FAMILY_AI) ||
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A))
 			uvd_cmd(ctx_addr, 0x206, &i);
-}
-	ib_cpu[i++] = 0x3BC6;
+	}
+
+	ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
 	ib_cpu[i++] = 0x1;
 	for (; i % 16; ++i)
 		ib_cpu[i] = 0x80000000;
 
 	r = submit(i, AMDGPU_HW_IP_UVD);
 	CU_ASSERT_EQUAL(r, 0);
 
 	/* TODO: use a real CRC32 */
 	for (i = 0, sum = 0; i < dt_size; ++i)
 		sum += ptr[i];
-- 
2.7.4

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[PATCH libdrm 6/7] tests/amdgpu: add vce unit test support for vega10

[Marek Olšák]

From: Leo Liu <leo.liu@amd.com>

swizzle mode needs reference and input picture luma and
chroma pitch aligned with 256

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 tests/amdgpu/vce_tests.c | 54 +++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 42 insertions(+), 12 deletions(-)

diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c
index de63aa1..b03807b 100644
--- a/tests/amdgpu/vce_tests.c
+++ b/tests/amdgpu/vce_tests.c
@@ -227,36 +227,39 @@ static void free_resource(struct amdgpu_vce_bo *vce_bo)
 	r = amdgpu_va_range_free(vce_bo->va_handle);
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_free(vce_bo->handle);
 	CU_ASSERT_EQUAL(r, 0);
 	memset(vce_bo, 0, sizeof(*vce_bo));
 }
 
 static void amdgpu_cs_vce_create(void)
 {
+	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
 	int len, r;
 
 	enc.width = vce_create[6];
 	enc.height = vce_create[7];
 
 	num_resources  = 0;
 	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
 	resources[num_resources++] = enc.fb[0].handle;
 	resources[num_resources++] = ib_handle;
 
 	len = 0;
 	memcpy(ib_cpu, vce_session, sizeof(vce_session));
 	len += sizeof(vce_session) / 4;
 	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
 	len += sizeof(vce_taskinfo) / 4;
 	memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
+	ib_cpu[len + 8] = ALIGN(enc.width, align);
+	ib_cpu[len + 9] = ALIGN(enc.width, align);
 	len += sizeof(vce_create) / 4;
 	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
 	ib_cpu[len + 2] = enc.fb[0].addr >> 32;
 	ib_cpu[len + 3] = enc.fb[0].addr;
 	len += sizeof(vce_feedback) / 4;
 
 	r = submit(len, AMDGPU_HW_IP_VCE);
 	CU_ASSERT_EQUAL(r, 0);
 
 	free_resource(&enc.fb[0]);
@@ -284,102 +287,118 @@ static void amdgpu_cs_vce_config(void)
 	len += sizeof(vce_pic_ctrl) / 4;
 
 	r = submit(len, AMDGPU_HW_IP_VCE);
 	CU_ASSERT_EQUAL(r, 0);
 }
 
 static  void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
 {
 
 	uint64_t luma_offset, chroma_offset;
-	int len = 0, r;
+	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
+	unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
+	int len = 0, i, r;
 
 	luma_offset = enc->vbuf.addr;
-	chroma_offset = luma_offset + enc->width * enc->height;
+	chroma_offset = luma_offset + luma_size;
 
 	memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
 	len += sizeof(vce_session) / 4;
 	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
 	len += sizeof(vce_taskinfo) / 4;
 	memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
 	ib_cpu[len + 2] = enc->bs[0].addr >> 32;
 	ib_cpu[len + 3] = enc->bs[0].addr;
 	len += sizeof(vce_bs_buffer) / 4;
 	memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
 	ib_cpu[len + 2] = enc->cpb.addr >> 32;
 	ib_cpu[len + 3] = enc->cpb.addr;
 	len += sizeof(vce_context_buffer) / 4;
 	memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
+	for (i = 0; i <  8; ++i)
+		ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
+	for (i = 0; i <  8; ++i)
+		ib_cpu[len + 10 + i] = luma_size * 1.5;
 	len += sizeof(vce_aux_buffer) / 4;
 	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
 	ib_cpu[len + 2] = enc->fb[0].addr >> 32;
 	ib_cpu[len + 3] = enc->fb[0].addr;
 	len += sizeof(vce_feedback) / 4;
 	memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
 	ib_cpu[len + 9] = luma_offset >> 32;
 	ib_cpu[len + 10] = luma_offset;
 	ib_cpu[len + 11] = chroma_offset >> 32;
 	ib_cpu[len + 12] = chroma_offset;
-	ib_cpu[len + 73] = 0x7800;
-	ib_cpu[len + 74] = 0x7800 + 0x5000;
+	ib_cpu[len + 14] = ALIGN(enc->width, align);
+	ib_cpu[len + 15] = ALIGN(enc->width, align);
+	ib_cpu[len + 73] = luma_size * 1.5;
+	ib_cpu[len + 74] = luma_size * 2.5;
 	len += sizeof(vce_encode) / 4;
 	enc->ib_len = len;
 	if (!enc->two_instance) {
 		r = submit(len, AMDGPU_HW_IP_VCE);
 		CU_ASSERT_EQUAL(r, 0);
 	}
 }
 
 static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc)
 {
 	uint64_t luma_offset, chroma_offset;
-	int len, r;
+	int len, i, r;
+	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
+	unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
 
 	len = (enc->two_instance) ? enc->ib_len : 0;
 	luma_offset = enc->vbuf.addr;
-	chroma_offset = luma_offset + enc->width * enc->height;
+	chroma_offset = luma_offset + luma_size;
 
 	if (!enc->two_instance) {
 		memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
 		len += sizeof(vce_session) / 4;
 	}
 	memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
 	len += sizeof(vce_taskinfo) / 4;
 	memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
 	ib_cpu[len + 2] = enc->bs[1].addr >> 32;
 	ib_cpu[len + 3] = enc->bs[1].addr;
 	len += sizeof(vce_bs_buffer) / 4;
 	memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
 	ib_cpu[len + 2] = enc->cpb.addr >> 32;
 	ib_cpu[len + 3] = enc->cpb.addr;
 	len += sizeof(vce_context_buffer) / 4;
 	memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
+	for (i = 0; i <  8; ++i)
+		ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
+	for (i = 0; i <  8; ++i)
+		ib_cpu[len + 10 + i] = luma_size * 1.5;
 	len += sizeof(vce_aux_buffer) / 4;
 	memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
 	ib_cpu[len + 2] = enc->fb[1].addr >> 32;
 	ib_cpu[len + 3] = enc->fb[1].addr;
 	len += sizeof(vce_feedback) / 4;
 	memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
 	ib_cpu[len + 2] = 0;
 	ib_cpu[len + 9] = luma_offset >> 32;
 	ib_cpu[len + 10] = luma_offset;
 	ib_cpu[len + 11] = chroma_offset >> 32;
 	ib_cpu[len + 12] = chroma_offset;
+	ib_cpu[len + 14] = ALIGN(enc->width, align);
+	ib_cpu[len + 15] = ALIGN(enc->width, align);
 	ib_cpu[len + 18] = 0;
 	ib_cpu[len + 19] = 0;
 	ib_cpu[len + 56] = 3;
 	ib_cpu[len + 57] = 0;
 	ib_cpu[len + 58] = 0;
-	ib_cpu[len + 59] = 0x7800;
-	ib_cpu[len + 60] = 0x7800 + 0x5000;
+	ib_cpu[len + 59] = luma_size * 1.5;
+	ib_cpu[len + 60] = luma_size * 2.5;
 	ib_cpu[len + 73] = 0;
-	ib_cpu[len + 74] = 0x5000;
+	ib_cpu[len + 74] = luma_size;
 	ib_cpu[len + 81] = 1;
 	ib_cpu[len + 82] = 1;
 	len += sizeof(vce_encode) / 4;
 
 	r = submit(len, AMDGPU_HW_IP_VCE);
 	CU_ASSERT_EQUAL(r, 0);
 }
 
 static void check_result(struct amdgpu_vce_encode *enc)
 {
@@ -401,42 +420,53 @@ static void check_result(struct amdgpu_vce_encode *enc)
 			sum += enc->bs[i].ptr[j];
 		CU_ASSERT_EQUAL(sum, s[i]);
 		r = amdgpu_bo_cpu_unmap(enc->bs[i].handle);
 		CU_ASSERT_EQUAL(r, 0);
 	}
 }
 
 static void amdgpu_cs_vce_encode(void)
 {
 	uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
-	int r;
+	unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
+	int i, r;
 
-	vbuf_size = enc.width * enc.height * 1.5;
+	vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
 	cpb_size = vbuf_size * 10;
 	num_resources = 0;
 	alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
 	resources[num_resources++] = enc.fb[0].handle;
 	alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT);
 	resources[num_resources++] = enc.fb[1].handle;
 	alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
 	resources[num_resources++] = enc.bs[0].handle;
 	alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT);
 	resources[num_resources++] = enc.bs[1].handle;
 	alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
 	resources[num_resources++] = enc.vbuf.handle;
 	alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
 	resources[num_resources++] = enc.cpb.handle;
 	resources[num_resources++] = ib_handle;
 
 	r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
 	CU_ASSERT_EQUAL(r, 0);
-	memcpy(enc.vbuf.ptr, frame, sizeof(frame));
+
+	memset(enc.vbuf.ptr, 0, vbuf_size);
+	for (i = 0; i < enc.height; ++i) {
+		memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
+		enc.vbuf.ptr += ALIGN(enc.width, align);
+	}
+	for (i = 0; i < enc.height / 2; ++i) {
+		memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
+		enc.vbuf.ptr += ALIGN(enc.width, align);
+	}
+
 	r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
 	CU_ASSERT_EQUAL(r, 0);
 
 	amdgpu_cs_vce_config();
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		vce_taskinfo[3] = 3;
 		amdgpu_cs_vce_encode_idr(&enc);
 		amdgpu_cs_vce_encode_p(&enc);
 		check_result(&enc);
-- 
2.7.4

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[PATCH libdrm 7/7] tests/amdgpu: add Polaris12 support for cs test

[Marek Olšák]

From: Junwei Zhang <Jerry.Zhang@amd.com>

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
---
 tests/amdgpu/cs_tests.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
index 0885d97..342815d 100644
--- a/tests/amdgpu/cs_tests.c
+++ b/tests/amdgpu/cs_tests.c
@@ -209,21 +209,22 @@ static void amdgpu_cs_uvd_create(void)
 
 	r = amdgpu_bo_cpu_map(buf_handle, &msg);
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		((uint8_t*)msg)[0x10] = 7;
 		/* chip beyond polaris 10/11 */
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			/* dpb size */
 			((uint8_t*)msg)[0x28] = 0x00;
 			((uint8_t*)msg)[0x29] = 0x94;
 			((uint8_t*)msg)[0x2A] = 0x6B;
 			((uint8_t*)msg)[0x2B] = 0x00;
 		}
 	}
 
 	r = amdgpu_bo_cpu_unmap(buf_handle);
 	CU_ASSERT_EQUAL(r, 0);
@@ -289,21 +290,22 @@ static void amdgpu_cs_uvd_decode(void)
 	CU_ASSERT_EQUAL(r, 0);
 
 	memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		ptr[0x10] = 7;
 		ptr[0x98] = 0x00;
 		ptr[0x99] = 0x02;
 		/* chip beyond polaris10/11 */
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			/* dpb size */
 			ptr[0x24] = 0x00;
 			ptr[0x25] = 0x94;
 			ptr[0x26] = 0x6B;
 			ptr[0x27] = 0x00;
 			/*ctx size */
 			ptr[0x2C] = 0x00;
 			ptr[0x2D] = 0xAF;
 			ptr[0x2E] = 0x50;
 			ptr[0x2F] = 0x00;
@@ -334,38 +336,40 @@ static void amdgpu_cs_uvd_decode(void)
 	fb_addr = msg_addr + 4*1024;
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		it_addr = fb_addr + 4*1024;
 		bs_addr = it_addr + 4*1024;
 	} else
 		bs_addr = fb_addr + 4*1024;
 	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64)) {
 			ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
 		}
 	}
 
 	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
 
 	i = 0;
 	uvd_cmd(msg_addr, 0x0, &i);
 	uvd_cmd(dpb_addr, 0x1, &i);
 	uvd_cmd(dt_addr, 0x2, &i);
 	uvd_cmd(fb_addr, 0x3, &i);
 	uvd_cmd(bs_addr, 0x100, &i);
 
 	if (family_id >= AMDGPU_FAMILY_VI) {
 		uvd_cmd(it_addr, 0x204, &i);
 		if ((family_id == AMDGPU_FAMILY_AI) ||
-		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A))
+		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
+		     chip_id == chip_rev+0x64))
 			uvd_cmd(ctx_addr, 0x206, &i);
 	}
 
 	ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
 	ib_cpu[i++] = 0x1;
 	for (; i % 16; ++i)
 		ib_cpu[i] = 0x80000000;
 
 	r = submit(i, AMDGPU_HW_IP_UVD);
 	CU_ASSERT_EQUAL(r, 0);
-- 
2.7.4

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RE: [PATCH libdrm 7/7] tests/amdgpu: add Polaris12 support for cs test

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Marek Olšák
> Sent: Tuesday, March 21, 2017 3:56 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH libdrm 7/7] tests/amdgpu: add Polaris12 support for cs test
> 
> From: Junwei Zhang <Jerry.Zhang@amd.com>
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
> ---
>  tests/amdgpu/cs_tests.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
> index 0885d97..342815d 100644
> --- a/tests/amdgpu/cs_tests.c
> +++ b/tests/amdgpu/cs_tests.c
> @@ -209,21 +209,22 @@ static void amdgpu_cs_uvd_create(void)
> 
>  	r = amdgpu_bo_cpu_map(buf_handle, &msg);
>  	CU_ASSERT_EQUAL(r, 0);
> 
>  	memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
> 
>  	if (family_id >= AMDGPU_FAMILY_VI) {
>  		((uint8_t*)msg)[0x10] = 7;
>  		/* chip beyond polaris 10/11 */
>  		if ((family_id == AMDGPU_FAMILY_AI) ||
> -		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
> +		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
> +		     chip_id == chip_rev+0x64)) {
>  			/* dpb size */
>  			((uint8_t*)msg)[0x28] = 0x00;
>  			((uint8_t*)msg)[0x29] = 0x94;
>  			((uint8_t*)msg)[0x2A] = 0x6B;
>  			((uint8_t*)msg)[0x2B] = 0x00;
>  		}
>  	}
> 
>  	r = amdgpu_bo_cpu_unmap(buf_handle);
>  	CU_ASSERT_EQUAL(r, 0);
> @@ -289,21 +290,22 @@ static void amdgpu_cs_uvd_decode(void)
>  	CU_ASSERT_EQUAL(r, 0);
> 
>  	memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
> 
>  	if (family_id >= AMDGPU_FAMILY_VI) {
>  		ptr[0x10] = 7;
>  		ptr[0x98] = 0x00;
>  		ptr[0x99] = 0x02;
>  		/* chip beyond polaris10/11 */
>  		if ((family_id == AMDGPU_FAMILY_AI) ||
> -		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
> +		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
> +		     chip_id == chip_rev+0x64)) {
>  			/* dpb size */
>  			ptr[0x24] = 0x00;
>  			ptr[0x25] = 0x94;
>  			ptr[0x26] = 0x6B;
>  			ptr[0x27] = 0x00;
>  			/*ctx size */
>  			ptr[0x2C] = 0x00;
>  			ptr[0x2D] = 0xAF;
>  			ptr[0x2E] = 0x50;
>  			ptr[0x2F] = 0x00;
> @@ -334,38 +336,40 @@ static void amdgpu_cs_uvd_decode(void)
>  	fb_addr = msg_addr + 4*1024;
>  	if (family_id >= AMDGPU_FAMILY_VI) {
>  		it_addr = fb_addr + 4*1024;
>  		bs_addr = it_addr + 4*1024;
>  	} else
>  		bs_addr = fb_addr + 4*1024;
>  	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
> 
>  	if (family_id >= AMDGPU_FAMILY_VI) {
>  		if ((family_id == AMDGPU_FAMILY_AI) ||
> -		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A)) {
> +		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
> +		     chip_id == chip_rev+0x64)) {
>  			ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
>  		}
>  	}
> 
>  	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
> 
>  	i = 0;
>  	uvd_cmd(msg_addr, 0x0, &i);
>  	uvd_cmd(dpb_addr, 0x1, &i);
>  	uvd_cmd(dt_addr, 0x2, &i);
>  	uvd_cmd(fb_addr, 0x3, &i);
>  	uvd_cmd(bs_addr, 0x100, &i);
> 
>  	if (family_id >= AMDGPU_FAMILY_VI) {
>  		uvd_cmd(it_addr, 0x204, &i);
>  		if ((family_id == AMDGPU_FAMILY_AI) ||
> -		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A))
> +		    (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A ||
> +		     chip_id == chip_rev+0x64))
>  			uvd_cmd(ctx_addr, 0x206, &i);
>  	}
> 
>  	ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6;
>  	ib_cpu[i++] = 0x1;
>  	for (; i % 16; ++i)
>  		ib_cpu[i] = 0x80000000;
> 
>  	r = submit(i, AMDGPU_HW_IP_UVD);
>  	CU_ASSERT_EQUAL(r, 0);
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Nicolai Hähnle]

In the past, I was told off for patches that update this file without 
following the procedure described in include/drm/README. Tbh, that 
procedure causes some annoyances.

Anyway, it's definitely useful to have the patch out on the mailing list 
in any case.

Cheers,
Nicolai

On 21.03.2017 20:56, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> ---
>  include/drm/amdgpu_drm.h | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index 5797283..d702a95 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -202,42 +202,47 @@ union drm_amdgpu_ctx {
>
>  struct drm_amdgpu_gem_userptr {
>  	__u64		addr;
>  	__u64		size;
>  	/* AMDGPU_GEM_USERPTR_* */
>  	__u32		flags;
>  	/* Resulting GEM handle */
>  	__u32		handle;
>  };
>
> +/* SI-CI-VI: */
>  /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
>  #define AMDGPU_TILING_ARRAY_MODE_SHIFT			0
>  #define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
>  #define AMDGPU_TILING_PIPE_CONFIG_SHIFT			4
>  #define AMDGPU_TILING_PIPE_CONFIG_MASK			0x1f
>  #define AMDGPU_TILING_TILE_SPLIT_SHIFT			9
>  #define AMDGPU_TILING_TILE_SPLIT_MASK			0x7
>  #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT		12
>  #define AMDGPU_TILING_MICRO_TILE_MODE_MASK		0x7
>  #define AMDGPU_TILING_BANK_WIDTH_SHIFT			15
>  #define AMDGPU_TILING_BANK_WIDTH_MASK			0x3
>  #define AMDGPU_TILING_BANK_HEIGHT_SHIFT			17
>  #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
>  #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
>  #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
>  #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
>
> +/* GFX9 and later: */
> +#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
> +#define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
> +
>  #define AMDGPU_TILING_SET(field, value) \
> -	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
> +	(((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
>  #define AMDGPU_TILING_GET(value, field) \
> -	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
> +	(((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
>
>  #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
>  #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
>
>  /** The same structure is shared for input/output */
>  struct drm_amdgpu_gem_metadata {
>  	/** GEM Object handle */
>  	__u32	handle;
>  	/** Do we want get or set metadata */
>  	__u32	op;
> @@ -748,16 +753,17 @@ struct drm_amdgpu_info_vce_clock_table {
>
>  /*
>   * Supported GPU families
>   */
>  #define AMDGPU_FAMILY_UNKNOWN			0
>  #define AMDGPU_FAMILY_SI			110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
>  #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
>  #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
>  #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
>  #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
> +#define AMDGPU_FAMILY_AI			141 /* Vega10 */
>
>  #if defined(__cplusplus)
>  }
>  #endif
>
>  #endif
>

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Re: [PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Marek Olšák]

On Tue, Mar 21, 2017 at 10:27 PM, Nicolai Hähnle <nhaehnle@gmail.com> wrote:
> In the past, I was told off for patches that update this file without
> following the procedure described in include/drm/README. Tbh, that procedure
> causes some annoyances.
>
> Anyway, it's definitely useful to have the patch out on the mailing list in
> any case.

Yeah, I know the correct process and I plan to ignore it this time if
I don't get too much backlash, because the alternative
(#ifdef/#define/#endif) is probably even worse.

Marek
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Re: [PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Michel Dänzer]

On 22/03/17 06:46 AM, Marek Olšák wrote:
> On Tue, Mar 21, 2017 at 10:27 PM, Nicolai Hähnle <nhaehnle@gmail.com> wrote:
>> In the past, I was told off for patches that update this file without
>> following the procedure described in include/drm/README. Tbh, that procedure
>> causes some annoyances.
>>
>> Anyway, it's definitely useful to have the patch out on the mailing list in
>> any case.
> 
> Yeah, I know the correct process and I plan to ignore it this time if
> I don't get too much backlash, because the alternative
> (#ifdef/#define/#endif) is probably even worse.

FWIW, only AMDGPU_TILING_SET/GET need #undef,
AMDGPU_TILING_SWIZZLE_MODE_SHIFT/MASK and AMDGPU_FAMILY_AI can just be
#defined directly, that way the preprocessor will warn if the
definitions in libdrm and Mesa end up being inconsistent for some reason.


The alternative is rushing out a libdrm release and making Mesa require
that, right? That doesn't seem obviously better than a handful of
temporary redundant defines in Mesa, hardly justification for bypassing
the normal process.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Marek Olšák]

[-- Attachment #1.1: Type: text/plain, Size: 1486 bytes --]

On Mar 22, 2017 2:44 AM, "Michel Dänzer" <michel-otUistvHUpPR7s880joybQ@public.gmane.org> wrote:

On 22/03/17 06:46 AM, Marek Olšák wrote:
> On Tue, Mar 21, 2017 at 10:27 PM, Nicolai Hähnle <nhaehnle-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
wrote:
>> In the past, I was told off for patches that update this file without
>> following the procedure described in include/drm/README. Tbh, that
procedure
>> causes some annoyances.
>>
>> Anyway, it's definitely useful to have the patch out on the mailing list
in
>> any case.
>
> Yeah, I know the correct process and I plan to ignore it this time if
> I don't get too much backlash, because the alternative
> (#ifdef/#define/#endif) is probably even worse.

FWIW, only AMDGPU_TILING_SET/GET need #undef,
AMDGPU_TILING_SWIZZLE_MODE_SHIFT/MASK and AMDGPU_FAMILY_AI can just be
#defined directly, that way the preprocessor will warn if the
definitions in libdrm and Mesa end up being inconsistent for some reason.


The alternative is rushing out a libdrm release and making Mesa require
that, right? That doesn't seem obviously better than a handful of
temporary redundant defines in Mesa, hardly justification for bypassing
the normal process.


I need a libdrm release because of the 3rd patch. I can't allow Mesa to run
without that.

Marek



--
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer

[-- Attachment #1.2: Type: text/html, Size: 2522 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH libdrm 2/7] amdgpu: update amdgpu_drm.h for Vega10

[Michel Dänzer]

On 22/03/17 07:13 PM, Marek Olšák wrote:
> On Mar 22, 2017 2:44 AM, "Michel Dänzer" <michel@daenzer.net 
> <mailto:michel@daenzer.net>> wrote:
>> On 22/03/17 06:46 AM, Marek Olšák wrote:
>>> On Tue, Mar 21, 2017 at 10:27 PM, Nicolai Hähnle 
>>> <nhaehnle@gmail.com <mailto:nhaehnle@gmail.com>> wrote:
>>>> In the past, I was told off for patches that update this file
>>>> without following the procedure described in
>>>> include/drm/README. Tbh, that procedure causes some
>>>> annoyances.
>>>> 
>>>> Anyway, it's definitely useful to have the patch out on the 
>>>> mailing list in any case.
>>> 
>>> Yeah, I know the correct process and I plan to ignore it this
>>> time if I don't get too much backlash, because the alternative 
>>> (#ifdef/#define/#endif) is probably even worse.
>> 
>> FWIW, only AMDGPU_TILING_SET/GET need #undef, 
>> AMDGPU_TILING_SWIZZLE_MODE_SHIFT/MASK and AMDGPU_FAMILY_AI can just
>> be #defined directly, that way the preprocessor will warn if the 
>> definitions in libdrm and Mesa end up being inconsistent for some 
>> reason.
>> 
>> 
>> The alternative is rushing out a libdrm release and making Mesa
>> require that, right? That doesn't seem obviously better than a
>> handful of temporary redundant defines in Mesa, hardly
>> justification for bypassing the normal process.
> 
> I need a libdrm release because of the 3rd patch. I can't allow Mesa
> to run without that.

Gotcha, thanks for the clarification.


-- 
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer

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