[PATCH] clk: aspeed: fix APB and AHB clock rates

["Cédric Le Goater" <clg@kaod.org>]

The masking is one bit too generous which generates really low clock
rates.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 drivers/clk/aspeed/clk-g4.c | 2 +-
 drivers/clk/aspeed/clk-g5.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/aspeed/clk-g4.c b/drivers/clk/aspeed/clk-g4.c
index bf61919ead52..50117ec16909 100644
--- a/drivers/clk/aspeed/clk-g4.c
+++ b/drivers/clk/aspeed/clk-g4.c
@@ -94,7 +94,7 @@ static unsigned long aspeed_clk_apb_recalc_rate(struct clk_hw *hw,
 		return ret;
 	}
 
-	reg = (reg >> 23) & GENMASK(2, 0);
+	reg = (reg >> 23) & 0x3;
 
 	return hpll_rate / (2 + 2 * reg);
 }
diff --git a/drivers/clk/aspeed/clk-g5.c b/drivers/clk/aspeed/clk-g5.c
index 6eb0004f894d..8f8f7f796cee 100644
--- a/drivers/clk/aspeed/clk-g5.c
+++ b/drivers/clk/aspeed/clk-g5.c
@@ -84,7 +84,7 @@ static unsigned long aspeed_clk_ahb_recalc_rate(struct clk_hw *hw,
 	}
 
 	/* Bits 11:9 define the AXI/AHB clock frequency ratio */
-	reg = (reg >> 9) & GENMASK(3, 0);
+	reg = (reg >> 9) & 0x7;
 
 	/* A value of zero is undefined */
 	WARN_ON(reg == 0);
@@ -108,7 +108,7 @@ static unsigned long aspeed_clk_apb_recalc_rate(struct clk_hw *hw,
 		return ret;
 	}
 
-	reg = (reg >> 23) & GENMASK(3, 0);
+	reg = (reg >> 23) & 0x7;
 
 	rate = hpll_rate / (4 * (reg + 1));
 
-- 
2.7.4