[PATCH 1/2] drm/amdgpu: drop GB_GPU_ID from the golden settings

[PATCH 1/2] drm/amdgpu: drop GB_GPU_ID from the golden settings

[Christian König]

From: Christian König <christian.koenig@amd.com>

That register is marked deprecated, reading it results in a bus error.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ad82ab7..b196431 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -88,7 +88,6 @@ static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 static const u32 golden_settings_gc_9_0[] =
 {
 	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
-	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
-- 
2.5.0

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[PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

[Christian König]

From: Christian König <christian.koenig@amd.com>

Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the
same info is available cached as enabled_rb_pipes_mask.

Also remove duplicate mmCP_CPF_BUSY_STAT.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7e54d9dc..be0d47f 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -296,11 +296,9 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
 	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
 	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
 	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
-	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
 	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
 	{ SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
 	{ SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
-	{ SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
 	{ SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
 	{ SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
 };
-- 
2.5.0

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Re: [PATCH 1/2] drm/amdgpu: drop GB_GPU_ID from the golden settings

[Alex Deucher]

On Fri, Mar 24, 2017 at 11:09 AM, Christian König
<deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> That register is marked deprecated, reading it results in a bus error.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Might want to compare with the latest golden register list in CAIL to
see if it's already removed and pick up any additional changes if
there are any.  Otherwise:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ad82ab7..b196431 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -88,7 +88,6 @@ static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
>  static const u32 golden_settings_gc_9_0[] =
>  {
>         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400,
> -       SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
>         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
>         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
>         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
> --
> 2.5.0
>
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Re: [PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

[Alex Deucher]

On Fri, Mar 24, 2017 at 11:09 AM, Christian König
<deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the
> same info is available cached as enabled_rb_pipes_mask.

NACK.  We need to implement the caching anyway for sr-iov.  We can
just port the cache changes over from VI.  Have you started looking at
that yet?

Alex

>
> Also remove duplicate mmCP_CPF_BUSY_STAT.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 7e54d9dc..be0d47f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -296,11 +296,9 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
>         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
>         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
>         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
> -       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
>         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
>         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
>         { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
> -       { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
>         { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
>         { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
>  };
> --
> 2.5.0
>
> _______________________________________________
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Re: [PATCH 2/2] drm/amdgpu: sanitize soc15_allowed_read_registers

[Christian König]

Am 24.03.2017 um 19:38 schrieb Alex Deucher:
> On Fri, Mar 24, 2017 at 11:09 AM, Christian König
> <deathsimple@vodafone.de> wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> Disallow mmCC_RB_BACKEND_DISABLE, reading it can cause GRBM problems and the
>> same info is available cached as enabled_rb_pipes_mask.
> NACK.  We need to implement the caching anyway for sr-iov.  We can
> just port the cache changes over from VI.  Have you started looking at
> that yet?

Yeah, had that halve way implemented and then realized that the 
registers aren't used by userspace any more.

The only user was addrlib and even there it actually looks incorrect to me.

Ken already had that mostly fixed in libdrm, but somehow missed that 
one. Going to send out libdrm changes to not read from it as well.

Additional to that it is completely pointless to read the register again 
when the info query already has everything from it anyway.

Christian.

>
> Alex
>
>> Also remove duplicate mmCP_CPF_BUSY_STAT.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/soc15.c | 2 --
>>   1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index 7e54d9dc..be0d47f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -296,11 +296,9 @@ static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
>>          { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
>>          { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
>>          { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
>> -       { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
>>          { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
>>          { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
>>          { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
>> -       { SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE), false, true},
>>          { SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE), false, true},
>>          { SOC15_REG_OFFSET(GC, 0, mmGB_BACKEND_MAP), false, false},
>>   };
>> --
>> 2.5.0
>>
>> _______________________________________________
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> _______________________________________________
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