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From: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: [PATCH 2/6] clk: qcom: Make clk_alpha_pll_configure available to modules
Date: Wed,  5 Apr 2017 10:25:25 +0530	[thread overview]
Message-ID: <1491368129-24721-3-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

Allow clk_alpha_pll_configure to be called from loadable
kernel modules.

Signed-off-by: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index ecb9e7f..7b06e21 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -141,6 +141,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 	if (pll->flags & SUPPORTS_FSM_MODE)
 		qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
 }
+EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

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WARNING: multiple messages have this Message-ID (diff)
From: Rajendra Nayak <rnayak@codeaurora.org>
To: sboyd@codeaurora.org, mturquette@baylibre.com
Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org,
	Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH 2/6] clk: qcom: Make clk_alpha_pll_configure available to modules
Date: Wed,  5 Apr 2017 10:25:25 +0530	[thread overview]
Message-ID: <1491368129-24721-3-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1491368129-24721-1-git-send-email-rnayak@codeaurora.org>

Allow clk_alpha_pll_configure to be called from loadable
kernel modules.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index ecb9e7f..7b06e21 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -141,6 +141,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 	if (pll->flags & SUPPORTS_FSM_MODE)
 		qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
 }
+EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2017-04-05  4:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-05  4:55 [PATCH 0/6] clk: qcom: CPU clock driver for msm8996 Rajendra Nayak
2017-04-05  4:55 ` Rajendra Nayak
2017-04-05  4:55 ` [PATCH 1/6] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update Rajendra Nayak
2017-04-05  4:55 ` [PATCH 3/6] clk: qcom: Add CPU clock driver for msm8996 Rajendra Nayak
2017-04-10 16:23   ` Rob Herring
2017-04-05  4:55 ` [PATCH 4/6] clk: qcom: cpu-8996: Add support to switch to alternate PLL Rajendra Nayak
     [not found] ` <1491368129-24721-1-git-send-email-rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-04-05  4:55   ` Rajendra Nayak [this message]
2017-04-05  4:55     ` [PATCH 2/6] clk: qcom: Make clk_alpha_pll_configure available to modules Rajendra Nayak
2017-04-05  4:55   ` [PATCH 5/6] clk: qcom: cpu-8996: Add support to switch below 600Mhz Rajendra Nayak
2017-04-05  4:55     ` Rajendra Nayak
2017-04-05  4:55   ` [PATCH 6/6] arm64: dts: msm8996: Add CPU clock controller node Rajendra Nayak
2017-04-05  4:55     ` Rajendra Nayak

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