* net/i40e: fix hash input set issue on X722
@ 2017-04-06 2:35 Jeff Guo
2017-04-11 3:43 ` Wu, Jingjing
0 siblings, 1 reply; 3+ messages in thread
From: Jeff Guo @ 2017-04-06 2:35 UTC (permalink / raw)
To: helin.zhang, jingjing.wu; +Cc: dev, jia.guo
Since there are some new pctypes on X722, but recently they have
not been announced on the RTE lib, so if it can not correspondently
set hash input set for these packet type, the hash function won’t
work. So we need to handle them base on the translation of the new
PCTYPE and the original PCTYPE.
Fixes: b6a0ec418274 ("i40e: use AQ for Rx control register read/write")
Signed-off-by: Jeff Guo <jia.guo@intel.com>
---
drivers/net/i40e/i40e_ethdev.c | 39 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 303027b..88b994b 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -7425,7 +7425,44 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
pctype = i40e_flowtype_to_pctype(i);
reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
- i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
+ if (hw->mac.type == I40E_MAC_X722) {
+ if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
+ reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
+ reg);
+ } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
+ reg);
+ } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
+ reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
+ reg);
+ } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
+ I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
+ reg);
+ } else {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
+ reg);
+ }
+ } else {
+ i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
+ }
}
reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: net/i40e: fix hash input set issue on X722
2017-04-06 2:35 net/i40e: fix hash input set issue on X722 Jeff Guo
@ 2017-04-11 3:43 ` Wu, Jingjing
2017-04-11 11:14 ` Ferruh Yigit
0 siblings, 1 reply; 3+ messages in thread
From: Wu, Jingjing @ 2017-04-11 3:43 UTC (permalink / raw)
To: Guo, Jia, Zhang, Helin; +Cc: dev
> -----Original Message-----
> From: Guo, Jia
> Sent: Thursday, April 6, 2017 10:35 AM
> To: Zhang, Helin <helin.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
> Subject: [dpdk-dev] net/i40e: fix hash input set issue on X722
>
> Since there are some new pctypes on X722, but recently they have not been
> announced on the RTE lib, so if it can not correspondently set hash input set for
> these packet type, the hash function won’t work. So we need to handle them
> base on the translation of the new PCTYPE and the original PCTYPE.
>
> Fixes: b6a0ec418274 ("i40e: use AQ for Rx control register read/write")
>
> Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: net/i40e: fix hash input set issue on X722
2017-04-11 3:43 ` Wu, Jingjing
@ 2017-04-11 11:14 ` Ferruh Yigit
0 siblings, 0 replies; 3+ messages in thread
From: Ferruh Yigit @ 2017-04-11 11:14 UTC (permalink / raw)
To: Wu, Jingjing, Guo, Jia, Zhang, Helin; +Cc: dev
On 4/11/2017 4:43 AM, Wu, Jingjing wrote:
>
>
>> -----Original Message-----
>> From: Guo, Jia
>> Sent: Thursday, April 6, 2017 10:35 AM
>> To: Zhang, Helin <helin.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>
>> Cc: dev@dpdk.org; Guo, Jia <jia.guo@intel.com>
>> Subject: [dpdk-dev] net/i40e: fix hash input set issue on X722
>>
>> Since there are some new pctypes on X722, but recently they have not been
>> announced on the RTE lib, so if it can not correspondently set hash input set for
>> these packet type, the hash function won’t work. So we need to handle them
>> base on the translation of the new PCTYPE and the original PCTYPE.
>>
>> Fixes: b6a0ec418274 ("i40e: use AQ for Rx control register read/write")
>>
>> Signed-off-by: Jeff Guo <jia.guo@intel.com>
> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-04-11 11:14 ` Ferruh Yigit
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