* [PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2) @ 2017-04-06 10:19 Junwei Zhang [not found] ` <1491473999-20529-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 4+ messages in thread From: Junwei Zhang @ 2017-04-06 10:19 UTC (permalink / raw) To: alexander.deucher-5C7GfCeVMHo Cc: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW By default, the value is set by individual gmc. if a specific value is input, it overrides the global value for all v2: create helper funcs Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ++++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++--- 8 files changed, 60 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1d0c742..8fce309 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1039,35 +1039,31 @@ static bool amdgpu_check_pot_argument(int arg) return (arg & (arg - 1)) == 0; } -static void amdgpu_get_block_size(struct amdgpu_device *adev) +static void amdgpu_check_block_size(struct amdgpu_device *adev) { /* defines number of bits in page table versus page directory, * a page is 4KB so we have 12 bits offset, minimum 9 bits in the * page table and the remaining bits are in the page directory */ - if (amdgpu_vm_block_size == -1) { - - /* Total bits covered by PD + PTs */ - unsigned bits = ilog2(amdgpu_vm_size) + 18; - - /* Make sure the PD is 4K in size up to 8GB address space. - Above that split equal between PD and PTs */ - if (amdgpu_vm_size <= 8) - amdgpu_vm_block_size = bits - 9; - else - amdgpu_vm_block_size = (bits + 3) / 2; + if (amdgpu_vm_block_size == -1) + return; - } else if (amdgpu_vm_block_size < 9) { + if (amdgpu_vm_block_size < 9) { dev_warn(adev->dev, "VM page table size (%d) too small\n", amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; + goto def_value; } if (amdgpu_vm_block_size > 24 || (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { dev_warn(adev->dev, "VM page table size (%d) too large\n", amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; + goto def_value; } + + return; + +def_value: + amdgpu_vm_block_size = -1; } static void amdgpu_check_vm_size(struct amdgpu_device *adev) @@ -1096,8 +1092,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) return; def_value: - amdgpu_vm_size = 8; - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); + amdgpu_vm_size = -1; } /** @@ -1131,7 +1126,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_check_vm_size(adev); - amdgpu_get_block_size(adev); + amdgpu_check_block_size(adev); if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index bfd945b..6238e2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -86,7 +86,7 @@ unsigned amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; -int amdgpu_vm_size = 64; +int amdgpu_vm_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8785420..bc2650ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, } } +static uint32_t amdgpu_get_block_size(uint64_t vm_size) +{ + /* Total bits covered by PD + PTs */ + unsigned bits = ilog2(vm_size) + 18; + + /* Make sure the PD is 4K in size up to 8GB address space. + Above that split equal between PD and PTs */ + if (vm_size <= 8) + return (bits - 9); + else + return ((bits + 3) / 2); +} + +/** + * amdgpu_vm_adjust_size - adjust vm size and block size + * + * @adev: amdgpu_device pointer + * @vm_size: the default vm size if it's set auto + */ +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) +{ + /* adjust vm size firstly */ + if (amdgpu_vm_size == -1) + adev->vm_manager.vm_size = vm_size; + else + adev->vm_manager.vm_size = amdgpu_vm_size; + + /* block size depends on vm size */ + if (amdgpu_vm_block_size == -1) + adev->vm_manager.block_size = + amdgpu_get_block_size(adev->vm_manager.vm_size); + else + adev->vm_manager.block_size = amdgpu_vm_block_size; + + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + adev->vm_manager.vm_size, adev->vm_manager.block_size); +} + /** * amdgpu_vm_init - initialize a vm instance * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 7d01372..6f158d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, uint64_t saddr, uint64_t size); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 30d5c42..631aef3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - adev->mc.mc_mask = 0xffffffffffULL; adev->need_dma32 = false; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 7113765..92abe12 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index b3d1f1b..f2ccefc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e1637d5..77e7784f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -552,8 +552,7 @@ static int gmc_v9_0_sw_init(void *handle) if (adev->flags & AMD_IS_APU) { adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); } else { /* XXX Don't know how to get VRAM type yet. */ adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; @@ -564,11 +563,11 @@ static int gmc_v9_0_sw_init(void *handle) */ adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + adev->vm_manager.vm_size, + adev->vm_manager.block_size); } - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, &adev->mc.vm_fault); -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
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* Re: [PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2) [not found] ` <1491473999-20529-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> @ 2017-04-06 12:07 ` Christian König [not found] ` <04eb5d6d-8d29-82aa-e367-d918e71253d2-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 4+ messages in thread From: Christian König @ 2017-04-06 12:07 UTC (permalink / raw) To: Junwei Zhang, alexander.deucher-5C7GfCeVMHo Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 06.04.2017 um 12:19 schrieb Junwei Zhang: > By default, the value is set by individual gmc. > if a specific value is input, it overrides the global value for all > > v2: create helper funcs > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> A few minor issues below, but apart from that looks good to me. > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ++++++++++-------------- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++++++++++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +---- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +---- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +---- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++--- > 8 files changed, 60 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 1d0c742..8fce309 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1039,35 +1039,31 @@ static bool amdgpu_check_pot_argument(int arg) > return (arg & (arg - 1)) == 0; > } > > -static void amdgpu_get_block_size(struct amdgpu_device *adev) > +static void amdgpu_check_block_size(struct amdgpu_device *adev) > { > /* defines number of bits in page table versus page directory, > * a page is 4KB so we have 12 bits offset, minimum 9 bits in the > * page table and the remaining bits are in the page directory */ > - if (amdgpu_vm_block_size == -1) { > - > - /* Total bits covered by PD + PTs */ > - unsigned bits = ilog2(amdgpu_vm_size) + 18; > - > - /* Make sure the PD is 4K in size up to 8GB address space. > - Above that split equal between PD and PTs */ > - if (amdgpu_vm_size <= 8) > - amdgpu_vm_block_size = bits - 9; > - else > - amdgpu_vm_block_size = (bits + 3) / 2; > + if (amdgpu_vm_block_size == -1) > + return; > > - } else if (amdgpu_vm_block_size < 9) { > + if (amdgpu_vm_block_size < 9) { > dev_warn(adev->dev, "VM page table size (%d) too small\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > > if (amdgpu_vm_block_size > 24 || > (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { > dev_warn(adev->dev, "VM page table size (%d) too large\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > + > + return; > + > +def_value: > + amdgpu_vm_block_size = -1; > } > > static void amdgpu_check_vm_size(struct amdgpu_device *adev) > @@ -1096,8 +1092,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) > return; > > def_value: > - amdgpu_vm_size = 8; > - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); > + amdgpu_vm_size = -1; > } > > /** > @@ -1131,7 +1126,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) > > amdgpu_check_vm_size(adev); > > - amdgpu_get_block_size(adev); > + amdgpu_check_block_size(adev); > > if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || > !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index bfd945b..6238e2e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -86,7 +86,7 @@ > unsigned amdgpu_ip_block_mask = 0xffffffff; > int amdgpu_bapm = -1; > int amdgpu_deep_color = 0; > -int amdgpu_vm_size = 64; > +int amdgpu_vm_size = -1; > int amdgpu_vm_block_size = -1; > int amdgpu_vm_fault_stop = 0; > int amdgpu_vm_debug = 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > index 8785420..bc2650ef 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > @@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, > } > } > > +static uint32_t amdgpu_get_block_size(uint64_t vm_size) Please rename that to amdgpu_vm_get_block_size(). > +{ > + /* Total bits covered by PD + PTs */ > + unsigned bits = ilog2(vm_size) + 18; > + > + /* Make sure the PD is 4K in size up to 8GB address space. > + Above that split equal between PD and PTs */ > + if (vm_size <= 8) > + return (bits - 9); > + else > + return ((bits + 3) / 2); > +} > + > +/** > + * amdgpu_vm_adjust_size - adjust vm size and block size > + * > + * @adev: amdgpu_device pointer > + * @vm_size: the default vm size if it's set auto > + */ > +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) > +{ > + /* adjust vm size firstly */ > + if (amdgpu_vm_size == -1) > + adev->vm_manager.vm_size = vm_size; > + else > + adev->vm_manager.vm_size = amdgpu_vm_size; > + > + /* block size depends on vm size */ > + if (amdgpu_vm_block_size == -1) > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + else > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + > + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", > + adev->vm_manager.vm_size, adev->vm_manager.block_size); > +} > + > /** > * amdgpu_vm_init - initialize a vm instance > * > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > index 7d01372..6f158d6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h > @@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, > uint64_t saddr, uint64_t size); > void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, > struct amdgpu_bo_va *bo_va); > +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); > > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > index 30d5c42..631aef3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > @@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle) > if (r) > return r; > > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + amdgpu_vm_adjust_size(adev, 64); > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > - DRM_INFO("vm size is %d GB, block size is %d-bit\n", > - adev->vm_manager.vm_size, adev->vm_manager.block_size); > - > adev->mc.mc_mask = 0xffffffffffULL; > > adev->need_dma32 = false; > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index 7113765..92abe12 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + amdgpu_vm_adjust_size(adev, 64); > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > - DRM_INFO("vm size is %d GB, block size is %d-bit\n", > - adev->vm_manager.vm_size, adev->vm_manager.block_size); > - > /* Set the internal MC address mask > * This is the max address of the GPU's > * internal address space. > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index b3d1f1b..f2ccefc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + amdgpu_vm_adjust_size(adev, 64); > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > - DRM_INFO("vm size is %d GB, block size is %d-bit\n", > - adev->vm_manager.vm_size, adev->vm_manager.block_size); > - > /* Set the internal MC address mask > * This is the max address of the GPU's > * internal address space. > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e1637d5..77e7784f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -552,8 +552,7 @@ static int gmc_v9_0_sw_init(void *handle) > > if (adev->flags & AMD_IS_APU) { > adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + amdgpu_vm_adjust_size(adev, 64); Make sure we also use 1 level page tables in the APU case as well. With that done and the function renamed the patch is Reviewed-by: Christian König <christian.koenig@amd.com>. Regards, Christian. > } else { > /* XXX Don't know how to get VRAM type yet. */ > adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; > @@ -564,11 +563,11 @@ static int gmc_v9_0_sw_init(void *handle) > */ > adev->vm_manager.vm_size = 1U << 18; > adev->vm_manager.block_size = 9; > + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", > + adev->vm_manager.vm_size, > + adev->vm_manager.block_size); > } > > - DRM_INFO("vm size is %d GB, block size is %d-bit\n", > - adev->vm_manager.vm_size, adev->vm_manager.block_size); > - > /* This interrupt is VMC page fault.*/ > r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, > &adev->mc.vm_fault); _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <04eb5d6d-8d29-82aa-e367-d918e71253d2-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* Re: [PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2) [not found] ` <04eb5d6d-8d29-82aa-e367-d918e71253d2-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2017-04-06 13:56 ` Zhang, Jerry [not found] ` <51C2AE07-B2D3-4A81-97FE-A79BDA5DBB8D-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 4+ messages in thread From: Zhang, Jerry @ 2017-04-06 13:56 UTC (permalink / raw) To: Christian König Cc: Zhang, Jerry, Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW [-- Attachment #1.1: Type: text/plain, Size: 9544 bytes --] 在 2017年4月6日,20:07,Christian König <deathsimple@vodafone.de<mailto:deathsimple@vodafone.de>> 写道: Am 06.04.2017 um 12:19 schrieb Junwei Zhang: By default, the value is set by individual gmc. if a specific value is input, it overrides the global value for all v2: create helper funcs Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com<mailto:Jerry.Zhang@amd.com>> A few minor issues below, but apart from that looks good to me. --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ++++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 ++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +---- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++--- 8 files changed, 60 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1d0c742..8fce309 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1039,35 +1039,31 @@ static bool amdgpu_check_pot_argument(int arg) return (arg & (arg - 1)) == 0; } -static void amdgpu_get_block_size(struct amdgpu_device *adev) +static void amdgpu_check_block_size(struct amdgpu_device *adev) { /* defines number of bits in page table versus page directory, * a page is 4KB so we have 12 bits offset, minimum 9 bits in the * page table and the remaining bits are in the page directory */ - if (amdgpu_vm_block_size == -1) { - - /* Total bits covered by PD + PTs */ - unsigned bits = ilog2(amdgpu_vm_size) + 18; - - /* Make sure the PD is 4K in size up to 8GB address space. - Above that split equal between PD and PTs */ - if (amdgpu_vm_size <= 8) - amdgpu_vm_block_size = bits - 9; - else - amdgpu_vm_block_size = (bits + 3) / 2; + if (amdgpu_vm_block_size == -1) + return; - } else if (amdgpu_vm_block_size < 9) { + if (amdgpu_vm_block_size < 9) { dev_warn(adev->dev, "VM page table size (%d) too small\n", amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; + goto def_value; } if (amdgpu_vm_block_size > 24 || (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { dev_warn(adev->dev, "VM page table size (%d) too large\n", amdgpu_vm_block_size); - amdgpu_vm_block_size = 9; + goto def_value; } + + return; + +def_value: + amdgpu_vm_block_size = -1; } static void amdgpu_check_vm_size(struct amdgpu_device *adev) @@ -1096,8 +1092,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) return; def_value: - amdgpu_vm_size = 8; - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); + amdgpu_vm_size = -1; } /** @@ -1131,7 +1126,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_check_vm_size(adev); - amdgpu_get_block_size(adev); + amdgpu_check_block_size(adev); if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index bfd945b..6238e2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -86,7 +86,7 @@ unsigned amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; -int amdgpu_vm_size = 64; +int amdgpu_vm_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8785420..bc2650ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, } } +static uint32_t amdgpu_get_block_size(uint64_t vm_size) Please rename that to amdgpu_vm_get_block_size(). +{ + /* Total bits covered by PD + PTs */ + unsigned bits = ilog2(vm_size) + 18; + + /* Make sure the PD is 4K in size up to 8GB address space. + Above that split equal between PD and PTs */ + if (vm_size <= 8) + return (bits - 9); + else + return ((bits + 3) / 2); +} + +/** + * amdgpu_vm_adjust_size - adjust vm size and block size + * + * @adev: amdgpu_device pointer + * @vm_size: the default vm size if it's set auto + */ +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) +{ + /* adjust vm size firstly */ + if (amdgpu_vm_size == -1) + adev->vm_manager.vm_size = vm_size; + else + adev->vm_manager.vm_size = amdgpu_vm_size; + + /* block size depends on vm size */ + if (amdgpu_vm_block_size == -1) + adev->vm_manager.block_size = + amdgpu_get_block_size(adev->vm_manager.vm_size); + else + adev->vm_manager.block_size = amdgpu_vm_block_size; + + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + adev->vm_manager.vm_size, adev->vm_manager.block_size); +} + /** * amdgpu_vm_init - initialize a vm instance * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 7d01372..6f158d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, uint64_t saddr, uint64_t size); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 30d5c42..631aef3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - adev->mc.mc_mask = 0xffffffffffULL; adev->need_dma32 = false; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 7113765..92abe12 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index b3d1f1b..f2ccefc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e1637d5..77e7784f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -552,8 +552,7 @@ static int gmc_v9_0_sw_init(void *handle) if (adev->flags & AMD_IS_APU) { adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - adev->vm_manager.vm_size = amdgpu_vm_size; - adev->vm_manager.block_size = amdgpu_vm_block_size; + amdgpu_vm_adjust_size(adev, 64); Make sure we also use 1 level page tables in the APU case as well. I also flashed a idea about it. Does APU still uses 1 level page now for gmc v9? Jerry With that done and the function renamed the patch is Reviewed-by: Christian König <christian.koenig@amd.com<mailto:christian.koenig@amd.com>>. Regards, Christian. } else { /* XXX Don't know how to get VRAM type yet. */ adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; @@ -564,11 +563,11 @@ static int gmc_v9_0_sw_init(void *handle) */ adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; + DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + adev->vm_manager.vm_size, + adev->vm_manager.block_size); } - DRM_INFO("vm size is %d GB, block size is %d-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); - /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, &adev->mc.vm_fault); [-- Attachment #1.2: Type: text/html, Size: 36515 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <51C2AE07-B2D3-4A81-97FE-A79BDA5DBB8D-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2) [not found] ` <51C2AE07-B2D3-4A81-97FE-A79BDA5DBB8D-5C7GfCeVMHo@public.gmane.org> @ 2017-04-07 2:35 ` zhoucm1 0 siblings, 0 replies; 4+ messages in thread From: zhoucm1 @ 2017-04-07 2:35 UTC (permalink / raw) To: Zhang, Jerry, Christian König Cc: Deucher, Alexander, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW [-- Attachment #1.1: Type: text/plain, Size: 10570 bytes --] On 2017年04月06日 21:56, Zhang, Jerry wrote: > >> 在 2017年4月6日,20:07,Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org >> <mailto:deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>> 写道: >> >> Am 06.04.2017 um 12:19 schrieb Junwei Zhang: >>> By default, the value is set by individual gmc. >>> if a specific value is input, it overrides the global value for all >>> >>> v2: create helper funcs >>> >>> Signed-off-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org >>> <mailto:Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>> >> >> A few minor issues below, but apart from that looks good to me. >> >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 >>> ++++++++++-------------- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 38 >>> ++++++++++++++++++++++++++++++ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 + >>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +---- >>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +---- >>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 +---- >>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++--- >>> 8 files changed, 60 insertions(+), 39 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> index 1d0c742..8fce309 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> @@ -1039,35 +1039,31 @@ static bool amdgpu_check_pot_argument(int arg) >>> return (arg & (arg - 1)) == 0; >>> } >>> -static void amdgpu_get_block_size(struct amdgpu_device *adev) >>> +static void amdgpu_check_block_size(struct amdgpu_device *adev) >>> { >>> /* defines number of bits in page table versus page directory, >>> * a page is 4KB so we have 12 bits offset, minimum 9 bits in the >>> * page table and the remaining bits are in the page directory */ >>> -if (amdgpu_vm_block_size == -1) { >>> - >>> -/* Total bits covered by PD + PTs */ >>> -unsigned bits = ilog2(amdgpu_vm_size) + 18; >>> - >>> -/* Make sure the PD is 4K in size up to 8GB address space. >>> - Above that split equal between PD and PTs */ >>> -if (amdgpu_vm_size <= 8) >>> -amdgpu_vm_block_size = bits - 9; >>> -else >>> -amdgpu_vm_block_size = (bits + 3) / 2; >>> +if (amdgpu_vm_block_size == -1) >>> +return; >>> -} else if (amdgpu_vm_block_size < 9) { >>> +if (amdgpu_vm_block_size < 9) { >>> dev_warn(adev->dev, "VM page table size (%d) too small\n", >>> amdgpu_vm_block_size); >>> -amdgpu_vm_block_size = 9; >>> +goto def_value; >>> } >>> if (amdgpu_vm_block_size > 24 || >>> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { >>> dev_warn(adev->dev, "VM page table size (%d) too large\n", >>> amdgpu_vm_block_size); >>> -amdgpu_vm_block_size = 9; >>> +goto def_value; >>> } >>> + >>> +return; >>> + >>> +def_value: >>> +amdgpu_vm_block_size = -1; >>> } >>> static void amdgpu_check_vm_size(struct amdgpu_device *adev) >>> @@ -1096,8 +1092,7 @@ static void amdgpu_check_vm_size(struct >>> amdgpu_device *adev) >>> return; >>> def_value: >>> -amdgpu_vm_size = 8; >>> -dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); >>> +amdgpu_vm_size = -1; >>> } >>> /** >>> @@ -1131,7 +1126,7 @@ static void amdgpu_check_arguments(struct >>> amdgpu_device *adev) >>> amdgpu_check_vm_size(adev); >>> -amdgpu_get_block_size(adev); >>> +amdgpu_check_block_size(adev); >>> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || >>> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> index bfd945b..6238e2e 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> @@ -86,7 +86,7 @@ >>> unsigned amdgpu_ip_block_mask = 0xffffffff; >>> int amdgpu_bapm = -1; >>> int amdgpu_deep_color = 0; >>> -int amdgpu_vm_size = 64; >>> +int amdgpu_vm_size = -1; >>> int amdgpu_vm_block_size = -1; >>> int amdgpu_vm_fault_stop = 0; >>> int amdgpu_vm_debug = 0; >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> index 8785420..bc2650ef 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> @@ -2064,6 +2064,44 @@ void amdgpu_vm_bo_invalidate(struct >>> amdgpu_device *adev, >>> } >>> } >>> +static uint32_t amdgpu_get_block_size(uint64_t vm_size) >> >> Please rename that to amdgpu_vm_get_block_size(). >> >>> +{ >>> +/* Total bits covered by PD + PTs */ >>> +unsigned bits = ilog2(vm_size) + 18; >>> + >>> +/* Make sure the PD is 4K in size up to 8GB address space. >>> + Above that split equal between PD and PTs */ >>> +if (vm_size <= 8) >>> +return (bits - 9); >>> +else >>> +return ((bits + 3) / 2); >>> +} >>> + >>> +/** >>> + * amdgpu_vm_adjust_size - adjust vm size and block size >>> + * >>> + * @adev: amdgpu_device pointer >>> + * @vm_size: the default vm size if it's set auto >>> + */ >>> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t >>> vm_size) >>> +{ >>> +/* adjust vm size firstly */ >>> +if (amdgpu_vm_size == -1) >>> +adev->vm_manager.vm_size = vm_size; >>> +else >>> +adev->vm_manager.vm_size = amdgpu_vm_size; >>> + >>> +/* block size depends on vm size */ >>> +if (amdgpu_vm_block_size == -1) >>> +adev->vm_manager.block_size = >>> +amdgpu_get_block_size(adev->vm_manager.vm_size); >>> +else >>> +adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + >>> +DRM_INFO("vm size is %llu GB, block size is %u-bit\n", >>> +adev->vm_manager.vm_size, adev->vm_manager.block_size); >>> +} >>> + >>> /** >>> * amdgpu_vm_init - initialize a vm instance >>> * >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> index 7d01372..6f158d6 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h >>> @@ -234,5 +234,6 @@ int amdgpu_vm_bo_clear_mappings(struct >>> amdgpu_device *adev, >>> uint64_t saddr, uint64_t size); >>> void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, >>> struct amdgpu_bo_va *bo_va); >>> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t >>> vm_size); >>> #endif >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> index 30d5c42..631aef3 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> @@ -849,13 +849,9 @@ static int gmc_v6_0_sw_init(void *handle) >>> if (r) >>> return r; >>> -adev->vm_manager.vm_size = amdgpu_vm_size; >>> -adev->vm_manager.block_size = amdgpu_vm_block_size; >>> +amdgpu_vm_adjust_size(adev, 64); >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> -DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> -adev->vm_manager.vm_size, adev->vm_manager.block_size); >>> - >>> adev->mc.mc_mask = 0xffffffffffULL; >>> adev->need_dma32 = false; >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> index 7113765..92abe12 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> @@ -1003,13 +1003,9 @@ static int gmc_v7_0_sw_init(void *handle) >>> * Currently set to 4GB ((1 << 20) 4k pages). >>> * Max GPUVM size for cayman and SI is 40 bits. >>> */ >>> -adev->vm_manager.vm_size = amdgpu_vm_size; >>> -adev->vm_manager.block_size = amdgpu_vm_block_size; >>> +amdgpu_vm_adjust_size(adev, 64); >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> -DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> -adev->vm_manager.vm_size, adev->vm_manager.block_size); >>> - >>> /* Set the internal MC address mask >>> * This is the max address of the GPU's >>> * internal address space. >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> index b3d1f1b..f2ccefc 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> @@ -1087,13 +1087,9 @@ static int gmc_v8_0_sw_init(void *handle) >>> * Currently set to 4GB ((1 << 20) 4k pages). >>> * Max GPUVM size for cayman and SI is 40 bits. >>> */ >>> -adev->vm_manager.vm_size = amdgpu_vm_size; >>> -adev->vm_manager.block_size = amdgpu_vm_block_size; >>> +amdgpu_vm_adjust_size(adev, 64); >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> -DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> -adev->vm_manager.vm_size, adev->vm_manager.block_size); >>> - >>> /* Set the internal MC address mask >>> * This is the max address of the GPU's >>> * internal address space. >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> index e1637d5..77e7784f 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> @@ -552,8 +552,7 @@ static int gmc_v9_0_sw_init(void *handle) >>> if (adev->flags & AMD_IS_APU) { >>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; >>> -adev->vm_manager.vm_size = amdgpu_vm_size; >>> -adev->vm_manager.block_size = amdgpu_vm_block_size; >>> +amdgpu_vm_adjust_size(adev, 64); >> >> Make sure we also use 1 level page tables in the APU case as well. > > I also flashed a idea about it. > Does APU still uses 1 level page now for gmc v9? No, it's same as Vega. David > > Jerry > >> >> With that done and the function renamed the patch is Reviewed-by: >> Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org >> <mailto:christian.koenig-5C7GfCeVMHo@public.gmane.org>>. >> >> Regards, >> Christian. >> >>> } else { >>> /* XXX Don't know how to get VRAM type yet. */ >>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; >>> @@ -564,11 +563,11 @@ static int gmc_v9_0_sw_init(void *handle) >>> */ >>> adev->vm_manager.vm_size = 1U << 18; >>> adev->vm_manager.block_size = 9; >>> +DRM_INFO("vm size is %llu GB, block size is %u-bit\n", >>> +adev->vm_manager.vm_size, >>> +adev->vm_manager.block_size); >>> } >>> -DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> -adev->vm_manager.vm_size, adev->vm_manager.block_size); >>> - >>> /* This interrupt is VMC page fault.*/ >>> r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, >>> &adev->mc.vm_fault); > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 45953 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-04-07 2:35 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-04-06 10:19 [PATCH v2] drm/amdgpu: set vm size and block size by individual gmc by default (v2) Junwei Zhang [not found] ` <1491473999-20529-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 2017-04-06 12:07 ` Christian König [not found] ` <04eb5d6d-8d29-82aa-e367-d918e71253d2-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2017-04-06 13:56 ` Zhang, Jerry [not found] ` <51C2AE07-B2D3-4A81-97FE-A79BDA5DBB8D-5C7GfCeVMHo@public.gmane.org> 2017-04-07 2:35 ` zhoucm1
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