[PATCH 0/5] Classify the engines in class + instance (v3)

[PATCH 0/5] Classify the engines in class + instance (v3)

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/intel_engine_cs.c       | 86 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.c             | 34 +++++++----
 drivers/gpu/drm/i915/intel_lrc.h             |  7 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 15 ++++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  2 +-
 6 files changed, 101 insertions(+), 57 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..49ca7d1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	enum intel_engine_class class;
+	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..4ab590b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,16 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	enum intel_engine_class {
+		RENDER_CLASS = 0,
+		VIDEO_DECODE_CLASS = 1,
+		VIDEO_ENHANCEMENT_CLASS = 2,
+		COPY_ENGINE_CLASS = 3,
+		OTHER_CLASS = 4
+	} class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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Re: [PATCH 1/5] drm/i915: Classify the engines in class + instance

[Michal Wajdeczko]

On Thu, Apr 06, 2017 at 08:00:12AM -0700, Oscar Mateo wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> In such a way that vcs and vcs2 are just two different instances (0 and 1)
> of the same engine class (VIDEO_DECODE_CLASS).
> 
> v2: Align the instance types (Tvrtko)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 854e8e0..49ca7d1 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -30,6 +30,8 @@
>  	const char *name;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> +	enum intel_engine_class class;
> +	u8 instance;
>  	u32 mmio_base;
>  	unsigned irq_shift;
>  	int (*init_legacy)(struct intel_engine_cs *engine);
> @@ -39,6 +41,8 @@
>  		.name = "rcs",
>  		.hw_id = RCS_HW,
>  		.exec_id = I915_EXEC_RENDER,
> +		.class = RENDER_CLASS,
> +		.instance = 0,
>  		.mmio_base = RENDER_RING_BASE,
>  		.irq_shift = GEN8_RCS_IRQ_SHIFT,
>  		.init_execlists = logical_render_ring_init,
> @@ -48,6 +52,8 @@
>  		.name = "bcs",
>  		.hw_id = BCS_HW,
>  		.exec_id = I915_EXEC_BLT,
> +		.class = COPY_ENGINE_CLASS,
> +		.instance = 0,
>  		.mmio_base = BLT_RING_BASE,
>  		.irq_shift = GEN8_BCS_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -57,6 +63,8 @@
>  		.name = "vcs",
>  		.hw_id = VCS_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.class = VIDEO_DECODE_CLASS,
> +		.instance = 0,
>  		.mmio_base = GEN6_BSD_RING_BASE,
>  		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -66,6 +74,8 @@
>  		.name = "vcs2",
>  		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.class = VIDEO_DECODE_CLASS,
> +		.instance = 1,
>  		.mmio_base = GEN8_BSD2_RING_BASE,
>  		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -75,6 +85,8 @@
>  		.name = "vecs",
>  		.hw_id = VECS_HW,
>  		.exec_id = I915_EXEC_VEBOX,
> +		.class = VIDEO_ENHANCEMENT_CLASS,
> +		.instance = 0,
>  		.mmio_base = VEBOX_RING_BASE,
>  		.irq_shift = GEN8_VECS_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -101,6 +113,8 @@
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
>  	engine->irq_shift = info->irq_shift;
> +	engine->class = info->class;
> +	engine->instance = info->instance;
>  
>  	/* Nothing to do here, execute in order of dependencies */
>  	engine->schedule = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index cbe61d3..4ab590b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -193,6 +193,16 @@ struct intel_engine_cs {
>  	enum intel_engine_id id;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> +
> +	enum intel_engine_class {
> +		RENDER_CLASS = 0,
> +		VIDEO_DECODE_CLASS = 1,
> +		VIDEO_ENHANCEMENT_CLASS = 2,
> +		COPY_ENGINE_CLASS = 3,
> +		OTHER_CLASS = 4
> +	} class;

Hmm, if this 'class' identifiers are related to the hw then maybe we should
move these definitions into i915_reg.h in similar way as it was done in

	237ae7c79e26 drm/i915: Don't use enums for hardware engine id

and here just keep class as "u8"

-Michal

> +	u8 instance;
> +
>  	unsigned int guc_id;
>  	u32		mmio_base;
>  	unsigned int irq_shift;
> -- 
> 1.9.1
> 
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Re: [PATCH 1/5] drm/i915: Classify the engines in class + instance

[Chris Wilson]

On Fri, Apr 07, 2017 at 11:45:32AM +0200, Michal Wajdeczko wrote:
> On Thu, Apr 06, 2017 at 08:00:12AM -0700, Oscar Mateo wrote:
> > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > 
> > In such a way that vcs and vcs2 are just two different instances (0 and 1)
> > of the same engine class (VIDEO_DECODE_CLASS).
> > 
> > v2: Align the instance types (Tvrtko)
> > 
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
> >  2 files changed, 24 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 854e8e0..49ca7d1 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -30,6 +30,8 @@
> >  	const char *name;
> >  	unsigned int exec_id;
> >  	unsigned int hw_id;
> > +	enum intel_engine_class class;
> > +	u8 instance;
> >  	u32 mmio_base;
> >  	unsigned irq_shift;
> >  	int (*init_legacy)(struct intel_engine_cs *engine);
> > @@ -39,6 +41,8 @@
> >  		.name = "rcs",
> >  		.hw_id = RCS_HW,
> >  		.exec_id = I915_EXEC_RENDER,
> > +		.class = RENDER_CLASS,
> > +		.instance = 0,
> >  		.mmio_base = RENDER_RING_BASE,
> >  		.irq_shift = GEN8_RCS_IRQ_SHIFT,
> >  		.init_execlists = logical_render_ring_init,
> > @@ -48,6 +52,8 @@
> >  		.name = "bcs",
> >  		.hw_id = BCS_HW,
> >  		.exec_id = I915_EXEC_BLT,
> > +		.class = COPY_ENGINE_CLASS,
> > +		.instance = 0,
> >  		.mmio_base = BLT_RING_BASE,
> >  		.irq_shift = GEN8_BCS_IRQ_SHIFT,
> >  		.init_execlists = logical_xcs_ring_init,
> > @@ -57,6 +63,8 @@
> >  		.name = "vcs",
> >  		.hw_id = VCS_HW,
> >  		.exec_id = I915_EXEC_BSD,
> > +		.class = VIDEO_DECODE_CLASS,
> > +		.instance = 0,
> >  		.mmio_base = GEN6_BSD_RING_BASE,
> >  		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
> >  		.init_execlists = logical_xcs_ring_init,
> > @@ -66,6 +74,8 @@
> >  		.name = "vcs2",
> >  		.hw_id = VCS2_HW,
> >  		.exec_id = I915_EXEC_BSD,
> > +		.class = VIDEO_DECODE_CLASS,
> > +		.instance = 1,
> >  		.mmio_base = GEN8_BSD2_RING_BASE,
> >  		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
> >  		.init_execlists = logical_xcs_ring_init,
> > @@ -75,6 +85,8 @@
> >  		.name = "vecs",
> >  		.hw_id = VECS_HW,
> >  		.exec_id = I915_EXEC_VEBOX,
> > +		.class = VIDEO_ENHANCEMENT_CLASS,
> > +		.instance = 0,
> >  		.mmio_base = VEBOX_RING_BASE,
> >  		.irq_shift = GEN8_VECS_IRQ_SHIFT,
> >  		.init_execlists = logical_xcs_ring_init,
> > @@ -101,6 +113,8 @@
> >  	engine->hw_id = engine->guc_id = info->hw_id;
> >  	engine->mmio_base = info->mmio_base;
> >  	engine->irq_shift = info->irq_shift;
> > +	engine->class = info->class;
> > +	engine->instance = info->instance;
> >  
> >  	/* Nothing to do here, execute in order of dependencies */
> >  	engine->schedule = NULL;
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index cbe61d3..4ab590b 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -193,6 +193,16 @@ struct intel_engine_cs {
> >  	enum intel_engine_id id;
> >  	unsigned int exec_id;
> >  	unsigned int hw_id;
> > +
> > +	enum intel_engine_class {
> > +		RENDER_CLASS = 0,
> > +		VIDEO_DECODE_CLASS = 1,
> > +		VIDEO_ENHANCEMENT_CLASS = 2,
> > +		COPY_ENGINE_CLASS = 3,
> > +		OTHER_CLASS = 4
> > +	} class;
> 
> Hmm, if this 'class' identifiers are related to the hw then maybe we should
> move these definitions into i915_reg.h in similar way as it was done in
> 
> 	237ae7c79e26 drm/i915: Don't use enums for hardware engine id
> 
> and here just keep class as "u8"

Yup, I presume they are hw/bsepc related due to the explicit use of
numbering. We might start being more honest with ourselves and calling
it intel_engine_bspec.h :)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

[Oscar Mateo]

If we needed to do something different for the init functions, we could
always look at the engine instance to make the distinction. But, in any
case, the two functions are virtually identical already (please notice
that BSD2_RING is only used from gen8 onwards).

With this, the init functions depends excusively on the engine class
(a fact that we will use soon).

v2: Commit message

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c | 14 --------------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 -
 3 files changed, 1 insertion(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 49ca7d1..bb10847 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -79,7 +79,7 @@
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd2_ring_buffer,
+		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VECS] = {
 		.name = "vecs",
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c98acc2..81eee42 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2175,20 +2175,6 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
 	return intel_init_ring_buffer(engine);
 }
 
-/**
- * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
- */
-int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
-{
-	struct drm_i915_private *dev_priv = engine->i915;
-
-	intel_ring_default_vfuncs(dev_priv, engine);
-
-	engine->emit_flush = gen6_bsd_ring_flush;
-
-	return intel_init_ring_buffer(engine);
-}
-
 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 4ab590b..5c1a27f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -561,7 +561,6 @@ int intel_ring_pin(struct intel_ring *ring,
 
 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
-int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
 
-- 
1.9.1

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[PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Oscar Mateo]

Not really needed, but makes the next change a little bit more compact.

v2:
  - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
  - Make sure the mock engine name is null-terminated (Tvrtko, Chris)

v3: Because I'm stupid (Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c       | 5 +++--
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
 drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index bb10847..c6a73d0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -71,7 +71,7 @@
 		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VCS2] = {
-		.name = "vcs2",
+		.name = "vcs",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
 		.class = VIDEO_DECODE_CLASS,
@@ -108,7 +108,8 @@
 
 	engine->id = id;
 	engine->i915 = dev_priv;
-	engine->name = info->name;
+	snprintf(engine->name, sizeof(engine->name), "%s%u",
+				info->name, info->instance);
 	engine->exec_id = info->exec_id;
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 5c1a27f..d617049 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -187,9 +187,11 @@ enum intel_engine_id {
 	VECS
 };
 
+#define INTEL_ENGINE_CS_MAX_NAME 8
+
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
-	const char	*name;
+	char name[INTEL_ENGINE_CS_MAX_NAME];
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
index b89050e..b8e53bd 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -140,7 +140,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
 
 	/* minimal engine setup for requests */
 	engine->base.i915 = i915;
-	engine->base.name = name;
+	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
 	engine->base.id = id++;
 	engine->base.status_page.page_addr = (void *)(engine + 1);
 
-- 
1.9.1

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Re: [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Tvrtko Ursulin]

On 06/04/2017 16:00, Oscar Mateo wrote:
> Not really needed, but makes the next change a little bit more compact.
>
> v2:
>   - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
>   - Make sure the mock engine name is null-terminated (Tvrtko, Chris)
>
> v3: Because I'm stupid (Chris)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c       | 5 +++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
>  drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
>  3 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bb10847..c6a73d0 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -71,7 +71,7 @@
>  		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VCS2] = {
> -		.name = "vcs2",
> +		.name = "vcs",
>  		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
>  		.class = VIDEO_DECODE_CLASS,
> @@ -108,7 +108,8 @@
>
>  	engine->id = id;
>  	engine->i915 = dev_priv;
> -	engine->name = info->name;
> +	snprintf(engine->name, sizeof(engine->name), "%s%u",
> +				info->name, info->instance);
>  	engine->exec_id = info->exec_id;
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 5c1a27f..d617049 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -187,9 +187,11 @@ enum intel_engine_id {
>  	VECS
>  };
>
> +#define INTEL_ENGINE_CS_MAX_NAME 8
> +
>  struct intel_engine_cs {
>  	struct drm_i915_private *i915;
> -	const char	*name;
> +	char name[INTEL_ENGINE_CS_MAX_NAME];
>  	enum intel_engine_id id;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
> index b89050e..b8e53bd 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_engine.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
> @@ -140,7 +140,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
>
>  	/* minimal engine setup for requests */
>  	engine->base.i915 = i915;
> -	engine->base.name = name;
> +	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
>  	engine->base.id = id++;
>  	engine->base.status_page.page_addr = (void *)(engine + 1);
>
>

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

[Michal Wajdeczko]

On Thu, Apr 06, 2017 at 08:00:14AM -0700, Oscar Mateo wrote:
> Not really needed, but makes the next change a little bit more compact.
> 
> v2:
>   - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris)
>   - Make sure the mock engine name is null-terminated (Tvrtko, Chris)
> 
> v3: Because I'm stupid (Chris)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c       | 5 +++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h      | 4 +++-
>  drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
>  3 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bb10847..c6a73d0 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -71,7 +71,7 @@
>  		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VCS2] = {
> -		.name = "vcs2",
> +		.name = "vcs",
>  		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
>  		.class = VIDEO_DECODE_CLASS,
> @@ -108,7 +108,8 @@
>  
>  	engine->id = id;
>  	engine->i915 = dev_priv;
> -	engine->name = info->name;
> +	snprintf(engine->name, sizeof(engine->name), "%s%u",
> +				info->name, info->instance);

Maybe we should verify that engine name was not truncated by the snprintf?

-Michal


>  	engine->exec_id = info->exec_id;
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 5c1a27f..d617049 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -187,9 +187,11 @@ enum intel_engine_id {
>  	VECS
>  };
>  
> +#define INTEL_ENGINE_CS_MAX_NAME 8
> +
>  struct intel_engine_cs {
>  	struct drm_i915_private *i915;
> -	const char	*name;
> +	char name[INTEL_ENGINE_CS_MAX_NAME];
>  	enum intel_engine_id id;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c
> index b89050e..b8e53bd 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_engine.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
> @@ -140,7 +140,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
>  
>  	/* minimal engine setup for requests */
>  	engine->base.i915 = i915;
> -	engine->base.name = name;
> +	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
>  	engine->base.id = id++;
>  	engine->base.status_page.page_addr = (void *)(engine + 1);
>  
> -- 
> 1.9.1
> 
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[PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Oscar Mateo]

There are some properties that logically belong to the engine class, and some
that belong to the engine instance. Make it explicit.

v2: Commit message (Tvrtko)

v3:
  - Rebased
  - Exec/uabi id should be per instance (Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 71 +++++++++++++++++++++-------------
 1 file changed, 44 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index c6a73d0..6eab22d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -26,71 +26,84 @@
 #include "intel_ringbuffer.h"
 #include "intel_lrc.h"
 
-static const struct engine_info {
+struct engine_class_info {
 	const char *name;
+	int (*init_legacy)(struct intel_engine_cs *engine);
+	int (*init_execlists)(struct intel_engine_cs *engine);
+};
+
+static const struct engine_class_info intel_engine_classes[] = {
+	[RENDER_CLASS] = {
+		.name = "rcs",
+		.init_execlists = logical_render_ring_init,
+		.init_legacy = intel_init_render_ring_buffer,
+	},
+	[COPY_ENGINE_CLASS] = {
+		.name = "bcs",
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_blt_ring_buffer,
+	},
+	[VIDEO_DECODE_CLASS] = {
+		.name = "vcs",
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_bsd_ring_buffer,
+	},
+	[VIDEO_ENHANCEMENT_CLASS] = {
+		.name = "vecs",
+		.init_execlists = logical_xcs_ring_init,
+		.init_legacy = intel_init_vebox_ring_buffer,
+	},
+};
+
+struct engine_info {
 	unsigned int exec_id;
 	unsigned int hw_id;
 	enum intel_engine_class class;
 	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
-	int (*init_legacy)(struct intel_engine_cs *engine);
-	int (*init_execlists)(struct intel_engine_cs *engine);
-} intel_engines[] = {
+};
+
+static const struct engine_info intel_engines[] = {
 	[RCS] = {
-		.name = "rcs",
-		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.hw_id = RCS_HW,
 		.class = RENDER_CLASS,
 		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
-		.init_execlists = logical_render_ring_init,
-		.init_legacy = intel_init_render_ring_buffer,
 	},
 	[BCS] = {
-		.name = "bcs",
-		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.hw_id = BCS_HW,
 		.class = COPY_ENGINE_CLASS,
 		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_blt_ring_buffer,
 	},
 	[VCS] = {
-		.name = "vcs",
-		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.hw_id = VCS_HW,
 		.class = VIDEO_DECODE_CLASS,
 		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VCS2] = {
-		.name = "vcs",
-		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.hw_id = VCS2_HW,
 		.class = VIDEO_DECODE_CLASS,
 		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_bsd_ring_buffer,
 	},
 	[VECS] = {
-		.name = "vecs",
-		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.hw_id = VECS_HW,
 		.class = VIDEO_ENHANCEMENT_CLASS,
 		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
-		.init_execlists = logical_xcs_ring_init,
-		.init_legacy = intel_init_vebox_ring_buffer,
 	},
 };
 
@@ -99,6 +112,8 @@
 		   enum intel_engine_id id)
 {
 	const struct engine_info *info = &intel_engines[id];
+	const struct engine_class_info *class_info =
+				&intel_engine_classes[info->class];
 	struct intel_engine_cs *engine;
 
 	GEM_BUG_ON(dev_priv->engine[id]);
@@ -109,7 +124,7 @@
 	engine->id = id;
 	engine->i915 = dev_priv;
 	snprintf(engine->name, sizeof(engine->name), "%s%u",
-				info->name, info->instance);
+				class_info->name, info->instance);
 	engine->exec_id = info->exec_id;
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
@@ -190,12 +205,14 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
 	int err = 0;
 
 	for_each_engine(engine, dev_priv, id) {
+		const struct engine_class_info *class_info =
+					&intel_engine_classes[engine->class];
 		int (*init)(struct intel_engine_cs *engine);
 
 		if (i915.enable_execlists)
-			init = intel_engines[id].init_execlists;
+			init = class_info->init_execlists;
 		else
-			init = intel_engines[id].init_legacy;
+			init = class_info->init_legacy;
 		if (!init) {
 			kfree(engine);
 			dev_priv->engine[id] = NULL;
-- 
1.9.1

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Re: [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Tvrtko Ursulin]

On 06/04/2017 16:00, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
>
> v2: Commit message (Tvrtko)
>
> v3:
>   - Rebased
>   - Exec/uabi id should be per instance (Chris)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 71 +++++++++++++++++++++-------------
>  1 file changed, 44 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c6a73d0..6eab22d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,71 +26,84 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>
> -static const struct engine_info {
> +struct engine_class_info {
>  	const char *name;
> +	int (*init_legacy)(struct intel_engine_cs *engine);
> +	int (*init_execlists)(struct intel_engine_cs *engine);
> +};
> +
> +static const struct engine_class_info intel_engine_classes[] = {
> +	[RENDER_CLASS] = {
> +		.name = "rcs",
> +		.init_execlists = logical_render_ring_init,
> +		.init_legacy = intel_init_render_ring_buffer,
> +	},
> +	[COPY_ENGINE_CLASS] = {
> +		.name = "bcs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_blt_ring_buffer,
> +	},
> +	[VIDEO_DECODE_CLASS] = {
> +		.name = "vcs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_bsd_ring_buffer,
> +	},
> +	[VIDEO_ENHANCEMENT_CLASS] = {
> +		.name = "vecs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_vebox_ring_buffer,
> +	},
> +};
> +
> +struct engine_info {
>  	unsigned int exec_id;
>  	unsigned int hw_id;
>  	enum intel_engine_class class;
>  	u8 instance;
>  	u32 mmio_base;
>  	unsigned irq_shift;
> -	int (*init_legacy)(struct intel_engine_cs *engine);
> -	int (*init_execlists)(struct intel_engine_cs *engine);
> -} intel_engines[] = {
> +};
> +
> +static const struct engine_info intel_engines[] = {
>  	[RCS] = {
> -		.name = "rcs",
> -		.hw_id = RCS_HW,
>  		.exec_id = I915_EXEC_RENDER,
> +		.hw_id = RCS_HW,

One more bit of polish - avoid re-ordering the two fields here and below 
for a smaller diff. Or it is a deliberate choice to re-order?

Regards,

Tvrtko

>  		.class = RENDER_CLASS,
>  		.instance = 0,
>  		.mmio_base = RENDER_RING_BASE,
>  		.irq_shift = GEN8_RCS_IRQ_SHIFT,
> -		.init_execlists = logical_render_ring_init,
> -		.init_legacy = intel_init_render_ring_buffer,
>  	},
>  	[BCS] = {
> -		.name = "bcs",
> -		.hw_id = BCS_HW,
>  		.exec_id = I915_EXEC_BLT,
> +		.hw_id = BCS_HW,
>  		.class = COPY_ENGINE_CLASS,
>  		.instance = 0,
>  		.mmio_base = BLT_RING_BASE,
>  		.irq_shift = GEN8_BCS_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_blt_ring_buffer,
>  	},
>  	[VCS] = {
> -		.name = "vcs",
> -		.hw_id = VCS_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.hw_id = VCS_HW,
>  		.class = VIDEO_DECODE_CLASS,
>  		.instance = 0,
>  		.mmio_base = GEN6_BSD_RING_BASE,
>  		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VCS2] = {
> -		.name = "vcs",
> -		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.hw_id = VCS2_HW,
>  		.class = VIDEO_DECODE_CLASS,
>  		.instance = 1,
>  		.mmio_base = GEN8_BSD2_RING_BASE,
>  		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VECS] = {
> -		.name = "vecs",
> -		.hw_id = VECS_HW,
>  		.exec_id = I915_EXEC_VEBOX,
> +		.hw_id = VECS_HW,
>  		.class = VIDEO_ENHANCEMENT_CLASS,
>  		.instance = 0,
>  		.mmio_base = VEBOX_RING_BASE,
>  		.irq_shift = GEN8_VECS_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_vebox_ring_buffer,
>  	},
>  };
>
> @@ -99,6 +112,8 @@
>  		   enum intel_engine_id id)
>  {
>  	const struct engine_info *info = &intel_engines[id];
> +	const struct engine_class_info *class_info =
> +				&intel_engine_classes[info->class];
>  	struct intel_engine_cs *engine;
>
>  	GEM_BUG_ON(dev_priv->engine[id]);
> @@ -109,7 +124,7 @@
>  	engine->id = id;
>  	engine->i915 = dev_priv;
>  	snprintf(engine->name, sizeof(engine->name), "%s%u",
> -				info->name, info->instance);
> +				class_info->name, info->instance);
>  	engine->exec_id = info->exec_id;
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
> @@ -190,12 +205,14 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
>  	int err = 0;
>
>  	for_each_engine(engine, dev_priv, id) {
> +		const struct engine_class_info *class_info =
> +					&intel_engine_classes[engine->class];
>  		int (*init)(struct intel_engine_cs *engine);
>
>  		if (i915.enable_execlists)
> -			init = intel_engines[id].init_execlists;
> +			init = class_info->init_execlists;
>  		else
> -			init = intel_engines[id].init_legacy;
> +			init = class_info->init_legacy;
>  		if (!init) {
>  			kfree(engine);
>  			dev_priv->engine[id] = NULL;
>
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Re: [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

[Michal Wajdeczko]

On Thu, Apr 06, 2017 at 08:00:15AM -0700, Oscar Mateo wrote:
> There are some properties that logically belong to the engine class, and some
> that belong to the engine instance. Make it explicit.
> 
> v2: Commit message (Tvrtko)
> 
> v3:
>   - Rebased
>   - Exec/uabi id should be per instance (Chris)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 71 +++++++++++++++++++++-------------
>  1 file changed, 44 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c6a73d0..6eab22d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,71 +26,84 @@
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> -static const struct engine_info {
> +struct engine_class_info {
>  	const char *name;
> +	int (*init_legacy)(struct intel_engine_cs *engine);
> +	int (*init_execlists)(struct intel_engine_cs *engine);
> +};
> +
> +static const struct engine_class_info intel_engine_classes[] = {
> +	[RENDER_CLASS] = {
> +		.name = "rcs",
> +		.init_execlists = logical_render_ring_init,
> +		.init_legacy = intel_init_render_ring_buffer,
> +	},
> +	[COPY_ENGINE_CLASS] = {
> +		.name = "bcs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_blt_ring_buffer,
> +	},
> +	[VIDEO_DECODE_CLASS] = {
> +		.name = "vcs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_bsd_ring_buffer,
> +	},
> +	[VIDEO_ENHANCEMENT_CLASS] = {
> +		.name = "vecs",
> +		.init_execlists = logical_xcs_ring_init,
> +		.init_legacy = intel_init_vebox_ring_buffer,
> +	},
> +};
> +
> +struct engine_info {
>  	unsigned int exec_id;
>  	unsigned int hw_id;
>  	enum intel_engine_class class;
>  	u8 instance;
>  	u32 mmio_base;
>  	unsigned irq_shift;
> -	int (*init_legacy)(struct intel_engine_cs *engine);
> -	int (*init_execlists)(struct intel_engine_cs *engine);
> -} intel_engines[] = {
> +};
> +
> +static const struct engine_info intel_engines[] = {
>  	[RCS] = {
> -		.name = "rcs",
> -		.hw_id = RCS_HW,
>  		.exec_id = I915_EXEC_RENDER,
> +		.hw_id = RCS_HW,
>  		.class = RENDER_CLASS,
>  		.instance = 0,
>  		.mmio_base = RENDER_RING_BASE,
>  		.irq_shift = GEN8_RCS_IRQ_SHIFT,
> -		.init_execlists = logical_render_ring_init,
> -		.init_legacy = intel_init_render_ring_buffer,
>  	},
>  	[BCS] = {
> -		.name = "bcs",
> -		.hw_id = BCS_HW,
>  		.exec_id = I915_EXEC_BLT,
> +		.hw_id = BCS_HW,
>  		.class = COPY_ENGINE_CLASS,
>  		.instance = 0,
>  		.mmio_base = BLT_RING_BASE,
>  		.irq_shift = GEN8_BCS_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_blt_ring_buffer,
>  	},
>  	[VCS] = {
> -		.name = "vcs",
> -		.hw_id = VCS_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.hw_id = VCS_HW,
>  		.class = VIDEO_DECODE_CLASS,
>  		.instance = 0,
>  		.mmio_base = GEN6_BSD_RING_BASE,
>  		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VCS2] = {
> -		.name = "vcs",
> -		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.hw_id = VCS2_HW,
>  		.class = VIDEO_DECODE_CLASS,
>  		.instance = 1,
>  		.mmio_base = GEN8_BSD2_RING_BASE,
>  		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_bsd_ring_buffer,
>  	},
>  	[VECS] = {
> -		.name = "vecs",
> -		.hw_id = VECS_HW,
>  		.exec_id = I915_EXEC_VEBOX,
> +		.hw_id = VECS_HW,
>  		.class = VIDEO_ENHANCEMENT_CLASS,
>  		.instance = 0,
>  		.mmio_base = VEBOX_RING_BASE,
>  		.irq_shift = GEN8_VECS_IRQ_SHIFT,
> -		.init_execlists = logical_xcs_ring_init,
> -		.init_legacy = intel_init_vebox_ring_buffer,
>  	},
>  };
>  
> @@ -99,6 +112,8 @@
>  		   enum intel_engine_id id)
>  {
>  	const struct engine_info *info = &intel_engines[id];
> +	const struct engine_class_info *class_info =
> +				&intel_engine_classes[info->class];

Hmm, maybe we should add some protection against out-of-bound access
to the class info array ? We can start with:

	GEM_BUG_ON(info->class > ARRAY_SIZE(intel_engine_classes));

-Michal

>  	struct intel_engine_cs *engine;
>  
>  	GEM_BUG_ON(dev_priv->engine[id]);
> @@ -109,7 +124,7 @@
>  	engine->id = id;
>  	engine->i915 = dev_priv;
>  	snprintf(engine->name, sizeof(engine->name), "%s%u",
> -				info->name, info->instance);
> +				class_info->name, info->instance);
>  	engine->exec_id = info->exec_id;
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
> @@ -190,12 +205,14 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
>  	int err = 0;
>  
>  	for_each_engine(engine, dev_priv, id) {
> +		const struct engine_class_info *class_info =
> +					&intel_engine_classes[engine->class];
>  		int (*init)(struct intel_engine_cs *engine);
>  
>  		if (i915.enable_execlists)
> -			init = intel_engines[id].init_execlists;
> +			init = class_info->init_execlists;
>  		else
> -			init = intel_engines[id].init_legacy;
> +			init = class_info->init_legacy;
>  		if (!init) {
>  			kfree(engine);
>  			dev_priv->engine[id] = NULL;
> -- 
> 1.9.1
> 
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[PATCH 5/5] drm/i915: Use the engine class to get the context size

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Technically speaking, the context size is per engine class, not per
instance.

v2: Add MISSING_CASE (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 34 ++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_lrc.h |  7 ++++++-
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0dc1cc4..c8abf89 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1908,8 +1908,10 @@ static void execlists_init_reg_state(u32 *regs,
 }
 
 /**
- * intel_lr_context_size() - return the size of the context for an engine
- * @engine: which engine to find the context size for
+ * intel_lr_class_context_size() - return the size of the context for a given
+ * engine class
+ * @dev_priv: i915 device private
+ * @class: which engine class to find the context size for
  *
  * Each engine may require a different amount of space for a context image,
  * so when allocating (or copying) an image, this function can be used to
@@ -1921,25 +1923,33 @@ static void execlists_init_reg_state(u32 *regs,
  * in LRC mode, but does not include the "shared data page" used with
  * GuC submission. The caller should account for this if using the GuC.
  */
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class)
 {
 	int ret = 0;
 
-	WARN_ON(INTEL_GEN(engine->i915) < 8);
+	WARN_ON(INTEL_GEN(dev_priv) < 8);
 
-	switch (engine->id) {
-	case RCS:
-		if (INTEL_GEN(engine->i915) >= 9)
+	switch (class) {
+	case RENDER_CLASS:
+		switch (INTEL_GEN(dev_priv)) {
+		default:
+			MISSING_CASE(INTEL_GEN(dev_priv));
+		case 9:
 			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
-		else
+			break;
+		case 8:
 			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
+			break;
+		}
 		break;
-	case VCS:
-	case BCS:
-	case VECS:
-	case VCS2:
+	case VIDEO_DECODE_CLASS:
+	case VIDEO_ENHANCEMENT_CLASS:
+	case COPY_ENGINE_CLASS:
 		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
 		break;
+	default:
+		MISSING_CASE(class);
 	}
 
 	return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index e8015e7..b3a4331 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -78,7 +78,12 @@ enum {
 struct drm_i915_private;
 struct i915_gem_context;
 
-uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
+uint32_t intel_lr_class_context_size(struct drm_i915_private *dev_priv,
+				     enum intel_engine_class class);
+static inline uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
+{
+	return intel_lr_class_context_size(engine->i915, engine->class);
+}
 
 void intel_lr_context_resume(struct drm_i915_private *dev_priv);
 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
-- 
1.9.1

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✓ Fi.CI.BAT: success for Classify the engines in class + instance (rev4)

[Patchwork]

== Series Details ==

Series: Classify the engines in class + instance (rev4)
URL   : https://patchwork.freedesktop.org/series/22535/
State : success

== Summary ==

Series 22535v4 Classify the engines in class + instance
https://patchwork.freedesktop.org/api/1.0/series/22535/revisions/4/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                pass       -> DMESG-WARN (fi-kbl-7560u) fdo#100125

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time: 433s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time: 428s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time: 581s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time: 506s
fi-bxt-t5700     total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  time: 552s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time: 480s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 478s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 410s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time: 401s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time: 420s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 482s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 466s
fi-kbl-7500u     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time: 457s
fi-kbl-7560u     total:278  pass:267  dwarn:1   dfail:0   fail:0   skip:10  time: 570s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 451s
fi-skl-6700hq    total:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  time: 574s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time: 459s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time: 489s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time: 431s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time: 530s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time: 400s

7aafd5c8395fea9a79fbee82de4ffc63c04790d6 drm-tip: 2017y-04m-06d-21h-02m-00s UTC integration manifest
27be514 drm/i915: Use the engine class to get the context size
cd1d0b5 drm/i915: Split the engine info table in two levels, using class + instance
235d2d6 drm/i915: Generate the engine name based on the instance number
3106538 drm/i915: Use the same vfunc for BSD2 ring init
d79773a drm/i915: Classify the engines in class + instance

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4432/
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[PATCH 0/5] Classify the engines in class + instance (v5)

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/i915_reg.h              |  8 +++
 drivers/gpu/drm/i915/intel_engine_cs.c       | 80 ++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_lrc.c             | 33 +++++++-----
 drivers/gpu/drm/i915/intel_lrc.h             |  6 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      |  9 +++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  2 +-
 7 files changed, 99 insertions(+), 53 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

v3: Don't use enums for bspec-defined stuff (Michal)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  8 ++++++++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4..4c72ada 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -85,6 +85,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VECS_HW		3
 #define VCS2_HW		4
 
+/* Engine class */
+
+#define RENDER_CLASS		0
+#define VIDEO_DECODE_CLASS	1
+#define VIDEO_ENHANCEMENT_CLASS	2
+#define COPY_ENGINE_CLASS	3
+#define OTHER_CLASS		4
+
 /* PCI config space */
 
 #define MCHBAR_I915 0x44
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 92f871c..bb22927 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	u8 class;
+	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..f54fe7d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,10 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	u8 class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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[PATCH 0/5] Classify the engines in class + instance (v4)

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/i915_reg.h              |  8 +++
 drivers/gpu/drm/i915/intel_engine_cs.c       | 80 ++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_lrc.c             | 33 +++++++-----
 drivers/gpu/drm/i915/intel_lrc.h             |  6 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      |  9 +++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  3 +-
 7 files changed, 100 insertions(+), 53 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

v3: Don't use enums for bspec-defined stuff (Michal)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  8 ++++++++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++++
 3 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 11b12f4..4c72ada 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -85,6 +85,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define VECS_HW		3
 #define VCS2_HW		4
 
+/* Engine class */
+
+#define RENDER_CLASS		0
+#define VIDEO_DECODE_CLASS	1
+#define VIDEO_ENHANCEMENT_CLASS	2
+#define COPY_ENGINE_CLASS	3
+#define OTHER_CLASS		4
+
 /* PCI config space */
 
 #define MCHBAR_I915 0x44
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..2d3456d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	u8 class;
+	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..f54fe7d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,10 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	u8 class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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Re: [PATCH 1/5] drm/i915: Classify the engines in class + instance

[Michal Wajdeczko]

On Fri, Apr 07, 2017 at 02:15:45AM -0700, Oscar Mateo wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> In such a way that vcs and vcs2 are just two different instances (0 and 1)
> of the same engine class (VIDEO_DECODE_CLASS).
> 
> v2: Align the instance types (Tvrtko)
> 
> v3: Don't use enums for bspec-defined stuff (Michal)
> 
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

-Michal
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[PATCH 0/5] Classify the engines in class + instance (v2)

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/intel_engine_cs.c       | 88 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.c             | 34 +++++++----
 drivers/gpu/drm/i915/intel_lrc.h             |  7 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 15 ++++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  2 +-
 6 files changed, 102 insertions(+), 58 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

v2: Align the instance types (Tvrtko)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..49ca7d1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	enum intel_engine_class class;
+	u8 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..4ab590b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,16 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	enum intel_engine_class {
+		RENDER_CLASS = 0,
+		VIDEO_DECODE_CLASS = 1,
+		VIDEO_ENHANCEMENT_CLASS = 2,
+		COPY_ENGINE_CLASS = 3,
+		OTHER_CLASS = 4
+	} class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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[PATCH 0/5] Classify the engines in class + instance

[Oscar Mateo]

This refactoring helps simplify a few things here and there.

Daniele Ceraolo Spurio (2):
  drm/i915: Classify the engines in class + instance
  drm/i915: Use the engine class to get the context size

Oscar Mateo (3):
  drm/i915: Use the same vfunc for BSD2 ring init
  drm/i915: Generate the engine name based on the instance number
  drm/i915: Split the engine info table in two levels, using class +
    instance

 drivers/gpu/drm/i915/intel_engine_cs.c       | 90 +++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_lrc.c             | 34 +++++++----
 drivers/gpu/drm/i915/intel_lrc.h             |  7 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.c      | 14 -----
 drivers/gpu/drm/i915/intel_ringbuffer.h      | 15 ++++-
 drivers/gpu/drm/i915/selftests/mock_engine.c |  2 +-
 6 files changed, 104 insertions(+), 58 deletions(-)

-- 
1.9.1

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[PATCH 1/5] drm/i915: Classify the engines in class + instance

[Oscar Mateo]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

In such a way that vcs and vcs2 are just two different instances (0 and 1)
of the same engine class (VIDEO_DECODE_CLASS).

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 854e8e0..b3d575a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -30,6 +30,8 @@
 	const char *name;
 	unsigned int exec_id;
 	unsigned int hw_id;
+	enum intel_engine_class class;
+	u32 instance;
 	u32 mmio_base;
 	unsigned irq_shift;
 	int (*init_legacy)(struct intel_engine_cs *engine);
@@ -39,6 +41,8 @@
 		.name = "rcs",
 		.hw_id = RCS_HW,
 		.exec_id = I915_EXEC_RENDER,
+		.class = RENDER_CLASS,
+		.instance = 0,
 		.mmio_base = RENDER_RING_BASE,
 		.irq_shift = GEN8_RCS_IRQ_SHIFT,
 		.init_execlists = logical_render_ring_init,
@@ -48,6 +52,8 @@
 		.name = "bcs",
 		.hw_id = BCS_HW,
 		.exec_id = I915_EXEC_BLT,
+		.class = COPY_ENGINE_CLASS,
+		.instance = 0,
 		.mmio_base = BLT_RING_BASE,
 		.irq_shift = GEN8_BCS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -57,6 +63,8 @@
 		.name = "vcs",
 		.hw_id = VCS_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 0,
 		.mmio_base = GEN6_BSD_RING_BASE,
 		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -66,6 +74,8 @@
 		.name = "vcs2",
 		.hw_id = VCS2_HW,
 		.exec_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 1,
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -75,6 +85,8 @@
 		.name = "vecs",
 		.hw_id = VECS_HW,
 		.exec_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 0,
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 		.init_execlists = logical_xcs_ring_init,
@@ -101,6 +113,8 @@
 	engine->hw_id = engine->guc_id = info->hw_id;
 	engine->mmio_base = info->mmio_base;
 	engine->irq_shift = info->irq_shift;
+	engine->class = info->class;
+	engine->instance = info->instance;
 
 	/* Nothing to do here, execute in order of dependencies */
 	engine->schedule = NULL;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cbe61d3..4ab590b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -193,6 +193,16 @@ struct intel_engine_cs {
 	enum intel_engine_id id;
 	unsigned int exec_id;
 	unsigned int hw_id;
+
+	enum intel_engine_class {
+		RENDER_CLASS = 0,
+		VIDEO_DECODE_CLASS = 1,
+		VIDEO_ENHANCEMENT_CLASS = 2,
+		COPY_ENGINE_CLASS = 3,
+		OTHER_CLASS = 4
+	} class;
+	u8 instance;
+
 	unsigned int guc_id;
 	u32		mmio_base;
 	unsigned int irq_shift;
-- 
1.9.1

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Re: [PATCH 1/5] drm/i915: Classify the engines in class + instance

[Tvrtko Ursulin]

On 05/04/2017 10:30, Oscar Mateo wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> In such a way that vcs and vcs2 are just two different instances (0 and 1)
> of the same engine class (VIDEO_DECODE_CLASS).
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c  | 14 ++++++++++++++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 10 ++++++++++
>  2 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 854e8e0..b3d575a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -30,6 +30,8 @@
>  	const char *name;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> +	enum intel_engine_class class;
> +	u32 instance;

Normal type I think, it's not anything hardware related to need explicit 
width. Or maybe make it u8 if it saves any space?

>  	u32 mmio_base;
>  	unsigned irq_shift;
>  	int (*init_legacy)(struct intel_engine_cs *engine);
> @@ -39,6 +41,8 @@
>  		.name = "rcs",
>  		.hw_id = RCS_HW,
>  		.exec_id = I915_EXEC_RENDER,
> +		.class = RENDER_CLASS,
> +		.instance = 0,
>  		.mmio_base = RENDER_RING_BASE,
>  		.irq_shift = GEN8_RCS_IRQ_SHIFT,
>  		.init_execlists = logical_render_ring_init,
> @@ -48,6 +52,8 @@
>  		.name = "bcs",
>  		.hw_id = BCS_HW,
>  		.exec_id = I915_EXEC_BLT,
> +		.class = COPY_ENGINE_CLASS,
> +		.instance = 0,
>  		.mmio_base = BLT_RING_BASE,
>  		.irq_shift = GEN8_BCS_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -57,6 +63,8 @@
>  		.name = "vcs",
>  		.hw_id = VCS_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.class = VIDEO_DECODE_CLASS,
> +		.instance = 0,
>  		.mmio_base = GEN6_BSD_RING_BASE,
>  		.irq_shift = GEN8_VCS1_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -66,6 +74,8 @@
>  		.name = "vcs2",
>  		.hw_id = VCS2_HW,
>  		.exec_id = I915_EXEC_BSD,
> +		.class = VIDEO_DECODE_CLASS,
> +		.instance = 1,
>  		.mmio_base = GEN8_BSD2_RING_BASE,
>  		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -75,6 +85,8 @@
>  		.name = "vecs",
>  		.hw_id = VECS_HW,
>  		.exec_id = I915_EXEC_VEBOX,
> +		.class = VIDEO_ENHANCEMENT_CLASS,
> +		.instance = 0,
>  		.mmio_base = VEBOX_RING_BASE,
>  		.irq_shift = GEN8_VECS_IRQ_SHIFT,
>  		.init_execlists = logical_xcs_ring_init,
> @@ -101,6 +113,8 @@
>  	engine->hw_id = engine->guc_id = info->hw_id;
>  	engine->mmio_base = info->mmio_base;
>  	engine->irq_shift = info->irq_shift;
> +	engine->class = info->class;
> +	engine->instance = info->instance;
>
>  	/* Nothing to do here, execute in order of dependencies */
>  	engine->schedule = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index cbe61d3..4ab590b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -193,6 +193,16 @@ struct intel_engine_cs {
>  	enum intel_engine_id id;
>  	unsigned int exec_id;
>  	unsigned int hw_id;
> +
> +	enum intel_engine_class {
> +		RENDER_CLASS = 0,
> +		VIDEO_DECODE_CLASS = 1,
> +		VIDEO_ENHANCEMENT_CLASS = 2,
> +		COPY_ENGINE_CLASS = 3,
> +		OTHER_CLASS = 4
> +	} class;
> +	u8 instance;

Oh it is already u8 here! :)

> +
>  	unsigned int guc_id;
>  	u32		mmio_base;
>  	unsigned int irq_shift;
>

Looks OK to me. With the types aligned:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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