[PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[Christian König]

From: Christian König <christian.koenig@amd.com>

Add the info which ring belonging to which VMHUB.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 2 ++
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    | 1 +
 5 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7479e47..45bb87b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
 	uint32_t		align_mask;
 	u32			nop;
 	bool			support_64bit_ptrs;
+	unsigned		vmhub;
 
 	/* ring read/write ptr handling */
 	u64 (*get_rptr)(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index cb6c7eb8..71b092b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3456,6 +3456,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.align_mask = 0xff,
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
+	.vmhub = AMDGPU_GFXHUB,
 	.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
 	.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
 	.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
@@ -3500,6 +3501,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.align_mask = 0xff,
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
+	.vmhub = AMDGPU_GFXHUB,
 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
@@ -3529,6 +3531,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 	.align_mask = 0xff,
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
+	.vmhub = AMDGPU_GFXHUB,
 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index d40eb31..8cbb49d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 	.align_mask = 0xf,
 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
 	.support_64bit_ptrs = true,
+	.vmhub = AMDGPU_MMHUB,
 	.get_rptr = sdma_v4_0_ring_get_rptr,
 	.get_wptr = sdma_v4_0_ring_get_wptr,
 	.set_wptr = sdma_v4_0_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 819148a..fa80465 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
 	.align_mask = 0xf,
 	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
 	.support_64bit_ptrs = false,
+	.vmhub = AMDGPU_MMHUB,
 	.get_rptr = uvd_v7_0_ring_get_rptr,
 	.get_wptr = uvd_v7_0_ring_get_wptr,
 	.set_wptr = uvd_v7_0_ring_set_wptr,
@@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.align_mask = 0x3f,
 	.nop = HEVC_ENC_CMD_NO_OP,
 	.support_64bit_ptrs = false,
+	.vmhub = AMDGPU_MMHUB,
 	.get_rptr = uvd_v7_0_enc_ring_get_rptr,
 	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
 	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 8dde83f..6374133 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
 	.align_mask = 0x3f,
 	.nop = VCE_CMD_NO_OP,
 	.support_64bit_ptrs = false,
+	.vmhub = AMDGPU_MMHUB,
 	.get_rptr = vce_v4_0_ring_get_rptr,
 	.get_wptr = vce_v4_0_ring_get_wptr,
 	.set_wptr = vce_v4_0_ring_set_wptr,
-- 
2.5.0

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[PATCH 2/8] drm/amdgpu: drop VMID per ring tracking

[Christian König]

From: Christian König <christian.koenig@amd.com>

David suggested this a long time ago, instead of checking
each ring just walk over all the VMIDs in reverse LRU order.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++--------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  3 ---
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 157ae50..de6558b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -463,17 +463,10 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 
 	job->vm_needs_flush = true;
 	/* Check if we can use a VMID already assigned to this VM */
-	i = ring->idx;
-	do {
+	list_for_each_entry_reverse(id, &adev->vm_manager.ids_lru, list) {
 		struct fence *flushed;
 
-		id = vm->ids[i++];
-		if (i == AMDGPU_MAX_RINGS)
-			i = 0;
-
 		/* Check all the prerequisites to using this VMID */
-		if (!id)
-			continue;
 		if (amdgpu_vm_had_gpu_reset(adev, id))
 			continue;
 
@@ -503,7 +496,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 			goto error;
 
 		list_move_tail(&id->list, &adev->vm_manager.ids_lru);
-		vm->ids[ring->idx] = id;
 
 		job->vm_id = id - adev->vm_manager.ids;
 		job->vm_needs_flush = false;
@@ -512,7 +504,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		mutex_unlock(&adev->vm_manager.lock);
 		return 0;
 
-	} while (i != ring->idx);
+	};
 
 	/* Still no ID to use? Then use the idle one found earlier */
 	id = idle;
@@ -532,7 +524,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
 	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
 	atomic64_set(&id->owner, vm->client_id);
-	vm->ids[ring->idx] = id;
 
 	job->vm_id = id - adev->vm_manager.ids;
 	trace_amdgpu_vm_grab_id(vm, ring->idx, job);
@@ -2117,10 +2108,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 	unsigned ring_instance;
 	struct amdgpu_ring *ring;
 	struct amd_sched_rq *rq;
-	int i, r;
+	int r;
 
-	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-		vm->ids[i] = NULL;
 	vm->va = RB_ROOT;
 	vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
 	spin_lock_init(&vm->status_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 6f158d6..46987b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -114,9 +114,6 @@ struct amdgpu_vm {
 	struct fence		*last_dir_update;
 	uint64_t		last_eviction_counter;
 
-	/* for id and flush management per ring */
-	struct amdgpu_vm_id	*ids[AMDGPU_MAX_RINGS];
-
 	/* protecting freed */
 	spinlock_t		freed_lock;
 
-- 
2.5.0

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[PATCH 3/8] drm/amdgpu: split VMID management by VMHUB

[Christian König]

From: Christian König <christian.koenig@amd.com>

This way GFX and MM won't fight for VMIDs any more.

Initially disabled since we need to stop flushing all HUBS
at the same time as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 82 ++++++++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     | 15 ++++--
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  3 +-
 10 files changed, 69 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8fce309..53996e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1886,7 +1886,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
 	/* mutex initialization are all done here so we
 	 * can recall function without having locking issues */
-	mutex_init(&adev->vm_manager.lock);
 	atomic_set(&adev->irq.ih.lock, 0);
 	mutex_init(&adev->firmware.mutex);
 	mutex_init(&adev->pm.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e382eb8..4480e01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -217,7 +217,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (r) {
 		dev_err(adev->dev, "failed to emit fence (%d)\n", r);
 		if (job && job->vm_id)
-			amdgpu_vm_reset_id(adev, job->vm_id);
+			amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
+					   job->vm_id);
 		amdgpu_ring_undo(ring);
 		return r;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index de6558b..db47c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -406,6 +406,9 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		      struct amdgpu_job *job)
 {
 	struct amdgpu_device *adev = ring->adev;
+	/* Temporary use only the first VM manager */
+	unsigned vmhub = 0; /*ring->funcs->vmhub;*/
+	struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	uint64_t fence_context = adev->fence_context + ring->idx;
 	struct fence *updates = sync->last_vm_update;
 	struct amdgpu_vm_id *id, *idle;
@@ -413,16 +416,15 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	unsigned i;
 	int r = 0;
 
-	fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
-			       GFP_KERNEL);
+	fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
 	if (!fences)
 		return -ENOMEM;
 
-	mutex_lock(&adev->vm_manager.lock);
+	mutex_lock(&id_mgr->lock);
 
 	/* Check if we have an idle VMID */
 	i = 0;
-	list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
+	list_for_each_entry(idle, &id_mgr->ids_lru, list) {
 		fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
 		if (!fences[i])
 			break;
@@ -430,7 +432,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	}
 
 	/* If we can't find a idle VMID to use, wait till one becomes available */
-	if (&idle->list == &adev->vm_manager.ids_lru) {
+	if (&idle->list == &id_mgr->ids_lru) {
 		u64 fence_context = adev->vm_manager.fence_context + ring->idx;
 		unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
 		struct fence_array *array;
@@ -455,7 +457,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		if (r)
 			goto error;
 
-		mutex_unlock(&adev->vm_manager.lock);
+		mutex_unlock(&id_mgr->lock);
 		return 0;
 
 	}
@@ -463,7 +465,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 
 	job->vm_needs_flush = true;
 	/* Check if we can use a VMID already assigned to this VM */
-	list_for_each_entry_reverse(id, &adev->vm_manager.ids_lru, list) {
+	list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
 		struct fence *flushed;
 
 		/* Check all the prerequisites to using this VMID */
@@ -495,13 +497,13 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		if (r)
 			goto error;
 
-		list_move_tail(&id->list, &adev->vm_manager.ids_lru);
+		list_move_tail(&id->list, &id_mgr->ids_lru);
 
-		job->vm_id = id - adev->vm_manager.ids;
+		job->vm_id = id - id_mgr->ids;
 		job->vm_needs_flush = false;
 		trace_amdgpu_vm_grab_id(vm, ring->idx, job);
 
-		mutex_unlock(&adev->vm_manager.lock);
+		mutex_unlock(&id_mgr->lock);
 		return 0;
 
 	};
@@ -522,14 +524,14 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 
 	id->pd_gpu_addr = job->vm_pd_addr;
 	id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
-	list_move_tail(&id->list, &adev->vm_manager.ids_lru);
+	list_move_tail(&id->list, &id_mgr->ids_lru);
 	atomic64_set(&id->owner, vm->client_id);
 
-	job->vm_id = id - adev->vm_manager.ids;
+	job->vm_id = id - id_mgr->ids;
 	trace_amdgpu_vm_grab_id(vm, ring->idx, job);
 
 error:
-	mutex_unlock(&adev->vm_manager.lock);
+	mutex_unlock(&id_mgr->lock);
 	return r;
 }
 
@@ -581,7 +583,9 @@ static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
 {
 	struct amdgpu_device *adev = ring->adev;
-	struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id];
+	unsigned vmhub = ring->funcs->vmhub;
+	struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+	struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
 	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
 		id->gds_base != job->gds_base ||
 		id->gds_size != job->gds_size ||
@@ -619,10 +623,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
 		if (r)
 			return r;
 
-		mutex_lock(&adev->vm_manager.lock);
+		mutex_lock(&id_mgr->lock);
 		fence_put(id->last_flush);
 		id->last_flush = fence;
-		mutex_unlock(&adev->vm_manager.lock);
+		mutex_unlock(&id_mgr->lock);
 	}
 
 	if (gds_switch_needed) {
@@ -657,9 +661,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
  *
  * Reset saved GDW, GWS and OA to force switch on next flush.
  */
-void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
+void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
+			unsigned vmid)
 {
-	struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
+	struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
+	struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
 
 	id->gds_base = 0;
 	id->gds_size = 0;
@@ -2230,22 +2236,28 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
  */
 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
 {
-	unsigned i;
+	unsigned i, j;
+
+	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+		struct amdgpu_vm_id_manager *id_mgr =
+			&adev->vm_manager.id_mgr[i];
 
-	INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
+		mutex_init(&id_mgr->lock);
+		INIT_LIST_HEAD(&id_mgr->ids_lru);
 
-	/* skip over VMID 0, since it is the system VM */
-	for (i = 1; i < adev->vm_manager.num_ids; ++i) {
-		amdgpu_vm_reset_id(adev, i);
-		amdgpu_sync_create(&adev->vm_manager.ids[i].active);
-		list_add_tail(&adev->vm_manager.ids[i].list,
-			      &adev->vm_manager.ids_lru);
+		/* skip over VMID 0, since it is the system VM */
+		for (j = 1; j < id_mgr->num_ids; ++j) {
+			amdgpu_vm_reset_id(adev, i, j);
+			amdgpu_sync_create(&id_mgr->ids[i].active);
+			list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
+		}
 	}
 
 	adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
 		adev->vm_manager.seqno[i] = 0;
 
+
 	atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
 	atomic64_set(&adev->vm_manager.client_counter, 0);
 	spin_lock_init(&adev->vm_manager.prt_lock);
@@ -2261,13 +2273,19 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
  */
 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
 {
-	unsigned i;
+	unsigned i, j;
 
-	for (i = 0; i < AMDGPU_NUM_VM; ++i) {
-		struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
+	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
+		struct amdgpu_vm_id_manager *id_mgr =
+			&adev->vm_manager.id_mgr[i];
 
-		amdgpu_sync_free(&adev->vm_manager.ids[i].active);
-		fence_put(id->flushed_updates);
-		fence_put(id->last_flush);
+		mutex_destroy(&id_mgr->lock);
+		for (j = 0; j < AMDGPU_NUM_VM; ++j) {
+			struct amdgpu_vm_id *id = &id_mgr->ids[j];
+
+			amdgpu_sync_free(&id->active);
+			fence_put(id->flushed_updates);
+			fence_put(id->last_flush);
+		}
 	}
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 46987b4..5389604 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -146,12 +146,16 @@ struct amdgpu_vm_id {
 	uint32_t		oa_size;
 };
 
+struct amdgpu_vm_id_manager {
+	struct mutex		lock;
+	unsigned		num_ids;
+	struct list_head	ids_lru;
+	struct amdgpu_vm_id	ids[AMDGPU_NUM_VM];
+};
+
 struct amdgpu_vm_manager {
 	/* Handling of VMIDs */
-	struct mutex				lock;
-	unsigned				num_ids;
-	struct list_head			ids_lru;
-	struct amdgpu_vm_id			ids[AMDGPU_NUM_VM];
+	struct amdgpu_vm_id_manager		id_mgr[AMDGPU_MAX_VMHUBS];
 
 	/* Handling of VM fences */
 	u64					fence_context;
@@ -197,7 +201,8 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		      struct amdgpu_sync *sync, struct fence *fence,
 		      struct amdgpu_job *job);
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
-void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
+void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
+			unsigned vmid);
 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 				 struct amdgpu_vm *vm);
 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 421408e..2be18d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1935,7 +1935,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
 				   INDEX_STRIDE, 3);
 
 	mutex_lock(&adev->srbm_mutex);
-	for (i = 0; i < adev->vm_manager.num_ids; i++) {
+	for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
 		if (i == 0)
 			sh_mem_base = 0;
 		else
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index df591fb..bb22fd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3890,7 +3890,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
 				   INDEX_STRIDE, 3);
 	mutex_lock(&adev->srbm_mutex);
-	for (i = 0; i < adev->vm_manager.num_ids; i++) {
+	for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
 		vi_srbm_select(adev, 0, 0, 0, i);
 		/* CP and shaders */
 		if (i == 0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 631aef3..31c50b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -621,7 +621,7 @@ static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
 	 * amdgpu graphics/compute will use VMIDs 1-7
 	 * amdkfd will use VMIDs 8-15
 	 */
-	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 92abe12..2217d4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -746,7 +746,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 	 * amdgpu graphics/compute will use VMIDs 1-7
 	 * amdkfd will use VMIDs 8-15
 	 */
-	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f2ccefc..e4f5df3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -949,7 +949,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 	 * amdgpu graphics/compute will use VMIDs 1-7
 	 * amdkfd will use VMIDs 8-15
 	 */
-	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 	adev->vm_manager.num_level = 1;
 	amdgpu_vm_manager_init(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3b045e0..7f5cc75 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -519,7 +519,8 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
 	 * amdgpu graphics/compute will use VMIDs 1-7
 	 * amdkfd will use VMIDs 8-15
 	 */
-	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 
 	/* TODO: fix num_level for APU when updating vm size and block size */
 	if (adev->flags & AMD_IS_APU)
-- 
2.5.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/8] drm/amdgpu: invalidate only the currently needed VMHUB v2

[Christian König]

From: Christian König <christian.koenig@amd.com>

Drop invalidating both hubs from each engine.

v2: don't use hardcoded values

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |   3 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |  36 +++++------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |  60 +++++++++---------
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 111 +++++++++++++++------------------
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  |  57 ++++++++---------
 5 files changed, 119 insertions(+), 148 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index db47c51..d6a6873 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -406,8 +406,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		      struct amdgpu_job *job)
 {
 	struct amdgpu_device *adev = ring->adev;
-	/* Temporary use only the first VM manager */
-	unsigned vmhub = 0; /*ring->funcs->vmhub;*/
+	unsigned vmhub = ring->funcs->vmhub;
 	struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 	uint64_t fence_context = adev->fence_context + ring->idx;
 	struct fence *updates = sync->last_vm_update;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 71b092b..8b35617 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2956,35 +2956,29 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					unsigned vm_id, uint64_t pd_addr)
 {
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	unsigned eng = ring->idx;
-	unsigned i;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
 	BUG_ON(pd_addr & 0xFFFF00000000003EULL);
 
-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-		struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
-
-		gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-					   hub->ctx0_ptb_addr_lo32
-					   + (2 * vm_id),
-					   lower_32_bits(pd_addr));
+	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+				   hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
+				   lower_32_bits(pd_addr));
 
-		gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-					   hub->ctx0_ptb_addr_hi32
-					   + (2 * vm_id),
-					   upper_32_bits(pd_addr));
+	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+				   hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
+				   upper_32_bits(pd_addr));
 
-		gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-					   hub->vm_inv_eng0_req + eng, req);
+	gfx_v9_0_write_data_to_reg(ring, usepfp, true,
+				   hub->vm_inv_eng0_req + eng, req);
 
-		/* wait for the invalidate to complete */
-		gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
-				      eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
-	}
+	/* wait for the invalidate to complete */
+	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
+			      eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
 
 	/* compute doesn't have PFP */
 	if (usepfp) {
@@ -3463,7 +3457,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
 		5 +  /* COND_EXEC */
 		7 +  /* PIPELINE_SYNC */
-		46 + /* VM_FLUSH */
+		24 + /* VM_FLUSH */
 		8 +  /* FENCE for VM_FLUSH */
 		20 + /* GDS switch */
 		4 + /* double SWITCH_BUFFER,
@@ -3510,7 +3504,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
 		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-		64 + /* gfx_v9_0_ring_emit_vm_flush */
+		24 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
@@ -3540,7 +3534,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
 		5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
-		64 + /* gfx_v9_0_ring_emit_vm_flush */
+		24 + /* gfx_v9_0_ring_emit_vm_flush */
 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_compute */
 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 8cbb49d..add9371 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1039,44 +1039,40 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					 unsigned vm_id, uint64_t pd_addr)
 {
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	unsigned eng = ring->idx;
-	unsigned i;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
 	BUG_ON(pd_addr & 0xFFFF00000000003EULL);
 
-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-		struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
-
-		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-				  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-		amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
-		amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-				  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-		amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
-		amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-		/* flush TLB */
-		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-				  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-		amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
-		amdgpu_ring_write(ring, req);
-
-		/* wait for flush */
-		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
-				  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
-				  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
-		amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-		amdgpu_ring_write(ring, 0);
-		amdgpu_ring_write(ring, 1 << vm_id); /* reference */
-		amdgpu_ring_write(ring, 1 << vm_id); /* mask */
-		amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
-				  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
-	}
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
+	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
+	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+
+	/* flush TLB */
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
+			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
+	amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
+	amdgpu_ring_write(ring, req);
+
+	/* wait for flush */
+	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
+			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
+			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
+	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
+	amdgpu_ring_write(ring, 0);
+	amdgpu_ring_write(ring, 1 << vm_id); /* reference */
+	amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
+			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
 }
 
 static int sdma_v4_0_early_init(void *handle)
@@ -1481,7 +1477,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
 		3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
-		36 + /* sdma_v4_0_ring_emit_vm_flush */
+		18 + /* sdma_v4_0_ring_emit_vm_flush */
 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
 	.emit_ib = sdma_v4_0_ring_emit_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index fa80465..45e86f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1034,42 +1034,38 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 					unsigned vm_id, uint64_t pd_addr)
 {
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	uint32_t data0, data1, mask;
 	unsigned eng = ring->idx;
-	unsigned i;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
 	BUG_ON(pd_addr & 0xFFFF00000000003EULL);
 
-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-		struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
-
-		data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
-		data1 = upper_32_bits(pd_addr);
-		uvd_v7_0_vm_reg_write(ring, data0, data1);
-
-		data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
-		data1 = lower_32_bits(pd_addr);
-		uvd_v7_0_vm_reg_write(ring, data0, data1);
-
-		data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
-		data1 = lower_32_bits(pd_addr);
-		mask = 0xffffffff;
-		uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
-
-		/* flush TLB */
-		data0 = (hub->vm_inv_eng0_req + eng) << 2;
-		data1 = req;
-		uvd_v7_0_vm_reg_write(ring, data0, data1);
-
-		/* wait for flush */
-		data0 = (hub->vm_inv_eng0_ack + eng) << 2;
-		data1 = 1 << vm_id;
-		mask =  1 << vm_id;
-		uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
-	}
+	data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+	data1 = upper_32_bits(pd_addr);
+	uvd_v7_0_vm_reg_write(ring, data0, data1);
+
+	data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+	data1 = lower_32_bits(pd_addr);
+	uvd_v7_0_vm_reg_write(ring, data0, data1);
+
+	data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+	data1 = lower_32_bits(pd_addr);
+	mask = 0xffffffff;
+	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
+
+	/* flush TLB */
+	data0 = (hub->vm_inv_eng0_req + eng) << 2;
+	data1 = req;
+	uvd_v7_0_vm_reg_write(ring, data0, data1);
+
+	/* wait for flush */
+	data0 = (hub->vm_inv_eng0_ack + eng) << 2;
+	data1 = 1 << vm_id;
+	mask =  1 << vm_id;
+	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
 }
 
 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
@@ -1080,44 +1076,37 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 			 unsigned int vm_id, uint64_t pd_addr)
 {
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	unsigned eng = ring->idx;
-	unsigned i;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
 	BUG_ON(pd_addr & 0xFFFF00000000003EULL);
 
-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-		struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
-
-		amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-		amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-		amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, 0xffffffff);
-		amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-		/* flush TLB */
-		amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
-		amdgpu_ring_write(ring, req);
-
-		/* wait for flush */
-		amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
-		amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-		amdgpu_ring_write(ring, 1 << vm_id);
-		amdgpu_ring_write(ring, 1 << vm_id);
-	}
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, 0xffffffff);
+	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+	/* flush TLB */
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
+	amdgpu_ring_write(ring, req);
+
+	/* wait for flush */
+	amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
+	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
+	amdgpu_ring_write(ring, 1 << vm_id);
+	amdgpu_ring_write(ring, 1 << vm_id);
 }
 
 #if 0
@@ -1455,7 +1444,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
 	.emit_frame_size =
 		2 + /* uvd_v7_0_ring_emit_hdp_flush */
 		2 + /* uvd_v7_0_ring_emit_hdp_invalidate */
-		34 * AMDGPU_MAX_VMHUBS + /* uvd_v7_0_ring_emit_vm_flush */
+		34 + /* uvd_v7_0_ring_emit_vm_flush */
 		14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
 	.emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
 	.emit_ib = uvd_v7_0_ring_emit_ib,
@@ -1481,7 +1470,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
 	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
 	.emit_frame_size =
-		17 * AMDGPU_MAX_VMHUBS + /* uvd_v7_0_enc_ring_emit_vm_flush */
+		17 + /* uvd_v7_0_enc_ring_emit_vm_flush */
 		5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
 		1, /* uvd_v7_0_enc_ring_insert_end */
 	.emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 6374133..c1a1708 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -973,44 +973,37 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
 static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
 			 unsigned int vm_id, uint64_t pd_addr)
 {
+	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	unsigned eng = ring->idx;
-	unsigned i;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
 	BUG_ON(pd_addr & 0xFFFF00000000003EULL);
 
-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
-		struct amdgpu_vmhub *hub = &ring->adev->vmhub[i];
-
-		amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, upper_32_bits(pd_addr));
-
-		amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-		amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
-		amdgpu_ring_write(ring,
-			(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
-		amdgpu_ring_write(ring, 0xffffffff);
-		amdgpu_ring_write(ring, lower_32_bits(pd_addr));
-
-		/* flush TLB */
-		amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-		amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
-		amdgpu_ring_write(ring, req);
-
-		/* wait for flush */
-		amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
-		amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-		amdgpu_ring_write(ring, 1 << vm_id);
-		amdgpu_ring_write(ring, 1 << vm_id);
-	}
+	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+
+	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+	amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
+	amdgpu_ring_write(ring,	(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+	amdgpu_ring_write(ring, 0xffffffff);
+	amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+	/* flush TLB */
+	amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
+	amdgpu_ring_write(ring,	(hub->vm_inv_eng0_req + eng) << 2);
+	amdgpu_ring_write(ring, req);
+
+	/* wait for flush */
+	amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
+	amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
+	amdgpu_ring_write(ring, 1 << vm_id);
+	amdgpu_ring_write(ring, 1 << vm_id);
 }
 
 static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,
@@ -1080,7 +1073,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
 	.set_wptr = vce_v4_0_ring_set_wptr,
 	.parse_cs = amdgpu_vce_ring_parse_cs_vm,
 	.emit_frame_size =
-		17 * AMDGPU_MAX_VMHUBS + /* vce_v4_0_emit_vm_flush */
+		17 + /* vce_v4_0_emit_vm_flush */
 		5 + 5 + /* amdgpu_vce_ring_emit_fence x2 vm fence */
 		1, /* vce_v4_0_ring_insert_end */
 	.emit_ib_size = 5, /* vce_v4_0_ring_emit_ib */
-- 
2.5.0

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[PATCH 5/8] drm/amdgpu: assign VM invalidation engine manually

[Christian König]

From: Christian König <christian.koenig@amd.com>

For Vega10 we have 18 VM invalidation engines for each VMHUB.

Start to assign them manually to the rings.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 12 ++++++++++++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    |  4 ++--
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    |  2 +-
 6 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 45bb87b..5786cc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -179,6 +179,7 @@ struct amdgpu_ring {
 	unsigned		cond_exe_offs;
 	u64			cond_exe_gpu_addr;
 	volatile u32		*cond_exe_cpu_addr;
+	unsigned		vm_inv_eng;
 #if defined(CONFIG_DEBUG_FS)
 	struct dentry *ent;
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8b35617..609ea29 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2959,7 +2959,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-	unsigned eng = ring->idx;
+	unsigned eng = ring->vm_inv_eng;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7f5cc75..e3d2cdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -386,6 +386,18 @@ static int gmc_v9_0_early_init(void *handle)
 static int gmc_v9_0_late_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 0 };
+	unsigned i;
+
+	for(i = 0; i < adev->num_rings; ++i) {
+		struct amdgpu_ring *ring = adev->rings[i];
+		unsigned vmhub = ring->funcs->vmhub;
+
+		ring->vm_inv_eng = vm_inv_eng[vmhub]++;
+		dev_info(adev->dev, "ring %u uses VM inv eng %u on hub %u\n",
+			 ring->idx, ring->vm_inv_eng, ring->funcs->vmhub);
+	}
+
 	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index add9371..d5065a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1041,7 +1041,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-	unsigned eng = ring->idx;
+	unsigned eng = ring->vm_inv_eng;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 45e86f8..bf35d56 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1037,7 +1037,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
 	uint32_t data0, data1, mask;
-	unsigned eng = ring->idx;
+	unsigned eng = ring->vm_inv_eng;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
@@ -1078,7 +1078,7 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-	unsigned eng = ring->idx;
+	unsigned eng = ring->vm_inv_eng;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index c1a1708..5240753 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -975,7 +975,7 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
 {
 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
-	unsigned eng = ring->idx;
+	unsigned eng = ring->vm_inv_eng;
 
 	pd_addr = pd_addr | 0x1; /* valid bit */
 	/* now only use physical base address of PDE and valid */
-- 
2.5.0

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Re: [PATCH 5/8] drm/amdgpu: assign VM invalidation engine manually

[Andres Rodriguez]

On 2017-04-07 12:11 PM, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> For Vega10 we have 18 VM invalidation engines for each VMHUB.
>
> Start to assign them manually to the rings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 12 ++++++++++++
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   |  2 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    |  2 +-
>  6 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 45bb87b..5786cc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -179,6 +179,7 @@ struct amdgpu_ring {
>  	unsigned		cond_exe_offs;
>  	u64			cond_exe_gpu_addr;
>  	volatile u32		*cond_exe_cpu_addr;
> +	unsigned		vm_inv_eng;
>  #if defined(CONFIG_DEBUG_FS)
>  	struct dentry *ent;
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8b35617..609ea29 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2959,7 +2959,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>  	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>  	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>  	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -	unsigned eng = ring->idx;
> +	unsigned eng = ring->vm_inv_eng;
>
>  	pd_addr = pd_addr | 0x1; /* valid bit */
>  	/* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 7f5cc75..e3d2cdd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -386,6 +386,18 @@ static int gmc_v9_0_early_init(void *handle)
>  static int gmc_v9_0_late_init(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 0 };
> +	unsigned i;
> +
> +	for(i = 0; i < adev->num_rings; ++i) {
> +		struct amdgpu_ring *ring = adev->rings[i];
> +		unsigned vmhub = ring->funcs->vmhub;
> +
> +		ring->vm_inv_eng = vm_inv_eng[vmhub]++;

Should there be a check here to make sure ring->vm_inv_eng does not 
exceed 18 (GFX9_INV_ENGINE_NUM or similar)?

It holds true that it should never happen for current gfx9 ASICs. But 
this will be copy pasted into gfxN in the future, and it may not hold 
true there.

Andres

> +		dev_info(adev->dev, "ring %u uses VM inv eng %u on hub %u\n",
> +			 ring->idx, ring->vm_inv_eng, ring->funcs->vmhub);
> +	}
> +
>  	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index add9371..d5065a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1041,7 +1041,7 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>  {
>  	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -	unsigned eng = ring->idx;
> +	unsigned eng = ring->vm_inv_eng;
>
>  	pd_addr = pd_addr | 0x1; /* valid bit */
>  	/* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 45e86f8..bf35d56 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1037,7 +1037,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>  	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
>  	uint32_t data0, data1, mask;
> -	unsigned eng = ring->idx;
> +	unsigned eng = ring->vm_inv_eng;
>
>  	pd_addr = pd_addr | 0x1; /* valid bit */
>  	/* now only use physical base address of PDE and valid */
> @@ -1078,7 +1078,7 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>  {
>  	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -	unsigned eng = ring->idx;
> +	unsigned eng = ring->vm_inv_eng;
>
>  	pd_addr = pd_addr | 0x1; /* valid bit */
>  	/* now only use physical base address of PDE and valid */
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index c1a1708..5240753 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -975,7 +975,7 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
>  {
>  	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
> -	unsigned eng = ring->idx;
> +	unsigned eng = ring->vm_inv_eng;
>
>  	pd_addr = pd_addr | 0x1; /* valid bit */
>  	/* now only use physical base address of PDE and valid */
>
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[PATCH 6/8] drm/amdgpu: allow concurrent VM flushes

[Christian König]

From: Christian König <christian.koenig@amd.com>

Enable concurrent VM flushes for Vega10.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 50 +++++++++++++++++++---------------
 1 file changed, 28 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d6a6873..d0b6f20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -462,10 +462,11 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	}
 	kfree(fences);
 
-	job->vm_needs_flush = true;
+	job->vm_needs_flush = false;
 	/* Check if we can use a VMID already assigned to this VM */
 	list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
 		struct fence *flushed;
+		bool needs_flush = false;
 
 		/* Check all the prerequisites to using this VMID */
 		if (amdgpu_vm_had_gpu_reset(adev, id))
@@ -477,16 +478,17 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		if (job->vm_pd_addr != id->pd_gpu_addr)
 			continue;
 
-		if (!id->last_flush)
-			continue;
-
-		if (id->last_flush->context != fence_context &&
-		    !fence_is_signaled(id->last_flush))
-			continue;
+		if (!id->last_flush ||
+		    (id->last_flush->context != fence_context &&
+		     !fence_is_signaled(id->last_flush)))
+			needs_flush = true;
 
 		flushed  = id->flushed_updates;
-		if (updates &&
-		    (!flushed || fence_is_later(updates, flushed)))
+		if (updates && (!flushed || fence_is_later(updates, flushed)))
+			needs_flush = true;
+
+		/* Concurrent flushes are only possible starting with Vega10 */
+		if (adev->asic_type < CHIP_VEGA10 && needs_flush)
 			continue;
 
 		/* Good we can use this VMID. Remember this submission as
@@ -496,14 +498,15 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 		if (r)
 			goto error;
 
-		list_move_tail(&id->list, &id_mgr->ids_lru);
-
-		job->vm_id = id - id_mgr->ids;
-		job->vm_needs_flush = false;
-		trace_amdgpu_vm_grab_id(vm, ring->idx, job);
+		if (updates && (!flushed || fence_is_later(updates, flushed))) {
+			fence_put(id->flushed_updates);
+			id->flushed_updates = fence_get(updates);
+		}
 
-		mutex_unlock(&id_mgr->lock);
-		return 0;
+		if (needs_flush)
+			goto needs_flush;
+		else
+			goto no_flush_needed;
 
 	};
 
@@ -515,17 +518,20 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	if (r)
 		goto error;
 
-	fence_put(id->last_flush);
-	id->last_flush = NULL;
-
+	id->pd_gpu_addr = job->vm_pd_addr;
 	fence_put(id->flushed_updates);
 	id->flushed_updates = fence_get(updates);
-
-	id->pd_gpu_addr = job->vm_pd_addr;
 	id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
-	list_move_tail(&id->list, &id_mgr->ids_lru);
 	atomic64_set(&id->owner, vm->client_id);
 
+needs_flush:
+	job->vm_needs_flush = true;
+	fence_put(id->last_flush);
+	id->last_flush = NULL;
+
+no_flush_needed:
+	list_move_tail(&id->list, &id_mgr->ids_lru);
+
 	job->vm_id = id - id_mgr->ids;
 	trace_amdgpu_vm_grab_id(vm, ring->idx, job);
 
-- 
2.5.0

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[PATCH 7/8] drm/amdgpu: trace the vmhub in grab_id as well

[Christian König]

From: Christian König <christian.koenig@amd.com>

Trace on which VMHUB we assigned an VMID.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 17 ++++++++++-------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 381b770..6032161 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -190,26 +190,29 @@ TRACE_EVENT(amdgpu_sched_run_job,
 
 
 TRACE_EVENT(amdgpu_vm_grab_id,
-	    TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),
+	    TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
+		     struct amdgpu_job *job),
 	    TP_ARGS(vm, ring, job),
 	    TP_STRUCT__entry(
 			     __field(struct amdgpu_vm *, vm)
 			     __field(u32, ring)
-			     __field(u32, vmid)
+			     __field(u32, vm_id)
+			     __field(u32, vm_hub)
 			     __field(u64, pd_addr)
 			     __field(u32, needs_flush)
 			     ),
 
 	    TP_fast_assign(
 			   __entry->vm = vm;
-			   __entry->ring = ring;
-			   __entry->vmid = job->vm_id;
+			   __entry->ring = ring->idx;
+			   __entry->vm_id = job->vm_id;
+			   __entry->vm_hub = ring->funcs->vmhub,
 			   __entry->pd_addr = job->vm_pd_addr;
 			   __entry->needs_flush = job->vm_needs_flush;
 			   ),
-	    TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx needs_flush=%u",
-		      __entry->vm, __entry->ring, __entry->vmid,
-		      __entry->pd_addr, __entry->needs_flush)
+	    TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
+		      __entry->vm, __entry->ring, __entry->vm_id,
+		      __entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
 );
 
 TRACE_EVENT(amdgpu_vm_bo_map,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d0b6f20..494645e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -533,7 +533,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 	list_move_tail(&id->list, &id_mgr->ids_lru);
 
 	job->vm_id = id - id_mgr->ids;
-	trace_amdgpu_vm_grab_id(vm, ring->idx, job);
+	trace_amdgpu_vm_grab_id(vm, ring, job);
 
 error:
 	mutex_unlock(&id_mgr->lock);
-- 
2.5.0

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Re: [PATCH 7/8] drm/amdgpu: trace the vmhub in grab_id as well

[Andres Rodriguez]

On 2017-04-07 12:11 PM, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Trace on which VMHUB we assigned an VMID.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 17 ++++++++++-------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
>  2 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 381b770..6032161 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -190,26 +190,29 @@ TRACE_EVENT(amdgpu_sched_run_job,
>
>
>  TRACE_EVENT(amdgpu_vm_grab_id,
> -	    TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),
> +	    TP_PROTO(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
> +		     struct amdgpu_job *job),
>  	    TP_ARGS(vm, ring, job),
>  	    TP_STRUCT__entry(
>  			     __field(struct amdgpu_vm *, vm)
>  			     __field(u32, ring)
> -			     __field(u32, vmid)
> +			     __field(u32, vm_id)
> +			     __field(u32, vm_hub)
>  			     __field(u64, pd_addr)
>  			     __field(u32, needs_flush)
>  			     ),
>
>  	    TP_fast_assign(
>  			   __entry->vm = vm;
> -			   __entry->ring = ring;
> -			   __entry->vmid = job->vm_id;
> +			   __entry->ring = ring->idx;
> +			   __entry->vm_id = job->vm_id;
> +			   __entry->vm_hub = ring->funcs->vmhub,
>  			   __entry->pd_addr = job->vm_pd_addr;
>  			   __entry->needs_flush = job->vm_needs_flush;
>  			   ),
> -	    TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx needs_flush=%u",
> -		      __entry->vm, __entry->ring, __entry->vmid,
> -		      __entry->pd_addr, __entry->needs_flush)
> +	    TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
> +		      __entry->vm, __entry->ring, __entry->vm_id,
> +		      __entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
>  );

This is where I meant to request tracing of the job id. This job may 
have incurred some extra overhead due to a vmid being requested. I think 
that information would be useful to capture and tie to the job 
submission traces.

Regards,
Andres

>
>  TRACE_EVENT(amdgpu_vm_bo_map,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index d0b6f20..494645e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -533,7 +533,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
>  	list_move_tail(&id->list, &id_mgr->ids_lru);
>
>  	job->vm_id = id - id_mgr->ids;
> -	trace_amdgpu_vm_grab_id(vm, ring->idx, job);
> +	trace_amdgpu_vm_grab_id(vm, ring, job);
>
>  error:
>  	mutex_unlock(&id_mgr->lock);
>
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[PATCH 8/8] drm/amdgpu: trace vm hub druing flush as well

[Christian König]

From: Christian König <christian.koenig@amd.com>

Trace on which hub we are doing the flush.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20 ++++++++++++--------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 6032161..f95a386 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -334,21 +334,25 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
 );
 
 TRACE_EVENT(amdgpu_vm_flush,
-	    TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
-	    TP_ARGS(pd_addr, ring, id),
+	    TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
+		     uint64_t pd_addr),
+	    TP_ARGS(ring, vm_id, pd_addr),
 	    TP_STRUCT__entry(
-			     __field(u64, pd_addr)
 			     __field(u32, ring)
-			     __field(u32, id)
+			     __field(u32, vm_id)
+			     __field(u32, vm_hub)
+			     __field(u64, pd_addr)
 			     ),
 
 	    TP_fast_assign(
+			   __entry->ring = ring->idx;
+			   __entry->vm_id = vm_id;
+			   __entry->vm_hub = ring->funcs->vmhub;
 			   __entry->pd_addr = pd_addr;
-			   __entry->ring = ring;
-			   __entry->id = id;
 			   ),
-	    TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
-		      __entry->ring, __entry->id, __entry->pd_addr)
+	    TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
+		      __entry->ring, __entry->vm_id,
+		      __entry->vm_hub,__entry->pd_addr)
 );
 
 TRACE_EVENT(amdgpu_bo_list_set,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 494645e..9017b51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -621,7 +621,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
 		u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
 		struct fence *fence;
 
-		trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
+		trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr);
 		amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
 
 		r = amdgpu_fence_emit(ring, &fence);
-- 
2.5.0

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Re: [PATCH 8/8] drm/amdgpu: trace vm hub druing flush as well

[Andres Rodriguez]

s/druing/during in subject

On 2017-04-07 12:11 PM, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Trace on which hub we are doing the flush.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20 ++++++++++++--------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
>   2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> index 6032161..f95a386 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
> @@ -334,21 +334,25 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
>   );
>   
>   TRACE_EVENT(amdgpu_vm_flush,
> -	    TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
> -	    TP_ARGS(pd_addr, ring, id),
> +	    TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
> +		     uint64_t pd_addr),
> +	    TP_ARGS(ring, vm_id, pd_addr),
>   	    TP_STRUCT__entry(
> -			     __field(u64, pd_addr)
>   			     __field(u32, ring)
> -			     __field(u32, id)
> +			     __field(u32, vm_id)
> +			     __field(u32, vm_hub)
> +			     __field(u64, pd_addr)
>   			     ),
>   
>   	    TP_fast_assign(
> +			   __entry->ring = ring->idx;
> +			   __entry->vm_id = vm_id;
> +			   __entry->vm_hub = ring->funcs->vmhub;
>   			   __entry->pd_addr = pd_addr;
> -			   __entry->ring = ring;
> -			   __entry->id = id;
>   			   ),
> -	    TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
> -		      __entry->ring, __entry->id, __entry->pd_addr)
> +	    TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
> +		      __entry->ring, __entry->vm_id,
> +		      __entry->vm_hub,__entry->pd_addr)

Can you also include job->base->id in this trace?

Andres
>   );
>   
>   TRACE_EVENT(amdgpu_bo_list_set,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 494645e..9017b51 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -621,7 +621,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
>   		u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
>   		struct fence *fence;
>   
> -		trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
> +		trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr);
>   		amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
>   
>   		r = amdgpu_fence_emit(ring, &fence);

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Re: [PATCH 8/8] drm/amdgpu: trace vm hub druing flush as well

[Christian König]

Am 07.04.2017 um 18:52 schrieb Andres Rodriguez:
>
> s/druing/during in subject
>
> On 2017-04-07 12:11 PM, Christian König wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> Trace on which hub we are doing the flush.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20 ++++++++++++--------
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
>>   2 files changed, 13 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>> index 6032161..f95a386 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>> @@ -334,21 +334,25 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
>>   );
>>     TRACE_EVENT(amdgpu_vm_flush,
>> -        TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
>> -        TP_ARGS(pd_addr, ring, id),
>> +        TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
>> +             uint64_t pd_addr),
>> +        TP_ARGS(ring, vm_id, pd_addr),
>>           TP_STRUCT__entry(
>> -                 __field(u64, pd_addr)
>>                    __field(u32, ring)
>> -                 __field(u32, id)
>> +                 __field(u32, vm_id)
>> +                 __field(u32, vm_hub)
>> +                 __field(u64, pd_addr)
>>                    ),
>>             TP_fast_assign(
>> +               __entry->ring = ring->idx;
>> +               __entry->vm_id = vm_id;
>> +               __entry->vm_hub = ring->funcs->vmhub;
>>                  __entry->pd_addr = pd_addr;
>> -               __entry->ring = ring;
>> -               __entry->id = id;
>>                  ),
>> -        TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
>> -              __entry->ring, __entry->id, __entry->pd_addr)
>> +        TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
>> +              __entry->ring, __entry->vm_id,
>> +              __entry->vm_hub,__entry->pd_addr)
>
> Can you also include job->base->id in this trace?

No, at least not of hand. VM flushes are meant to be independent of job 
submission.

Christian.

>
> Andres
>>   );
>>     TRACE_EVENT(amdgpu_bo_list_set,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 494645e..9017b51 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -621,7 +621,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, 
>> struct amdgpu_job *job)
>>           u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
>>           struct fence *fence;
>>   -        trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
>> +        trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr);
>>           amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
>>             r = amdgpu_fence_emit(ring, &fence);
>

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Re: [PATCH 8/8] drm/amdgpu: trace vm hub druing flush as well

[Andres Rodriguez]

On 2017-04-11 04:45 AM, Christian König wrote:
> Am 07.04.2017 um 18:52 schrieb Andres Rodriguez:
>>
>> s/druing/during in subject
>>
>> On 2017-04-07 12:11 PM, Christian König wrote:
>>> From: Christian König <christian.koenig@amd.com>
>>>
>>> Trace on which hub we are doing the flush.
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20 ++++++++++++--------
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c    |  2 +-
>>>   2 files changed, 13 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>>> index 6032161..f95a386 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
>>> @@ -334,21 +334,25 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
>>>   );
>>>     TRACE_EVENT(amdgpu_vm_flush,
>>> -        TP_PROTO(uint64_t pd_addr, unsigned ring, unsigned id),
>>> -        TP_ARGS(pd_addr, ring, id),
>>> +        TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
>>> +             uint64_t pd_addr),
>>> +        TP_ARGS(ring, vm_id, pd_addr),
>>>           TP_STRUCT__entry(
>>> -                 __field(u64, pd_addr)
>>>                    __field(u32, ring)
>>> -                 __field(u32, id)
>>> +                 __field(u32, vm_id)
>>> +                 __field(u32, vm_hub)
>>> +                 __field(u64, pd_addr)
>>>                    ),
>>>             TP_fast_assign(
>>> +               __entry->ring = ring->idx;
>>> +               __entry->vm_id = vm_id;
>>> +               __entry->vm_hub = ring->funcs->vmhub;
>>>                  __entry->pd_addr = pd_addr;
>>> -               __entry->ring = ring;
>>> -               __entry->id = id;
>>>                  ),
>>> -        TP_printk("ring=%u, id=%u, pd_addr=%010Lx",
>>> -              __entry->ring, __entry->id, __entry->pd_addr)
>>> +        TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
>>> +              __entry->ring, __entry->vm_id,
>>> +              __entry->vm_hub,__entry->pd_addr)
>>
>> Can you also include job->base->id in this trace?
>
> No, at least not of hand. VM flushes are meant to be independent of job
> submission.
>

Sorry about the confusion. This comment should've been on patch 7/8 
instead of this one.


> Christian.
>
>>
>> Andres
>>>   );
>>>     TRACE_EVENT(amdgpu_bo_list_set,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> index 494645e..9017b51 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> @@ -621,7 +621,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring,
>>> struct amdgpu_job *job)
>>>           u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
>>>           struct fence *fence;
>>>   -        trace_amdgpu_vm_flush(pd_addr, ring->idx, job->vm_id);
>>> +        trace_amdgpu_vm_flush(ring, job->vm_id, pd_addr);
>>>           amdgpu_ring_emit_vm_flush(ring, job->vm_id, pd_addr);
>>>             r = amdgpu_fence_emit(ring, &fence);
>>
>
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Re: [PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[Andres Rodriguez]

Some minor nitpicks as replies to the other emails.

With those fixed, this series is:
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>

I've learned about VMHUB from your patches, so take it with a little 
grain of salt though.

On 2017-04-07 12:11 PM, Christian König wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Add the info which ring belonging to which VMHUB.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 3 +++
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 2 ++
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    | 1 +
>  5 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7479e47..45bb87b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
>  	uint32_t		align_mask;
>  	u32			nop;
>  	bool			support_64bit_ptrs;
> +	unsigned		vmhub;
>
>  	/* ring read/write ptr handling */
>  	u64 (*get_rptr)(struct amdgpu_ring *ring);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index cb6c7eb8..71b092b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3456,6 +3456,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>  	.align_mask = 0xff,
>  	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
>  	.support_64bit_ptrs = true,
> +	.vmhub = AMDGPU_GFXHUB,
>  	.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
>  	.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
>  	.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
> @@ -3500,6 +3501,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
>  	.align_mask = 0xff,
>  	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
>  	.support_64bit_ptrs = true,
> +	.vmhub = AMDGPU_GFXHUB,
>  	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
>  	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
>  	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
> @@ -3529,6 +3531,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
>  	.align_mask = 0xff,
>  	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
>  	.support_64bit_ptrs = true,
> +	.vmhub = AMDGPU_GFXHUB,
>  	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
>  	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
>  	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index d40eb31..8cbb49d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
>  	.align_mask = 0xf,
>  	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>  	.support_64bit_ptrs = true,
> +	.vmhub = AMDGPU_MMHUB,
>  	.get_rptr = sdma_v4_0_ring_get_rptr,
>  	.get_wptr = sdma_v4_0_ring_get_wptr,
>  	.set_wptr = sdma_v4_0_ring_set_wptr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 819148a..fa80465 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
>  	.align_mask = 0xf,
>  	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
>  	.support_64bit_ptrs = false,
> +	.vmhub = AMDGPU_MMHUB,
>  	.get_rptr = uvd_v7_0_ring_get_rptr,
>  	.get_wptr = uvd_v7_0_ring_get_wptr,
>  	.set_wptr = uvd_v7_0_ring_set_wptr,
> @@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
>  	.align_mask = 0x3f,
>  	.nop = HEVC_ENC_CMD_NO_OP,
>  	.support_64bit_ptrs = false,
> +	.vmhub = AMDGPU_MMHUB,
>  	.get_rptr = uvd_v7_0_enc_ring_get_rptr,
>  	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
>  	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 8dde83f..6374133 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
>  	.align_mask = 0x3f,
>  	.nop = VCE_CMD_NO_OP,
>  	.support_64bit_ptrs = false,
> +	.vmhub = AMDGPU_MMHUB,
>  	.get_rptr = vce_v4_0_ring_get_rptr,
>  	.get_wptr = vce_v4_0_ring_get_wptr,
>  	.set_wptr = vce_v4_0_ring_set_wptr,
>
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Re: [PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[zhoucm1]

On 2017年04月08日 00:59, Andres Rodriguez wrote:
> Some minor nitpicks as replies to the other emails.
>
> With those fixed, this series is:
Looks good to me.

David
> Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
>
> I've learned about VMHUB from your patches, so take it with a little 
> grain of salt though.
>
> On 2017-04-07 12:11 PM, Christian König wrote:
>> From: Christian König <christian.koenig@amd.com>
>>
>> Add the info which ring belonging to which VMHUB.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 3 +++
>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
>>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 2 ++
>>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    | 1 +
>>  5 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> index 7479e47..45bb87b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> @@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
>>      uint32_t        align_mask;
>>      u32            nop;
>>      bool            support_64bit_ptrs;
>> +    unsigned        vmhub;
>>
>>      /* ring read/write ptr handling */
>>      u64 (*get_rptr)(struct amdgpu_ring *ring);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index cb6c7eb8..71b092b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3456,6 +3456,7 @@ static const struct amdgpu_ring_funcs 
>> gfx_v9_0_ring_funcs_gfx = {
>>      .align_mask = 0xff,
>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>      .support_64bit_ptrs = true,
>> +    .vmhub = AMDGPU_GFXHUB,
>>      .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
>>      .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
>>      .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
>> @@ -3500,6 +3501,7 @@ static const struct amdgpu_ring_funcs 
>> gfx_v9_0_ring_funcs_compute = {
>>      .align_mask = 0xff,
>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>      .support_64bit_ptrs = true,
>> +    .vmhub = AMDGPU_GFXHUB,
>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>> @@ -3529,6 +3531,7 @@ static const struct amdgpu_ring_funcs 
>> gfx_v9_0_ring_funcs_kiq = {
>>      .align_mask = 0xff,
>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>      .support_64bit_ptrs = true,
>> +    .vmhub = AMDGPU_GFXHUB,
>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index d40eb31..8cbb49d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs 
>> sdma_v4_0_ring_funcs = {
>>      .align_mask = 0xf,
>>      .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>>      .support_64bit_ptrs = true,
>> +    .vmhub = AMDGPU_MMHUB,
>>      .get_rptr = sdma_v4_0_ring_get_rptr,
>>      .get_wptr = sdma_v4_0_ring_get_wptr,
>>      .set_wptr = sdma_v4_0_ring_set_wptr,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index 819148a..fa80465 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs 
>> uvd_v7_0_ring_vm_funcs = {
>>      .align_mask = 0xf,
>>      .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
>>      .support_64bit_ptrs = false,
>> +    .vmhub = AMDGPU_MMHUB,
>>      .get_rptr = uvd_v7_0_ring_get_rptr,
>>      .get_wptr = uvd_v7_0_ring_get_wptr,
>>      .set_wptr = uvd_v7_0_ring_set_wptr,
>> @@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs 
>> uvd_v7_0_enc_ring_vm_funcs = {
>>      .align_mask = 0x3f,
>>      .nop = HEVC_ENC_CMD_NO_OP,
>>      .support_64bit_ptrs = false,
>> +    .vmhub = AMDGPU_MMHUB,
>>      .get_rptr = uvd_v7_0_enc_ring_get_rptr,
>>      .get_wptr = uvd_v7_0_enc_ring_get_wptr,
>>      .set_wptr = uvd_v7_0_enc_ring_set_wptr,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index 8dde83f..6374133 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs 
>> vce_v4_0_ring_vm_funcs = {
>>      .align_mask = 0x3f,
>>      .nop = VCE_CMD_NO_OP,
>>      .support_64bit_ptrs = false,
>> +    .vmhub = AMDGPU_MMHUB,
>>      .get_rptr = vce_v4_0_ring_get_rptr,
>>      .get_wptr = vce_v4_0_ring_get_wptr,
>>      .set_wptr = vce_v4_0_ring_set_wptr,
>>
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Re: [PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[Christian König]

Am 10.04.2017 um 05:41 schrieb zhoucm1:
>
>
> On 2017年04月08日 00:59, Andres Rodriguez wrote:
>> Some minor nitpicks as replies to the other emails.
>>
>> With those fixed, this series is:
> Looks good to me.

Does that mean I can stitch your rb on it and commit it?

Thanks,
Christian.

>
> David
>> Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
>>
>> I've learned about VMHUB from your patches, so take it with a little 
>> grain of salt though.
>>
>> On 2017-04-07 12:11 PM, Christian König wrote:
>>> From: Christian König <christian.koenig@amd.com>
>>>
>>> Add the info which ring belonging to which VMHUB.
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 3 +++
>>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
>>>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 2 ++
>>>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    | 1 +
>>>  5 files changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>> index 7479e47..45bb87b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>> @@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
>>>      uint32_t        align_mask;
>>>      u32            nop;
>>>      bool            support_64bit_ptrs;
>>> +    unsigned        vmhub;
>>>
>>>      /* ring read/write ptr handling */
>>>      u64 (*get_rptr)(struct amdgpu_ring *ring);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index cb6c7eb8..71b092b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -3456,6 +3456,7 @@ static const struct amdgpu_ring_funcs 
>>> gfx_v9_0_ring_funcs_gfx = {
>>>      .align_mask = 0xff,
>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>      .support_64bit_ptrs = true,
>>> +    .vmhub = AMDGPU_GFXHUB,
>>>      .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
>>>      .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
>>>      .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
>>> @@ -3500,6 +3501,7 @@ static const struct amdgpu_ring_funcs 
>>> gfx_v9_0_ring_funcs_compute = {
>>>      .align_mask = 0xff,
>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>      .support_64bit_ptrs = true,
>>> +    .vmhub = AMDGPU_GFXHUB,
>>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>>> @@ -3529,6 +3531,7 @@ static const struct amdgpu_ring_funcs 
>>> gfx_v9_0_ring_funcs_kiq = {
>>>      .align_mask = 0xff,
>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>      .support_64bit_ptrs = true,
>>> +    .vmhub = AMDGPU_GFXHUB,
>>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> index d40eb31..8cbb49d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> @@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs 
>>> sdma_v4_0_ring_funcs = {
>>>      .align_mask = 0xf,
>>>      .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>>>      .support_64bit_ptrs = true,
>>> +    .vmhub = AMDGPU_MMHUB,
>>>      .get_rptr = sdma_v4_0_ring_get_rptr,
>>>      .get_wptr = sdma_v4_0_ring_get_wptr,
>>>      .set_wptr = sdma_v4_0_ring_set_wptr,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>> index 819148a..fa80465 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>> @@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs 
>>> uvd_v7_0_ring_vm_funcs = {
>>>      .align_mask = 0xf,
>>>      .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
>>>      .support_64bit_ptrs = false,
>>> +    .vmhub = AMDGPU_MMHUB,
>>>      .get_rptr = uvd_v7_0_ring_get_rptr,
>>>      .get_wptr = uvd_v7_0_ring_get_wptr,
>>>      .set_wptr = uvd_v7_0_ring_set_wptr,
>>> @@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs 
>>> uvd_v7_0_enc_ring_vm_funcs = {
>>>      .align_mask = 0x3f,
>>>      .nop = HEVC_ENC_CMD_NO_OP,
>>>      .support_64bit_ptrs = false,
>>> +    .vmhub = AMDGPU_MMHUB,
>>>      .get_rptr = uvd_v7_0_enc_ring_get_rptr,
>>>      .get_wptr = uvd_v7_0_enc_ring_get_wptr,
>>>      .set_wptr = uvd_v7_0_enc_ring_set_wptr,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
>>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>> index 8dde83f..6374133 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>> @@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs 
>>> vce_v4_0_ring_vm_funcs = {
>>>      .align_mask = 0x3f,
>>>      .nop = VCE_CMD_NO_OP,
>>>      .support_64bit_ptrs = false,
>>> +    .vmhub = AMDGPU_MMHUB,
>>>      .get_rptr = vce_v4_0_ring_get_rptr,
>>>      .get_wptr = vce_v4_0_ring_get_wptr,
>>>      .set_wptr = vce_v4_0_ring_set_wptr,
>>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>

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Re: [PATCH 1/8] drm/amdgpu: add VMHUB to ring association

[zhoucm1]

On 2017年04月11日 16:45, Christian König wrote:
> Am 10.04.2017 um 05:41 schrieb zhoucm1:
>>
>>
>> On 2017年04月08日 00:59, Andres Rodriguez wrote:
>>> Some minor nitpicks as replies to the other emails.
>>>
>>> With those fixed, this series is:
>> Looks good to me.
>
> Does that mean I can stitch your rb on it and commit it?
Already has Andres's RB, go ahead to push it.

Thanks,
David Zhou
>
> Thanks,
> Christian.
>
>>
>> David
>>> Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
>>>
>>> I've learned about VMHUB from your patches, so take it with a little 
>>> grain of salt though.
>>>
>>> On 2017-04-07 12:11 PM, Christian König wrote:
>>>> From: Christian König <christian.koenig@amd.com>
>>>>
>>>> Add the info which ring belonging to which VMHUB.
>>>>
>>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>>>> ---
>>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>>>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 3 +++
>>>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 1 +
>>>>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c    | 2 ++
>>>>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c    | 1 +
>>>>  5 files changed, 8 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>>> index 7479e47..45bb87b 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>>>> @@ -99,6 +99,7 @@ struct amdgpu_ring_funcs {
>>>>      uint32_t        align_mask;
>>>>      u32            nop;
>>>>      bool            support_64bit_ptrs;
>>>> +    unsigned        vmhub;
>>>>
>>>>      /* ring read/write ptr handling */
>>>>      u64 (*get_rptr)(struct amdgpu_ring *ring);
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> index cb6c7eb8..71b092b 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> @@ -3456,6 +3456,7 @@ static const struct amdgpu_ring_funcs 
>>>> gfx_v9_0_ring_funcs_gfx = {
>>>>      .align_mask = 0xff,
>>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>>      .support_64bit_ptrs = true,
>>>> +    .vmhub = AMDGPU_GFXHUB,
>>>>      .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
>>>>      .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
>>>>      .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
>>>> @@ -3500,6 +3501,7 @@ static const struct amdgpu_ring_funcs 
>>>> gfx_v9_0_ring_funcs_compute = {
>>>>      .align_mask = 0xff,
>>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>>      .support_64bit_ptrs = true,
>>>> +    .vmhub = AMDGPU_GFXHUB,
>>>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>>>> @@ -3529,6 +3531,7 @@ static const struct amdgpu_ring_funcs 
>>>> gfx_v9_0_ring_funcs_kiq = {
>>>>      .align_mask = 0xff,
>>>>      .nop = PACKET3(PACKET3_NOP, 0x3FFF),
>>>>      .support_64bit_ptrs = true,
>>>> +    .vmhub = AMDGPU_GFXHUB,
>>>>      .get_rptr = gfx_v9_0_ring_get_rptr_compute,
>>>>      .get_wptr = gfx_v9_0_ring_get_wptr_compute,
>>>>      .set_wptr = gfx_v9_0_ring_set_wptr_compute,
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>>> index d40eb31..8cbb49d 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>>> @@ -1473,6 +1473,7 @@ static const struct amdgpu_ring_funcs 
>>>> sdma_v4_0_ring_funcs = {
>>>>      .align_mask = 0xf,
>>>>      .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>>>>      .support_64bit_ptrs = true,
>>>> +    .vmhub = AMDGPU_MMHUB,
>>>>      .get_rptr = sdma_v4_0_ring_get_rptr,
>>>>      .get_wptr = sdma_v4_0_ring_get_wptr,
>>>>      .set_wptr = sdma_v4_0_ring_set_wptr,
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>>> index 819148a..fa80465 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>>> @@ -1448,6 +1448,7 @@ static const struct amdgpu_ring_funcs 
>>>> uvd_v7_0_ring_vm_funcs = {
>>>>      .align_mask = 0xf,
>>>>      .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
>>>>      .support_64bit_ptrs = false,
>>>> +    .vmhub = AMDGPU_MMHUB,
>>>>      .get_rptr = uvd_v7_0_ring_get_rptr,
>>>>      .get_wptr = uvd_v7_0_ring_get_wptr,
>>>>      .set_wptr = uvd_v7_0_ring_set_wptr,
>>>> @@ -1475,6 +1476,7 @@ static const struct amdgpu_ring_funcs 
>>>> uvd_v7_0_enc_ring_vm_funcs = {
>>>>      .align_mask = 0x3f,
>>>>      .nop = HEVC_ENC_CMD_NO_OP,
>>>>      .support_64bit_ptrs = false,
>>>> +    .vmhub = AMDGPU_MMHUB,
>>>>      .get_rptr = uvd_v7_0_enc_ring_get_rptr,
>>>>      .get_wptr = uvd_v7_0_enc_ring_get_wptr,
>>>>      .set_wptr = uvd_v7_0_enc_ring_set_wptr,
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
>>>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>>> index 8dde83f..6374133 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>>> @@ -1074,6 +1074,7 @@ static const struct amdgpu_ring_funcs 
>>>> vce_v4_0_ring_vm_funcs = {
>>>>      .align_mask = 0x3f,
>>>>      .nop = VCE_CMD_NO_OP,
>>>>      .support_64bit_ptrs = false,
>>>> +    .vmhub = AMDGPU_MMHUB,
>>>>      .get_rptr = vce_v4_0_ring_get_rptr,
>>>>      .get_wptr = vce_v4_0_ring_get_wptr,
>>>>      .set_wptr = vce_v4_0_ring_set_wptr,
>>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>

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