* [PATCH] drm/amdgpu: set cpg doorbeel for fiji and polaris.
@ 2017-04-11 13:52 Rex Zhu
[not found] ` <1491918734-9496-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Rex Zhu @ 2017-04-11 13:52 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
add set_doorbell functions for mec and cpg.
Change-Id: Ie696798633bc1d511a6526b2113907b70a92b303
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 ++++++++++++++++++-----------------
1 file changed, 43 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 19d466b..a865acf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4465,6 +4465,39 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
return 0;
}
+static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+{
+ u32 tmp;
+ /* no gfx doorbells on iceland */
+ if (adev->asic_type == CHIP_TOPAZ)
+ return;
+
+ tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
+
+ if (ring->use_doorbell) {
+ tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+ DOORBELL_OFFSET, ring->doorbell_index);
+ tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+ DOORBELL_HIT, 0);
+ tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
+ DOORBELL_EN, 1);
+ } else {
+ tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
+ }
+
+ WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
+
+ if (adev->flags & AMD_IS_APU)
+ return;
+
+ tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
+ DOORBELL_RANGE_LOWER,
+ AMDGPU_DOORBELL_GFX_RING0);
+ WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
+
+ WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
+ CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
+}
static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
{
@@ -4512,34 +4545,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
WREG32(mmCP_RB0_BASE, rb_addr);
WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
- /* no gfx doorbells on iceland */
- if (adev->asic_type != CHIP_TOPAZ) {
- tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
- if (ring->use_doorbell) {
- tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- DOORBELL_OFFSET, ring->doorbell_index);
- tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- DOORBELL_HIT, 0);
- tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- DOORBELL_EN, 1);
- } else {
- tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
- DOORBELL_EN, 0);
- }
- WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
-
- if (adev->asic_type == CHIP_TONGA) {
- tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
- DOORBELL_RANGE_LOWER,
- AMDGPU_DOORBELL_GFX_RING0);
- WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
-
- WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
- CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
- }
-
- }
-
+ gfx_v8_0_set_cpg_door_bell(adev, ring);
/* start the ring */
amdgpu_ring_clear_ring(ring);
gfx_v8_0_cp_gfx_start(adev);
@@ -5016,6 +5022,14 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
return 0;
}
+static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
+{
+ if (adev->asic_type > CHIP_TONGA) {
+ WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);
+ WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);
+ }
+}
+
static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = NULL;
@@ -5056,17 +5070,7 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
goto done;
}
- if ((adev->asic_type == CHIP_CARRIZO) ||
- (adev->asic_type == CHIP_FIJI) ||
- (adev->asic_type == CHIP_STONEY) ||
- (adev->asic_type == CHIP_POLARIS10) ||
- (adev->asic_type == CHIP_POLARIS11) ||
- (adev->asic_type == CHIP_POLARIS12)) {
- WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
- AMDGPU_DOORBELL_KIQ << 2);
- WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
- AMDGPU_DOORBELL_MEC_RING7 << 2);
- }
+ gfx_v8_0_set_mec_doorbell_range(adev);
r = gfx_v8_0_kiq_kcq_enable(adev);
if (r)
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu: set cpg doorbeel for fiji and polaris.
[not found] ` <1491918734-9496-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-04-11 14:40 ` Deucher, Alexander
0 siblings, 0 replies; 2+ messages in thread
From: Deucher, Alexander @ 2017-04-11 14:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Tuesday, April 11, 2017 9:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: set cpg doorbeel for fiji and polaris.
Good catch!
Typo in the patch title "doorbeel" with that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> add set_doorbell functions for mec and cpg.
>
> Change-Id: Ie696798633bc1d511a6526b2113907b70a92b303
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 ++++++++++++++++++------
> -----------
> 1 file changed, 43 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 19d466b..a865acf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4465,6 +4465,39 @@ static int gfx_v8_0_cp_gfx_start(struct
> amdgpu_device *adev)
>
> return 0;
> }
> +static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev,
> struct amdgpu_ring *ring)
> +{
> + u32 tmp;
> + /* no gfx doorbells on iceland */
> + if (adev->asic_type == CHIP_TOPAZ)
> + return;
> +
> + tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
> +
> + if (ring->use_doorbell) {
> + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
> + DOORBELL_OFFSET, ring->doorbell_index);
> + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
> + DOORBELL_HIT, 0);
> + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
> + DOORBELL_EN, 1);
> + } else {
> + tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
> DOORBELL_EN, 0);
> + }
> +
> + WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
> +
> + if (adev->flags & AMD_IS_APU)
> + return;
> +
> + tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
> + DOORBELL_RANGE_LOWER,
> + AMDGPU_DOORBELL_GFX_RING0);
> + WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
> +
> + WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
> +
> CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_M
> ASK);
> +}
>
> static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
> {
> @@ -4512,34 +4545,7 @@ static int gfx_v8_0_cp_gfx_resume(struct
> amdgpu_device *adev)
> WREG32(mmCP_RB0_BASE, rb_addr);
> WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
>
> - /* no gfx doorbells on iceland */
> - if (adev->asic_type != CHIP_TOPAZ) {
> - tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
> - if (ring->use_doorbell) {
> - tmp = REG_SET_FIELD(tmp,
> CP_RB_DOORBELL_CONTROL,
> - DOORBELL_OFFSET, ring-
> >doorbell_index);
> - tmp = REG_SET_FIELD(tmp,
> CP_RB_DOORBELL_CONTROL,
> - DOORBELL_HIT, 0);
> - tmp = REG_SET_FIELD(tmp,
> CP_RB_DOORBELL_CONTROL,
> - DOORBELL_EN, 1);
> - } else {
> - tmp = REG_SET_FIELD(tmp,
> CP_RB_DOORBELL_CONTROL,
> - DOORBELL_EN, 0);
> - }
> - WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
> -
> - if (adev->asic_type == CHIP_TONGA) {
> - tmp = REG_SET_FIELD(0,
> CP_RB_DOORBELL_RANGE_LOWER,
> - DOORBELL_RANGE_LOWER,
> -
> AMDGPU_DOORBELL_GFX_RING0);
> - WREG32(mmCP_RB_DOORBELL_RANGE_LOWER,
> tmp);
> -
> - WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
> -
> CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
> - }
> -
> - }
> -
> + gfx_v8_0_set_cpg_door_bell(adev, ring);
> /* start the ring */
> amdgpu_ring_clear_ring(ring);
> gfx_v8_0_cp_gfx_start(adev);
> @@ -5016,6 +5022,14 @@ static int gfx_v8_0_kcq_init_queue(struct
> amdgpu_ring *ring)
> return 0;
> }
>
> +static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device
> *adev)
> +{
> + if (adev->asic_type > CHIP_TONGA) {
> + WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
> AMDGPU_DOORBELL_KIQ << 2);
> + WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
> AMDGPU_DOORBELL_MEC_RING7 << 2);
> + }
> +}
> +
> static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
> {
> struct amdgpu_ring *ring = NULL;
> @@ -5056,17 +5070,7 @@ static int gfx_v8_0_kiq_resume(struct
> amdgpu_device *adev)
> goto done;
> }
>
> - if ((adev->asic_type == CHIP_CARRIZO) ||
> - (adev->asic_type == CHIP_FIJI) ||
> - (adev->asic_type == CHIP_STONEY) ||
> - (adev->asic_type == CHIP_POLARIS10) ||
> - (adev->asic_type == CHIP_POLARIS11) ||
> - (adev->asic_type == CHIP_POLARIS12)) {
> - WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
> - AMDGPU_DOORBELL_KIQ << 2);
> - WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
> - AMDGPU_DOORBELL_MEC_RING7 << 2);
> - }
> + gfx_v8_0_set_mec_doorbell_range(adev);
>
> r = gfx_v8_0_kiq_kcq_enable(adev);
> if (r)
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2017-04-11 14:40 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-11 13:52 [PATCH] drm/amdgpu: set cpg doorbeel for fiji and polaris Rex Zhu
[not found] ` <1491918734-9496-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-04-11 14:40 ` Deucher, Alexander
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.