[U-Boot] [PATCH v3 0/7] rockchip: spl: rk3399: prepare to have SPI config per-board

[U-Boot] [PATCH v3 0/7] rockchip: spl: rk3399: prepare to have SPI config per-board

[Philipp Tomsich]

To support SPI flashes (via the device model) and enable loading of
later-stage images from SPI in SPL, we need a few adjustments to the
common configuration header for the RK3399:
 - enable SPL_SPI_LOAD if SPI is enabled for SPL (in rk3399_common)
 - move CONFIG_SPI and CONFIG_SPI_FLASH (from rk3399_common) to defconfig

Changes in v3:
- replaced macro-pasting with a lookup table to improve readability
  (as requested by Simon)
- increase the module input clock from 99MHz to 198MHz for the RK3399
  (added in version 3)
- change the top bitrate permissible (without generating a -EINVAL)
  from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for
  a 99MHz module input clock)

Changes in v2:
- fixes a wrong macro usage, which caused the SPI module input clock
  frequency to be significantly higher than intended
- frequencies have now been validated using an oscilloscope (keep in mind
  that all frequencies are derived from a 99MHz module input clock) at the
  following measurement points (assuming the other fix for the usage of
  DIV_RATE from the series):
    *  1 MHz ...  0.99 MHz
    *  5 MHz ...  4.95 MHz
    * 10 MHz ...  9.9  MHz
    * 30 MHz ... 33    MHz
    * 50 MHz ... 49.5  MHz
- fixes an off-by-one for the RK3399 that cause the SPI module input
  clock to be misstated as 84MHz (even though it was running at 99MHz)

Jakob Unterwurzacher (1):
  rockchip: spi: enable support for the rk_spi driver for the RK3399

Philipp Tomsich (6):
  rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
  rockchip: clk: rk3399: fix off-by one during rate calculation in
    i2c/spi_set_rate
  rockchip: spi: rk_spi: select 198MHz input to the SPI module for the
    RK3399
  rockchip: spi: rk_spi: improve clocking code for the RK3399
  rockchip: pinctrl: rk3399: add support for the SPI5 controller
  rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for
    SPL

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h |  12 +++
 arch/arm/include/asm/arch-rockchip/periph.h     |   3 +
 drivers/clk/rockchip/clk_rk3399.c               | 115 ++++++++++++++++++++++--
 drivers/pinctrl/rockchip/pinctrl_rk3399.c       |  17 ++++
 drivers/spi/rk_spi.c                            |  17 +++-
 drivers/spi/rk_spi.h                            |   7 ++
 include/configs/rk3399_common.h                 |   3 +
 7 files changed, 163 insertions(+), 11 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH v3 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

[Philipp Tomsich]

This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>

Cover-Letter:
rockchip: spi: rk3399: add SPI support for the RK3399

This series adds SPI support for the RK3399 (SPI1 and SPI5). This
consists of the following individual changes:
- clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2,
  SPI 4 and SPI5)
- pinctrl for SPI1 and SPI5
- changes the SPI module input clock to 198MHz (instead of 99MHz) for
  the RK3399 to improve the available bitrates at higher frequencies
  (e.g. adding the 39MBit and 28MBit operating points)
- modifies the calculation of the top frequency permissible (as the
  49.5MBit operating point had not been permissible due to a hard
  limit at 48MBit)
END

---

Changes in v3:
- replaced macro-pasting with a lookup table to improve readability
  (as requested by Simon)

Changes in v2:
- fixes a wrong macro usage, which caused the SPI module input clock
  frequency to be significantly higher than intended
- frequencies have now been validated using an oscilloscope (keep in mind
  that all frequencies are derived from a 99MHz module input clock) at the
  following measurement points (assuming the other fix for the usage of
  DIV_RATE from the series):
    *  1 MHz ...  0.99 MHz
    *  5 MHz ...  4.95 MHz
    * 10 MHz ...  9.9  MHz
    * 30 MHz ... 33    MHz
    * 50 MHz ... 49.5  MHz

 drivers/clk/rockchip/clk_rk3399.c | 114 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 108 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index f778ddf..fab36fa 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1,5 +1,6 @@
 /*
  * (C) Copyright 2015 Google, Inc
+ * (C) 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:	GPL-2.0
  */
@@ -207,12 +208,15 @@ enum {
 	DCLK_VOP_DIV_CON_SHIFT          = 0,
 
 	/* CLKSEL_CON58 */
-	CLK_SPI_PLL_SEL_MASK		= 1,
-	CLK_SPI_PLL_SEL_CPLL		= 0,
-	CLK_SPI_PLL_SEL_GPLL		= 1,
-	CLK_SPI_PLL_DIV_CON_MASK	= 0x7f,
-	CLK_SPI5_PLL_DIV_CON_SHIFT	= 8,
-	CLK_SPI5_PLL_SEL_SHIFT		= 15,
+	CLK_SPI_PLL_SEL_WIDTH = 1,
+	CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
+	CLK_SPI_PLL_SEL_CPLL = 0,
+	CLK_SPI_PLL_SEL_GPLL = 1,
+	CLK_SPI_PLL_DIV_CON_WIDTH = 7,
+	CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
+
+	CLK_SPI5_PLL_DIV_CON_SHIFT      = 8,
+	CLK_SPI5_PLL_SEL_SHIFT	        = 15,
 
 	/* CLKSEL_CON59 */
 	CLK_SPI1_PLL_SEL_SHIFT		= 15,
@@ -605,6 +609,96 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 }
 
+/*
+ * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+	uint8_t reg;  /* CLKSEL_CON[reg] register in CRU */
+	uint8_t div_shift;
+	uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ *
+ * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
+ * logic is not supported).
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+	[0] = { .reg = 59,
+		.div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
+		.sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
+	[1] = { .reg = 59,
+		.div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
+		.sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
+	[2] = { .reg = 60,
+		.div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
+		.sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
+	[3] = { .reg = 60,
+		.div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
+		.sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
+	[4] = { .reg = 58,
+		.div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
+		.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+	return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
+{
+	const struct spi_clkreg *spiclk = NULL;
+	u32 div, val;
+
+	switch (clk_id) {
+	case SCLK_SPI0 ... SCLK_SPI5:
+		spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+		break;
+
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	val = readl(&cru->clksel_con[spiclk->reg]);
+	div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
+
+	return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
+{
+	const struct spi_clkreg *spiclk = NULL;
+	int src_clk_div;
+
+	src_clk_div = GPLL_HZ / hz;
+	assert((src_clk_div - 1) < 127);
+
+	switch (clk_id) {
+	case SCLK_SPI1 ... SCLK_SPI5:
+		spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+		break;
+
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[spiclk->reg],
+		     ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
+		       (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
+		     ((src_clk_div << spiclk->div_shift) |
+		      (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
+
+
+	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
+}
+
 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
 {
 	struct pll_div vpll_config = {0};
@@ -780,6 +874,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 	case SCLK_I2C7:
 		rate = rk3399_i2c_get_clk(priv->cru, clk->id);
 		break;
+	case SCLK_SPI1:
+	case SCLK_SPI5:
+		rate = rk3399_spi_get_clk(priv->cru, clk->id);
+		break;
 	case SCLK_UART0:
 	case SCLK_UART2:
 		return 24000000;
@@ -818,6 +916,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_I2C7:
 		ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
 		break;
+	case SCLK_SPI1:
+	case SCLK_SPI5:
+		ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
+		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
 		ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
-- 
1.9.1

[U-Boot] [PATCH v3 2/7] rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate

[Philipp Tomsich]

For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
  1. calculates 'src_div := src_freq / target_freq'
  2. stores 'src_div - 1' into the register (the actual divider applied
     in hardware is biased by adding 1)
  3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
     expects the (decremented) divider from the hardware-register and
     implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')

This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.

To fix, we have two options:
 * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
   make for a particularily nice read
 * we simply call the i2c/spi_get_rate function (introducing additional
   overhead for the additional register-read), which reads the divider
   from the register and then passes it through the DIV_RATE macro

Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>

---

Changes in v3: None
Changes in v2:
- fixes an off-by-one for the RK3399 that cause the SPI module input
  clock to be misstated as 84MHz (even though it was running at 99MHz)

 drivers/clk/rockchip/clk_rk3399.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index fab36fa..5c2d898 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -606,7 +606,7 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 		return -EINVAL;
 	}
 
-	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
+	return rk3399_i2c_get_clk(cru, clk_id);
 }
 
 /*
@@ -695,8 +695,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
 		     ((src_clk_div << spiclk->div_shift) |
 		      (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
 
-
-	return DIV_TO_RATE(GPLL_HZ, src_clk_div);
+	return rk3399_spi_get_clk(cru, clk_id);
 }
 
 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
-- 
1.9.1

[U-Boot] [PATCH v3 3/7] rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399

[Philipp Tomsich]

To provide more (runtime) configuration points for the SPI data rate
at higher speeds (e.g. above 9MHz), we increase the module input rate
to 198MHz (from 99MHz) for the RK3399.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v3:
- increase the module input clock from 99MHz to 198MHz for the RK3399
  (added in version 3)

Changes in v2: None

 drivers/spi/rk_spi.c | 7 ++++---
 drivers/spi/rk_spi.h | 7 +++++++
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 3e44f17..63cceef 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -208,10 +208,11 @@ static int rockchip_spi_probe(struct udevice *bus)
 	priv->max_freq = plat->frequency;
 
 	/*
-	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
-	 * is the assumed speed for CLK_GENERAL.
+	 * Use 99 MHz (198MHz on the RK3399) as our clock since it
+	 * divides nicely into 594 MHz which is the assumed speed for
+	 * CLK_GENERAL.
 	 */
-	ret = clk_set_rate(&priv->clk, 99000000);
+	ret = clk_set_rate(&priv->clk, ROCKCHIP_SPI_MOD_CLK);
 	if (ret < 0) {
 		debug("%s: Failed to set clock: %d\n", __func__, ret);
 		return ret;
diff --git a/drivers/spi/rk_spi.h b/drivers/spi/rk_spi.h
index f1ac812..ea262ed 100644
--- a/drivers/spi/rk_spi.h
+++ b/drivers/spi/rk_spi.h
@@ -119,6 +119,13 @@ enum {
 };
 
 #define ROCKCHIP_SPI_TIMEOUT_MS		1000
+
+#if defined(CONFIG_ROCKCHIP_RK3399)
+#define ROCKCHIP_SPI_MOD_CLK            198000000
+#define ROCKCHIP_SPI_MAX_RATE		50000000
+#else
+#define ROCKCHIP_SPI_MOD_CLK            99000000
 #define ROCKCHIP_SPI_MAX_RATE		48000000
+#endif
 
 #endif /* __RK_SPI_H */
-- 
1.9.1

[U-Boot] [PATCH v3 4/7] rockchip: spi: rk_spi: improve clocking code for the RK3399

[Philipp Tomsich]

The original code for the clock clamping did not support going up to
half the module input frequency (even when clocking the module at
99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate.

This rewrites the check to allow frequencies of up to half the SPI
module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v3:
- change the top bitrate permissible (without generating a -EINVAL)
  from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for
  a 99MHz module input clock)

Changes in v2: None

 drivers/spi/rk_spi.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 63cceef..d518f9d 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -372,10 +372,17 @@ static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
 {
 	struct rockchip_spi_priv *priv = dev_get_priv(bus);
 
-	if (speed > ROCKCHIP_SPI_MAX_RATE)
+	/*
+	 * The minimum divider configurable is 2, so we can't exceed
+	 * half the input frequency for the SPI module.
+	 */
+	if (speed > (priv->input_rate / 2))
 		return -EINVAL;
+
+	/* Clamp to the maximum frequency specified in the DTS */
 	if (speed > priv->max_freq)
 		speed = priv->max_freq;
+
 	priv->speed_hz = speed;
 
 	return 0;
-- 
1.9.1

[U-Boot] [PATCH v3 5/7] rockchip: pinctrl: rk3399: add support for the SPI5 controller

[Philipp Tomsich]

This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
 * grf_rk3399.h: adds definition for configuring the SPI5 pins
   		 in the GPIO2C group
 * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
 * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
   		     PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
		     through SPI5 to the appropriate pin-config
		     function; implements the pin-configuration
		     for PERIPH_ID_SPI5 using the GPIO2C group

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++
 arch/arm/include/asm/arch-rockchip/periph.h     |  3 +++
 drivers/pinctrl/rockchip/pinctrl_rk3399.c       | 17 +++++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index c424753..cbcff2e 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -344,6 +344,18 @@ enum {
 	GRF_GPIO2C1_SEL_SHIFT   = 2,
 	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
 	GRF_UART0BT_SOUT        = 1,
+	GRF_GPIO2C4_SEL_SHIFT   = 8,
+	GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_RXD     = 2,
+	GRF_GPIO2C5_SEL_SHIFT   = 10,
+	GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_TXD     = 2,
+	GRF_GPIO2C6_SEL_SHIFT   = 12,
+	GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CLK     = 2,
+	GRF_GPIO2C7_SEL_SHIFT   = 14,
+	GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CSN0    = 2,
 
 	/* GRF_GPIO3A_IOMUX */
 	GRF_GPIO3A0_SEL_SHIFT   = 0,
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
index 239a274..8018d47 100644
--- a/arch/arm/include/asm/arch-rockchip/periph.h
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -27,6 +27,9 @@ enum periph_id {
 	PERIPH_ID_SPI0,
 	PERIPH_ID_SPI1,
 	PERIPH_ID_SPI2,
+	PERIPH_ID_SPI3,
+	PERIPH_ID_SPI4,
+	PERIPH_ID_SPI5,
 	PERIPH_ID_UART0,
 	PERIPH_ID_UART1,
 	PERIPH_ID_UART2,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index 507bec4..6eb657f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
 			     | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 			     | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 		break;
+	case PERIPH_ID_SPI5:
+		if (cs != 0)
+			goto err;
+		rk_clrsetreg(&grf->gpio2c_iomux,
+			     GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
+			     | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
+			     GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
+			     | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
+		break;
 	default:
+		printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
 		goto err;
 	}
 
@@ -259,6 +271,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 	case PERIPH_ID_SPI2:
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+	case PERIPH_ID_SPI5:
 		pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 		break;
 	case PERIPH_ID_UART0:
@@ -307,6 +322,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_SPI1;
 	case 52:
 		return PERIPH_ID_SPI2;
+	case 132:
+		return PERIPH_ID_SPI5;
 	case 57:
 		return PERIPH_ID_I2C0;
 	case 59: /* Note strange order */
-- 
1.9.1

[U-Boot] [PATCH v3 6/7] rockchip: spi: enable support for the rk_spi driver for the RK3399

[Philipp Tomsich]

From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>

The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
---

Changes in v3: None
Changes in v2: None

 drivers/spi/rk_spi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index d518f9d..35c29b2 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -411,6 +411,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
 
 static const struct udevice_id rockchip_spi_ids[] = {
 	{ .compatible = "rockchip,rk3288-spi" },
+	{ .compatible = "rockchip,rk3399-spi" },
 	{ }
 };
 
-- 
1.9.1

[U-Boot] [PATCH v3 7/7] rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL

[Philipp Tomsich]

To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v3: None
Changes in v2: None

 include/configs/rk3399_common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 9d22e0c..c409d95 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -18,6 +18,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+#define CONFIG_SPL_SPI_LOAD
+#endif
 
 #define COUNTER_FREQUENCY               24000000
 
-- 
1.9.1

[U-Boot] [PATCH v3 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> This change adds support for configuring the module clocks for SPI1 and
> SPI5 from the 594MHz GPLL.
>
> Note that the driver (rk_spi.c) always sets this to 99MHz, but the
> implemented functionality is more general and will also support
> different clock configurations.
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <
jakob.unterwurzacher@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
>
> Cover-Letter:

Odd that this came through - is it the capital L?

> rockchip: spi: rk3399: add SPI support for the RK3399
>
> This series adds SPI support for the RK3399 (SPI1 and SPI5). This
> consists of the following individual changes:
> - clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2,
> SPI 4 and SPI5)
> - pinctrl for SPI1 and SPI5
> - changes the SPI module input clock to 198MHz (instead of 99MHz) for
> the RK3399 to improve the available bitrates at higher frequencies
> (e.g. adding the 39MBit and 28MBit operating points)
> - modifies the calculation of the top frequency permissible (as the
> 49.5MBit operating point had not been permissible due to a hard
> limit at 48MBit)
> END
>
> ---
>
> Changes in v3:
> - replaced macro-pasting with a lookup table to improve readability
> (as requested by Simon)
>
> Changes in v2:
> - fixes a wrong macro usage, which caused the SPI module input clock
> frequency to be significantly higher than intended
> - frequencies have now been validated using an oscilloscope (keep in mind
> that all frequencies are derived from a 99MHz module input clock) at the
> following measurement points (assuming the other fix for the usage of
> DIV_RATE from the series):
> * 1 MHz ... 0.99 MHz
> * 5 MHz ... 4.95 MHz
> * 10 MHz ... 9.9 MHz
> * 30 MHz ... 33 MHz
> * 50 MHz ... 49.5 MHz
>
> drivers/clk/rockchip/clk_rk3399.c | 114
++++++++++++++++++++++++++++++++++++--
> 1 file changed, 108 insertions(+), 6 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 2/7] rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
> which had been mindlessly following the template of the i2c_set_rate
> implementation) miscalculates the rate returned due to a off-by-one
> error resulting from the following sequence of events:
> 1. calculates 'src_div := src_freq / target_freq'
> 2. stores 'src_div - 1' into the register (the actual divider applied
> in hardware is biased by adding 1)
> 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
> expects the (decremented) divider from the hardware-register and
> implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')
>
> This can be observed with the SPI driver, which sets a rate of 99MHz
> based on the GPLL frequency of 594MHz: the hardware generates a clock
> of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
> but reports a frequency of 84MHz (594 / 7) on return.
>
> To fix, we have two options:
> * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
> make for a particularily nice read
> * we simply call the i2c/spi_get_rate function (introducing additional
> overhead for the additional register-read), which reads the divider
> from the register and then passes it through the DIV_RATE macro
>
> Given that this code is not time-critical, the more readable solution
> (i.e. calling the appropriate get_rate function) is implemented in this
> change.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
>
> ---
>
> Changes in v3: None
> Changes in v2:
> - fixes an off-by-one for the RK3399 that cause the SPI module input
> clock to be misstated as 84MHz (even though it was running at 99MHz)
>
> drivers/clk/rockchip/clk_rk3399.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 3/7] rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399

[Simon Glass]

Hi Philipp,

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> To provide more (runtime) configuration points for the SPI data rate
> at higher speeds (e.g. above 9MHz), we increase the module input rate
> to 198MHz (from 99MHz) for the RK3399.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - increase the module input clock from 99MHz to 198MHz for the RK3399
> (added in version 3)
>
> Changes in v2: None
>
> drivers/spi/rk_spi.c | 7 ++++---
> drivers/spi/rk_spi.h | 7 +++++++
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
> index 3e44f17..63cceef 100644
> --- a/drivers/spi/rk_spi.c
> +++ b/drivers/spi/rk_spi.c
> @@ -208,10 +208,11 @@ static int rockchip_spi_probe(struct udevice *bus)
> priv->max_freq = plat->frequency;
>
> /*
> - * Use 99 MHz as our clock since it divides nicely into 594 MHz which
> - * is the assumed speed for CLK_GENERAL.
> + * Use 99 MHz (198MHz on the RK3399) as our clock since it
> + * divides nicely into 594 MHz which is the assumed speed for
> + * CLK_GENERAL.
> */
> - ret = clk_set_rate(&priv->clk, 99000000);
> + ret = clk_set_rate(&priv->clk, ROCKCHIP_SPI_MOD_CLK);
> if (ret < 0) {
> debug("%s: Failed to set clock: %d\n", __func__, ret);
> return ret;
> diff --git a/drivers/spi/rk_spi.h b/drivers/spi/rk_spi.h
> index f1ac812..ea262ed 100644
> --- a/drivers/spi/rk_spi.h
> +++ b/drivers/spi/rk_spi.h
> @@ -119,6 +119,13 @@ enum {
> };
>
> #define ROCKCHIP_SPI_TIMEOUT_MS 1000
> +
> +#if defined(CONFIG_ROCKCHIP_RK3399)
> +#define ROCKCHIP_SPI_MOD_CLK 198000000
> +#define ROCKCHIP_SPI_MAX_RATE 50000000
> +#else
> +#define ROCKCHIP_SPI_MOD_CLK 99000000
> #define ROCKCHIP_SPI_MAX_RATE 48000000
> +#endif

I'd like to avoid board- or soc-specific code in drivers. Is this setting
available in the device tree node? If not, perhaps use the root node
compatible string?

>
> #endif /* __RK_SPI_H */
> --
> 1.9.1
>

Regards,
Simon

[U-Boot] [PATCH v3 4/7] rockchip: spi: rk_spi: improve clocking code for the RK3399

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> The original code for the clock clamping did not support going up to
> half the module input frequency (even when clocking the module at
> 99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate.
>
> This rewrites the check to allow frequencies of up to half the SPI
> module rate as bitrates and then clamps to whatever the DTS allows
> as a maximum (board-specific) frequency.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - change the top bitrate permissible (without generating a -EINVAL)
> from 48MHz/MBit to half the input clockrate (i.e. 49.5MHz/MBit for
> a 99MHz module input clock)
>
> Changes in v2: None
>
> drivers/spi/rk_spi.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 6/7] rockchip: spi: enable support for the rk_spi driver for the RK3399

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> From: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
>
> The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
> block found in the RK3399. This has been confirmed both with SPI NOR
> flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
>
> This change adds the 'rockchip,rk3399-spi' string to its compatible
> list to allow reuse of the existing driver.
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <
jakob.unterwurzacher@theobroma-systems.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/spi/rk_spi.c | 1 +
> 1 file changed, 1 insertion(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 7/7] rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> To include the ability to load from an SPI flash in SPL, it's not
> sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
> Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
> is already enabled for SPL via Kconfig.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> include/configs/rk3399_common.h | 3 +++
> 1 file changed, 3 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 5/7] rockchip: pinctrl: rk3399: add support for the SPI5 controller

[Simon Glass]

On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.tomsich@theobroma-systems.com> wrote:
> This commit adds support for the pin-configuration of the SPI5
> controller of the RK3399 through the following changes:
> * grf_rk3399.h: adds definition for configuring the SPI5 pins
> in the GPIO2C group
> * periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
> * pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
> PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
> through SPI5 to the appropriate pin-config
> function; implements the pin-configuration
> for PERIPH_ID_SPI5 using the GPIO2C group
>
> X-AffectedPlatforms: RK3399-Q7
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Jakob Unterwurzacher <
jakob.unterwurzacher@theobroma-systems.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 12 ++++++++++++
> arch/arm/include/asm/arch-rockchip/periph.h | 3 +++
> drivers/pinctrl/rockchip/pinctrl_rk3399.c | 17 +++++++++++++++++
> 3 files changed, 32 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v3 1/7] rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5

[Simon Glass]

On 17 April 2017 at 21:59, Simon Glass <sjg@chromium.org> wrote:
> On 17 April 2017 at 09:43, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> This change adds support for configuring the module clocks for SPI1 and
>> SPI5 from the 594MHz GPLL.
>>
>> Note that the driver (rk_spi.c) always sets this to 99MHz, but the
>> implemented functionality is more general and will also support
>> different clock configurations.
>>
>> X-AffectedPlatforms: RK3399-Q7
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> Tested-by: Jakob Unterwurzacher
>> <jakob.unterwurzacher@theobroma-systems.com>
>> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
>>
>> Cover-Letter:
>
> Odd that this came through - is it the capital L?
>
>
>> rockchip: spi: rk3399: add SPI support for the RK3399
>>
>> This series adds SPI support for the RK3399 (SPI1 and SPI5). This
>> consists of the following individual changes:
>> - clock support for the SPI blocks clocked from GRF (i.e. SPI1, SPI2,
>> SPI 4 and SPI5)
>> - pinctrl for SPI1 and SPI5
>> - changes the SPI module input clock to 198MHz (instead of 99MHz) for
>> the RK3399 to improve the available bitrates at higher frequencies
>> (e.g. adding the 39MBit and 28MBit operating points)
>> - modifies the calculation of the top frequency permissible (as the
>> 49.5MBit operating point had not been permissible due to a hard
>> limit at 48MBit)
>> END
>>
>> ---
>>
>> Changes in v3:
>> - replaced macro-pasting with a lookup table to improve readability
>> (as requested by Simon)
>>
>> Changes in v2:
>> - fixes a wrong macro usage, which caused the SPI module input clock
>> frequency to be significantly higher than intended
>> - frequencies have now been validated using an oscilloscope (keep in mind
>> that all frequencies are derived from a 99MHz module input clock) at the
>> following measurement points (assuming the other fix for the usage of
>> DIV_RATE from the series):
>> * 1 MHz ... 0.99 MHz
>> * 5 MHz ... 4.95 MHz
>> * 10 MHz ... 9.9 MHz
>> * 30 MHz ... 33 MHz
>> * 50 MHz ... 49.5 MHz
>>
>> drivers/clk/rockchip/clk_rk3399.c | 114
>> ++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 108 insertions(+), 6 deletions(-)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!