* [PATCH] clk: renesas: r8a7796: Add EHCI/OHCI clocks
@ 2017-04-19 17:46 Yoshihiro Kaneko
2017-04-20 18:29 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Yoshihiro Kaneko @ 2017-04-19 17:46 UTC (permalink / raw)
To: linux-clk
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Simon Horman, Magnus Damm, linux-renesas-soc
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the clk-next branch of linux-clk tree.
drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 1d8c5c2..c6c5026 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -165,6 +165,8 @@ enum clk_ids {
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
--
1.9.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: renesas: r8a7796: Add EHCI/OHCI clocks
2017-04-19 17:46 [PATCH] clk: renesas: r8a7796: Add EHCI/OHCI clocks Yoshihiro Kaneko
@ 2017-04-20 18:29 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2017-04-20 18:29 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-clk, Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Simon Horman, Magnus Damm, Linux-Renesas
Hi Kaneko-san,
On Wed, Apr 19, 2017 at 7:46 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
>
> This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.
>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> ---
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
I.e. will queue in clk-renesas-for-v4.13.
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -165,6 +165,8 @@ enum clk_ids {
> DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
> DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
> + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
> + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
I cannot confirm the parent clock, though.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2017-04-19 17:46 [PATCH] clk: renesas: r8a7796: Add EHCI/OHCI clocks Yoshihiro Kaneko
2017-04-20 18:29 ` Geert Uytterhoeven
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