* [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers
@ 2017-04-25 16:53 Geert Uytterhoeven
[not found] ` <1493139200-27396-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
` (9 more replies)
0 siblings, 10 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Hi all,
Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2 and
clk-mstp drivers, which depend on most clocks being described in DT.
Especially the module (MSTP) clocks are cumbersome and error prone,
due to 3 arrays (clocks, clock-indices, and clock-output-names) to be
kept in sync. In addition, the clk-mstp driver cannot be extended easily
to also support module resets, which are provided by the same hardware
module.
Hence when developing support for R-Car Gen3 SoCs, another approach was
chosen, which led to the CPG/MSSR driver core, and SoC-specific
subdrivers (initially for R-Car Gen3, but later also for RZ/G1).
This series introduces new clock drivers for all supported R-Car Gen2
SoCs, using the CPG/MSSR driver core, and the support for RZ/G1. They
provide all clocks supported by the old driver, plus a few more.
The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.
This series does not include the corresponding DTS updates. These will
be posted as a separate series later.
This series depends on "[PATCH/RFC 0/2] clk / soc: renesas: Rework
Kconfig and Makefile logic", which I posted before.
For testing, this patch series, incl. all dependencies and the DTS
updates, are available in the topic/rcar2-cpg-mssr branch of my
renesas-drivers git repository at
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
This has been tested on r8a7790/lager, r8a7791/koelsch, r8a7792/blanche,
r8a7793/gose, and r8a7794/alt. /sys/kernel/debug/clk/clk_summary has
been compared before and after the conversion.
I hope to queue this up in clk-renesas-for-v4.13.
Thanks!
Geert Uytterhoeven (10):
clk: renesas: cpg-mssr: Document R-Car Gen2 support
clk: renesas: Add r8a7790 CPG Core Clock Definitions
clk: renesas: Add r8a7791 CPG Core Clock Definitions
clk: renesas: Add r8a7792 CPG Core Clock Definitions
clk: renesas: Add r8a7793 CPG Core Clock Definitions
clk: renesas: Add r8a7794 CPG Core Clock Definitions
clk: renesas: r8a7790: Add new CPG/MSSR driver
clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driver
clk: renesas: r8a7792: Add new CPG/MSSR driver
clk: renesas: r8a7794: Add new CPG/MSSR driver
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 +-
drivers/clk/renesas/Kconfig | 22 +-
drivers/clk/renesas/Makefile | 4 +
drivers/clk/renesas/r8a7790-cpg-mssr.c | 278 ++++++++++++++++++++
drivers/clk/renesas/r8a7791-cpg-mssr.c | 286 +++++++++++++++++++++
drivers/clk/renesas/r8a7792-cpg-mssr.c | 221 ++++++++++++++++
drivers/clk/renesas/r8a7794-cpg-mssr.c | 255 ++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 29 +++
drivers/clk/renesas/renesas-cpg-mssr.h | 4 +
include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++
include/dt-bindings/clock/r8a7791-cpg-mssr.h | 48 ++++
include/dt-bindings/clock/r8a7792-cpg-mssr.h | 43 ++++
include/dt-bindings/clock/r8a7793-cpg-mssr.h | 48 ++++
include/dt-bindings/clock/r8a7794-cpg-mssr.h | 47 ++++
14 files changed, 1341 insertions(+), 6 deletions(-)
create mode 100644 drivers/clk/renesas/r8a7790-cpg-mssr.c
create mode 100644 drivers/clk/renesas/r8a7791-cpg-mssr.c
create mode 100644 drivers/clk/renesas/r8a7792-cpg-mssr.c
create mode 100644 drivers/clk/renesas/r8a7794-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h
create mode 100644 include/dt-bindings/clock/r8a7791-cpg-mssr.h
create mode 100644 include/dt-bindings/clock/r8a7792-cpg-mssr.h
create mode 100644 include/dt-bindings/clock/r8a7793-cpg-mssr.h
create mode 100644 include/dt-bindings/clock/r8a7794-cpg-mssr.h
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions Geert Uytterhoeven
` (8 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven,
Rob Herring, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
Document use of the Renesas Clock Pulse Generator / Module Standby and
Software Reset DT Bindings for various member of the R-Car Gen2 family
(H2, M2-W, V2H, M2-N, and E2).
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index f4f944d813081857..0cd894f987a38e81 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,11 @@ Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+ - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
+ - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
+ - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
+ - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
+ - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
@@ -24,9 +29,10 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
+ - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+ r8a7795, r8a7796)
- "extalr" (r8a7795, r8a7796)
- - "usb_extal" (r8a7743, r8a7745)
+ - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support
@ 2017-04-25 16:53 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven, Rob Herring,
Mark Rutland, devicetree
Document use of the Renesas Clock Pulse Generator / Module Standby and
Software Reset DT Bindings for various member of the R-Car Gen2 family
(H2, M2-W, V2H, M2-N, and E2).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index f4f944d813081857..0cd894f987a38e81 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -15,6 +15,11 @@ Required Properties:
- compatible: Must be one of:
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
+ - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
+ - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
+ - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
+ - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
+ - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
@@ -24,9 +29,10 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7745, r8a7795, r8a7796)
+ - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
+ r8a7795, r8a7796)
- "extalr" (r8a7795, r8a7796)
- - "usb_extal" (r8a7743, r8a7745)
+ - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
[not found] ` <1493139200-27396-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-28 12:38 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 03/10] clk: renesas: Add r8a7791 " Geert Uytterhoeven
` (7 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644
index 0000000000000000..1625b8bf34822b6e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z 0
+#define R8A7790_CLK_Z2 1
+#define R8A7790_CLK_ZG 2
+#define R8A7790_CLK_ZTR 3
+#define R8A7790_CLK_ZTRD2 4
+#define R8A7790_CLK_ZT 5
+#define R8A7790_CLK_ZX 6
+#define R8A7790_CLK_ZS 7
+#define R8A7790_CLK_HP 8
+#define R8A7790_CLK_I 9
+#define R8A7790_CLK_B 10
+#define R8A7790_CLK_LB 11
+#define R8A7790_CLK_P 12
+#define R8A7790_CLK_CL 13
+#define R8A7790_CLK_M2 14
+#define R8A7790_CLK_ADSP 15
+#define R8A7790_CLK_IMP 16
+#define R8A7790_CLK_ZB3 17
+#define R8A7790_CLK_ZB3D2 18
+#define R8A7790_CLK_DDR 19
+#define R8A7790_CLK_SDH 20
+#define R8A7790_CLK_SD0 21
+#define R8A7790_CLK_SD1 22
+#define R8A7790_CLK_SD2 23
+#define R8A7790_CLK_SD3 24
+#define R8A7790_CLK_MMC0 25
+#define R8A7790_CLK_MMC1 26
+#define R8A7790_CLK_MP 27
+#define R8A7790_CLK_SSP 28
+#define R8A7790_CLK_SSPRS 29
+#define R8A7790_CLK_QSPI 30
+#define R8A7790_CLK_CP 31
+#define R8A7790_CLK_RCAN 32
+#define R8A7790_CLK_R 33
+#define R8A7790_CLK_OSC 34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 03/10] clk: renesas: Add r8a7791 CPG Core Clock Definitions
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
[not found] ` <1493139200-27396-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2017-04-25 16:53 ` [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-28 12:42 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 04/10] clk: renesas: Add r8a7792 " Geert Uytterhoeven
` (6 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/clock/r8a7791-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7791-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
new file mode 100644
index 0000000000000000..e8823410c01c5a09
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7791 CPG Core Clocks */
+#define R8A7791_CLK_Z 0
+#define R8A7791_CLK_ZG 1
+#define R8A7791_CLK_ZTR 2
+#define R8A7791_CLK_ZTRD2 3
+#define R8A7791_CLK_ZT 4
+#define R8A7791_CLK_ZX 5
+#define R8A7791_CLK_ZS 6
+#define R8A7791_CLK_HP 7
+#define R8A7791_CLK_I 8
+#define R8A7791_CLK_B 9
+#define R8A7791_CLK_LB 10
+#define R8A7791_CLK_P 11
+#define R8A7791_CLK_CL 12
+#define R8A7791_CLK_M2 13
+#define R8A7791_CLK_ADSP 14
+#define R8A7791_CLK_ZB3 15
+#define R8A7791_CLK_ZB3D2 16
+#define R8A7791_CLK_DDR 17
+#define R8A7791_CLK_SDH 18
+#define R8A7791_CLK_SD0 19
+#define R8A7791_CLK_SD2 20
+#define R8A7791_CLK_SD3 21
+#define R8A7791_CLK_MMC0 22
+#define R8A7791_CLK_MP 23
+#define R8A7791_CLK_SSP 24
+#define R8A7791_CLK_SSPRS 25
+#define R8A7791_CLK_QSPI 26
+#define R8A7791_CLK_CP 27
+#define R8A7791_CLK_RCAN 28
+#define R8A7791_CLK_R 29
+#define R8A7791_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 04/10] clk: renesas: Add r8a7792 CPG Core Clock Definitions
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (2 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 03/10] clk: renesas: Add r8a7791 " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-28 12:44 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 05/10] clk: renesas: Add r8a7793 " Geert Uytterhoeven
` (5 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/clock/r8a7792-cpg-mssr.h | 43 ++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7792-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
new file mode 100644
index 0000000000000000..72ce85cb2f94b0ab
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7792 CPG Core Clocks */
+#define R8A7792_CLK_Z 0
+#define R8A7792_CLK_ZG 1
+#define R8A7792_CLK_ZTR 2
+#define R8A7792_CLK_ZTRD2 3
+#define R8A7792_CLK_ZT 4
+#define R8A7792_CLK_ZX 5
+#define R8A7792_CLK_ZS 6
+#define R8A7792_CLK_HP 7
+#define R8A7792_CLK_I 8
+#define R8A7792_CLK_B 9
+#define R8A7792_CLK_LB 10
+#define R8A7792_CLK_P 11
+#define R8A7792_CLK_CL 12
+#define R8A7792_CLK_M2 13
+#define R8A7792_CLK_IMP 14
+#define R8A7792_CLK_ZB3 15
+#define R8A7792_CLK_ZB3D2 16
+#define R8A7792_CLK_DDR 17
+#define R8A7792_CLK_SD 18
+#define R8A7792_CLK_MP 19
+#define R8A7792_CLK_QSPI 20
+#define R8A7792_CLK_CP 21
+#define R8A7792_CLK_CPEX 22
+#define R8A7792_CLK_RCAN 23
+#define R8A7792_CLK_R 24
+#define R8A7792_CLK_OSC 25
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 05/10] clk: renesas: Add r8a7793 CPG Core Clock Definitions
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (3 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 04/10] clk: renesas: Add r8a7792 " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-28 12:46 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 06/10] clk: renesas: Add r8a7794 " Geert Uytterhoeven
` (4 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed
in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
Hardware User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/clock/r8a7793-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7793-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
new file mode 100644
index 0000000000000000..8809b0f62d615457
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7793 CPG Core Clocks */
+#define R8A7793_CLK_Z 0
+#define R8A7793_CLK_ZG 1
+#define R8A7793_CLK_ZTR 2
+#define R8A7793_CLK_ZTRD2 3
+#define R8A7793_CLK_ZT 4
+#define R8A7793_CLK_ZX 5
+#define R8A7793_CLK_ZS 6
+#define R8A7793_CLK_HP 7
+#define R8A7793_CLK_I 8
+#define R8A7793_CLK_B 9
+#define R8A7793_CLK_LB 10
+#define R8A7793_CLK_P 11
+#define R8A7793_CLK_CL 12
+#define R8A7793_CLK_M2 13
+#define R8A7793_CLK_ADSP 14
+#define R8A7793_CLK_ZB3 15
+#define R8A7793_CLK_ZB3D2 16
+#define R8A7793_CLK_DDR 17
+#define R8A7793_CLK_SDH 18
+#define R8A7793_CLK_SD0 19
+#define R8A7793_CLK_SD2 20
+#define R8A7793_CLK_SD3 21
+#define R8A7793_CLK_MMC0 22
+#define R8A7793_CLK_MP 23
+#define R8A7793_CLK_SSP 24
+#define R8A7793_CLK_SSPRS 25
+#define R8A7793_CLK_QSPI 26
+#define R8A7793_CLK_CP 27
+#define R8A7793_CLK_RCAN 28
+#define R8A7793_CLK_R 29
+#define R8A7793_CLK_OSC 30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 06/10] clk: renesas: Add r8a7794 CPG Core Clock Definitions
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (4 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 05/10] clk: renesas: Add r8a7793 " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-28 12:49 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 07/10] clk: renesas: r8a7790: Add new CPG/MSSR driver Geert Uytterhoeven
` (3 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware
User's Manual rev. 2.00.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/clock/r8a7794-cpg-mssr.h | 47 ++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a7794-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
new file mode 100644
index 0000000000000000..9d720311ae3a229a
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2 0
+#define R8A7794_CLK_ZG 1
+#define R8A7794_CLK_ZTR 2
+#define R8A7794_CLK_ZTRD2 3
+#define R8A7794_CLK_ZT 4
+#define R8A7794_CLK_ZX 5
+#define R8A7794_CLK_ZS 6
+#define R8A7794_CLK_HP 7
+#define R8A7794_CLK_I 8
+#define R8A7794_CLK_B 9
+#define R8A7794_CLK_LB 10
+#define R8A7794_CLK_P 11
+#define R8A7794_CLK_CL 12
+#define R8A7794_CLK_CP 13
+#define R8A7794_CLK_M2 14
+#define R8A7794_CLK_ADSP 15
+#define R8A7794_CLK_ZB3 16
+#define R8A7794_CLK_ZB3D2 17
+#define R8A7794_CLK_DDR 18
+#define R8A7794_CLK_SDH 19
+#define R8A7794_CLK_SD0 20
+#define R8A7794_CLK_SD2 21
+#define R8A7794_CLK_SD3 22
+#define R8A7794_CLK_MMC0 23
+#define R8A7794_CLK_MP 24
+#define R8A7794_CLK_QSPI 25
+#define R8A7794_CLK_CPEX 26
+#define R8A7794_CLK_RCAN 27
+#define R8A7794_CLK_R 28
+#define R8A7794_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 07/10] clk: renesas: r8a7790: Add new CPG/MSSR driver
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (5 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 06/10] clk: renesas: Add r8a7794 " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 08/10] clk: renesas: r8a7791/r8a7793: " Geert Uytterhoeven
` (2 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.
The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 13 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7790-cpg-mssr.c | 278 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 298 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r8a7790-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ec17edc6c4ab2e2a..a9f9800d08a2cdc9 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -19,6 +19,16 @@ config CLK_RENESAS
if CLK_RENESAS
+config CLK_RENESAS_LEGACY
+ bool "Legacy DT clock support"
+ depends on CLK_R8A7790
+ default y
+ help
+ Enable backward compatibility with old device trees describing a
+ hierarchical representation of the various CPG and MSTP clocks.
+
+ Say Y if you want your kernel to work with old DTBs.
+
# SoC
config CLK_EMEV2
bool "Emma Mobile EV2 clock support" if COMPILE_TEST
@@ -55,7 +65,8 @@ config CLK_R8A7779
config CLK_R8A7790
bool "R-Car H2 clock support" if COMPILE_TEST
- select CLK_RCAR_GEN2
+ select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
+ select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7791
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index aa24c2f5078ca333..f0c622aadc6745bf 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
+obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
new file mode 100644
index 0000000000000000..46bb55bb223de0b6
--- /dev/null
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -0,0 +1,278 @@
+/*
+ * r8a7790 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7790_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z", R8A7790_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
+ DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
+ DEF_BASE("qspi", R8A7790_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7790_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
+ DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
+ DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
+ DEF_FIXED("zb3", R8A7790_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7790_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7790_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7790_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7790_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7790_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7790_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7790_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+ DEF_DIV6P1("mmc1", R8A7790_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
+ DEF_DIV6P1("ssp", R8A7790_CLK_SSP, CLK_PLL1_DIV2, 0x248),
+ DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
+};
+
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
+ DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
+ DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
+ DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7790_CLK_M2),
+ DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7790_CLK_P),
+ DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-2", 117, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-1", 118, R8A7790_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7790_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7790_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7790_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7790_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7790_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7790_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7790_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
+ DEF_MOD("msiof3", 215, R8A7790_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7790_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7790_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7790_CLK_ZS),
+ DEF_MOD("iic2", 300, R8A7790_CLK_HP),
+ DEF_MOD("tpu0", 304, R8A7790_CLK_CP),
+ DEF_MOD("mmcif1", 305, R8A7790_CLK_MMC1),
+ DEF_MOD("scif2", 310, R8A7790_CLK_P),
+ DEF_MOD("sdhi3", 311, R8A7790_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7790_CLK_SD2),
+ DEF_MOD("sdhi1", 313, R8A7790_CLK_SD1),
+ DEF_MOD("sdhi0", 314, R8A7790_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7790_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7790_CLK_HP),
+ DEF_MOD("pciec", 319, R8A7790_CLK_MP),
+ DEF_MOD("iic1", 323, R8A7790_CLK_HP),
+ DEF_MOD("usb3.0", 328, R8A7790_CLK_MP),
+ DEF_MOD("cmt1", 329, R8A7790_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7790_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
+ DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
+ DEF_MOD("audio-dmac0", 502, R8A7790_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7790_CLK_ADSP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7790_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7790_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7790_CLK_HP),
+ DEF_MOD("hscif1", 716, R8A7790_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7790_CLK_ZS),
+ DEF_MOD("scif1", 720, R8A7790_CLK_P),
+ DEF_MOD("scif0", 721, R8A7790_CLK_P),
+ DEF_MOD("du2", 722, R8A7790_CLK_ZX),
+ DEF_MOD("du1", 723, R8A7790_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7790_CLK_ZX),
+ DEF_MOD("lvds1", 725, R8A7790_CLK_ZX),
+ DEF_MOD("lvds0", 726, R8A7790_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7790_CLK_HP),
+ DEF_MOD("vin3", 808, R8A7790_CLK_ZG),
+ DEF_MOD("vin2", 809, R8A7790_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7790_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7790_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7790_CLK_HP),
+ DEF_MOD("ether", 813, R8A7790_CLK_P),
+ DEF_MOD("sata1", 814, R8A7790_CLK_ZS),
+ DEF_MOD("sata0", 815, R8A7790_CLK_ZS),
+ DEF_MOD("gyro-adc", 901, R8A7790_CLK_P),
+ DEF_MOD("gpio5", 907, R8A7790_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7790_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7790_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7790_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7790_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7790_CLK_CP),
+ DEF_MOD("can1", 915, R8A7790_CLK_P),
+ DEF_MOD("can0", 916, R8A7790_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7790_CLK_QSPI),
+ DEF_MOD("iicdvfs", 926, R8A7790_CLK_CP),
+ DEF_MOD("i2c3", 928, R8A7790_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7790_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7790_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7790_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7790_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7790_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+};
+
+static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *1
+ *---------------------------------------------------
+ * 0 0 0 15 x172/2 x208/2 x106
+ * 0 0 1 15 x172/2 x208/2 x88
+ * 0 1 0 20 x130/2 x156/2 x80
+ * 0 1 1 20 x130/2 x156/2 x66
+ * 1 0 0 26 / 2 x200/2 x240/2 x122
+ * 1 0 1 26 / 2 x200/2 x240/2 x102
+ * 1 1 0 30 / 2 x172/2 x208/2 x106
+ * 1 1 1 30 / 2 x172/2 x208/2 x88
+ *
+ * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
+ { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+};
+
+static int __init r8a7790_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a7790_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7790_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7790_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7790_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7790_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7790_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7790_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7790_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 4b281a8d06edf1d3..36a09cf68b2de93c 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -639,6 +639,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7745_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A7790
+ {
+ .compatible = "renesas,r8a7790-cpg-mssr",
+ .data = &r8a7790_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 148f4f0aa2a487b0..38fcb25c876ea3b5 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -132,6 +132,7 @@ struct cpg_mssr_info {
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 08/10] clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driver
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (6 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 07/10] clk: renesas: r8a7790: Add new CPG/MSSR driver Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 09/10] clk: renesas: r8a7792: " Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 10/10] clk: renesas: r8a7794: " Geert Uytterhoeven
9 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and
Software Reset driver, using the CPG/MSSR driver core.
The small difference between R-Car M2-N and M2-W is handled by patching
the clock tables at runtime.
The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 5 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7791-cpg-mssr.c | 286 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 11 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 302 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/renesas/r8a7791-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a9f9800d08a2cdc9..d12248c80d67ee28 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,7 +21,7 @@ if CLK_RENESAS
config CLK_RENESAS_LEGACY
bool "Legacy DT clock support"
- depends on CLK_R8A7790
+ depends on CLK_R8A7790 || CLK_R8A7791
default y
help
Enable backward compatibility with old device trees describing a
@@ -71,7 +71,8 @@ config CLK_R8A7790
config CLK_R8A7791
bool "R-Car M2-W/N clock support" if COMPILE_TEST
- select CLK_RCAR_GEN2
+ select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
+ select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7792
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f0c622aadc6745bf..7f70a2a1c514e91f 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
new file mode 100644
index 0000000000000000..c0b51f9bb2789350
--- /dev/null
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -0,0 +1,286 @@
+/*
+ * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2015-2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
+ DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
+ DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+ DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
+ DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
+};
+
+static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
+ DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7791_CLK_M2),
+ DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
+ DEF_MOD("tmu1", 111, R8A7791_CLK_P),
+ DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
+ DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7791_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7791_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7791_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7791_CLK_HP),
+ DEF_MOD("pciec", 319, R8A7791_CLK_MP),
+ DEF_MOD("iic1", 323, R8A7791_CLK_HP),
+ DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
+ DEF_MOD("cmt1", 329, R8A7791_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7791_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
+ DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
+ DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7791_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
+ DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
+ DEF_MOD("scif5", 714, R8A7791_CLK_P),
+ DEF_MOD("scif4", 715, R8A7791_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7791_CLK_P),
+ DEF_MOD("scif2", 719, R8A7791_CLK_P),
+ DEF_MOD("scif1", 720, R8A7791_CLK_P),
+ DEF_MOD("scif0", 721, R8A7791_CLK_P),
+ DEF_MOD("du1", 723, R8A7791_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7791_CLK_ZX),
+ DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
+ DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7791_CLK_HP),
+ DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
+ DEF_MOD("ether", 813, R8A7791_CLK_P),
+ DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
+ DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
+ DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
+ DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
+ DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
+ DEF_MOD("can1", 915, R8A7791_CLK_P),
+ DEF_MOD("can0", 916, R8A7791_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
+ DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
+ DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
+};
+
+static const unsigned int r8a7791_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *1
+ *---------------------------------------------------
+ * 0 0 0 15 x172/2 x208/2 x106
+ * 0 0 1 15 x172/2 x208/2 x88
+ * 0 1 0 20 x130/2 x156/2 x80
+ * 0 1 1 20 x130/2 x156/2 x66
+ * 1 0 0 26 / 2 x200/2 x240/2 x122
+ * 1 0 1 26 / 2 x200/2 x240/2 x102
+ * 1 1 0 30 / 2 x172/2 x208/2 x106
+ * 1 1 1 30 / 2 x172/2 x208/2 x88
+ *
+ * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
+ { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
+};
+
+static int __init r8a7791_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ struct device_node *np = dev->of_node;
+ unsigned int i;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ if (of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr")) {
+ /* R-Car M2-N uses a 1/5 divider for ZG */
+ for (i = 0; i < ARRAY_SIZE(r8a7791_core_clks); i++)
+ if (r8a7791_core_clks[i].id == R8A7791_CLK_ZG) {
+ r8a7791_core_clks[i].div = 5;
+ break;
+ }
+ }
+ return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a7791_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7791_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7791_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7791_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7791_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7791_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7791_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7791_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 36a09cf68b2de93c..04ac51dcf48203ac 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -645,6 +645,17 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7790_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A7791
+ {
+ .compatible = "renesas,r8a7791-cpg-mssr",
+ .data = &r8a7791_cpg_mssr_info,
+ },
+ /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
+ {
+ .compatible = "renesas,r8a7793-cpg-mssr",
+ .data = &r8a7791_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 38fcb25c876ea3b5..c93f36c471a32841 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -133,6 +133,7 @@ struct cpg_mssr_info {
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 09/10] clk: renesas: r8a7792: Add new CPG/MSSR driver
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (7 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 08/10] clk: renesas: r8a7791/r8a7793: " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 10/10] clk: renesas: r8a7794: " Geert Uytterhoeven
9 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.
The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 5 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7792-cpg-mssr.c | 221 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 232 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/renesas/r8a7792-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d12248c80d67ee28..4b9ce278a4e9ddc5 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,7 +21,7 @@ if CLK_RENESAS
config CLK_RENESAS_LEGACY
bool "Legacy DT clock support"
- depends on CLK_R8A7790 || CLK_R8A7791
+ depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792
default y
help
Enable backward compatibility with old device trees describing a
@@ -77,7 +77,8 @@ config CLK_R8A7791
config CLK_R8A7792
bool "R-Car V2H clock support" if COMPILE_TEST
- select CLK_RCAR_GEN2
+ select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
+ select CLK_RCAR_GEN2_CPG
config CLK_R8A7794
bool "R-Car E2 clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 7f70a2a1c514e91f..f14a4e5d629bfc85 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
new file mode 100644
index 0000000000000000..a832b9b6f7b0dde8
--- /dev/null
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -0,0 +1,221 @@
+/*
+ * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+
+ DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
+ DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
+ DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
+ DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
+ DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
+ DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
+ DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
+ DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
+};
+
+static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
+ DEF_MOD("jpu", 106, R8A7792_CLK_M2),
+ DEF_MOD("tmu1", 111, R8A7792_CLK_P),
+ DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7792_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7792_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7792_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
+ DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
+ DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
+ DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
+ DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
+ DEF_MOD("cmt1", 329, R8A7792_CLK_R),
+ DEF_MOD("irqc", 407, R8A7792_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
+ DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
+ DEF_MOD("thermal", 522, CLK_EXTAL),
+ DEF_MOD("pwm", 523, R8A7792_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7792_CLK_P),
+ DEF_MOD("scif2", 719, R8A7792_CLK_P),
+ DEF_MOD("scif1", 720, R8A7792_CLK_P),
+ DEF_MOD("scif0", 721, R8A7792_CLK_P),
+ DEF_MOD("du1", 723, R8A7792_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7792_CLK_ZX),
+ DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
+ DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
+ DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
+ DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
+ DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
+ DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
+ DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
+ DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
+ DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
+ DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
+ DEF_MOD("can1", 915, R8A7792_CLK_P),
+ DEF_MOD("can0", 916, R8A7792_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
+ DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
+ DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
+ DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
+ DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
+ DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+};
+
+static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+ * 0 0 0 15 x200/3 x208/2 x106
+ * 0 0 1 15 x200/3 x208/2 x88
+ * 0 1 0 20 x150/3 x156/2 x80
+ * 0 1 1 20 x150/3 x156/2 x66
+ * 1 0 0 26 / 2 x230/3 x240/2 x122
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+ * 1 1 0 30 / 2 x200/3 x208/2 x106
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
+ (((md) & BIT(13)) >> 12) | \
+ (((md) & BIT(19)) >> 19))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+ { 1, 208, 106, 200 },
+ { 1, 208, 88, 200 },
+ { 1, 156, 80, 150 },
+ { 1, 156, 66, 150 },
+ { 2, 240, 122, 230 },
+ { 2, 240, 102, 230 },
+ { 2, 208, 106, 200 },
+ { 2, 208, 88, 200 },
+};
+
+static int __init r8a7792_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a7792_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7792_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7792_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7792_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7792_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7792_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7792_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7792_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 04ac51dcf48203ac..27b4ca8c7b90bec3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -656,6 +656,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7791_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A7792
+ {
+ .compatible = "renesas,r8a7792-cpg-mssr",
+ .data = &r8a7792_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index c93f36c471a32841..07d53fa3e867fa7b 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -134,6 +134,7 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 10/10] clk: renesas: r8a7794: Add new CPG/MSSR driver
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
` (8 preceding siblings ...)
2017-04-25 16:53 ` [PATCH 09/10] clk: renesas: r8a7792: " Geert Uytterhoeven
@ 2017-04-25 16:53 ` Geert Uytterhoeven
9 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-25 16:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.
The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 5 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a7794-cpg-mssr.c | 255 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 266 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/renesas/r8a7794-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 4b9ce278a4e9ddc5..2dd9efac3a996a32 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,7 +21,7 @@ if CLK_RENESAS
config CLK_RENESAS_LEGACY
bool "Legacy DT clock support"
- depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792
+ depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
default y
help
Enable backward compatibility with old device trees describing a
@@ -82,7 +82,8 @@ config CLK_R8A7792
config CLK_R8A7794
bool "R-Car E2 clock support" if COMPILE_TEST
- select CLK_RCAR_GEN2
+ select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
+ select CLK_RCAR_GEN2_CPG
select CLK_RENESAS_DIV6
config CLK_R8A7795
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f14a4e5d629bfc85..02d04124371f717a 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
new file mode 100644
index 0000000000000000..ec091a42da54d8c8
--- /dev/null
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -0,0 +1,255 @@
+/*
+ * r8a7794 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2017 Glider bvba
+ *
+ * Based on clk-rcar-gen2.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen2-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_USB_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("usb_extal", CLK_USB_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+
+ /* Core Clock Outputs */
+ DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
+ DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
+ DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
+ DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
+ DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
+ DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
+
+ DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
+ DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
+ DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
+ DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
+ DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
+ DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
+ DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
+ DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
+ DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
+ DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
+ DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
+ DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
+ DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
+ DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
+ DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
+ DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
+
+ DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
+ DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
+ DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
+};
+
+static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+ DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
+ DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
+ DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
+ DEF_MOD("jpu", 106, R8A7794_CLK_M2),
+ DEF_MOD("tmu1", 111, R8A7794_CLK_P),
+ DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
+ DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
+ DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
+ DEF_MOD("tmu3", 121, R8A7794_CLK_P),
+ DEF_MOD("tmu2", 122, R8A7794_CLK_P),
+ DEF_MOD("cmt0", 124, R8A7794_CLK_R),
+ DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
+ DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
+ DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
+ DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
+ DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
+ DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
+ DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
+ DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
+ DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
+ DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
+ DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
+ DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
+ DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
+ DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
+ DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
+ DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
+ DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
+ DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
+ DEF_MOD("iic0", 318, R8A7794_CLK_HP),
+ DEF_MOD("iic1", 323, R8A7794_CLK_HP),
+ DEF_MOD("cmt1", 329, R8A7794_CLK_R),
+ DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
+ DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
+ DEF_MOD("irqc", 407, R8A7794_CLK_CP),
+ DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
+ DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
+ DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
+ DEF_MOD("pwm", 523, R8A7794_CLK_P),
+ DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
+ DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
+ DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
+ DEF_MOD("scif5", 714, R8A7794_CLK_P),
+ DEF_MOD("scif4", 715, R8A7794_CLK_P),
+ DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
+ DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
+ DEF_MOD("scif3", 718, R8A7794_CLK_P),
+ DEF_MOD("scif2", 719, R8A7794_CLK_P),
+ DEF_MOD("scif1", 720, R8A7794_CLK_P),
+ DEF_MOD("scif0", 721, R8A7794_CLK_P),
+ DEF_MOD("du1", 723, R8A7794_CLK_ZX),
+ DEF_MOD("du0", 724, R8A7794_CLK_ZX),
+ DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
+ DEF_MOD("mlb", 802, R8A7794_CLK_HP),
+ DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
+ DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
+ DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
+ DEF_MOD("ether", 813, R8A7794_CLK_P),
+ DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
+ DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
+ DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
+ DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
+ DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
+ DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
+ DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
+ DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
+ DEF_MOD("can1", 915, R8A7794_CLK_P),
+ DEF_MOD("can0", 916, R8A7794_CLK_P),
+ DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
+ DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
+ DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
+ DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
+ DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
+ DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
+ DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
+ DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
+ DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
+ DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
+ DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
+ DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
+ DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
+ DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
+ DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
+ DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
+};
+
+static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
+ MOD_CLK_ID(408), /* INTC-SYS (GIC) */
+};
+
+/*
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL3
+ * 14 13 19 (MHz) *1 *2
+ *---------------------------------------------------
+ * 0 0 1 15 x200/3 x208/2 x88
+ * 0 1 1 20 x150/3 x156/2 x66
+ * 1 0 1 26 / 2 x230/3 x240/2 x102
+ * 1 1 1 30 / 2 x200/3 x208/2 x88
+ *
+ * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
+ * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+ { 1, 208, 88, 200 },
+ { 1, 156, 66, 150 },
+ { 2, 240, 102, 230 },
+ { 2, 208, 88, 200 },
+};
+
+static int __init r8a7794_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+ return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a7794_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a7794_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a7794_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a7794_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a7794_mod_clks),
+ .num_hw_mod_clks = 12 * 32,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r8a7794_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r8a7794_crit_mod_clks),
+
+ /* Callbacks */
+ .init = r8a7794_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen2_cpg_clk_register,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 27b4ca8c7b90bec3..2c833025648081c3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -662,6 +662,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a7792_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A7794
+ {
+ .compatible = "renesas,r8a7794-cpg-mssr",
+ .data = &r8a7794_cpg_mssr_info,
+ },
+#endif
#ifdef CONFIG_CLK_R8A7795
{
.compatible = "renesas,r8a7795-cpg-mssr",
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 07d53fa3e867fa7b..43d7c7f6832df0b2 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -135,6 +135,7 @@ extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
--
2.7.4
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions
2017-04-25 16:53 ` [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions Geert Uytterhoeven
@ 2017-04-28 12:38 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:38 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..1625b8bf34822b6e
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7790 CPG Core Clocks */
> +#define R8A7790_CLK_Z 0
> +#define R8A7790_CLK_Z2 1
> +#define R8A7790_CLK_ZG 2
> +#define R8A7790_CLK_ZTR 3
> +#define R8A7790_CLK_ZTRD2 4
> +#define R8A7790_CLK_ZT 5
> +#define R8A7790_CLK_ZX 6
> +#define R8A7790_CLK_ZS 7
> +#define R8A7790_CLK_HP 8
> +#define R8A7790_CLK_I 9
> +#define R8A7790_CLK_B 10
> +#define R8A7790_CLK_LB 11
> +#define R8A7790_CLK_P 12
> +#define R8A7790_CLK_CL 13
> +#define R8A7790_CLK_M2 14
> +#define R8A7790_CLK_ADSP 15
> +#define R8A7790_CLK_IMP 16
> +#define R8A7790_CLK_ZB3 17
> +#define R8A7790_CLK_ZB3D2 18
> +#define R8A7790_CLK_DDR 19
> +#define R8A7790_CLK_SDH 20
> +#define R8A7790_CLK_SD0 21
> +#define R8A7790_CLK_SD1 22
> +#define R8A7790_CLK_SD2 23
> +#define R8A7790_CLK_SD3 24
> +#define R8A7790_CLK_MMC0 25
> +#define R8A7790_CLK_MMC1 26
> +#define R8A7790_CLK_MP 27
> +#define R8A7790_CLK_SSP 28
> +#define R8A7790_CLK_SSPRS 29
> +#define R8A7790_CLK_QSPI 30
> +#define R8A7790_CLK_CP 31
> +#define R8A7790_CLK_RCAN 32
> +#define R8A7790_CLK_R 33
> +#define R8A7790_CLK_OSC 34
The last two are called RCLR and OSCCLK in the Table 7.2a ("List of
Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions
@ 2017-04-28 12:38 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:38 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7790-cpg-mssr.h | 52 ++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7790-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..1625b8bf34822b6e
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7790 CPG Core Clocks */
> +#define R8A7790_CLK_Z 0
> +#define R8A7790_CLK_Z2 1
> +#define R8A7790_CLK_ZG 2
> +#define R8A7790_CLK_ZTR 3
> +#define R8A7790_CLK_ZTRD2 4
> +#define R8A7790_CLK_ZT 5
> +#define R8A7790_CLK_ZX 6
> +#define R8A7790_CLK_ZS 7
> +#define R8A7790_CLK_HP 8
> +#define R8A7790_CLK_I 9
> +#define R8A7790_CLK_B 10
> +#define R8A7790_CLK_LB 11
> +#define R8A7790_CLK_P 12
> +#define R8A7790_CLK_CL 13
> +#define R8A7790_CLK_M2 14
> +#define R8A7790_CLK_ADSP 15
> +#define R8A7790_CLK_IMP 16
> +#define R8A7790_CLK_ZB3 17
> +#define R8A7790_CLK_ZB3D2 18
> +#define R8A7790_CLK_DDR 19
> +#define R8A7790_CLK_SDH 20
> +#define R8A7790_CLK_SD0 21
> +#define R8A7790_CLK_SD1 22
> +#define R8A7790_CLK_SD2 23
> +#define R8A7790_CLK_SD3 24
> +#define R8A7790_CLK_MMC0 25
> +#define R8A7790_CLK_MMC1 26
> +#define R8A7790_CLK_MP 27
> +#define R8A7790_CLK_SSP 28
> +#define R8A7790_CLK_SSPRS 29
> +#define R8A7790_CLK_QSPI 30
> +#define R8A7790_CLK_CP 31
> +#define R8A7790_CLK_RCAN 32
> +#define R8A7790_CLK_R 33
> +#define R8A7790_CLK_OSC 34
The last two are called RCLR and OSCCLK in the Table 7.2a ("List of
Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 03/10] clk: renesas: Add r8a7791 CPG Core Clock Definitions
2017-04-25 16:53 ` [PATCH 03/10] clk: renesas: Add r8a7791 " Geert Uytterhoeven
@ 2017-04-28 12:42 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:13 +0200, Geert Uytterhoeven wrote:
> Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
> in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
> Hardware User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7791-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7791-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..e8823410c01c5a09
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7791 CPG Core Clocks */
> +#define R8A7791_CLK_Z 0
> +#define R8A7791_CLK_ZG 1
> +#define R8A7791_CLK_ZTR 2
> +#define R8A7791_CLK_ZTRD2 3
> +#define R8A7791_CLK_ZT 4
> +#define R8A7791_CLK_ZX 5
> +#define R8A7791_CLK_ZS 6
> +#define R8A7791_CLK_HP 7
> +#define R8A7791_CLK_I 8
> +#define R8A7791_CLK_B 9
> +#define R8A7791_CLK_LB 10
> +#define R8A7791_CLK_P 11
> +#define R8A7791_CLK_CL 12
> +#define R8A7791_CLK_M2 13
> +#define R8A7791_CLK_ADSP 14
> +#define R8A7791_CLK_ZB3 15
> +#define R8A7791_CLK_ZB3D2 16
> +#define R8A7791_CLK_DDR 17
> +#define R8A7791_CLK_SDH 18
> +#define R8A7791_CLK_SD0 19
> +#define R8A7791_CLK_SD2 20
> +#define R8A7791_CLK_SD3 21
> +#define R8A7791_CLK_MMC0 22
> +#define R8A7791_CLK_MP 23
> +#define R8A7791_CLK_SSP 24
> +#define R8A7791_CLK_SSPRS 25
> +#define R8A7791_CLK_QSPI 26
> +#define R8A7791_CLK_CP 27
> +#define R8A7791_CLK_RCAN 28
> +#define R8A7791_CLK_R 29
> +#define R8A7791_CLK_OSC 30
The last two are called RCLR and OSCCLK in the Table 7.2b ("List of
Clocks [R-Car M2-W/M2-N]"). I'm sure this is intentional on your side,
and if so:
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 03/10] clk: renesas: Add r8a7791 CPG Core Clock Definitions
@ 2017-04-28 12:42 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:13 +0200, Geert Uytterhoeven wrote:
> Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed
> in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
> Hardware User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7791-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7791-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..e8823410c01c5a09
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7791 CPG Core Clocks */
> +#define R8A7791_CLK_Z 0
> +#define R8A7791_CLK_ZG 1
> +#define R8A7791_CLK_ZTR 2
> +#define R8A7791_CLK_ZTRD2 3
> +#define R8A7791_CLK_ZT 4
> +#define R8A7791_CLK_ZX 5
> +#define R8A7791_CLK_ZS 6
> +#define R8A7791_CLK_HP 7
> +#define R8A7791_CLK_I 8
> +#define R8A7791_CLK_B 9
> +#define R8A7791_CLK_LB 10
> +#define R8A7791_CLK_P 11
> +#define R8A7791_CLK_CL 12
> +#define R8A7791_CLK_M2 13
> +#define R8A7791_CLK_ADSP 14
> +#define R8A7791_CLK_ZB3 15
> +#define R8A7791_CLK_ZB3D2 16
> +#define R8A7791_CLK_DDR 17
> +#define R8A7791_CLK_SDH 18
> +#define R8A7791_CLK_SD0 19
> +#define R8A7791_CLK_SD2 20
> +#define R8A7791_CLK_SD3 21
> +#define R8A7791_CLK_MMC0 22
> +#define R8A7791_CLK_MP 23
> +#define R8A7791_CLK_SSP 24
> +#define R8A7791_CLK_SSPRS 25
> +#define R8A7791_CLK_QSPI 26
> +#define R8A7791_CLK_CP 27
> +#define R8A7791_CLK_RCAN 28
> +#define R8A7791_CLK_R 29
> +#define R8A7791_CLK_OSC 30
The last two are called RCLR and OSCCLK in the Table 7.2b ("List of
Clocks [R-Car M2-W/M2-N]"). I'm sure this is intentional on your side,
and if so:
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 04/10] clk: renesas: Add r8a7792 CPG Core Clock Definitions
2017-04-25 16:53 ` [PATCH 04/10] clk: renesas: Add r8a7792 " Geert Uytterhoeven
@ 2017-04-28 12:44 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:44 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:14 +0200, Geert Uytterhoeven wrote:
> Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7792-cpg-mssr.h | 43 ++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7792-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..72ce85cb2f94b0ab
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7792 CPG Core Clocks */
> +#define R8A7792_CLK_Z 0
> +#define R8A7792_CLK_ZG 1
> +#define R8A7792_CLK_ZTR 2
> +#define R8A7792_CLK_ZTRD2 3
> +#define R8A7792_CLK_ZT 4
> +#define R8A7792_CLK_ZX 5
> +#define R8A7792_CLK_ZS 6
> +#define R8A7792_CLK_HP 7
> +#define R8A7792_CLK_I 8
> +#define R8A7792_CLK_B 9
> +#define R8A7792_CLK_LB 10
> +#define R8A7792_CLK_P 11
> +#define R8A7792_CLK_CL 12
> +#define R8A7792_CLK_M2 13
> +#define R8A7792_CLK_IMP 14
> +#define R8A7792_CLK_ZB3 15
> +#define R8A7792_CLK_ZB3D2 16
> +#define R8A7792_CLK_DDR 17
> +#define R8A7792_CLK_SD 18
> +#define R8A7792_CLK_MP 19
> +#define R8A7792_CLK_QSPI 20
> +#define R8A7792_CLK_CP 21
> +#define R8A7792_CLK_CPEX 22
> +#define R8A7792_CLK_RCAN 23
> +#define R8A7792_CLK_R 24
> +#define R8A7792_CLK_OSC 25
The last two are called RCLK and OSCCLK in the Table 7.2c ("List of
Clocks [R-Car V2H]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 04/10] clk: renesas: Add r8a7792 CPG Core Clock Definitions
@ 2017-04-28 12:44 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:44 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:14 +0200, Geert Uytterhoeven wrote:
> Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7792-cpg-mssr.h | 43 ++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7792-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..72ce85cb2f94b0ab
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7792 CPG Core Clocks */
> +#define R8A7792_CLK_Z 0
> +#define R8A7792_CLK_ZG 1
> +#define R8A7792_CLK_ZTR 2
> +#define R8A7792_CLK_ZTRD2 3
> +#define R8A7792_CLK_ZT 4
> +#define R8A7792_CLK_ZX 5
> +#define R8A7792_CLK_ZS 6
> +#define R8A7792_CLK_HP 7
> +#define R8A7792_CLK_I 8
> +#define R8A7792_CLK_B 9
> +#define R8A7792_CLK_LB 10
> +#define R8A7792_CLK_P 11
> +#define R8A7792_CLK_CL 12
> +#define R8A7792_CLK_M2 13
> +#define R8A7792_CLK_IMP 14
> +#define R8A7792_CLK_ZB3 15
> +#define R8A7792_CLK_ZB3D2 16
> +#define R8A7792_CLK_DDR 17
> +#define R8A7792_CLK_SD 18
> +#define R8A7792_CLK_MP 19
> +#define R8A7792_CLK_QSPI 20
> +#define R8A7792_CLK_CP 21
> +#define R8A7792_CLK_CPEX 22
> +#define R8A7792_CLK_RCAN 23
> +#define R8A7792_CLK_R 24
> +#define R8A7792_CLK_OSC 25
The last two are called RCLK and OSCCLK in the Table 7.2c ("List of
Clocks [R-Car V2H]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions
2017-04-28 12:38 ` Niklas Söderlund
@ 2017-04-28 12:45 ` Geert Uytterhoeven
-1 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-28 12:45 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas
Hi Niklas,
On Fri, Apr 28, 2017 at 2:38 PM, Niklas Söderlund
<niklas.soderlund@ragnatech.se> wrote:
>
> On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
>> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
>> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
>> User's Manual rev. 2.00.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
>> +#define R8A7790_CLK_R 33
>> +#define R8A7790_CLK_OSC 34
>
> The last two are called RCLR and OSCCLK in the Table 7.2a ("List of
> Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if
> so:
It's a bit silly to have two clocks with "clk" in their name, while
all others don't.
We did the same on R-Car Gen3.
> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions
@ 2017-04-28 12:45 ` Geert Uytterhoeven
0 siblings, 0 replies; 26+ messages in thread
From: Geert Uytterhoeven @ 2017-04-28 12:45 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas
Hi Niklas,
On Fri, Apr 28, 2017 at 2:38 PM, Niklas S=C3=B6derlund
<niklas.soderlund@ragnatech.se> wrote:
>
> On 2017-04-25 18:53:12 +0200, Geert Uytterhoeven wrote:
>> Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in
>> Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware
>> User's Manual rev. 2.00.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
>> +#define R8A7790_CLK_R 33
>> +#define R8A7790_CLK_OSC 34
>
> The last two are called RCLR and OSCCLK in the Table 7.2a ("List of
> Clocks [R-Car H2]"). I'm sure this is intentional on your side, and if
> so:
It's a bit silly to have two clocks with "clk" in their name, while
all others don't.
We did the same on R-Car Gen3.
> Reviewed-by: Niklas S=C3=B6derlund <niklas.soderlund+renesas@ragnatech.se=
>
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k=
.org
In personal conversations with technical people, I call myself a hacker. Bu=
t
when I'm talking to journalists I just say "programmer" or something like t=
hat.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 05/10] clk: renesas: Add r8a7793 CPG Core Clock Definitions
2017-04-25 16:53 ` [PATCH 05/10] clk: renesas: Add r8a7793 " Geert Uytterhoeven
@ 2017-04-28 12:46 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:15 +0200, Geert Uytterhoeven wrote:
> Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed
> in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
> Hardware User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7793-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7793-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..8809b0f62d615457
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7793 CPG Core Clocks */
> +#define R8A7793_CLK_Z 0
> +#define R8A7793_CLK_ZG 1
> +#define R8A7793_CLK_ZTR 2
> +#define R8A7793_CLK_ZTRD2 3
> +#define R8A7793_CLK_ZT 4
> +#define R8A7793_CLK_ZX 5
> +#define R8A7793_CLK_ZS 6
> +#define R8A7793_CLK_HP 7
> +#define R8A7793_CLK_I 8
> +#define R8A7793_CLK_B 9
> +#define R8A7793_CLK_LB 10
> +#define R8A7793_CLK_P 11
> +#define R8A7793_CLK_CL 12
> +#define R8A7793_CLK_M2 13
> +#define R8A7793_CLK_ADSP 14
> +#define R8A7793_CLK_ZB3 15
> +#define R8A7793_CLK_ZB3D2 16
> +#define R8A7793_CLK_DDR 17
> +#define R8A7793_CLK_SDH 18
> +#define R8A7793_CLK_SD0 19
> +#define R8A7793_CLK_SD2 20
> +#define R8A7793_CLK_SD3 21
> +#define R8A7793_CLK_MMC0 22
> +#define R8A7793_CLK_MP 23
> +#define R8A7793_CLK_SSP 24
> +#define R8A7793_CLK_SSPRS 25
> +#define R8A7793_CLK_QSPI 26
> +#define R8A7793_CLK_CP 27
> +#define R8A7793_CLK_RCAN 28
> +#define R8A7793_CLK_R 29
> +#define R8A7793_CLK_OSC 30
The last two are called RCLK and OSCCLK in the Table 7.2b ("List of
Clocks [R-Car M2-W/M2-N]"). I'm sure this is intentional on your side,
and if so:
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 05/10] clk: renesas: Add r8a7793 CPG Core Clock Definitions
@ 2017-04-28 12:46 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:15 +0200, Geert Uytterhoeven wrote:
> Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed
> in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2
> Hardware User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7793-cpg-mssr.h | 48 ++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7793-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..8809b0f62d615457
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7793 CPG Core Clocks */
> +#define R8A7793_CLK_Z 0
> +#define R8A7793_CLK_ZG 1
> +#define R8A7793_CLK_ZTR 2
> +#define R8A7793_CLK_ZTRD2 3
> +#define R8A7793_CLK_ZT 4
> +#define R8A7793_CLK_ZX 5
> +#define R8A7793_CLK_ZS 6
> +#define R8A7793_CLK_HP 7
> +#define R8A7793_CLK_I 8
> +#define R8A7793_CLK_B 9
> +#define R8A7793_CLK_LB 10
> +#define R8A7793_CLK_P 11
> +#define R8A7793_CLK_CL 12
> +#define R8A7793_CLK_M2 13
> +#define R8A7793_CLK_ADSP 14
> +#define R8A7793_CLK_ZB3 15
> +#define R8A7793_CLK_ZB3D2 16
> +#define R8A7793_CLK_DDR 17
> +#define R8A7793_CLK_SDH 18
> +#define R8A7793_CLK_SD0 19
> +#define R8A7793_CLK_SD2 20
> +#define R8A7793_CLK_SD3 21
> +#define R8A7793_CLK_MMC0 22
> +#define R8A7793_CLK_MP 23
> +#define R8A7793_CLK_SSP 24
> +#define R8A7793_CLK_SSPRS 25
> +#define R8A7793_CLK_QSPI 26
> +#define R8A7793_CLK_CP 27
> +#define R8A7793_CLK_RCAN 28
> +#define R8A7793_CLK_R 29
> +#define R8A7793_CLK_OSC 30
The last two are called RCLK and OSCCLK in the Table 7.2b ("List of
Clocks [R-Car M2-W/M2-N]"). I'm sure this is intentional on your side,
and if so:
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/10] clk: renesas: Add r8a7794 CPG Core Clock Definitions
2017-04-25 16:53 ` [PATCH 06/10] clk: renesas: Add r8a7794 " Geert Uytterhoeven
@ 2017-04-28 12:49 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:49 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:16 +0200, Geert Uytterhoeven wrote:
> Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7794-cpg-mssr.h | 47 ++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7794-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..9d720311ae3a229a
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7794 CPG Core Clocks */
> +#define R8A7794_CLK_Z2 0
> +#define R8A7794_CLK_ZG 1
> +#define R8A7794_CLK_ZTR 2
> +#define R8A7794_CLK_ZTRD2 3
> +#define R8A7794_CLK_ZT 4
> +#define R8A7794_CLK_ZX 5
> +#define R8A7794_CLK_ZS 6
> +#define R8A7794_CLK_HP 7
> +#define R8A7794_CLK_I 8
> +#define R8A7794_CLK_B 9
> +#define R8A7794_CLK_LB 10
> +#define R8A7794_CLK_P 11
> +#define R8A7794_CLK_CL 12
> +#define R8A7794_CLK_CP 13
> +#define R8A7794_CLK_M2 14
> +#define R8A7794_CLK_ADSP 15
> +#define R8A7794_CLK_ZB3 16
> +#define R8A7794_CLK_ZB3D2 17
> +#define R8A7794_CLK_DDR 18
> +#define R8A7794_CLK_SDH 19
> +#define R8A7794_CLK_SD0 20
> +#define R8A7794_CLK_SD2 21
> +#define R8A7794_CLK_SD3 22
> +#define R8A7794_CLK_MMC0 23
> +#define R8A7794_CLK_MP 24
> +#define R8A7794_CLK_QSPI 25
> +#define R8A7794_CLK_CPEX 26
> +#define R8A7794_CLK_RCAN 27
> +#define R8A7794_CLK_R 28
> +#define R8A7794_CLK_OSC 29
The last two are called RCLK and OSCCLK in the Table 7.2d ("List of
Clocks [R-Car E2]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 06/10] clk: renesas: Add r8a7794 CPG Core Clock Definitions
@ 2017-04-28 12:49 ` Niklas Söderlund
0 siblings, 0 replies; 26+ messages in thread
From: Niklas Söderlund @ 2017-04-28 12:49 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
Hi Geert,
On 2017-04-25 18:53:16 +0200, Geert Uytterhoeven wrote:
> Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in
> Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware
> User's Manual rev. 2.00.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> include/dt-bindings/clock/r8a7794-cpg-mssr.h | 47 ++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 include/dt-bindings/clock/r8a7794-cpg-mssr.h
>
> diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
> new file mode 100644
> index 0000000000000000..9d720311ae3a229a
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a7794 CPG Core Clocks */
> +#define R8A7794_CLK_Z2 0
> +#define R8A7794_CLK_ZG 1
> +#define R8A7794_CLK_ZTR 2
> +#define R8A7794_CLK_ZTRD2 3
> +#define R8A7794_CLK_ZT 4
> +#define R8A7794_CLK_ZX 5
> +#define R8A7794_CLK_ZS 6
> +#define R8A7794_CLK_HP 7
> +#define R8A7794_CLK_I 8
> +#define R8A7794_CLK_B 9
> +#define R8A7794_CLK_LB 10
> +#define R8A7794_CLK_P 11
> +#define R8A7794_CLK_CL 12
> +#define R8A7794_CLK_CP 13
> +#define R8A7794_CLK_M2 14
> +#define R8A7794_CLK_ADSP 15
> +#define R8A7794_CLK_ZB3 16
> +#define R8A7794_CLK_ZB3D2 17
> +#define R8A7794_CLK_DDR 18
> +#define R8A7794_CLK_SDH 19
> +#define R8A7794_CLK_SD0 20
> +#define R8A7794_CLK_SD2 21
> +#define R8A7794_CLK_SD3 22
> +#define R8A7794_CLK_MMC0 23
> +#define R8A7794_CLK_MP 24
> +#define R8A7794_CLK_QSPI 25
> +#define R8A7794_CLK_CPEX 26
> +#define R8A7794_CLK_RCAN 27
> +#define R8A7794_CLK_R 28
> +#define R8A7794_CLK_OSC 29
The last two are called RCLK and OSCCLK in the Table 7.2d ("List of
Clocks [R-Car E2]"). I'm sure this is intentional on your side, and if
so:
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
> --
> 2.7.4
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support
2017-04-25 16:53 ` Geert Uytterhoeven
@ 2017-04-28 19:42 ` Rob Herring
-1 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2017-04-28 19:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
On Tue, Apr 25, 2017 at 06:53:11PM +0200, Geert Uytterhoeven wrote:
> Document use of the Renesas Clock Pulse Generator / Module Standby and
> Software Reset DT Bindings for various member of the R-Car Gen2 family
> (H2, M2-W, V2H, M2-N, and E2).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support
@ 2017-04-28 19:42 ` Rob Herring
0 siblings, 0 replies; 26+ messages in thread
From: Rob Herring @ 2017-04-28 19:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc,
Mark Rutland, devicetree
On Tue, Apr 25, 2017 at 06:53:11PM +0200, Geert Uytterhoeven wrote:
> Document use of the Renesas Clock Pulse Generator / Module Standby and
> Software Reset DT Bindings for various member of the R-Car Gen2 family
> (H2, M2-W, V2H, M2-N, and E2).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> ---
> Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2017-04-28 19:42 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-25 16:53 [PATCH 00/10] clk: renesas: rcar-gen2: Add new CPG/MSSR drivers Geert Uytterhoeven
[not found] ` <1493139200-27396-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2017-04-25 16:53 ` [PATCH 01/10] clk: renesas: cpg-mssr: Document R-Car Gen2 support Geert Uytterhoeven
2017-04-25 16:53 ` Geert Uytterhoeven
[not found] ` <1493139200-27396-2-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2017-04-28 19:42 ` Rob Herring
2017-04-28 19:42 ` Rob Herring
2017-04-25 16:53 ` [PATCH 02/10] clk: renesas: Add r8a7790 CPG Core Clock Definitions Geert Uytterhoeven
2017-04-28 12:38 ` Niklas Söderlund
2017-04-28 12:38 ` Niklas Söderlund
2017-04-28 12:45 ` Geert Uytterhoeven
2017-04-28 12:45 ` Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 03/10] clk: renesas: Add r8a7791 " Geert Uytterhoeven
2017-04-28 12:42 ` Niklas Söderlund
2017-04-28 12:42 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 04/10] clk: renesas: Add r8a7792 " Geert Uytterhoeven
2017-04-28 12:44 ` Niklas Söderlund
2017-04-28 12:44 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 05/10] clk: renesas: Add r8a7793 " Geert Uytterhoeven
2017-04-28 12:46 ` Niklas Söderlund
2017-04-28 12:46 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 06/10] clk: renesas: Add r8a7794 " Geert Uytterhoeven
2017-04-28 12:49 ` Niklas Söderlund
2017-04-28 12:49 ` Niklas Söderlund
2017-04-25 16:53 ` [PATCH 07/10] clk: renesas: r8a7790: Add new CPG/MSSR driver Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 08/10] clk: renesas: r8a7791/r8a7793: " Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 09/10] clk: renesas: r8a7792: " Geert Uytterhoeven
2017-04-25 16:53 ` [PATCH 10/10] clk: renesas: r8a7794: " Geert Uytterhoeven
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