[U-Boot] [PATCH v8 0/9] Add mipi dsi display support for rockchip soc.

[U-Boot] [PATCH v8 0/9] Add mipi dsi display support for rockchip soc.

[Eric Gao]

Changes in v8:
-Set vop disabled by default.
-Move unused config.

Changes in v7:
-Using IS_ERR_VALUE to check the clk_set_rate' return value.

Changes in v6:
-Move panel and backlight configuration to it's define node, and set it
 disbabled defaultly.

Changes in v5:
-Modify indentation for better readability.
-Make all enum variate have explicit value.
-Merge Kconfig and Makefile changes into this patch.
-Drop previous change, and modify clk_set_rate implement in rk3399.
-Regenerate defconfig file using "make savedefconfig"

Changes in v4:
-Move this patch to an early stage.

Changes in v3:
-Split GRF changes as a single patch
-Split mipi dsi driver file and header as a single patch.
-Improve indentation relationship
-Add more description in the commit message
-Add ret value in debug message.

Changes in v2:
-Fix rk_display_init() function report error(err:-19).
-Add mipi display mode for vop.
-Add compatible items for rk3399 vop.
-Change the bitwidth for different display mode.
-Extend frame buffer size for mipi display
-Add pwm0 pinctrl init for lcd backlight.
-Add dts config for mipi display.
-Add defconfigs for mipi display, so that it can be enabled by default.

Eric Gao (9):
  rockchip: include: grf: Add GRF register declaration for mipi dsi
  rockchip: video: Add mipi driver support for rockchip soc
  rockchip: video: vop: Fix rk_display_init() return error
  rockchip: video: vop: Add mipi display mode for rk3399
  rockchip: video: vop: Set different bitwidth for different display
    mode
  rockchip: video: vop: Reserve enough space for mipi dispaly
  rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight
  rockchip: dts: Add mipi dsi support for rk3399
  rockchip: defconfigs: Add mipi dsi support for rk3399 evb board

 arch/arm/dts/rk3399-evb.dts                        |  76 ++++
 arch/arm/dts/rk3399.dtsi                           |  71 +++
 arch/arm/include/asm/arch-rockchip/grf_rk3399.h    |  29 +-
 .../include/asm/arch-rockchip/rockchip_mipi_dsi.h  | 195 ++++++++
 arch/arm/include/asm/arch-rockchip/vop_rk3288.h    |   1 +
 board/rockchip/evb_rk3399/evb-rk3399.c             |   7 +
 configs/evb-rk3399_defconfig                       |  14 +-
 drivers/video/rockchip/Kconfig                     |   9 +-
 drivers/video/rockchip/Makefile                    |   1 +
 drivers/video/rockchip/rk_mipi.c                   | 491 +++++++++++++++++++++
 drivers/video/rockchip/rk_vop.c                    |  30 +-
 11 files changed, 908 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
 create mode 100644 drivers/video/rockchip/rk_mipi.c

-- 
1.9.1

[U-Boot] [PATCH v8 1/9] rockchip: include: grf: Add GRF register declaration for mipi dsi

[Eric Gao]

Add GRF register declaration for mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Modify indentation for better readability.
-Make all enum variate have explicit value.

Changes in v4: None
Changes in v3:
-Split GRF changes as a single patch

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 29 ++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index cbcff2e..387c1ff5 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -456,9 +456,32 @@ enum {
 	GRF_PWM_1               = 1,
 
 	/* GRF_SOC_CON7 */
-	GRF_UART_DBG_SEL_SHIFT	= 10,
-	GRF_UART_DBG_SEL_MASK	= 3 << GRF_UART_DBG_SEL_SHIFT,
-	GRF_UART_DBG_SEL_C	= 2,
+	GRF_UART_DBG_SEL_SHIFT  = 10,
+	GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+	GRF_UART_DBG_SEL_C      = 2,
+
+	/* GRF_SOC_CON20 */
+	GRF_DSI0_VOP_SEL_SHIFT  = 0,
+	GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+	GRF_DSI0_VOP_SEL_B      = 0,
+	GRF_DSI0_VOP_SEL_L      = 1,
+
+	/* GRF_SOC_CON22 */
+	GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+	GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+	GRF_DPHY_TX0_RXMODE_EN    = 0xb,
+	GRF_DPHY_TX0_RXMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+	GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+	GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
+	GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+	GRF_DPHY_TX0_TURNREQUEST_MASK  =
+		0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+	GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
+	GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
 
 	/*  PMUGRF_GPIO0A_IOMUX */
 	PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
-- 
1.9.1

[U-Boot] [PATCH v8 2/9] rockchip: video: Add mipi driver support for rockchip soc

[Eric Gao]

Add basic driver for mipi display on rockchip soc platform.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Merge Kconfig and Makefile changes into this patch.

Changes in v4: None
Changes in v3:
-Split mipi dsi driver file and header as a single patch.

Changes in v2: None

 .../include/asm/arch-rockchip/rockchip_mipi_dsi.h  | 195 ++++++++
 drivers/video/rockchip/Kconfig                     |   9 +-
 drivers/video/rockchip/Makefile                    |   1 +
 drivers/video/rockchip/rk_mipi.c                   | 491 +++++++++++++++++++++
 4 files changed, 695 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
 create mode 100644 drivers/video/rockchip/rk_mipi.c

diff --git a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
new file mode 100644
index 0000000..d7f79c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * author: Eric Gao <eric.gao@rock-chips.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ROCKCHIP_MIPI_DSI_H
+#define ROCKCHIP_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide reg address offset,
+ * bits width, bit offset for a specified register bits. With these message, we
+ * can set or clear every bits individually for a 32bit widthregister. We use
+ * DSI_HOST_BITS macro definition to combinat these message using the following
+ * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * For example:
+ *    #define SHUTDOWNZ           DSI_HOST_BITS(0x004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
+ * offset is 0x004.The conbinat result  = (0x004 << 16) | (1 << 8) | 0
+ */
+#define ADDR_SHIFT 16
+#define BITS_SHIFT 8
+#define OFFSET_SHIFT 0
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
+
+/* DWC_DSI_VERSION_0x3133302A */
+#define VERSION				DSI_HOST_BITS(0x000, 32, 0)
+#define SHUTDOWNZ			DSI_HOST_BITS(0x004, 1, 0)
+#define TO_CLK_DIVISION		DSI_HOST_BITS(0x008, 8, 8)
+#define TX_ESC_CLK_DIVISION	DSI_HOST_BITS(0x008, 8, 0)
+#define DPI_VCID			DSI_HOST_BITS(0x00c, 2, 0)
+#define EN18_LOOSELY		DSI_HOST_BITS(0x010, 1, 8)
+#define DPI_COLOR_CODING	DSI_HOST_BITS(0x010, 4, 0)
+#define COLORM_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 4)
+#define SHUTD_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 3)
+#define HSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 2)
+#define VSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 1)
+#define DATAEN_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 0)
+#define OUTVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 16)
+#define INVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 0)
+#define CRC_RX_EN			DSI_HOST_BITS(0x02c, 1, 4)
+#define ECC_RX_EN			DSI_HOST_BITS(0x02c, 1, 3)
+#define BTA_EN				DSI_HOST_BITS(0x02c, 1, 2)
+#define EOTP_RX_EN			DSI_HOST_BITS(0x02c, 1, 1)
+#define EOTP_TX_EN			DSI_HOST_BITS(0x02c, 1, 0)
+#define GEN_VID_RX			DSI_HOST_BITS(0x030, 2, 0)
+#define CMD_VIDEO_MODE		DSI_HOST_BITS(0x034, 1, 0)
+#define VPG_ORIENTATION		DSI_HOST_BITS(0x038, 1, 24)
+#define VPG_MODE			DSI_HOST_BITS(0x038, 1, 20)
+#define VPG_EN				DSI_HOST_BITS(0x038, 1, 16)
+#define LP_CMD_EN			DSI_HOST_BITS(0x038, 1, 15)
+#define FRAME_BTA_ACK_EN	DSI_HOST_BITS(0x038, 1, 14)
+#define LP_HFP_EN			DSI_HOST_BITS(0x038, 1, 13)
+#define LP_HBP_EN			DSI_HOST_BITS(0x038, 1, 12)
+#define LP_VACT_EN			DSI_HOST_BITS(0x038, 1, 11)
+#define LP_VFP_EN			DSI_HOST_BITS(0x038, 1, 10)
+#define LP_VBP_EN			DSI_HOST_BITS(0x038, 1, 9)
+#define LP_VSA_EN			DSI_HOST_BITS(0x038, 1, 8)
+#define VID_MODE_TYPE		DSI_HOST_BITS(0x038, 2, 0)
+#define VID_PKT_SIZE		DSI_HOST_BITS(0x03c, 14, 0)
+#define NUM_CHUNKS			DSI_HOST_BITS(0x040, 13, 0)
+#define NULL_PKT_SIZE		DSI_HOST_BITS(0x044, 13, 0)
+#define VID_HSA_TIME		DSI_HOST_BITS(0x048, 12, 0)
+#define VID_HBP_TIME		DSI_HOST_BITS(0x04c, 12, 0)
+#define VID_HLINE_TIME		DSI_HOST_BITS(0x050, 15, 0)
+#define VID_VSA_LINES		DSI_HOST_BITS(0x054, 10, 0)
+#define VID_VBP_LINES		DSI_HOST_BITS(0x058, 10, 0)
+#define VID_VFP_LINES		DSI_HOST_BITS(0x05c, 10, 0)
+#define VID_ACTIVE_LINES	DSI_HOST_BITS(0x060, 14, 0)
+#define EDPI_CMD_SIZE		DSI_HOST_BITS(0x064, 16, 0)
+#define MAX_RD_PKT_SIZE		DSI_HOST_BITS(0x068, 1, 24)
+#define DCS_LW_TX			DSI_HOST_BITS(0x068, 1, 19)
+#define DCS_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 18)
+#define DCS_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 17)
+#define DCS_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 16)
+#define GEN_LW_TX			DSI_HOST_BITS(0x068, 1, 14)
+#define GEN_SR_2P_TX		DSI_HOST_BITS(0x068, 1, 13)
+#define GEN_SR_1P_TX		DSI_HOST_BITS(0x068, 1, 12)
+#define GEN_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 11)
+#define GEN_SW_2P_TX		DSI_HOST_BITS(0x068, 1, 10)
+#define GEN_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 9)
+#define GEN_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 8)
+#define ACK_RQST_EN			DSI_HOST_BITS(0x068, 1, 1)
+#define TEAR_FX_EN			DSI_HOST_BITS(0x068, 1, 0)
+#define GEN_WC_MSBYTE		DSI_HOST_BITS(0x06c, 14, 16)
+#define GEN_WC_LSBYTE		DSI_HOST_BITS(0x06c, 8, 8)
+#define GEN_VC				DSI_HOST_BITS(0x06c, 2, 6)
+#define GEN_DT				DSI_HOST_BITS(0x06c, 6, 0)
+#define GEN_PLD_DATA		DSI_HOST_BITS(0x070, 32, 0)
+#define GEN_RD_CMD_BUSY		DSI_HOST_BITS(0x074, 1, 6)
+#define GEN_PLD_R_FULL		DSI_HOST_BITS(0x074, 1, 5)
+#define GEN_PLD_R_EMPTY		DSI_HOST_BITS(0x074, 1, 4)
+#define GEN_PLD_W_FULL		DSI_HOST_BITS(0x074, 1, 3)
+#define GEN_PLD_W_EMPTY		DSI_HOST_BITS(0x074, 1, 2)
+#define GEN_CMD_FULL		DSI_HOST_BITS(0x074, 1, 1)
+#define GEN_CMD_EMPTY		DSI_HOST_BITS(0x074, 1, 0)
+#define HSTX_TO_CNT			DSI_HOST_BITS(0x078, 16, 16)
+#define LPRX_TO_CNT			DSI_HOST_BITS(0x078, 16, 0)
+#define HS_RD_TO_CNT		DSI_HOST_BITS(0x07c, 16, 0)
+#define LP_RD_TO_CNT		DSI_HOST_BITS(0x080, 16, 0)
+#define PRESP_TO_MODE		DSI_HOST_BITS(0x084, 1, 24)
+#define HS_WR_TO_CNT		DSI_HOST_BITS(0x084, 16, 0)
+#define LP_WR_TO_CNT		DSI_HOST_BITS(0x088, 16, 0)
+#define BTA_TO_CNT			DSI_HOST_BITS(0x08c, 16, 0)
+#define AUTO_CLKLANE_CTRL	DSI_HOST_BITS(0x094, 1, 1)
+#define PHY_TXREQUESTCLKHS	DSI_HOST_BITS(0x094, 1, 0)
+#define PHY_HS2LP_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 16)
+#define PHY_HS2HS_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 0)
+#define PHY_HS2LP_TIME		DSI_HOST_BITS(0x09c, 8, 24)
+#define PHY_LP2HS_TIME		DSI_HOST_BITS(0x09c, 8, 16)
+#define MAX_RD_TIME			DSI_HOST_BITS(0x09c, 15, 0)
+#define PHY_FORCEPLL		DSI_HOST_BITS(0x0a0, 1, 3)
+#define PHY_ENABLECLK		DSI_HOST_BITS(0x0a0, 1, 2)
+#define PHY_RSTZ			DSI_HOST_BITS(0x0a0, 1, 1)
+#define PHY_SHUTDOWNZ		DSI_HOST_BITS(0x0a0, 1, 0)
+#define PHY_STOP_WAIT_TIME	DSI_HOST_BITS(0x0a4, 8, 8)
+#define N_LANES				DSI_HOST_BITS(0x0a4, 2, 0)
+#define PHY_TXEXITULPSLAN	DSI_HOST_BITS(0x0a8, 1, 3)
+#define PHY_TXREQULPSLAN	DSI_HOST_BITS(0x0a8, 1, 2)
+#define PHY_TXEXITULPSCLK	DSI_HOST_BITS(0x0a8, 1, 1)
+#define PHY_TXREQULPSCLK	DSI_HOST_BITS(0x0a8, 1, 0)
+#define PHY_TX_TRIGGERS		DSI_HOST_BITS(0x0ac, 4, 0)
+#define PHYSTOPSTATECLKLANE	DSI_HOST_BITS(0x0b0, 1, 2)
+#define PHYLOCK				DSI_HOST_BITS(0x0b0, 1, 0)
+#define PHY_TESTCLK			DSI_HOST_BITS(0x0b4, 1, 1)
+#define PHY_TESTCLR			DSI_HOST_BITS(0x0b4, 1, 0)
+#define PHY_TESTEN			DSI_HOST_BITS(0x0b8, 1, 16)
+#define PHY_TESTDOUT		DSI_HOST_BITS(0x0b8, 8, 8)
+#define PHY_TESTDIN			DSI_HOST_BITS(0x0b8, 8, 0)
+#define PHY_TEST_CTRL1		DSI_HOST_BITS(0x0b8, 17, 0)
+#define PHY_TEST_CTRL0		DSI_HOST_BITS(0x0b4, 2, 0)
+#define INT_ST0				DSI_HOST_BITS(0x0bc, 21, 0)
+#define INT_ST1				DSI_HOST_BITS(0x0c0, 18, 0)
+#define INT_MKS0			DSI_HOST_BITS(0x0c4, 21, 0)
+#define INT_MKS1			DSI_HOST_BITS(0x0c8, 18, 0)
+#define INT_FORCE0			DSI_HOST_BITS(0x0d8, 21, 0)
+#define INT_FORCE1			DSI_HOST_BITS(0x0dc, 18, 0)
+
+#define CODE_HS_RX_CLOCK	0x34
+#define CODE_HS_RX_LANE0	0x44
+#define CODE_HS_RX_LANE1	0x54
+#define CODE_HS_RX_LANE2	0x84
+#define CODE_HS_RX_LANE3	0x94
+
+#define CODE_PLL_VCORANGE_VCOCAP	0x10
+#define CODE_PLL_CPCTRL	0x11
+#define CODE_PLL_LPF_CP 0x12
+#define CODE_PLL_INPUT_DIV_RAT	0x17
+#define CODE_PLL_LOOP_DIV_RAT	0x18
+#define CODE_PLL_INPUT_LOOP_DIV_RAT	0x19
+#define CODE_BANDGAP_BIAS_CTRL	0x20
+#define CODE_TERMINATION_CTRL	0x21
+#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22
+
+#define CODE_HSTXDATALANEREQUSETSTATETIME	0x70
+#define CODE_HSTXDATALANEPREPARESTATETIME	0x71
+#define CODE_HSTXDATALANEHSZEROSTATETIME	0x72
+
+/* Transmission mode between vop and MIPI controller */
+enum vid_mode_type_t {
+	NON_BURST_SYNC_PLUSE = 0,
+	NON_BURST_SYNC_EVENT,
+	BURST_MODE,
+};
+
+enum cmd_video_mode {
+	VIDEO_MODE = 0,
+	CMD_MODE,
+};
+
+/* Indicate MIPI DSI color mode */
+enum dpi_color_coding {
+	DPI_16BIT_CFG_1 = 0,
+	DPI_16BIT_CFG_2,
+	DPI_16BIT_CFG_3,
+	DPI_18BIT_CFG_1,
+	DPI_18BIT_CFG_2,
+	DPI_24BIT,
+	DPI_20BIT_YCBCR_422_LP,
+	DPI_24BIT_YCBCR_422,
+	DPI_16BIT_YCBCR_422,
+	DPI_30BIT,
+	DPI_36BIT,
+	DPI_12BIT_YCBCR_420,
+};
+
+/* Indicate which VOP the MIPI DSI use, bit or little one */
+enum  vop_id {
+	VOP_B = 0,
+	VOP_L,
+};
+
+#endif /* end of ROCKCHIP_MIPI_DSI_H */
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index d94afbd..9267b28 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -39,5 +39,12 @@ config DISPLAY_ROCKCHIP_HDMI
 	help
 	  This enables High-Definition Multimedia Interface display support.
 
-endif
+config DISPLAY_ROCKCHIP_MIPI
+	bool "MIPI Port"
+	depends on VIDEO_ROCKCHIP
+	help
+	  This enables Mobile Industry Processor Interface(MIPI) display
+	  support. The mipi controller and dphy on rk3288& rk3399 support
+	  16,18, 24 bits per pixel with upto 2k resolution ratio.
 
+endif
diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile
index 3bb0519..c742902 100644
--- a/drivers/video/rockchip/Makefile
+++ b/drivers/video/rockchip/Makefile
@@ -10,4 +10,5 @@ obj-y += rk_vop.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
 obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o
+obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o
 endif
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
new file mode 100644
index 0000000..4d9d12e
--- /dev/null
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Eric Gao <eric.gao@rock-chips.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <display.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <panel.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass-internal.h>
+#include <linux/kernel.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/rockchip_mipi_dsi.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Private information for rk mipi
+ *
+ * @regs: mipi controller address
+ * @grf: GRF register
+ * @panel: panel assined by device tree
+ * @ref_clk: reference clock for mipi dsi pll
+ * @sysclk: config clock for mipi dsi register
+ * @pix_clk: pixel clock for vop->dsi data transmission
+ * @phy_clk: mipi dphy output clock
+ * @txbyte_clk: clock for dsi->dphy high speed data transmission
+ * @txesc_clk: clock for tx esc mode
+ */
+struct rk_mipi_priv {
+	void __iomem *regs;
+	struct rk3399_grf_regs *grf;
+	struct udevice *panel;
+	struct mipi_dsi *dsi;
+	u32 ref_clk;
+	u32 sys_clk;
+	u32 pix_clk;
+	u32 phy_clk;
+	u32 txbyte_clk;
+	u32 txesc_clk;
+};
+
+static int rk_mipi_read_timing(struct udevice *dev,
+			       struct display_timing *timing)
+{
+	int ret;
+
+	ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
+					 0, timing);
+	if (ret) {
+		debug("%s: Failed to decode display timing (ret=%d)\n",
+		      __func__, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * Register write function used only for mipi dsi controller.
+ * Parameter:
+ *  @regs: mipi controller address
+ *  @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
+ *        use define in rk_mipi.h directly for this parameter
+ *  @val: value that will be write to specified bits of register
+ */
+static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val)
+{
+	u32 dat;
+	u32 mask;
+	u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
+	u32 bits = (reg >> BITS_SHIFT) & 0xff;
+	u64 addr = (reg >> ADDR_SHIFT) + regs;
+
+	/* Mask for specifiled bits,the corresponding bits will be clear */
+	mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
+
+	/* Make sure val in the available range */
+	val &= ~(0xffffffff << bits);
+
+	/* Get register's original val */
+	dat = readl(addr);
+
+	/* Clear specified bits */
+	dat &= mask;
+
+	/* Fill specified bits */
+	dat |= val << offset;
+
+	writel(dat, addr);
+}
+
+static int rk_mipi_dsi_enable(struct udevice *dev,
+			      const struct display_timing *timing)
+{
+	int node, timing_node;
+	int val;
+	struct rk_mipi_priv *priv = dev_get_priv(dev);
+	u64 regs = (u64)priv->regs;
+	struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
+	u32 txbyte_clk = priv->txbyte_clk;
+	u32 txesc_clk = priv->txesc_clk;
+
+	txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
+
+	/* Select the video source */
+	switch (disp_uc_plat->source_id) {
+	case VOP_B:
+		rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+			     GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
+		 break;
+	case VOP_L:
+		rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
+			     GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
+		 break;
+	default:
+		 debug("%s: Invalid VOP id\n", __func__);
+		 return -EINVAL;
+	}
+
+	/* Set Controller as TX mode */
+	val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
+
+	/* Exit tx stop mode */
+	val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
+
+	/* Disable turnequest */
+	val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
+	rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
+
+	/* Set Display timing parameter */
+	rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
+	rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
+	rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
+			  + timing->hback_porch.typ + timing->hactive.typ
+			  + timing->hfront_porch.typ));
+	rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
+	rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
+	rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
+	rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
+
+	/* Set Signal Polarity */
+	val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
+	rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
+
+	val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
+	rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
+
+	val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
+	rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val);
+
+	val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
+	rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
+
+	/* Set video mode */
+	rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
+
+	/* Set video mode transmission type as burst mode */
+	rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
+
+	/* Set pix num in a video package */
+	rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
+
+	/* Set dpi color coding depth 24 bit */
+	timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
+									 "display-timings");
+	node = fdt_first_subnode(gd->fdt_blob, timing_node);
+	val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
+	switch (val) {
+	case 16:
+		rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
+		break;
+	case 24:
+		rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
+		break;
+	case 30:
+		rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
+		break;
+	default:
+		rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
+	}
+	/* Enable low power mode */
+	rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
+	rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
+	rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
+	rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
+	rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
+	rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
+
+	/* Division for timeout counter clk */
+	rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
+
+	/* Tx esc clk division from txbyte clk */
+	rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
+
+	/* Timeout count for hs<->lp transation between Line period */
+	rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
+
+	/* Phy State transfer timing */
+	rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
+	rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
+	rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
+	rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
+	rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
+
+	/* Power on */
+	rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
+
+	return 0;
+}
+
+/* rk mipi dphy write function. It is used to write test data to dphy */
+static void rk_mipi_phy_write(u32 regs, unsigned char test_code,
+			      unsigned char *test_data, unsigned char size)
+{
+	int i = 0;
+
+	/* Write Test code */
+	rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
+	rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
+	rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
+	rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
+	rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
+
+	/* Write Test data */
+	for (i = 0; i < size; i++) {
+		rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
+		rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
+		rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
+	}
+}
+
+/*
+ * Mipi dphy config function. Calculate the suitable prediv, feedback div,
+ * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
+ * and then enable phy.
+ */
+static int rk_mipi_phy_enable(struct udevice *dev)
+{
+	int i;
+	struct rk_mipi_priv *priv = dev_get_priv(dev);
+	u64 regs = (u64)priv->regs;
+	u64 fbdiv;
+	u64 prediv = 1;
+	u32 max_fbdiv = 512;
+	u32 max_prediv, min_prediv;
+	u64 ddr_clk = priv->phy_clk;
+	u32 refclk = priv->ref_clk;
+	u32 remain = refclk;
+	unsigned char test_data[2] = {0};
+
+	int freq_rang[][2] = {
+		{90, 0x01},   {100, 0x10},  {110, 0x20},  {130, 0x01},
+		{140, 0x11},  {150, 0x21},  {170, 0x02},  {180, 0x12},
+		{200, 0x22},  {220, 0x03},  {240, 0x13},  {250, 0x23},
+		{270, 0x04},  {300, 0x14},  {330, 0x05},  {360, 0x15},
+		{400, 0x25},  {450, 0x06},  {500, 0x16},  {550, 0x07},
+		{600, 0x17},  {650, 0x08},  {700, 0x18},  {750, 0x09},
+		{800, 0x19},  {850, 0x29},  {900, 0x39},  {950, 0x0a},
+		{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
+		{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
+		{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+	};
+
+	/* Shutdown mode */
+	rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
+	rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
+	rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
+
+	/* Pll locking */
+	rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
+
+	/* config cp and lfp */
+	test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
+	rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
+
+	test_data[0] = 0x8;
+	rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
+
+	test_data[0] = 0x80 | 0x40;
+	rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
+
+	/* select the suitable value for fsfreqrang reg */
+	for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
+		if (ddr_clk / (MHz) >= freq_rang[i][0])
+			break;
+	}
+	if (i == ARRAY_SIZE(freq_rang)) {
+		debug("%s: Dphy freq out of range!\n", __func__);
+		return -EINVAL;
+	}
+	test_data[0] = freq_rang[i][1] << 1;
+	rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
+
+	/*
+	 * Calculate the best ddrclk and it's corresponding div value. If the
+	 * given pixelclock is great than 250M, ddrclk will be fix 1500M.
+	 * Otherwise,
+	 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
+	 * according to spec.
+	 */
+	max_prediv = (refclk / (5 * MHz));
+	min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
+
+	debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
+	      min_prediv);
+
+	if (max_prediv < min_prediv) {
+		debug("%s: Invalid refclk value\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Calculate the best refclk and feedback division value for dphy pll */
+	for (i = min_prediv; i < max_prediv; i++) {
+		if ((ddr_clk * i % refclk < remain) &&
+		    (ddr_clk * i / refclk) < max_fbdiv) {
+			prediv = i;
+			remain = ddr_clk * i % refclk;
+		}
+	}
+	fbdiv = ddr_clk * prediv / refclk;
+	ddr_clk = refclk * fbdiv / prediv;
+	priv->phy_clk = ddr_clk;
+
+	debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
+	      __func__, refclk, prediv, fbdiv, ddr_clk);
+
+	/* config prediv and feedback reg */
+	test_data[0] = prediv - 1;
+	rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
+	test_data[0] = (fbdiv - 1) & 0x1f;
+	rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
+	test_data[0] = (fbdiv - 1) >> 5 | 0x80;
+	rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
+	test_data[0] = 0x30;
+	rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
+
+	/* rest config */
+	test_data[0] = 0x4d;
+	rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
+
+	test_data[0] = 0x3d;
+	rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
+
+	test_data[0] = 0xdf;
+	rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
+
+	test_data[0] =  0x7;
+	rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
+
+	test_data[0] = 0x80 | 0x7;
+	rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
+
+	test_data[0] = 0x80 | 15;
+	rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
+			  test_data, 1);
+	test_data[0] = 0x80 | 85;
+	rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
+			  test_data, 1);
+	test_data[0] = 0x40 | 10;
+	rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
+			  test_data, 1);
+
+	/* enter into stop mode */
+	rk_mipi_dsi_write(regs, N_LANES, 0x03);
+	rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
+	rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
+	rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
+	rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
+
+	return 0;
+}
+
+/*
+ * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
+ * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
+ * enable backlight.
+ */
+static int rk_display_enable(struct udevice *dev, int panel_bpp,
+			  const struct display_timing *timing)
+{
+	int ret;
+	struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+	/* Fill the mipi controller parameter */
+	priv->ref_clk = 24 * MHz;
+	priv->sys_clk = priv->ref_clk;
+	priv->pix_clk = timing->pixelclock.typ;
+	priv->phy_clk = priv->pix_clk * 6;
+	priv->txbyte_clk = priv->phy_clk / 8;
+	priv->txesc_clk = 20 * MHz;
+
+	/* Config  and enable mipi dsi according to timing */
+	ret = rk_mipi_dsi_enable(dev, timing);
+	if (ret) {
+		debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	/* Config and enable mipi phy */
+	ret = rk_mipi_phy_enable(dev);
+	if (ret) {
+		debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	/* Enable backlight */
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		debug("%s: panel_enable_backlight() failed (err=%d)\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	if (priv->grf <= 0) {
+		debug("%s: Get syscon grf failed (ret=%llu)\n",
+		      __func__, (u64)priv->grf);
+		return  -ENXIO;
+	}
+	priv->regs = (void *)dev_get_addr(dev);
+	if (priv->regs <= 0) {
+		debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__,
+		      (u64)priv->regs);
+		return  -ENXIO;
+	}
+
+	return 0;
+}
+
+/*
+ * Probe function: check panel existence and readingit's timing. Then config
+ * mipi dsi controller and enable it according to the timing parameter.
+ */
+static int rk_mipi_probe(struct udevice *dev)
+{
+	int ret;
+	struct rk_mipi_priv *priv = dev_get_priv(dev);
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
+					   &priv->panel);
+	if (ret) {
+		debug("%s: Can not find panel (err=%d)\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct dm_display_ops rk_mipi_dsi_ops = {
+	.read_timing = rk_mipi_read_timing,
+	.enable = rk_display_enable,
+};
+
+static const struct udevice_id rk_mipi_dsi_ids[] = {
+	{ .compatible = "rockchip,rk3399_mipi_dsi" },
+	{ }
+};
+
+U_BOOT_DRIVER(rk_mipi_dsi) = {
+	.name	= "rk_mipi_dsi",
+	.id	= UCLASS_DISPLAY,
+	.of_match = rk_mipi_dsi_ids,
+	.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
+	.probe	= rk_mipi_probe,
+	.ops	= &rk_mipi_dsi_ops,
+	.priv_auto_alloc_size   = sizeof(struct rk_mipi_priv),
+};
-- 
1.9.1

[U-Boot] [PATCH v8 3/9] rockchip: video: vop: Fix rk_display_init() return error

[Eric Gao]

It's caused by the difference of clk_set_rate function implement between
rk3288 andd rk3399.

clk_set_rate() of rk3288 return 0 in normal condition.
clk_set_rate() of rk3399 return input parameter in normal condition.

So check clk_set_rate's return value by IS_ERR_VALUE.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>

---

Changes in v8: None
Changes in v7:
-Using IS_ERR_VALUE to check the clk_set_rate' return value.

Changes in v6: None
Changes in v5:
-Drop previous change, and modify clk_set_rate implement in rk3399.

Changes in v4:
-Move this patch to an early stage.

Changes in v3:
-Improve indentation relationship

Changes in v2:
-Fix rk_display_init() function report error(err:-19).

 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index bc02f80..c12c24b 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -244,7 +244,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 	ret = clk_get_by_index(dev, 1, &clk);
 	if (!ret)
 		ret = clk_set_rate(&clk, timing.pixelclock.typ);
-	if (ret) {
+	if (IS_ERR_VALUE(ret)) {
 		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 		return ret;
 	}
-- 
1.9.1

[U-Boot] [PATCH v8 4/9] rockchip: video: vop: Add mipi display mode for rk3399

[Eric Gao]

Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Add mipi display mode for vop.
-Add compatible items for rk3399 vop.

 arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
 drivers/video/rockchip/rk_vop.c                 | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
index 0ce3d67..d5599ec 100644
--- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -90,6 +90,7 @@ enum vop_modes {
 	VOP_MODE_EDP = 0,
 	VOP_MODE_HDMI,
 	VOP_MODE_LVDS,
+	VOP_MODE_MIPI,
 	VOP_MODE_NONE,
 	VOP_MODE_AUTO_DETECT,
 	VOP_MODE_UNKNOWN,
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index c12c24b..6809246 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -117,6 +117,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
 		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
 				V_RGB_OUT_EN(1));
 		break;
+	case VOP_MODE_MIPI:
+		clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
+				V_MIPI_OUT_EN(1));
+		 break;
 	}
 
 	if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
@@ -350,6 +354,8 @@ static const struct video_ops rk_vop_ops = {
 };
 
 static const struct udevice_id rk_vop_ids[] = {
+	{ .compatible = "rockchip,rk3399-vop-big" },
+	{ .compatible = "rockchip,rk3399-vop-lit" },
 	{ .compatible = "rockchip,rk3288-vop" },
 	{ }
 };
-- 
1.9.1

[U-Boot] [PATCH v8 5/9] rockchip: video: vop: Set different bitwidth for different display mode

[Eric Gao]

Because the bitwidth is different for different display mode, so we need
to set them according to demand.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Change the bitwidth for different display mode.

 drivers/video/rockchip/rk_vop.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 6809246..6e0fffa 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -181,13 +181,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
  *
  * @dev:	VOP device that we want to connect to the display
  * @fbbase:	Frame buffer address
- * @l2bpp	Log2 of bits-per-pixels for the display
  * @ep_node:	Device tree node to process - this is the offset of an endpoint
  *		node within the VOP's 'port' list.
  * @return 0 if OK, -ve if something went wrong
  */
-int rk_display_init(struct udevice *dev, ulong fbbase,
-		    enum video_log2_bpp l2bpp, int ep_node)
+int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
 {
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	const void *blob = gd->fdt_blob;
@@ -199,6 +197,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 	int ret, remote, i, offset;
 	struct display_plat *disp_uc_plat;
 	struct clk clk;
+	enum video_log2_bpp l2bpp;
 
 	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
 	debug("vop_id=%d\n", vop_id);
@@ -253,6 +252,19 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 		return ret;
 	}
 
+	/* Set bitwidth for vop display according to vop mode */
+	switch (vop_id) {
+	case VOP_MODE_EDP:
+	case VOP_MODE_HDMI:
+	case VOP_MODE_LVDS:
+		l2bpp = VIDEO_BPP16;
+		break;
+	case VOP_MODE_MIPI:
+		l2bpp = VIDEO_BPP32;
+		break;
+	default:
+		l2bpp = VIDEO_BPP16;
+	}
 	rkvop_mode_set(regs, &timing, vop_id);
 
 	rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
@@ -330,7 +342,7 @@ static int rk_vop_probe(struct udevice *dev)
 	for (node = fdt_first_subnode(blob, port);
 	     node > 0;
 	     node = fdt_next_subnode(blob, node)) {
-		ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
+		ret = rk_display_init(dev, plat->base, node);
 		if (ret)
 			debug("Device failed: ret=%d\n", ret);
 		if (!ret)
-- 
1.9.1

[U-Boot] [PATCH v8 6/9] rockchip: video: vop: Reserve enough space for mipi dispaly

[Eric Gao]

plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
-Add more description in the commit message

Changes in v2:
-Extend frame buffer size for mipi display

 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index 6e0fffa..aa6ca8c 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -357,7 +357,7 @@ static int rk_vop_bind(struct udevice *dev)
 {
 	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 
-	plat->size = 1920 * 1080 * 2;
+	plat->size = 1920 * 1200 * 4;
 
 	return 0;
 }
-- 
1.9.1

[U-Boot] [PATCH v8 7/9] rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight

[Eric Gao]

Enable pwm0 for display of rk3399 evb board. The PWM do not have decicated
interrupt number in dts and can not get periph_id by pinctrl framework. So
init them here.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
-Add ret value in debug message.

Changes in v2:
-Add pwm0 pinctrl init for lcd backlight.

 board/rockchip/evb_rk3399/evb-rk3399.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index e83dedb..f63f003 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -29,6 +29,13 @@ int board_init(void)
 		goto out;
 	}
 
+	/* Enable pwm0 for panel backlight */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
+	if (ret) {
+		debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret);
+		goto out;
+	}
+
 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
 	if (ret) {
 		debug("%s PWM2 pinctrl init fail!\n", __func__);
-- 
1.9.1

[U-Boot] [PATCH v8 8/9] rockchip: dts: Add mipi dsi support for rk3399

[Eric Gao]

Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v8:
-Set vop disabled by default.
-Move unused config.

Changes in v7: None
Changes in v6:
-Move panel and backlight configuration to it's define node, and set it
 disbabled defaultly.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Add dts config for mipi display.

 arch/arm/dts/rk3399-evb.dts | 76 +++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/rk3399.dtsi    | 71 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 147 insertions(+)

diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 574eb1c..820c4a9 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -59,6 +59,58 @@
 		gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&vccsys>;
+		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+		pwms = <&pwm0 0 25000 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pwm0_pin>;
+		pwm-delay-us = <10000>;
+		status = "disabled";
+	};
+
+	panel:panel {
+		compatible = "simple-panel";
+		power-supply = <&vcc33_lcd>;
+		backlight = <&backlight>;
+		/*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
+		status = "disabled";
+	};
 };
 
 &emmc_phy {
@@ -141,6 +193,7 @@
 		status = "okay";
 
 		vcc12-supply = <&vcc3v3_sys>;
+
 		regulators {
 			vcc33_lcd: SWITCH_REG2 {
 				regulator-always-on;
@@ -151,6 +204,29 @@
 	};
 };
 
+&mipi_dsi {
+	status = "disabled";
+	rockchip,panel = <&panel>;
+	display-timings {
+		timing0 {
+		bits-per-pixel = <24>;
+		clock-frequency = <160000000>;
+		hfront-porch = <120>;
+		hsync-len = <20>;
+		hback-porch = <21>;
+		hactive = <1200>;
+		vfront-porch = <21>;
+		vsync-len = <3>;
+		vback-porch = <18>;
+		vactive = <1920>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		de-active = <1>;
+		pixelclk-active = <0>;
+		};
+	};
+};
+
 &pinctrl {
 	pmic {
 		pmic_int_l: pmic-int-l {
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index d94d780..9933401 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -684,6 +684,77 @@
 		status = "disabled";
 	};
 
+	vopl: vop at ff8f0000 {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3399-vop-lit";
+		reg = <0x0 0xff8f0000 0x0 0x3efc>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+		reset-names = "axi", "ahb", "dclk";
+		status = "disabled";
+		vopl_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vopl_out_mipi: endpoint at 0 {
+				reg = <3>;
+				remote-endpoint = <&mipi_in_vopl>;
+			};
+		};
+	};
+
+	vopb: vop at ff900000 {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3399-vop-big";
+		reg = <0x0 0xff900000 0x0 0x3efc>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+		#clock-cells = <0>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+		reset-names = "axi", "ahb", "dclk";
+		status = "disabled";
+		vopb_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vopb_out_mipi: endpoint at 0 {
+				reg = <3>;
+				remote-endpoint = <&mipi_in_vopb>;
+			};
+		};
+	};
+
+	mipi_dsi: mipi at ff960000 {
+		compatible = "rockchip,rk3399_mipi_dsi";
+		reg = <0x0 0xff960000 0x0 0x8000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+		         <&cru SCLK_DPHY_TX0_CFG>;
+		clock-names = "ref", "pclk", "phy_cfg";
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			mipi_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mipi_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi>;
+				};
+				mipi_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi>;
+				};
+			};
+		};
+	};
+
 	pinctrl: pinctrl {
 		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3399-pinctrl";
-- 
1.9.1

[U-Boot] [PATCH v8 9/9] rockchip: defconfigs: Add mipi dsi support for rk3399 evb board

[Eric Gao]

Add mipi dsi configs for rk3399 evb board

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Regenerate defconfig file using "make savedefconfig"

Changes in v4: None
Changes in v3: None
Changes in v2:
-Add defconfigs for mipi display, so that it can be enabled by default.

 configs/evb-rk3399_defconfig | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index cfa103a..3a07f0c 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -30,14 +30,18 @@ CONFIG_SPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_ROCKCHIP_RK3399_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK808=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK808=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
@@ -54,11 +58,9 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_MIPI=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_ERRNO_STR=y
-CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_CHILDREN=y
-CONFIG_SPL_PMIC_CHILDREN=y
-CONFIG_PMIC_RK808=y
-CONFIG_REGULATOR_RK808=y
-- 
1.9.1

[U-Boot] [PATCH v8 9/9] rockchip: defconfigs: Add mipi dsi support for rk3399 evb board

[sjg at google.com]

Add mipi dsi configs for rk3399 evb board

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Regenerate defconfig file using "make savedefconfig"

Changes in v4: None
Changes in v3: None
Changes in v2:
-Add defconfigs for mipi display, so that it can be enabled by default.

 configs/evb-rk3399_defconfig | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 8/9] rockchip: dts: Add mipi dsi support for rk3399

[sjg at google.com]

Add dts config for mipi display, include vop, mipi controller, panel, backlight
. And Enable rk808 for lcd_3v3 in another patch.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v8:
-Set vop disabled by default.
-Move unused config.

Changes in v7: None
Changes in v6:
-Move panel and backlight configuration to it's define node, and set it
 disbabled defaultly.

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Add dts config for mipi display.

 arch/arm/dts/rk3399-evb.dts | 76 +++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/dts/rk3399.dtsi    | 71 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 147 insertions(+)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 7/9] rockchip: board: evb_rk3399: initialize pwm0 for dispaly backlight

[sjg at google.com]

Enable pwm0 for display of rk3399 evb board. The PWM do not have decicated
interrupt number in dts and can not get periph_id by pinctrl framework. So
init them here.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
-Add ret value in debug message.

Changes in v2:
-Add pwm0 pinctrl init for lcd backlight.

 board/rockchip/evb_rk3399/evb-rk3399.c | 7 +++++++
 1 file changed, 7 insertions(+)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 5/9] rockchip: video: vop: Set different bitwidth for different display mode

[sjg at google.com]

Because the bitwidth is different for different display mode, so we need
to set them according to demand.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Change the bitwidth for different display mode.

 drivers/video/rockchip/rk_vop.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 6/9] rockchip: video: vop: Reserve enough space for mipi dispaly

[sjg at google.com]

plat->size here is used to reserve frame buffer space befor relocation.
our mipi panel use 24 bitwidth, and vop require 32bit align. So the frame
buffer size should be at least 1920*1200*32/8.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
-Add more description in the commit message

Changes in v2:
-Extend frame buffer size for mipi display

 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 4/9] rockchip: video: vop: Add mipi display mode for rk3399

[sjg at google.com]

Add mipi display mode for rk3399 vop, so that we can use mipi panel
for display.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
-Add mipi display mode for vop.
-Add compatible items for rk3399 vop.

 arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 1 +
 drivers/video/rockchip/rk_vop.c                 | 6 ++++++
 2 files changed, 7 insertions(+)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 3/9] rockchip: video: vop: Fix rk_display_init() return error

[sjg at google.com]

It's caused by the difference of clk_set_rate function implement between
rk3288 andd rk3399.

clk_set_rate() of rk3288 return 0 in normal condition.
clk_set_rate() of rk3399 return input parameter in normal condition.

So check clk_set_rate's return value by IS_ERR_VALUE.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>

---

Changes in v8: None
Changes in v7:
-Using IS_ERR_VALUE to check the clk_set_rate' return value.

Changes in v6: None
Changes in v5:
-Drop previous change, and modify clk_set_rate implement in rk3399.

Changes in v4:
-Move this patch to an early stage.

Changes in v3:
-Improve indentation relationship

Changes in v2:
-Fix rk_display_init() function report error(err:-19).

 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 2/9] rockchip: video: Add mipi driver support for rockchip soc

[sjg at google.com]

Add basic driver for mipi display on rockchip soc platform.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Merge Kconfig and Makefile changes into this patch.

Changes in v4: None
Changes in v3:
-Split mipi dsi driver file and header as a single patch.

Changes in v2: None

 .../include/asm/arch-rockchip/rockchip_mipi_dsi.h  | 195 ++++++++
 drivers/video/rockchip/Kconfig                     |   9 +-
 drivers/video/rockchip/Makefile                    |   1 +
 drivers/video/rockchip/rk_mipi.c                   | 491 +++++++++++++++++++++
 4 files changed, 695 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
 create mode 100644 drivers/video/rockchip/rk_mipi.c

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v8 1/9] rockchip: include: grf: Add GRF register declaration for mipi dsi

[sjg at google.com]

Add GRF register declaration for mipi dsi.

Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
-Modify indentation for better readability.
-Make all enum variate have explicit value.

Changes in v4: None
Changes in v3:
-Split GRF changes as a single patch

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 29 ++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

Applied to u-boot-rockchip/next, thanks!