[U-Boot] [PATCH 0/5] dm: rst: add BCM6345 reset controller support

[U-Boot] [PATCH 0/5] dm: rst: add BCM6345 reset controller support

[Álvaro Fernández Rojas]

Broadcom MIPS SoCs have reset controllers which supports asserting and
deasserting each peripheral controller.
Checking reset status is not supported, which is why delays are used.

Álvaro Fernández Rojas (5):
  dm: reset: add BCM6345 reset driver
  mips: bmips: add bcm6345-rst driver support for BCM6358
  mips: bmips: add bcm6345-rst driver support for BCM6328
  mips: bmips: add bcm6345-rst driver support for BCM63268
  mips: bmips: enable bcm6345-reset driver for all BMIPS boards

 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++
 arch/mips/dts/brcm,bcm6328.dtsi            |  7 +++
 arch/mips/dts/brcm,bcm6358.dtsi            |  7 +++
 configs/comtrend_ar5387un_ram_defconfig    |  3 +
 configs/comtrend_vr3032u_ram_defconfig     |  3 +
 configs/huawei_hg556a_ram_defconfig        |  3 +
 configs/sfr_nb4-ser_ram_defconfig          |  3 +
 drivers/reset/Kconfig                      |  6 ++
 drivers/reset/Makefile                     |  1 +
 drivers/reset/reset-bcm6345.c              | 89 ++++++++++++++++++++++++++++++
 include/dt-bindings/reset/bcm63268-reset.h | 32 +++++++++++
 include/dt-bindings/reset/bcm6328-reset.h  | 24 ++++++++
 include/dt-bindings/reset/bcm6358-reset.h  | 21 +++++++
 13 files changed, 206 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h

-- 
2.1.4

[U-Boot] [PATCH 1/5] dm: reset: add BCM6345 reset driver

[Álvaro Fernández Rojas]

This is a simplified version of linux/arch/mips/bcm63xx/reset.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 drivers/reset/Kconfig         |  6 +++
 drivers/reset/Makefile        |  1 +
 drivers/reset/reset-bcm6345.c | 89 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index fa77ee4..822d7f1 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -42,6 +42,12 @@ config TEGRA186_RESET
 	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
 	  requests to the BPMP (Boot and Power Management Processor).
 
+config RESET_BCM6345
+	bool "Reset controller driver for BCM6345"
+	depends on DM_RESET && ARCH_BMIPS
+	help
+	  Support reset controller on BCM6345.
+
 config RESET_UNIPHIER
 	bool "Reset controller driver for UniPhier SoCs"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 2b96396..f29fb20 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
 obj-$(CONFIG_STI_RESET) += sti-reset.o
 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c
new file mode 100644
index 0000000..774c2a7
--- /dev/null
+++ b/drivers/reset/reset-bcm6345.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/reset.c:
+ *	Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+
+#define MAX_RESETS	32
+
+struct bcm6345_reset_priv {
+	void __iomem *regs;
+};
+
+static int bcm6345_reset_assert(struct reset_ctl *rst)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
+
+	clrbits_be32(priv->regs, BIT(rst->id));
+	mdelay(20);
+
+	return 0;
+}
+
+static int bcm6345_reset_deassert(struct reset_ctl *rst)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(rst->dev);
+
+	setbits_be32(priv->regs, BIT(rst->id));
+	mdelay(20);
+
+	return 0;
+}
+
+static int bcm6345_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int bcm6345_reset_request(struct reset_ctl *rst)
+{
+	if (rst->id >= MAX_RESETS)
+		return -EINVAL;
+
+	return bcm6345_reset_assert(rst);
+}
+
+struct reset_ops bcm6345_reset_reset_ops = {
+	.free = bcm6345_reset_free,
+	.request = bcm6345_reset_request,
+	.rst_assert = bcm6345_reset_assert,
+	.rst_deassert = bcm6345_reset_deassert,
+};
+
+static const struct udevice_id bcm6345_reset_ids[] = {
+	{ .compatible = "brcm,bcm6345-reset" },
+	{ /* sentinel */ }
+};
+
+static int bcm6345_reset_probe(struct udevice *dev)
+{
+	struct bcm6345_reset_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = dev_get_addr_size_index(dev, 0, &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = ioremap(addr, size);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(bcm6345_reset) = {
+	.name = "bcm6345-reset",
+	.id = UCLASS_RESET,
+	.of_match = bcm6345_reset_ids,
+	.ops = &bcm6345_reset_reset_ops,
+	.probe = bcm6345_reset_probe,
+	.priv_auto_alloc_size = sizeof(struct bcm6345_reset_priv),
+};
-- 
2.1.4

[U-Boot] [PATCH 2/5] mips: bmips: add bcm6345-rst driver support for BCM6358

[Álvaro Fernández Rojas]

This driver can control up to 32 resets.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 arch/mips/dts/brcm,bcm6358.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6358-reset.h | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h

diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi
index 369c240..df75988 100644
--- a/arch/mips/dts/brcm,bcm6358.dtsi
+++ b/arch/mips/dts/brcm,bcm6358.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm6358-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6358-reset.h>
 #include "skeleton.dtsi"
 
 / {
@@ -80,6 +81,12 @@
 			mask = <0x1>;
 		};
 
+		periph_rst: reset-controller at fffe0034 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0034 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpio1: gpio-controller at fffe0080 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h
new file mode 100644
index 0000000..4b3cff3
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6358-reset.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6358_H
+#define __DT_BINDINGS_RESET_BCM6358_H
+
+#define BCM6358_RST_SPI		0
+#define BCM6358_RST_ENET	2
+#define BCM6358_RST_MPI		3
+#define BCM6358_RST_EPHY	6
+#define BCM6358_RST_SAR		7
+#define BCM6358_RST_USBH	12
+#define BCM6358_RST_PCM		13
+#define BCM6358_RST_ADSL	14
+
+#endif /* __DT_BINDINGS_RESET_BCM6358_H */
-- 
2.1.4

[U-Boot] [PATCH 3/5] mips: bmips: add bcm6345-rst driver support for BCM6328

[Álvaro Fernández Rojas]

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 arch/mips/dts/brcm,bcm6328.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6328-reset.h | 24 ++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 6b5c5dd..9b76a23 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm6328-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6328-reset.h>
 #include "skeleton.dtsi"
 
 / {
@@ -58,6 +59,12 @@
 		#size-cells = <1>;
 		u-boot,dm-pre-reloc;
 
+		periph_rst: reset-controller at 10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
 		pll_cntl: syscon at 10000068 {
 			compatible = "syscon";
 			reg = <0x10000068 0x4>;
diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h
new file mode 100644
index 0000000..c144ad2
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6328-reset.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6328_H
+#define __DT_BINDINGS_RESET_BCM6328_H
+
+#define BCM6328_RST_SPI		0
+#define BCM6328_RST_EPHY	1
+#define BCM6328_RST_SAR		2
+#define BCM6328_RST_ENETSW	3
+#define BCM6328_RST_USBS	4
+#define BCM6328_RST_USBH	5
+#define BCM6328_RST_PCM		6
+#define BCM6328_RST_PCIE_CORE	7
+#define BCM6328_RST_PCIE	8
+#define BCM6328_RST_PCIE_EXT	9
+#define BCM6328_RST_PCIE_HARD	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6328_H */
-- 
2.1.4

[U-Boot] [PATCH 4/5] mips: bmips: add bcm6345-rst driver support for BCM63268

[Álvaro Fernández Rojas]

This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm63268-reset.h | 32 ++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h

diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi
index 4d02024..8ff13c1 100644
--- a/arch/mips/dts/brcm,bcm63268.dtsi
+++ b/arch/mips/dts/brcm,bcm63268.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm63268-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm63268-reset.h>
 #include "skeleton.dtsi"
 
 / {
@@ -76,6 +77,12 @@
 			mask = <0x1>;
 		};
 
+		periph_rst: reset-controller at 10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpio1: gpio-controller at 100000c0 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h
new file mode 100644
index 0000000..1373884
--- /dev/null
+++ b/include/dt-bindings/reset/bcm63268-reset.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM63268_H
+#define __DT_BINDINGS_RESET_BCM63268_H
+
+#define BCM63268_RST_SPI	0
+#define BCM63268_RST_IPSEC	1
+#define BCM63268_RST_EPHY	2
+#define BCM63268_RST_SAR	3
+#define BCM63268_RST_ENETSW	4
+#define BCM63268_RST_USBS	5
+#define BCM63268_RST_USBH	6
+#define BCM63268_RST_PCM	7
+#define BCM63268_RST_PCIE_CORE	8
+#define BCM63268_RST_PCIE	9
+#define BCM63268_RST_PCIE_EXT	10
+#define BCM63268_RST_WLAN_SHIM	11
+#define BCM63268_RST_DDR_PHY	12
+#define BCM63268_RST_FAP0	13
+#define BCM63268_RST_WLAN_UBUS	14
+#define BCM63268_RST_DECT	15
+#define BCM63268_RST_FAP1	16
+#define BCM63268_RST_PCIE_HARD	17
+#define BCM63268_RST_GPHY	18
+
+#endif /* __DT_BINDINGS_RESET_BCM63268_H */
-- 
2.1.4

[U-Boot] [PATCH 5/5] mips: bmips: enable bcm6345-reset driver for all BMIPS boards

[Álvaro Fernández Rojas]

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
---
 configs/comtrend_ar5387un_ram_defconfig | 3 +++
 configs/comtrend_vr3032u_ram_defconfig  | 3 +++
 configs/huawei_hg556a_ram_defconfig     | 3 +++
 configs/sfr_nb4-ser_ram_defconfig       | 3 +++
 4 files changed, 12 insertions(+)

diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig
index 55cb4bf..d613740 100644
--- a/configs/comtrend_ar5387un_ram_defconfig
+++ b/configs/comtrend_ar5387un_ram_defconfig
@@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y
@@ -41,6 +42,8 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6328=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig
index 7f13d24..fa2b2ae 100644
--- a/configs/comtrend_vr3032u_ram_defconfig
+++ b/configs/comtrend_vr3032u_ram_defconfig
@@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y
@@ -41,6 +42,8 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM63268=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig
index 71e1163..c2e6472 100644
--- a/configs/huawei_hg556a_ram_defconfig
+++ b/configs/huawei_hg556a_ram_defconfig
@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y
@@ -45,6 +46,8 @@ CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6358=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig
index cd6c4a2..d7c8329 100644
--- a/configs/sfr_nb4-ser_ram_defconfig
+++ b/configs/sfr_nb4-ser_ram_defconfig
@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y
@@ -46,6 +47,8 @@ CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6358=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-- 
2.1.4

[U-Boot] [PATCH 1/5] dm: reset: add BCM6345 reset driver

[Simon Glass]

On 3 May 2017 at 07:10, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> This is a simplified version of linux/arch/mips/bcm63xx/reset.c
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  drivers/reset/Kconfig         |  6 +++
>  drivers/reset/Makefile        |  1 +
>  drivers/reset/reset-bcm6345.c | 89 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 96 insertions(+)
>  create mode 100644 drivers/reset/reset-bcm6345.c

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 2/5] mips: bmips: add bcm6345-rst driver support for BCM6358

[Simon Glass]

On 3 May 2017 at 07:10, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> This driver can control up to 32 resets.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  arch/mips/dts/brcm,bcm6358.dtsi           |  7 +++++++
>  include/dt-bindings/reset/bcm6358-reset.h | 21 +++++++++++++++++++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/5] mips: bmips: add bcm6345-rst driver support for BCM6328

[Simon Glass]

On 3 May 2017 at 07:10, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> This driver can control up to 32 clocks.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  arch/mips/dts/brcm,bcm6328.dtsi           |  7 +++++++
>  include/dt-bindings/reset/bcm6328-reset.h | 24 ++++++++++++++++++++++++
>  2 files changed, 31 insertions(+)
>  create mode 100644 include/dt-bindings/reset/bcm6328-reset.h

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/5] mips: bmips: add bcm6345-rst driver support for BCM63268

[Simon Glass]

On 3 May 2017 at 07:10, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> This driver can control up to 32 clocks.
>
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++++++
>  include/dt-bindings/reset/bcm63268-reset.h | 32 ++++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
>  create mode 100644 include/dt-bindings/reset/bcm63268-reset.h

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/5] mips: bmips: enable bcm6345-reset driver for all BMIPS boards

[Simon Glass]

On 3 May 2017 at 07:10, Álvaro Fernández Rojas <noltari@gmail.com> wrote:
> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
> ---
>  configs/comtrend_ar5387un_ram_defconfig | 3 +++
>  configs/comtrend_vr3032u_ram_defconfig  | 3 +++
>  configs/huawei_hg556a_ram_defconfig     | 3 +++
>  configs/sfr_nb4-ser_ram_defconfig       | 3 +++
>  4 files changed, 12 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Also consider using imply.

[U-Boot] [PATCH 0/5] dm: rst: add BCM6345 reset controller support

[Daniel Schwierzeck]

Am 03.05.2017 um 15:10 schrieb Álvaro Fernández Rojas:
> Broadcom MIPS SoCs have reset controllers which supports asserting and
> deasserting each peripheral controller.
> Checking reset status is not supported, which is why delays are used.
> 
> Álvaro Fernández Rojas (5):
>   dm: reset: add BCM6345 reset driver
>   mips: bmips: add bcm6345-rst driver support for BCM6358
>   mips: bmips: add bcm6345-rst driver support for BCM6328
>   mips: bmips: add bcm6345-rst driver support for BCM63268
>   mips: bmips: enable bcm6345-reset driver for all BMIPS boards
> 
>  arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++
>  arch/mips/dts/brcm,bcm6328.dtsi            |  7 +++
>  arch/mips/dts/brcm,bcm6358.dtsi            |  7 +++
>  configs/comtrend_ar5387un_ram_defconfig    |  3 +
>  configs/comtrend_vr3032u_ram_defconfig     |  3 +
>  configs/huawei_hg556a_ram_defconfig        |  3 +
>  configs/sfr_nb4-ser_ram_defconfig          |  3 +
>  drivers/reset/Kconfig                      |  6 ++
>  drivers/reset/Makefile                     |  1 +
>  drivers/reset/reset-bcm6345.c              | 89 ++++++++++++++++++++++++++++++
>  include/dt-bindings/reset/bcm63268-reset.h | 32 +++++++++++
>  include/dt-bindings/reset/bcm6328-reset.h  | 24 ++++++++
>  include/dt-bindings/reset/bcm6358-reset.h  | 21 +++++++
>  13 files changed, 206 insertions(+)
>  create mode 100644 drivers/reset/reset-bcm6345.c
>  create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
>  create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
>  create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
> 

series applied to u-boot-mips/next, thanks

-- 
- Daniel

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