[U-Boot] [PATCH 1/8] armv7: Add workaround for USB erratum A-009008

[U-Boot] [PATCH 1/8] armv7: Add workaround for USB erratum A-009008

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed (HS) EYE Height Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  4 ++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
 	return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+	val &= ~(0xF << 6);
+	out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,8 @@ int arch_soc_init(void)
 	 */
 	out_be32(&scfg->eddrtqcfg, 0x63b20042);
 
+	/* Erratum */
+	erratum_a009008();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 2f7233f..5b89f16 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -110,6 +110,10 @@
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009008
+#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..f474cfd 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -172,6 +172,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG0	0x00080000
 #define SCFG_PMCINTECR_ETSECERRG1	0x00040000
 #define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
+#define SCFG_BASE                       0x01570000
+#define SCFG_USB3PRM1CR                 0x070
+#define USB_TXVREFTUNE                  0x9
+
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 2/8] armv7: Add workaround for USB erratum A-009798

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 10 ++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+	out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
 	/* Erratum */
 	erratum_a009008();
+	erratum_a009798();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 5b89f16..14d5de1 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -113,6 +113,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009008
+#define CONFIG_SYS_FSL_ERRATUM_A009798
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f474cfd..bfc92ee 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -175,6 +175,7 @@ struct ccsr_gur {
 #define SCFG_BASE                       0x01570000
 #define SCFG_USB3PRM1CR                 0x070
 #define USB_TXVREFTUNE                  0x9
+#define USB_SQRXTUNE                    0xFC7FFFFF
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 3/8] armv7: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 16 ++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +++++++++
 3 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+	writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+	writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+	writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+	writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
 	/* Erratum */
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 14d5de1..1bec9d0 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -114,6 +114,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
+#define CONFIG_SYS_FSL_ERRATUM_A008997
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index bfc92ee..5f05e0d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR                 0x070
 #define USB_TXVREFTUNE                  0x9
 #define USB_SQRXTUNE                    0xFC7FFFFF
+#define USB_PHY_BASE                    0x08510000
+#define USB_PHY_TX_OVRD_DRV_LO          0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI         0x0024
+#define USB_PHY_LEVEL_OVRD_IN           0x002a
+#define USB_PHY_TX_OVRD_IN_HI           0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL      0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL     0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL       0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL       0x0003
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 4/8] armv7: Add workaround for USB erratum A-009007

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
 	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 1bec9d0..20a7baf 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -115,6 +115,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
 #define CONFIG_SYS_FSL_ERRATUM_A008997
+#define CONFIG_SYS_FSL_ERRATUM_A009007
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 5f05e0d..fc406f7 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,10 +181,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI         0x0024
 #define USB_PHY_LEVEL_OVRD_IN           0x002a
 #define USB_PHY_TX_OVRD_IN_HI           0x2002
+#define USB_PHY_RX_OVRD_IN_HI           0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL      0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL     0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL       0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL       0x0003
+#define USB_PHY_RX_EQ_VAL_1             0x0000
+#define USB_PHY_RX_EQ_VAL_2             0x8000
+#define USB_PHY_RX_EQ_VAL_3             0x8004
+#define USB_PHY_RX_EQ_VAL_4             0x800C
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 5/8] armv8: Add workaround for USB erratum A-009798

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB High Speed Squelch Threshold Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 22 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  5 +++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 30 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1544eaa..27eb8fb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -28,6 +28,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+       val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+       val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+       u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+       u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+       scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -200,6 +219,8 @@ void fsl_lsch3_early_init_f(void)
 #endif
 	erratum_a008514();
 	erratum_a008336();
+	erratum_a009008();
+	erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -471,6 +492,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009929();
 	erratum_a009660();
 	erratum_a010539();
+	erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8f66938..e66253f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -113,6 +113,7 @@
 #define EPU_EPGCR		0x700060000ULL
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009798
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5210b8c..5763586 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,6 +198,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_USB3PRM1CR_USB2           0x07C
+#define SCFG_USB3PRM1CR_USB3           0x088
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
+
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
 	u32     devdisr4;       /* Device disable control 4 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e181ef2..281f0ee 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -130,6 +130,8 @@
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
+#define USB_TXVREFTUNE                 0x9
+#define USB_SQRXTUNE                   0xFC7FFFFF
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 6/8] armv8: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 29 ++++++++++++++++++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 3 files changed, 35 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 27eb8fb..c42d778 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+	val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+	val &= ~(0x7F << 9);
+	scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+		   val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a008336();
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009798();
+	erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+#define SCFG_BASE                      0x01570000
+#define SCFG_USB3PRM1CR_USB1           0x070
+#define SCFG_USB3PRM2CR_USB1           0x074
 #define SCFG_USB3PRM1CR_USB2           0x07C
 #define SCFG_USB3PRM1CR_USB3           0x088
+#define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 281f0ee..b428b18 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -129,9 +129,11 @@
 /* Supplemental Configuration */
 #define SCFG_BASE		0x01fc0000
 #define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM2CR                 0x004
 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
 #define SCFG_QSPICLKCTLR	0x10
 
 #define TP_ITYP_AV		0x00000001	/* Initiator available */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 7/8] armv8: Add workaround for USB erratum A-009007

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3PHY Observing Intermittent Failure in Rx
This patch is adding the erratum for LS1043 and LS2080 SoCs.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 43 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  5 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 12 ++++++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  7 ++++
 4 files changed, 67 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c42d778..4e9c718 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -74,6 +74,47 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	usb_phy = (u32 __iomem *)USB_PHY2;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	usb_phy = (u32 __iomem *)USB_PHY3;
+	writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+	u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+	writew(USB_PHY_RX_EQ_VAL_1,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4,
+	       (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_1,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_2,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_3,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+	writew(USB_PHY_RX_EQ_VAL_4,
+	       (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 bool soc_has_dp_ddr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +290,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009008();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -522,6 +564,7 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a010539();
 	erratum_a009798();
 	erratum_a008997();
+	erratum_a009007();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index e66253f..7d263fa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -114,6 +114,11 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 #define CONFIG_SYS_FSL_ERRATUM_A009798
+#define CONFIG_SYS_FSL_ERRATUM_A008997
+#define CONFIG_SYS_FSL_ERRATUM_A009007
+#define CONFIG_SYS_FSL_ERRATUM_A010165
+
+
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 554def5..2634195 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -206,6 +206,18 @@ struct ccsr_gur {
 #define SCFG_USB3PRM2CR_USB3           0x08c
 #define USB_TXVREFTUNE                 0x9
 #define USB_SQRXTUNE                   0xFC7FFFFF
+#define USB_PCSTXSWINGFULL             0x47
+#define USB_PHY1                       0x084F0000
+#define USB_PHY2                       0x08500000
+#define USB_PHY3                       0x08510000
+#define USB_PHY_RX_OVRD_IN_HI          0x200c
+/* TODO : make it generic */
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x8000
+#define USB_PHY_RX_EQ_VAL_3            0x8003
+
+#define USB_PHY_RX_EQ_VAL_4            0x800b
+
 
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b428b18..a7a9364 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -120,6 +120,13 @@
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
 
 #define DCFG_DCSR_BASE		0X700100000ULL
+#define DCSR_USB_PHY1                  0x4600000
+#define DCSR_USB_PHY2                  0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI     0x1006
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x0080
+#define USB_PHY_RX_EQ_VAL_3            0x0380
+#define USB_PHY_RX_EQ_VAL_4            0x0b80
 #define DCFG_DCSR_PORCR1		0x000
 
 /* Interrupt Sampling Control */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 8/8] USB: config: fix compiler problem for ls1021atwr

[yinbo.zhu]

Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
---
 arch/arm/include/asm/arch-ls102xa/config.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 20a7baf..2f7233f 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -110,13 +110,6 @@
 
 #ifdef CONFIG_LS102XA
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
-#define CONFIG_SYS_FSL_ERRATUM_A008378
-#define CONFIG_SYS_FSL_ERRATUM_A009663
-#define CONFIG_SYS_FSL_ERRATUM_A009008
-#define CONFIG_SYS_FSL_ERRATUM_A009798
-#define CONFIG_SYS_FSL_ERRATUM_A008997
-#define CONFIG_SYS_FSL_ERRATUM_A009007
-#define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 1/8] armv7: Add workaround for USB erratum A-009008

[Tom Rini]

On Thu, May 04, 2017 at 12:53:15PM +0800, yinbo.zhu wrote:

> From: Suresh Gupta <suresh.gupta@freescale.com>
> 
> USB High Speed (HS) EYE Height Adjustment
> This patch is adding the erratum for LS1021.
> 
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
> ---
>  arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
>  arch/arm/include/asm/arch-ls102xa/config.h        |  4 ++++
>  arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++++
>  3 files changed, 20 insertions(+)

This needs to be selected / enabled in defconfigs not config.h, please
fix the entire series, thanks!

-- 
Tom
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[U-Boot] [PATCH 3/8] armv7: Add workaround for USB erratum A-008997

[yinbo.zhu]

From: Suresh Gupta <suresh.gupta@freescale.com>

USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1021.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 16 ++++++++++++++++
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +++++++++
 3 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+	u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+	writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+	writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+	writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+	writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+	       (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
 	/* Erratum */
 	erratum_a009008();
 	erratum_a009798();
+	erratum_a008997();
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 14d5de1..1bec9d0 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -114,6 +114,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009008
 #define CONFIG_SYS_FSL_ERRATUM_A009798
+#define CONFIG_SYS_FSL_ERRATUM_A008997
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index bfc92ee..5f05e0d 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR                 0x070
 #define USB_TXVREFTUNE                  0x9
 #define USB_SQRXTUNE                    0xFC7FFFFF
+#define USB_PHY_BASE                    0x08510000
+#define USB_PHY_TX_OVRD_DRV_LO          0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI         0x0024
+#define USB_PHY_LEVEL_OVRD_IN           0x002a
+#define USB_PHY_TX_OVRD_IN_HI           0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL      0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL     0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL       0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL       0x0003
 
 
 /* Supplemental Configuration Unit */
-- 
2.1.0.27.g96db324