* [PATCH 000/117] Raven Support
@ 2017-05-10 18:45 Alex Deucher
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:45 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
This patch set adds support for the new "Raven" APU.
The first 12 patches add support for the new ACP
audio hardware on Raven. Patches 11 and 12 are not
meant for upstream, they are for early hardware testing.
The rest add GPU support. Patches 17-24 are register
headers (which are relatively large), so I'm not sending
them out.
You can view the whole patch set here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
Alex Deucher (12):
drm/amdgpu: add gpu_info firmware (v3)
drm/amdgpu: parse the gpu_info firmware (v4)
drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
drm/amdgpu: add register headers for DCN 1.0
drm/amdgpu: add register headers for GC 9.1
drm/amdgpu: add register headers for MMHUB 9.1
drm/amdgpu: add register headers for MP 10.0
drm/amdgpu: add register headers for NBIO 7.0
drm/amdgpu: add register headers for SDMA 4.1
drm/amdgpu: add register headers for THM 10.0
drm/amdgpu: add register headers for VCN 1.0
drm/amdgpu/raven: power up/down VCN via the SMU (v2)
Andrey Grodzovsky (1):
drm/amd: Add DCN ivsrcids (v2)
Chunming Zhou (17):
drm/amdgpu: add RAVEN family id definition
drm/amdgpu: add Raven ip blocks
drm/amdgpu/soc15: add Raven golden setting
drm/amdgpu: add Raven chip id case for ucode
drm/amdgpu: add module firmware for raven
drm/amdgpu: add gc9.1 golden setting (v2)
drm/amdgpu/gfx9: add chip name for raven when initializing microcode
drm/amdgpu/gfx9: add raven gfx config
drm/amdgpu: add raven case for gmc9 golden setting
drm/amdgpu/gmc9: set mc vm fb offset for raven
drm/amdgpu/gmc9: change fb offset sequence so that used wider
drm/amdgpu: add Raven sdma golden setting and chip id case
drm/amdgpu: add nbio7 support
drm/amdgpu: apply nbio7 for Raven (v3)
drm/amd/powerplay/rv: power up/down sdma via the SMU
drm/amdgpu/powerplay/raven: add smu block and enable powerplay
drm/amdgpu: add RAVEN pci id
Harry Wentland (7):
drm/amdgpu/display: Add calcs code for DCN
drm/amdgpu/display: Add core dc support for DCN
drm/amdgpu/display: Add dml support for DCN
drm/amdgpu/display: Add gpio support for DCN
drm/amdgpu/display: Add i2c/aux support for DCN
drm/amdgpu/display: Add irq support for DCN
drm/amdgpu/display: Enable DCN in DC
Hawking Zhang (13):
drm/amd/amdgpu: fill in raven case in soc15 early init
drm/amdgpu/gfx9: extend rlc fw setup
drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
drm/amdgpu: correct gfx9 csb size
drm/amdgpu/gfx9: add rlc bo init/fini
drm/amdgpu/gfx9: rlc save&restore list programming
drm/amdgpu: init gfx power gating on raven
drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
drm/amdgpu/gfx9: allow updating gfx cgpg state
drm/amdgpu/gfx9: allow updating gfx mgpg state
drm/amdgpu: enable dcn1.0 dc support on raven
Huang Rui (17):
drm/amdgpu/soc15: add clock gating functions for raven
drm/amdgpu: enable soc15 clock gating flags for raven
drm/amdgpu: add gfx clock gating for raven
drm/amdgpu: add raven clock gating and light sleep for mmhub
drm/amdgpu: enable MC MGCG and LS for raven
drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
drm/amdgpu: enable sdma v4 MGCG and LS for raven
drm/amdgpu: init sdma power gating for raven
drm/amdgpu/sdma4: add dynamic power gating for raven
drm/amdgpu: enable sdma power gating for raven
drm/amdgpu: add nbio MGCG for raven
drm/amdgpu: add psp v10 function callback for raven
drm/amdgpu: add psp v10 ip block
drm/amdgpu: register the psp v10 function pointers at psp sw_init
drm/amdgpu/soc15: add psp ip block
drm/amdgpu/vcn: add sw clock gating
drm/amdgpu: enable sw clock gating for vcn
Leo Liu (32):
drm/amdgpu: add initial vcn support and decode tests
drm/amdgpu: add encode tests for vcn
drm/amdgpu: add vcn ip block functions (v2)
drm/amdgpu: add vcn decode ring support
drm/amdgpu: add vcn decode ring type and functions
drm/amdgpu: add vcn irq functions
drm/amdgpu: add vcn ip block and type
drm/amdgpu: move amdgpu_vcn structure to vcn header
drm/amdgpu: re-group the functions in amdgpu_vcn.c
drm/amdgpu: move vcn ring test to amdgpu_vcn.c
drm/amdgpu: expose vcn RB command
drm/amdgpu: add a ring func for vcn start command
drm/amdgpu: implement vcn start RB command
drm/amdgpu: implement insert end ring function for vcn decode
drm/amdgpu/vcn: implement ib tests with new message buffer interface
uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
drm/amdgpu: Disable uvd and vce free handles for raven
drm/amdgpu: implement new vcn cache window programming
drm/amdgpu: add vcn ip block to soc15
drm/amdgpu: change vcn dec rb command specific for decode
drm/amdgpu: add vcn enc rings
drm/amdgpu: add vcn enc ring type and functions
drm/amdgpu: add vcn enc irq support
drm/amdgpu: enable vcn encode ring tests
drm/amdgpu: add vcn enc ib test
drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
drm/amdgpu: add vcn firmware header offset
drm/amdgpu: update vcn decode create msg
Maruthi Srinivas Bayyavarapu (12):
ASoC: AMD: add ACP 3.x IP register header
ASoC: AMD: add ACP3.0 PCI driver
ASoC: AMD: create ACP3x PCM platform device
ASoC: AMD: add ACP3x PCM platform driver
ASoC: AMD: handle ACP3x i2s watermark interrupt
ASoC: AMD: add ACP3x PCM driver DMA ops
ASoC: AMD: add ACP3x i2s ops
ASoC: AMD: add ACP3x TDM mode support
ASoC: AMD: Add ACP3x runtime pm ops
ASoC: AMD: Add ACP3x system resume pm op
ASoC: AMD: enable ACP3x drivers build
ASoC: AMD: create/add dummy codec and machine devices/drivers
Rex Zhu (5):
drm/amdgpu/powerplay: add header file for smu10. (v2)
drm/amdgpu: add raven related define in pptable.h.
drm/amd/powerplay: add ppt_v3 define
drm/amd/powerplay: add raven support in smumgr. (v2)
drm/amd/powerplay: add raven support in hwmgr. (v2)
Vijendar Mukunda (1):
soc/amd/raven: Disabling TDM mode flag
drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 111 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 654 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 77 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 793 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 25 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 128 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 103 +-
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1190 +
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +-
drivers/gpu/drm/amd/display/Kconfig | 7 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
drivers/gpu/drm/amd/display/dc/Makefile | 5 +
.../amd/display/dc/bios/command_table_helper2.c | 5 +
drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 +
drivers/gpu/drm/amd/display/dc/dc.h | 18 +
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +
.../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 +
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 +
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
.../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +
.../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +
drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +
.../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
.../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 +
.../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
.../drm/amd/display/dc/dml/display_mode_structs.h | 429 +
.../drm/amd/display/dc/dml/display_mode_support.c | 2326 +
.../drm/amd/display/dc/dml/display_mode_support.h | 199 +
.../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +
.../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
.../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +
.../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 +
.../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +
.../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
.../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +
.../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
.../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 +
.../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
.../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
.../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 +
.../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 +
.../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +
.../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 +
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
.../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +
.../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 +
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 +
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 +
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 +
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
.../drm/amd/display/dc/inc/hw/timing_generator.h | 16 +
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +
.../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 +
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
drivers/gpu/drm/amd/include/amd_shared.h | 4 +-
.../include/asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ++
.../include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 14087 +++
.../include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 54316 ++++++++
.../include/asic_reg/raven1/GC/gc_9_1_default.h | 4005 +
.../amd/include/asic_reg/raven1/GC/gc_9_1_offset.h | 7491 ++
.../include/asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 +++++
.../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 +
.../asic_reg/raven1/MMHUB/mmhub_9_1_offset.h | 1999 +
.../asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h | 9790 ++
.../include/asic_reg/raven1/MP/mp_10_0_default.h | 182 +
.../include/asic_reg/raven1/MP/mp_10_0_offset.h | 336 +
.../include/asic_reg/raven1/MP/mp_10_0_sh_mask.h | 886 +
.../asic_reg/raven1/NBIO/nbio_7_0_default.h | 14865 +++
.../include/asic_reg/raven1/NBIO/nbio_7_0_offset.h | 4640 +
.../asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h | 118945 ++++++++++++++++++
.../asic_reg/raven1/SDMA0/sdma0_4_1_default.h | 242 +
.../asic_reg/raven1/SDMA0/sdma0_4_1_offset.h | 459 +
.../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 +
.../include/asic_reg/raven1/THM/thm_10_0_default.h | 141 +
.../include/asic_reg/raven1/THM/thm_10_0_offset.h | 257 +
.../include/asic_reg/raven1/THM/thm_10_0_sh_mask.h | 885 +
.../include/asic_reg/raven1/VCN/vcn_1_0_default.h | 202 +
.../include/asic_reg/raven1/VCN/vcn_1_0_offset.h | 376 +
.../include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h | 1308 +
.../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 +
drivers/gpu/drm/amd/include/pptable.h | 57 +-
drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
.../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +
drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +
drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +
.../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +
drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 399 +
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 +
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
include/uapi/drm/amdgpu_drm.h | 5 +-
sound/soc/amd/Kconfig | 4 +
sound/soc/amd/Makefile | 1 +
sound/soc/amd/raven/Makefile | 8 +
sound/soc/amd/raven/acp3x-dummy5102.c | 136 +
sound/soc/amd/raven/acp3x-pcm-dma.c | 805 +
sound/soc/amd/raven/acp3x.h | 34 +
sound/soc/amd/raven/chip_offset_byte.h | 655 +
sound/soc/amd/raven/dummy-w5102.c | 102 +
sound/soc/amd/raven/pci-acp3x.c | 189 +
175 files changed, 314946 insertions(+), 121 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
create mode 100644 sound/soc/amd/raven/Makefile
create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
create mode 100644 sound/soc/amd/raven/acp3x.h
create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
create mode 100644 sound/soc/amd/raven/dummy-w5102.c
create mode 100644 sound/soc/amd/raven/pci-acp3x.c
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH 001/117] ASoC: AMD: add ACP 3.x IP register header
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 002/117] ASoC: AMD: add ACP3.0 PCI driver Alex Deucher
` (108 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP 3.x is a new audio block in raven. Added register header
of the same.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/chip_offset_byte.h | 655 +++++++++++++++++++++++++++++++++
1 file changed, 655 insertions(+)
create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
diff --git a/sound/soc/amd/raven/chip_offset_byte.h b/sound/soc/amd/raven/chip_offset_byte.h
new file mode 100644
index 0000000..3ce4c36
--- /dev/null
+++ b/sound/soc/amd/raven/chip_offset_byte.h
@@ -0,0 +1,655 @@
+/*
+ * ACP 3.0 Register documentation
+ *
+ * Copyright (C) 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _acp_ip_OFFSET_HEADER
+#define _acp_ip_OFFSET_HEADER
+// Registers from ACP_DMA block
+
+#define mmACP_DMA_CNTL_0 0x1240000
+#define mmACP_DMA_CNTL_1 0x1240004
+#define mmACP_DMA_CNTL_2 0x1240008
+#define mmACP_DMA_CNTL_3 0x124000C
+#define mmACP_DMA_CNTL_4 0x1240010
+#define mmACP_DMA_CNTL_5 0x1240014
+#define mmACP_DMA_CNTL_6 0x1240018
+#define mmACP_DMA_CNTL_7 0x124001C
+#define mmACP_DMA_DSCR_STRT_IDX_0 0x1240020
+#define mmACP_DMA_DSCR_STRT_IDX_1 0x1240024
+#define mmACP_DMA_DSCR_STRT_IDX_2 0x1240028
+#define mmACP_DMA_DSCR_STRT_IDX_3 0x124002C
+#define mmACP_DMA_DSCR_STRT_IDX_4 0x1240030
+#define mmACP_DMA_DSCR_STRT_IDX_5 0x1240034
+#define mmACP_DMA_DSCR_STRT_IDX_6 0x1240038
+#define mmACP_DMA_DSCR_STRT_IDX_7 0x124003C
+#define mmACP_DMA_DSCR_CNT_0 0x1240040
+#define mmACP_DMA_DSCR_CNT_1 0x1240044
+#define mmACP_DMA_DSCR_CNT_2 0x1240048
+#define mmACP_DMA_DSCR_CNT_3 0x124004C
+#define mmACP_DMA_DSCR_CNT_4 0x1240050
+#define mmACP_DMA_DSCR_CNT_5 0x1240054
+#define mmACP_DMA_DSCR_CNT_6 0x1240058
+#define mmACP_DMA_DSCR_CNT_7 0x124005C
+#define mmACP_DMA_PRIO_0 0x1240060
+#define mmACP_DMA_PRIO_1 0x1240064
+#define mmACP_DMA_PRIO_2 0x1240068
+#define mmACP_DMA_PRIO_3 0x124006C
+#define mmACP_DMA_PRIO_4 0x1240070
+#define mmACP_DMA_PRIO_5 0x1240074
+#define mmACP_DMA_PRIO_6 0x1240078
+#define mmACP_DMA_PRIO_7 0x124007C
+#define mmACP_DMA_CUR_DSCR_0 0x1240080
+#define mmACP_DMA_CUR_DSCR_1 0x1240084
+#define mmACP_DMA_CUR_DSCR_2 0x1240088
+#define mmACP_DMA_CUR_DSCR_3 0x124008C
+#define mmACP_DMA_CUR_DSCR_4 0x1240090
+#define mmACP_DMA_CUR_DSCR_5 0x1240094
+#define mmACP_DMA_CUR_DSCR_6 0x1240098
+#define mmACP_DMA_CUR_DSCR_7 0x124009C
+#define mmACP_DMA_CUR_TRANS_CNT_0 0x12400A0
+#define mmACP_DMA_CUR_TRANS_CNT_1 0x12400A4
+#define mmACP_DMA_CUR_TRANS_CNT_2 0x12400A8
+#define mmACP_DMA_CUR_TRANS_CNT_3 0x12400AC
+#define mmACP_DMA_CUR_TRANS_CNT_4 0x12400B0
+#define mmACP_DMA_CUR_TRANS_CNT_5 0x12400B4
+#define mmACP_DMA_CUR_TRANS_CNT_6 0x12400B8
+#define mmACP_DMA_CUR_TRANS_CNT_7 0x12400BC
+#define mmACP_DMA_ERR_STS_0 0x12400C0
+#define mmACP_DMA_ERR_STS_1 0x12400C4
+#define mmACP_DMA_ERR_STS_2 0x12400C8
+#define mmACP_DMA_ERR_STS_3 0x12400CC
+#define mmACP_DMA_ERR_STS_4 0x12400D0
+#define mmACP_DMA_ERR_STS_5 0x12400D4
+#define mmACP_DMA_ERR_STS_6 0x12400D8
+#define mmACP_DMA_ERR_STS_7 0x12400DC
+#define mmACP_DMA_DESC_BASE_ADDR 0x12400E0
+#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4
+#define mmACP_DMA_CH_STS 0x12400E8
+#define mmACP_DMA_CH_GROUP 0x12400EC
+#define mmACP_DMA_CH_RST_STS 0x12400F0
+
+
+// Registers from ACP_AXI2AXIATU block
+
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34
+#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38
+#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C
+#define mmACPAXI2AXI_ATU_CTRL 0x1240C40
+
+
+// Registers from ACP_CLKRST block
+
+#define mmACP_SOFT_RESET 0x1241000
+#define mmACP_CONTROL 0x1241004
+#define mmACP_STATUS 0x1241008
+#define mmACP_DSP0_OCD_HALT_ON_RST 0x124100C
+#define mmACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010
+
+
+// Registers from ACP_MISC block
+
+#define mmACP_EXTERNAL_INTR_ENB 0x1241800
+#define mmACP_EXTERNAL_INTR_CNTL 0x1241804
+#define mmACP_EXTERNAL_INTR_STAT 0x1241808
+#define mmACP_DSP0_INTR_CNTL 0x124180C
+#define mmACP_DSP0_INTR_STAT 0x1241810
+#define mmACP_DSP_SW_INTR_CNTL 0x1241814
+#define mmACP_DSP_SW_INTR_STAT 0x1241818
+#define mmACP_SW_INTR_TRIG 0x124181C
+#define mmACP_SMU_MAILBOX 0x1241820
+#define mmDSP_INTERRUPT_ROUTING_CTRL 0x1241824
+#define mmACP_DSP0_WATCHDOG_TIMER_CNTL 0x1241828
+#define mmACP_DSP0_EXT_TIMER1_CNTL 0x124182C
+#define mmACP_DSP0_EXT_TIMER2_CNTL 0x1241830
+#define mmACP_DSP0_EXT_TIMER3_CNTL 0x1241834
+#define mmACP_DSP0_EXT_TIMER4_CNTL 0x1241838
+#define mmACP_DSP0_EXT_TIMER5_CNTL 0x124183C
+#define mmACP_DSP0_EXT_TIMER6_CNTL 0x1241840
+#define mmACP_DSP0_EXT_TIMER1_CURR_VALUE 0x1241844
+#define mmACP_DSP0_EXT_TIMER2_CURR_VALUE 0x1241848
+#define mmACP_DSP0_EXT_TIMER3_CURR_VALUE 0x124184C
+#define mmACP_DSP0_EXT_TIMER4_CURR_VALUE 0x1241850
+#define mmACP_DSP0_EXT_TIMER5_CURR_VALUE 0x1241854
+#define mmACP_DSP0_EXT_TIMER6_CURR_VALUE 0x1241858
+#define mmACP_FW_STATUS 0x124185C
+#define mmACP_TIMER 0x1241874
+#define mmACP_TIMER_CNTL 0x1241878
+#define mmACP_PGMEM_CTRL 0x12418C0
+#define mmACP_ERROR_STATUS 0x12418C4
+#define mmACP_SW_I2S_ERROR_REASON 0x12418C8
+#define mmACP_MEM_PG_STS 0x12418CC
+
+
+// Registers from ACP_PGFSM block
+
+#define mmACP_I2S_PIN_CONFIG 0x1241400
+#define mmACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404
+#define mmACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408
+#define mmACP_SW_PAD_KEEPER_EN 0x124140C
+#define mmACP_SW_WAKE_EN 0x1241410
+#define mmACP_I2S_WAKE_EN 0x1241414
+#define mmACP_PME_EN 0x1241418
+#define mmACP_PGFSM_CONTROL 0x124141C
+#define mmACP_PGFSM_STATUS 0x1241420
+
+
+// Registers from ACP_SCRATCH block
+
+#define mmACP_SCRATCH_REG_0 0x1250000
+#define mmACP_SCRATCH_REG_1 0x1250004
+#define mmACP_SCRATCH_REG_2 0x1250008
+#define mmACP_SCRATCH_REG_3 0x125000C
+#define mmACP_SCRATCH_REG_4 0x1250010
+#define mmACP_SCRATCH_REG_5 0x1250014
+#define mmACP_SCRATCH_REG_6 0x1250018
+#define mmACP_SCRATCH_REG_7 0x125001C
+#define mmACP_SCRATCH_REG_8 0x1250020
+#define mmACP_SCRATCH_REG_9 0x1250024
+#define mmACP_SCRATCH_REG_10 0x1250028
+#define mmACP_SCRATCH_REG_11 0x125002C
+#define mmACP_SCRATCH_REG_12 0x1250030
+#define mmACP_SCRATCH_REG_13 0x1250034
+#define mmACP_SCRATCH_REG_14 0x1250038
+#define mmACP_SCRATCH_REG_15 0x125003C
+#define mmACP_SCRATCH_REG_16 0x1250040
+#define mmACP_SCRATCH_REG_17 0x1250044
+#define mmACP_SCRATCH_REG_18 0x1250048
+#define mmACP_SCRATCH_REG_19 0x125004C
+#define mmACP_SCRATCH_REG_20 0x1250050
+#define mmACP_SCRATCH_REG_21 0x1250054
+#define mmACP_SCRATCH_REG_22 0x1250058
+#define mmACP_SCRATCH_REG_23 0x125005C
+#define mmACP_SCRATCH_REG_24 0x1250060
+#define mmACP_SCRATCH_REG_25 0x1250064
+#define mmACP_SCRATCH_REG_26 0x1250068
+#define mmACP_SCRATCH_REG_27 0x125006C
+#define mmACP_SCRATCH_REG_28 0x1250070
+#define mmACP_SCRATCH_REG_29 0x1250074
+#define mmACP_SCRATCH_REG_30 0x1250078
+#define mmACP_SCRATCH_REG_31 0x125007C
+#define mmACP_SCRATCH_REG_32 0x1250080
+#define mmACP_SCRATCH_REG_33 0x1250084
+#define mmACP_SCRATCH_REG_34 0x1250088
+#define mmACP_SCRATCH_REG_35 0x125008C
+#define mmACP_SCRATCH_REG_36 0x1250090
+#define mmACP_SCRATCH_REG_37 0x1250094
+#define mmACP_SCRATCH_REG_38 0x1250098
+#define mmACP_SCRATCH_REG_39 0x125009C
+#define mmACP_SCRATCH_REG_40 0x12500A0
+#define mmACP_SCRATCH_REG_41 0x12500A4
+#define mmACP_SCRATCH_REG_42 0x12500A8
+#define mmACP_SCRATCH_REG_43 0x12500AC
+#define mmACP_SCRATCH_REG_44 0x12500B0
+#define mmACP_SCRATCH_REG_45 0x12500B4
+#define mmACP_SCRATCH_REG_46 0x12500B8
+#define mmACP_SCRATCH_REG_47 0x12500BC
+#define mmACP_SCRATCH_REG_48 0x12500C0
+#define mmACP_SCRATCH_REG_49 0x12500C4
+#define mmACP_SCRATCH_REG_50 0x12500C8
+#define mmACP_SCRATCH_REG_51 0x12500CC
+#define mmACP_SCRATCH_REG_52 0x12500D0
+#define mmACP_SCRATCH_REG_53 0x12500D4
+#define mmACP_SCRATCH_REG_54 0x12500D8
+#define mmACP_SCRATCH_REG_55 0x12500DC
+#define mmACP_SCRATCH_REG_56 0x12500E0
+#define mmACP_SCRATCH_REG_57 0x12500E4
+#define mmACP_SCRATCH_REG_58 0x12500E8
+#define mmACP_SCRATCH_REG_59 0x12500EC
+#define mmACP_SCRATCH_REG_60 0x12500F0
+#define mmACP_SCRATCH_REG_61 0x12500F4
+#define mmACP_SCRATCH_REG_62 0x12500F8
+#define mmACP_SCRATCH_REG_63 0x12500FC
+#define mmACP_SCRATCH_REG_64 0x1250100
+#define mmACP_SCRATCH_REG_65 0x1250104
+#define mmACP_SCRATCH_REG_66 0x1250108
+#define mmACP_SCRATCH_REG_67 0x125010C
+#define mmACP_SCRATCH_REG_68 0x1250110
+#define mmACP_SCRATCH_REG_69 0x1250114
+#define mmACP_SCRATCH_REG_70 0x1250118
+#define mmACP_SCRATCH_REG_71 0x125011C
+#define mmACP_SCRATCH_REG_72 0x1250120
+#define mmACP_SCRATCH_REG_73 0x1250124
+#define mmACP_SCRATCH_REG_74 0x1250128
+#define mmACP_SCRATCH_REG_75 0x125012C
+#define mmACP_SCRATCH_REG_76 0x1250130
+#define mmACP_SCRATCH_REG_77 0x1250134
+#define mmACP_SCRATCH_REG_78 0x1250138
+#define mmACP_SCRATCH_REG_79 0x125013C
+#define mmACP_SCRATCH_REG_80 0x1250140
+#define mmACP_SCRATCH_REG_81 0x1250144
+#define mmACP_SCRATCH_REG_82 0x1250148
+#define mmACP_SCRATCH_REG_83 0x125014C
+#define mmACP_SCRATCH_REG_84 0x1250150
+#define mmACP_SCRATCH_REG_85 0x1250154
+#define mmACP_SCRATCH_REG_86 0x1250158
+#define mmACP_SCRATCH_REG_87 0x125015C
+#define mmACP_SCRATCH_REG_88 0x1250160
+#define mmACP_SCRATCH_REG_89 0x1250164
+#define mmACP_SCRATCH_REG_90 0x1250168
+#define mmACP_SCRATCH_REG_91 0x125016C
+#define mmACP_SCRATCH_REG_92 0x1250170
+#define mmACP_SCRATCH_REG_93 0x1250174
+#define mmACP_SCRATCH_REG_94 0x1250178
+#define mmACP_SCRATCH_REG_95 0x125017C
+#define mmACP_SCRATCH_REG_96 0x1250180
+#define mmACP_SCRATCH_REG_97 0x1250184
+#define mmACP_SCRATCH_REG_98 0x1250188
+#define mmACP_SCRATCH_REG_99 0x125018C
+#define mmACP_SCRATCH_REG_100 0x1250190
+#define mmACP_SCRATCH_REG_101 0x1250194
+#define mmACP_SCRATCH_REG_102 0x1250198
+#define mmACP_SCRATCH_REG_103 0x125019C
+#define mmACP_SCRATCH_REG_104 0x12501A0
+#define mmACP_SCRATCH_REG_105 0x12501A4
+#define mmACP_SCRATCH_REG_106 0x12501A8
+#define mmACP_SCRATCH_REG_107 0x12501AC
+#define mmACP_SCRATCH_REG_108 0x12501B0
+#define mmACP_SCRATCH_REG_109 0x12501B4
+#define mmACP_SCRATCH_REG_110 0x12501B8
+#define mmACP_SCRATCH_REG_111 0x12501BC
+#define mmACP_SCRATCH_REG_112 0x12501C0
+#define mmACP_SCRATCH_REG_113 0x12501C4
+#define mmACP_SCRATCH_REG_114 0x12501C8
+#define mmACP_SCRATCH_REG_115 0x12501CC
+#define mmACP_SCRATCH_REG_116 0x12501D0
+#define mmACP_SCRATCH_REG_117 0x12501D4
+#define mmACP_SCRATCH_REG_118 0x12501D8
+#define mmACP_SCRATCH_REG_119 0x12501DC
+#define mmACP_SCRATCH_REG_120 0x12501E0
+#define mmACP_SCRATCH_REG_121 0x12501E4
+#define mmACP_SCRATCH_REG_122 0x12501E8
+#define mmACP_SCRATCH_REG_123 0x12501EC
+#define mmACP_SCRATCH_REG_124 0x12501F0
+#define mmACP_SCRATCH_REG_125 0x12501F4
+#define mmACP_SCRATCH_REG_126 0x12501F8
+#define mmACP_SCRATCH_REG_127 0x12501FC
+#define mmACP_SCRATCH_REG_128 0x1250200
+
+
+// Registers from ACP_SW_ACLK block
+
+#define mmSW_CORB_Base_Address 0x1243200
+#define mmSW_CORB_Write_Pointer 0x1243204
+#define mmSW_CORB_Read_Pointer 0x1243208
+#define mmSW_CORB_Control 0x124320C
+#define mmSW_CORB_Size 0x1243214
+#define mmSW_RIRB_Base_Address 0x1243218
+#define mmSW_RIRB_Write_Pointer 0x124321C
+#define mmSW_RIRB_Response_Interrupt_Count 0x1243220
+#define mmSW_RIRB_Control 0x1243224
+#define mmSW_RIRB_Size 0x1243228
+#define mmSW_RIRB_FIFO_MIN_THDL 0x124322C
+#define mmSW_imm_cmd_UPPER_WORD 0x1243230
+#define mmSW_imm_cmd_LOWER_QWORD 0x1243234
+#define mmSW_imm_resp_UPPER_WORD 0x1243238
+#define mmSW_imm_resp_LOWER_QWORD 0x124323C
+#define mmSW_imm_cmd_sts 0x1243240
+#define mmSW_BRA_BASE_ADDRESS 0x1243244
+#define mmSW_BRA_TRANSFER_SIZE 0x1243248
+#define mmSW_BRA_DMA_BUSY 0x124324C
+#define mmSW_BRA_RESP 0x1243250
+#define mmSW_BRA_RESP_FRAME_ADDR 0x1243254
+#define mmSW_BRA_CURRENT_TRANSFER_SIZE 0x1243258
+#define mmSW_STATE_CHANGE_STATUS_0TO7 0x124325C
+#define mmSW_STATE_CHANGE_STATUS_8TO11 0x1243260
+#define mmSW_STATE_CHANGE_STATUS_MASK_0to7 0x1243264
+#define mmSW_STATE_CHANGE_STATUS_MASK_8to11 0x1243268
+#define mmSW_CLK_FREQUENCY_CTRL 0x124326C
+#define mmSW_ERROR_INTR_MASK 0x1243270
+#define mmSW_PHY_TEST_MODE_DATA_OFF 0x1243274
+
+
+// Registers from ACP_SW_SWCLK block
+
+#define mmACP_SW_EN 0x1243000
+#define mmACP_SW_EN_STATUS 0x1243004
+#define mmACP_SW_FRAMESIZE 0x1243008
+#define mmACP_SW_SSP_Counter 0x124300C
+#define mmACP_SW_Audio_TX_EN 0x1243010
+#define mmACP_SW_Audio_TX_EN_STATUS 0x1243014
+#define mmACP_SW_Audio_TX_Frame_Format 0x1243018
+#define mmACP_SW_Audio_TX_SampleInterval 0x124301C
+#define mmACP_SW_Audio_TX_Hctrl_DP0 0x1243020
+#define mmACP_SW_Audio_TX_Hctrl_DP1 0x1243024
+#define mmACP_SW_Audio_TX_Hctrl_DP2 0x1243028
+#define mmACP_SW_Audio_TX_Hctrl_DP3 0x124302C
+#define mmACP_SW_Audio_TX_offset_DP0 0x1243030
+#define mmACP_SW_Audio_TX_offset_DP1 0x1243034
+#define mmACP_SW_Audio_TX_offset_DP2 0x1243038
+#define mmACP_SW_Audio_TX_offset_DP3 0x124303C
+#define mmACP_SW_Audio_TX_Channel_Enable_DP0 0x1243040
+#define mmACP_SW_Audio_TX_Channel_Enable_DP1 0x1243044
+#define mmACP_SW_Audio_TX_Channel_Enable_DP2 0x1243048
+#define mmACP_SW_Audio_TX_Channel_Enable_DP3 0x124304C
+#define mmACP_SW_BT_TX_EN 0x1243050
+#define mmACP_SW_BT_TX_EN_STATUS 0x1243054
+#define mmACP_SW_BT_TX_Frame_Format 0x1243058
+#define mmACP_SW_BT_TX_SampleInterval 0x124305C
+#define mmACP_SW_BT_TX_Hctrl 0x1243060
+#define mmACP_SW_BT_TX_offset 0x1243064
+#define mmACP_SW_BT_TX_Channel_Enable_DP0 0x1243068
+#define mmACP_SW_Headset_TX_EN 0x124306C
+#define mmACP_SW_Headset_TX_EN_STATUS 0x1243070
+#define mmACP_SW_Headset_TX_Frame_Format 0x1243074
+#define mmACP_SW_Headset_TX_SampleInterval 0x1243078
+#define mmACP_SW_Headset_TX_Hctrl 0x124307C
+#define mmACP_SW_Headset_TX_offset 0x1243080
+#define mmACP_SW_Headset_TX_Channel_Enable_DP0 0x1243084
+#define mmACP_SW_Audio_RX_EN 0x1243088
+#define mmACP_SW_Audio_RX_EN_STATUS 0x124308C
+#define mmACP_SW_Audio_RX_Frame_Format 0x1243090
+#define mmACP_SW_Audio_RX_SampleInterval 0x1243094
+#define mmACP_SW_Audio_RX_Hctrl_DP0 0x1243098
+#define mmACP_SW_Audio_RX_Hctrl_DP1 0x124309C
+#define mmACP_SW_Audio_RX_Hctrl_DP2 0x1243100
+#define mmACP_SW_Audio_RX_Hctrl_DP3 0x1243104
+#define mmACP_SW_Audio_RX_offset_DP0 0x1243108
+#define mmACP_SW_Audio_RX_offset_DP1 0x124310C
+#define mmACP_SW_Audio_RX_offset_DP2 0x1243110
+#define mmACP_SW_Audio_RX_offset_DP3 0x1243114
+#define mmACP_SW_Audio_RX_Channel_Enable_DP0 0x1243118
+#define mmACP_SW_Audio_RX_Channel_Enable_DP1 0x124311C
+#define mmACP_SW_Audio_RX_Channel_Enable_DP2 0x1243120
+#define mmACP_SW_Audio_RX_Channel_Enable_DP3 0x1243124
+#define mmACP_SW_BT_RX_EN 0x1243128
+#define mmACP_SW_BT_RX_EN_STATUS 0x124312C
+#define mmACP_SW_BT_RX_Frame_Format 0x1243130
+#define mmACP_SW_BT_RX_SampleInterval 0x1243134
+#define mmACP_SW_BT_RX_Hctrl 0x1243138
+#define mmACP_SW_BT_RX_offset 0x124313C
+#define mmACP_SW_BT_RX_Channel_Enable_DP0 0x1243140
+#define mmACP_SW_Headset_RX_EN 0x1243144
+#define mmACP_SW_Headset_RX_EN_STATUS 0x1243148
+#define mmACP_SW_Headset_RX_Frame_Format 0x124314C
+#define mmACP_SW_Headset_RX_SampleInterval 0x1243150
+#define mmACP_SW_Headset_RX_Hctrl 0x1243154
+#define mmACP_SW_Headset_RX_offset 0x1243158
+#define mmACP_SW_Headset_RX_Channel_Enable_DP0 0x124315C
+#define mmACP_SW_BPT_PORT_EN 0x1243160
+#define mmACP_SW_BPT_PORT_EN_STATUS 0x1243164
+#define mmACP_SW_BPT_PORT_Frame_Format 0x1243168
+#define mmACP_SW_BPT_PORT_SampleInterval 0x124316C
+#define mmACP_SW_BPT_PORT_Hctrl 0x1243170
+#define mmACP_SW_BPT_PORT_offset 0x1243174
+#define mmACP_SW_BPT_PORT_Channel_Enable 0x1243178
+#define mmACP_SW_BPT_PORT_First_byte_addr 0x124317C
+#define mmACP_SW_CLK_RESUME_CTRL 0x1243180
+#define mmACP_SW_CLK_RESUME_Delay_Cntr 0x1243184
+#define mmACP_SW_BUS_RESET_CTRL 0x1243188
+#define mmACP_SW_PRBS_ERR_STATUS 0x124318C
+
+
+// Registers from ACP_AUDIO_BUFFERS block
+
+#define mmACP_I2S_RX_RINGBUFADDR 0x1242000
+#define mmACP_I2S_RX_RINGBUFSIZE 0x1242004
+#define mmACP_I2S_RX_LINKPOSITIONCNTR 0x1242008
+#define mmACP_I2S_RX_FIFOADDR 0x124200C
+#define mmACP_I2S_RX_FIFOSIZE 0x1242010
+#define mmACP_I2S_RX_DMA_SIZE 0x1242014
+#define mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018
+#define mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C
+#define mmACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020
+#define mmACP_I2S_TX_RINGBUFADDR 0x1242024
+#define mmACP_I2S_TX_RINGBUFSIZE 0x1242028
+#define mmACP_I2S_TX_LINKPOSITIONCNTR 0x124202C
+#define mmACP_I2S_TX_FIFOADDR 0x1242030
+#define mmACP_I2S_TX_FIFOSIZE 0x1242034
+#define mmACP_I2S_TX_DMA_SIZE 0x1242038
+#define mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C
+#define mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040
+#define mmACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044
+#define mmACP_BT_RX_RINGBUFADDR 0x1242048
+#define mmACP_BT_RX_RINGBUFSIZE 0x124204C
+#define mmACP_BT_RX_LINKPOSITIONCNTR 0x1242050
+#define mmACP_BT_RX_FIFOADDR 0x1242054
+#define mmACP_BT_RX_FIFOSIZE 0x1242058
+#define mmACP_BT_RX_DMA_SIZE 0x124205C
+#define mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060
+#define mmACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064
+#define mmACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068
+#define mmACP_BT_TX_RINGBUFADDR 0x124206C
+#define mmACP_BT_TX_RINGBUFSIZE 0x1242070
+#define mmACP_BT_TX_LINKPOSITIONCNTR 0x1242074
+#define mmACP_BT_TX_FIFOADDR 0x1242078
+#define mmACP_BT_TX_FIFOSIZE 0x124207C
+#define mmACP_BT_TX_DMA_SIZE 0x1242080
+#define mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084
+#define mmACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088
+#define mmACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C
+#define mmACP_HS_RX_RINGBUFADDR 0x1242090
+#define mmACP_HS_RX_RINGBUFSIZE 0x1242094
+#define mmACP_HS_RX_LINKPOSITIONCNTR 0x1242098
+#define mmACP_HS_RX_FIFOADDR 0x124209C
+#define mmACP_HS_RX_FIFOSIZE 0x12420A0
+#define mmACP_HS_RX_DMA_SIZE 0x12420A4
+#define mmACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8
+#define mmACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC
+#define mmACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0
+#define mmACP_HS_TX_RINGBUFADDR 0x12420B4
+#define mmACP_HS_TX_RINGBUFSIZE 0x12420B8
+#define mmACP_HS_TX_LINKPOSITIONCNTR 0x12420BC
+#define mmACP_HS_TX_FIFOADDR 0x12420C0
+#define mmACP_HS_TX_FIFOSIZE 0x12420C4
+#define mmACP_HS_TX_DMA_SIZE 0x12420C8
+#define mmACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC
+#define mmACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0
+#define mmACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4
+
+
+// Registers from ACP_I2S_TDM block
+
+#define mmACP_I2STDM_IER 0x1242400
+#define mmACP_I2STDM_IRER 0x1242404
+#define mmACP_I2STDM_RXFRMT 0x1242408
+#define mmACP_I2STDM_ITER 0x124240C
+#define mmACP_I2STDM_TXFRMT 0x1242410
+
+
+// Registers from ACP_BT_TDM block
+
+#define mmACP_BTTDM_IER 0x1242800
+#define mmACP_BTTDM_IRER 0x1242804
+#define mmACP_BTTDM_RXFRMT 0x1242808
+#define mmACP_BTTDM_ITER 0x124280C
+#define mmACP_BTTDM_TXFRMT 0x1242810
+
+
+// Registers from AZALIA_IP block
+
+#define mmAudio_Az_Global_Capabilities 0x1200000
+#define mmAudio_Az_Minor_Version 0x1200002
+#define mmAudio_Az_Major_Version 0x1200003
+#define mmAudio_Az_Output_Payload_Capability 0x1200004
+#define mmAudio_Az_Input_Payload_Capability 0x1200006
+#define mmAudio_Az_Global_Control 0x1200008
+#define mmAudio_Az_Wake_Enable 0x120000C
+#define mmAudio_Az_State_Change_Status 0x120000E
+#define mmAudio_Az_Global_Status 0x1200010
+#define mmAudio_Az_Linked_List_Capability_Header 0x1200014
+#define mmAudio_Az_Output_Stream_Payload_Capability 0x1200018
+#define mmAudio_Az_Input_Stream_Payload_Capability 0x120001A
+#define mmAudio_Az_Interrupt_Control 0x1200020
+#define mmAudio_Az_Interrupt_Status 0x1200024
+#define mmAudio_Az_Wall_Clock_Counter 0x1200030
+#define mmAudio_Az_Stream_Synchronization 0x1200038
+#define mmAudio_Az_CORB_Lower_Base_Address 0x1200040
+#define mmAudio_Az_CORB_Upper_Base_Address 0x1200044
+#define mmAudio_Az_CORB_Write_Pointer 0x1200048
+#define mmAudio_Az_CORB_Read_Pointer 0x120004A
+#define mmAudio_Az_CORB_Control 0x120004C
+#define mmAudio_Az_CORB_Status 0x120004D
+#define mmAudio_Az_CORB_Size 0x120004E
+#define mmAudio_Az_RIRB_Lower_Base_Address 0x1200050
+#define mmAudio_Az_RIRB_Upper_Base_Address 0x1200054
+#define mmAudio_Az_RIRB_Write_Pointer 0x1200058
+#define mmAudio_Az_RIRB_Response_Interrupt_Count 0x120005A
+#define mmAudio_Az_RIRB_Control 0x120005C
+#define mmAudio_Az_RIRB_Status 0x120005D
+#define mmAudio_Az_RIRB_Size 0x120005E
+#define mmAudio_Az_Immediate_Command_Output_Interface 0x1200060
+#define mmAudio_Az_Immediate_Response_Input_Interface 0x1200064
+#define mmAudio_Az_Immediate_Command_Status 0x1200068
+#define mmAudio_Az_DPLBASE 0x1200070
+#define mmAudio_Az_DPUBASE 0x1200074
+#define mmAudio_Az_Input_SD0CTL_and_STS 0x1200080
+#define mmAudio_Az_Input_SD0LPIB 0x1200084
+#define mmAudio_Az_Input_SD0CBL 0x1200088
+#define mmAudio_Az_Input_SD0LVI 0x120008C
+#define mmAudio_Az_Input_SD0FIFOS 0x1200090
+#define mmAudio_Az_Input_SD0FMT 0x1200092
+#define mmAudio_Az_Input_SD0BDPL 0x1200098
+#define mmAudio_Az_Input_SD0BDPU 0x120009C
+#define mmAudio_Az_Input_SD1CTL_and_STS 0x12000A0
+#define mmAudio_Az_Input_SD1LPIB 0x12000A4
+#define mmAudio_Az_Input_SD1CBL 0x12000A8
+#define mmAudio_Az_Input_SD1LVI 0x12000AC
+#define mmAudio_Az_Input_SD1FIFOS 0x12000B0
+#define mmAudio_Az_Input_SD1FMT 0x12000B2
+#define mmAudio_Az_Input_SD1BDPL 0x12000B8
+#define mmAudio_Az_Input_SD1BDPU 0x12000BC
+#define mmAudio_Az_Input_SD2CTL_and_STS 0x12000C0
+#define mmAudio_Az_Input_SD2LPIB 0x12000C4
+#define mmAudio_Az_Input_SD2CBL 0x12000C8
+#define mmAudio_Az_Input_SD2LVI 0x12000CC
+#define mmAudio_Az_Input_SD2FIFOS 0x12000D0
+#define mmAudio_Az_Input_SD2FMT 0x12000D2
+#define mmAudio_Az_Input_SD2BDPL 0x12000D8
+#define mmAudio_Az_Input_SD2BDPU 0x12000DC
+#define mmAudio_Az_Input_SD3CTL_and_STS 0x12000E0
+#define mmAudio_Az_Input_SD3LPIB 0x12000E4
+#define mmAudio_Az_Input_SD3CBL 0x12000E8
+#define mmAudio_Az_Input_SD3LVI 0x12000EC
+#define mmAudio_Az_Input_SD3FIFOS 0x12000F0
+#define mmAudio_Az_Input_SD3FMT 0x12000F2
+#define mmAudio_Az_Input_SD3BDPL 0x12000F8
+#define mmAudio_Az_Input_SD3BDPU 0x12000FC
+#define mmAudio_Az_Output_SD0CTL_and_STS 0x1200100
+#define mmAudio_Az_Output_SD0LPIB 0x1200104
+#define mmAudio_Az_Output_SD0CBL 0x1200108
+#define mmAudio_Az_Output_SD0LVI 0x120010C
+#define mmAudio_Az_Output_SD0FIFOS 0x1200110
+#define mmAudio_Az_Output_SD0FMT 0x1200112
+#define mmAudio_Az_Output_SD0BDPL 0x1200118
+#define mmAudio_Az_Output_SD0BDPU 0x120011C
+#define mmAudio_Az_Output_SD1CTL_and_STS 0x1200120
+#define mmAudio_Az_Output_SD1LPIB 0x1200124
+#define mmAudio_Az_Output_SD1CBL 0x1200128
+#define mmAudio_Az_Output_SD1LVI 0x120012C
+#define mmAudio_Az_Output_SD1FIFOS 0x1200130
+#define mmAudio_Az_Output_SD1FMT 0x1200132
+#define mmAudio_Az_Output_SD1BDPL 0x1200138
+#define mmAudio_Az_Output_SD1BDPU 0x120013C
+#define mmAudio_Az_Output_SD2CTL_and_STS 0x1200140
+#define mmAudio_Az_Output_SD2LPIB 0x1200144
+#define mmAudio_Az_Output_SD2CBL 0x1200148
+#define mmAudio_Az_Output_SD2LVI 0x120014C
+#define mmAudio_Az_Output_SD2FIFOS 0x1200150
+#define mmAudio_Az_Output_SD2FMT 0x1200152
+#define mmAudio_Az_Output_SD2BDPL 0x1200158
+#define mmAudio_Az_Output_SD2BDPU 0x120015C
+#define mmAudio_Az_Output_SD3CTL_and_STS 0x1200160
+#define mmAudio_Az_Output_SD3LPIB 0x1200164
+#define mmAudio_Az_Output_SD3CBL 0x1200168
+#define mmAudio_Az_Output_SD3LVI 0x120016C
+#define mmAudio_Az_Output_SD3FIFOS 0x1200170
+#define mmAudio_Az_Output_SD3FMT 0x1200172
+#define mmAudio_Az_Output_SD3BDPL 0x1200178
+#define mmAudio_Az_Output_SD3BDPU 0x120017C
+#define mmAudioAZ_Misc_Control_Register_1 0x1200180
+#define mmAudioAZ_Misc_Control_Register_2 0x1200182
+#define mmAudioAZ_Misc_Control_Register_3 0x1200183
+#define mmAudio_AZ_Multiple_Links_Capability_Header 0x1200200
+#define mmAudio_AZ_Multiple_Links_Capability_Declaration 0x1200204
+#define mmAudio_AZ_Link0_Capabilities 0x1200240
+#define mmAudio_AZ_Link0_Control 0x1200244
+#define mmAudio_AZ_Link0_Output_Stream_ID 0x1200248
+#define mmAudio_AZ_Link0_SDI_Identifier 0x120024C
+#define mmAudio_AZ_Link0_Per_Stream_Overhead 0x1200250
+#define mmAudio_AZ_Link0_Wall_Frame_Counter 0x1200258
+#define mmAudio_AZ_Link0_Output_Payload_Capability_L 0x1200260
+#define mmAudio_AZ_Link0_Output_Payload_Capability_U 0x1200264
+#define mmAudio_AZ_Link0_Input_Payload_Capability_L 0x1200270
+#define mmAudio_AZ_Link0_Input_Payload_Capability_U 0x1200274
+#define mmAudio_Az_Input_SD0LICBA 0x1202084
+#define mmAudio_Az_Input_SD1LICBA 0x12020A4
+#define mmAudio_Az_Input_SD2LICBA 0x12020C4
+#define mmAudio_Az_Input_SD3LICBA 0x12020E4
+#define mmAudio_Az_Output_SD0LICBA 0x1202104
+#define mmAudio_Az_Output_SD1LICBA 0x1202124
+#define mmAudio_Az_Output_SD2LICBA 0x1202144
+#define mmAudio_Az_Output_SD3LICBA 0x1202164
+#define mmAUDIO_AZ_POWER_MANAGEMENT_CONTROL 0x1204000
+#define mmAUDIO_AZ_IOC_SOFTRST_CONTROL 0x1204004
+#define mmAUDIO_AZ_IOC_CLKGATE_CONTROL 0x1204008
+
+
+// Registers from ACP_AZALIA block
+
+#define mmACP_AZ_PAGE0_LBASE_ADDR 0x1243800
+#define mmACP_AZ_PAGE0_UBASE_ADDR 0x1243804
+#define mmACP_AZ_PAGE0_PGEN_SIZE 0x1243808
+#define mmACP_AZ_PAGE0_OFFSET 0x124380C
+#define mmACP_AZ_PAGE1_LBASE_ADDR 0x1243810
+#define mmACP_AZ_PAGE1_UBASE_ADDR 0x1243814
+#define mmACP_AZ_PAGE1_PGEN_SIZE 0x1243818
+#define mmACP_AZ_PAGE1_OFFSET 0x124381C
+#define mmACP_AZ_PAGE2_LBASE_ADDR 0x1243820
+#define mmACP_AZ_PAGE2_UBASE_ADDR 0x1243824
+#define mmACP_AZ_PAGE2_PGEN_SIZE 0x1243828
+#define mmACP_AZ_PAGE2_OFFSET 0x124382C
+#define mmACP_AZ_PAGE3_LBASE_ADDR 0x1243830
+#define mmACP_AZ_PAGE3_UBASE_ADDR 0x1243834
+#define mmACP_AZ_PAGE3_PGEN_SIZE 0x1243838
+#define mmACP_AZ_PAGE3_OFFSET 0x124383C
+#define mmACP_AZ_PAGE4_LBASE_ADDR 0x1243840
+#define mmACP_AZ_PAGE4_UBASE_ADDR 0x1243844
+#define mmACP_AZ_PAGE4_PGEN_SIZE 0x1243848
+#define mmACP_AZ_PAGE4_OFFSET 0x124384C
+#define mmACP_AZ_PAGE5_LBASE_ADDR 0x1243850
+#define mmACP_AZ_PAGE5_UBASE_ADDR 0x1243854
+#define mmACP_AZ_PAGE5_PGEN_SIZE 0x1243858
+#define mmACP_AZ_PAGE5_OFFSET 0x124385C
+#define mmACP_AZ_PAGE6_LBASE_ADDR 0x1243860
+#define mmACP_AZ_PAGE6_UBASE_ADDR 0x1243864
+#define mmACP_AZ_PAGE6_PGEN_SIZE 0x1243868
+#define mmACP_AZ_PAGE6_OFFSET 0x124386C
+#define mmACP_AZ_PAGE7_LBASE_ADDR 0x1243870
+#define mmACP_AZ_PAGE7_UBASE_ADDR 0x1243874
+#define mmACP_AZ_PAGE7_PGEN_SIZE 0x1243878
+#define mmACP_AZ_PAGE7_OFFSET 0x124387C
+
+
+#endif
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 002/117] ASoC: AMD: add ACP3.0 PCI driver
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2017-05-10 18:46 ` [PATCH 001/117] ASoC: AMD: add ACP 3.x IP register header Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 003/117] ASoC: AMD: create ACP3x PCM platform device Alex Deucher
` (107 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP 3.0 is a PCI audio device. This patch adds PCI driver to bind
to this device and get PCI resources.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x.h | 13 ++++++
sound/soc/amd/raven/pci-acp3x.c | 97 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 sound/soc/amd/raven/acp3x.h
create mode 100644 sound/soc/amd/raven/pci-acp3x.c
diff --git a/sound/soc/amd/raven/acp3x.h b/sound/soc/amd/raven/acp3x.h
new file mode 100644
index 0000000..e9b4df0
--- /dev/null
+++ b/sound/soc/amd/raven/acp3x.h
@@ -0,0 +1,13 @@
+#include "chip_offset_byte.h"
+
+#define ACP3x_PHY_BASE_ADDRESS 0x1240000
+
+static inline u32 rv_readl(void __iomem *base_addr)
+{
+ return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);
+}
+
+static inline void rv_writel(u32 val, void __iomem *base_addr)
+{
+ writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
+}
diff --git a/sound/soc/amd/raven/pci-acp3x.c b/sound/soc/amd/raven/pci-acp3x.c
new file mode 100644
index 0000000..204212b
--- /dev/null
+++ b/sound/soc/amd/raven/pci-acp3x.c
@@ -0,0 +1,97 @@
+/*
+ * AMD ALSA SoC PCM Driver
+ *
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/pci.h>
+#include <linux/module.h>
+
+#include "acp3x.h"
+
+struct acp3x_dev_data {
+ void __iomem *acp3x_base;
+};
+
+static int snd_acp3x_probe(struct pci_dev *pci,
+ const struct pci_device_id *pci_id)
+{
+ int ret;
+ u32 addr;
+ struct acp3x_dev_data *adata;
+
+ if (pci_enable_device(pci)) {
+ dev_err(&pci->dev, "pci_enable_device failed\n");
+ return -ENODEV;
+ }
+
+ ret = pci_request_regions(pci, "AMD ACP3x audio");
+ if (ret < 0) {
+ dev_err(&pci->dev, "pci_request_regions failed\n");
+ goto disable_pci;
+ }
+
+ adata = devm_kzalloc(&pci->dev, sizeof(struct acp3x_dev_data),
+ GFP_KERNEL);
+ if (adata == NULL) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+
+ addr = pci_resource_start(pci, 0);
+ adata->acp3x_base = ioremap(addr, pci_resource_len(pci, 0));
+ if (adata->acp3x_base == NULL) {
+ ret = -ENOMEM;
+ goto release_regions;
+ }
+
+ pci_set_drvdata(pci, adata);
+
+ return 0;
+
+release_regions:
+ pci_release_regions(pci);
+disable_pci:
+ pci_disable_device(pci);
+
+ return ret;
+}
+
+static void snd_acp3x_remove(struct pci_dev *pci)
+{
+ struct acp3x_dev_data *adata = pci_get_drvdata(pci);
+
+ iounmap(adata->acp3x_base);
+ pci_release_regions(pci);
+ pci_disable_device(pci);
+}
+
+static const struct pci_device_id snd_acp3x_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x15e2),
+ .class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
+ .class_mask = 0xffffff },
+ { 0, },
+};
+MODULE_DEVICE_TABLE(pci, snd_acp3x_ids);
+
+static struct pci_driver acp3x_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = snd_acp3x_ids,
+ .probe = snd_acp3x_probe,
+ .remove = snd_acp3x_remove,
+};
+
+module_pci_driver(acp3x_driver);
+
+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
+MODULE_DESCRIPTION("AMD ACP3x PCI driver");
+MODULE_LICENSE("GPL v2");
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 003/117] ASoC: AMD: create ACP3x PCM platform device
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2017-05-10 18:46 ` [PATCH 001/117] ASoC: AMD: add ACP 3.x IP register header Alex Deucher
2017-05-10 18:46 ` [PATCH 002/117] ASoC: AMD: add ACP3.0 PCI driver Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 004/117] ASoC: AMD: add ACP3x PCM platform driver Alex Deucher
` (106 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP 3x IP have I2S controller device as one of IP blocks.
Create a platform device for it, so that PCM platform driver
can be binded to this device. Pass PCI resources like MMIO, irq
to the platform device.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x.h | 3 ++
sound/soc/amd/raven/pci-acp3x.c | 68 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/sound/soc/amd/raven/acp3x.h b/sound/soc/amd/raven/acp3x.h
index e9b4df0..1996faf 100644
--- a/sound/soc/amd/raven/acp3x.h
+++ b/sound/soc/amd/raven/acp3x.h
@@ -1,6 +1,9 @@
#include "chip_offset_byte.h"
#define ACP3x_PHY_BASE_ADDRESS 0x1240000
+#define ACP3x_I2S_MODE 0
+#define ACP3x_REG_START 0x1240000
+#define ACP3x_REG_END 0x1250200
static inline u32 rv_readl(void __iomem *base_addr)
{
diff --git a/sound/soc/amd/raven/pci-acp3x.c b/sound/soc/amd/raven/pci-acp3x.c
index 204212b..a182013 100644
--- a/sound/soc/amd/raven/pci-acp3x.c
+++ b/sound/soc/amd/raven/pci-acp3x.c
@@ -15,19 +15,26 @@
#include <linux/pci.h>
#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
#include "acp3x.h"
struct acp3x_dev_data {
void __iomem *acp3x_base;
+ bool acp3x_audio_mode;
+ struct resource *res;
+ struct platform_device *pdev;
};
static int snd_acp3x_probe(struct pci_dev *pci,
const struct pci_device_id *pci_id)
{
int ret;
- u32 addr;
+ u32 addr, val;
struct acp3x_dev_data *adata;
+ struct platform_device_info pdevinfo;
+ unsigned int irqflags;
if (pci_enable_device(pci)) {
dev_err(&pci->dev, "pci_enable_device failed\n");
@@ -47,6 +54,15 @@ static int snd_acp3x_probe(struct pci_dev *pci,
goto release_regions;
}
+ /* check for msi interrupt support */
+ ret = pci_enable_msi(pci);
+ if (ret)
+ /* msi is not enabled */
+ irqflags = IRQF_SHARED;
+ else
+ /* msi is enabled */
+ irqflags = 0;
+
addr = pci_resource_start(pci, 0);
adata->acp3x_base = ioremap(addr, pci_resource_len(pci, 0));
if (adata->acp3x_base == NULL) {
@@ -56,8 +72,55 @@ static int snd_acp3x_probe(struct pci_dev *pci,
pci_set_drvdata(pci, adata);
+ val = rv_readl(adata->acp3x_base + mmACP_I2S_PIN_CONFIG);
+ if (val == 0x4) {
+ adata->res = devm_kzalloc(&pci->dev,
+ sizeof(struct resource) * 2,
+ GFP_KERNEL);
+ if (adata->res == NULL) {
+ ret = -ENOMEM;
+ goto unmap_mmio;
+ }
+
+ adata->res[0].name = "acp3x_i2s_iomem";
+ adata->res[0].flags = IORESOURCE_MEM;
+ adata->res[0].start = addr;
+ adata->res[0].end = addr + (ACP3x_REG_END - ACP3x_REG_START);
+
+ adata->res[1].name = "acp3x_i2s_irq";
+ adata->res[1].flags = IORESOURCE_IRQ;
+ adata->res[1].start = pci->irq;
+ adata->res[1].end = pci->irq;
+
+ adata->acp3x_audio_mode = ACP3x_I2S_MODE;
+
+ memset(&pdevinfo, 0, sizeof(pdevinfo));
+ pdevinfo.name = "acp3x_rv_i2s";
+ pdevinfo.id = 0;
+ pdevinfo.parent = &pci->dev;
+ pdevinfo.num_res = 2;
+ pdevinfo.res = adata->res;
+ pdevinfo.data = &irqflags;
+ pdevinfo.size_data = sizeof(irqflags);
+
+ adata->pdev = platform_device_register_full(&pdevinfo);
+ if (adata->pdev == NULL) {
+ dev_err(&pci->dev, "cannot register %s device\n",
+ pdevinfo.name);
+ ret = -ENODEV;
+ goto unmap_mmio;
+ }
+ } else {
+ dev_err(&pci->dev, "Inavlid ACP audio mode : %d\n", val);
+ ret = -ENODEV;
+ goto unmap_mmio;
+ }
+
return 0;
+unmap_mmio:
+ pci_disable_msi(pci);
+ iounmap(adata->acp3x_base);
release_regions:
pci_release_regions(pci);
disable_pci:
@@ -70,7 +133,10 @@ static void snd_acp3x_remove(struct pci_dev *pci)
{
struct acp3x_dev_data *adata = pci_get_drvdata(pci);
+ platform_device_unregister(adata->pdev);
iounmap(adata->acp3x_base);
+
+ pci_disable_msi(pci);
pci_release_regions(pci);
pci_disable_device(pci);
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 004/117] ASoC: AMD: add ACP3x PCM platform driver
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 003/117] ASoC: AMD: create ACP3x PCM platform device Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 005/117] ASoC: AMD: handle ACP3x i2s watermark interrupt Alex Deucher
` (105 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
PCM platform driver binds to the platform device creatd by ACP3x PCI
device. PCM driver registers ALSA DMA and CPU DAI components with ASoC
framework.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 278 ++++++++++++++++++++++++++++++++++++
sound/soc/amd/raven/acp3x.h | 3 +
2 files changed, 281 insertions(+)
create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
new file mode 100644
index 0000000..3fd9f86
--- /dev/null
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -0,0 +1,278 @@
+/*
+ * AMD ALSA SoC PCM Driver
+ *
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+
+#include "acp3x.h"
+
+struct i2s_dev_data {
+ void __iomem *acp3x_base;
+ struct snd_pcm_substream *play_stream;
+ struct snd_pcm_substream *capture_stream;
+};
+
+static int acp3x_power_on(void __iomem *acp3x_base, bool on)
+{
+ u16 val, mask;
+ u32 timeout;
+
+ if (on == true) {
+ val = 1;
+ mask = 0;
+ } else {
+ val = 0;
+ mask = 2;
+ }
+
+ rv_writel(val, acp3x_base + mmACP_PGFSM_CONTROL);
+ timeout = 0;
+ while (true) {
+ val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS);
+ if ((val & 0x3) == mask)
+ break;
+ if (timeout > 100) {
+ pr_err("ACP3x power state change failure\n");
+ return -ENODEV;
+ }
+ timeout++;
+ cpu_relax();
+ }
+ return 0;
+}
+
+static int acp3x_reset(void __iomem *acp3x_base)
+{
+ u32 val, timeout;
+
+ rv_writel(1, acp3x_base + mmACP_SOFT_RESET);
+ timeout = 0;
+ while (true) {
+ val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
+ if ((val & 0x00010001) || timeout > 100) {
+ if (val & 0x00010001)
+ break;
+ return -ENODEV;
+ }
+ timeout++;
+ cpu_relax();
+ }
+
+ rv_writel(0, acp3x_base + mmACP_SOFT_RESET);
+ timeout = 0;
+ while (true) {
+ val = rv_readl(acp3x_base + mmACP_SOFT_RESET);
+ if (!val || timeout > 100) {
+ if (!val)
+ break;
+ return -ENODEV;
+ }
+ timeout++;
+ cpu_relax();
+ }
+ return 0;
+}
+
+static int acp3x_init(void __iomem *acp3x_base)
+{
+ int ret;
+
+ /* power on */
+ ret = acp3x_power_on(acp3x_base, true);
+ if (ret) {
+ pr_err("ACP3x power on failed\n");
+ return ret;
+ }
+
+ /* Reset */
+ ret = acp3x_reset(acp3x_base);
+ if (ret) {
+ pr_err("ACP3x reset failed\n");
+ return ret;
+ }
+
+ pr_info("ACP Initialized\n");
+ return 0;
+}
+
+static int acp3x_deinit(void __iomem *acp3x_base)
+{
+ int ret;
+
+ /* Reset */
+ ret = acp3x_reset(acp3x_base);
+ if (ret) {
+ pr_err("ACP3x reset failed\n");
+ return ret;
+ }
+
+ /* power off */
+ ret = acp3x_power_on(acp3x_base, false);
+ if (ret) {
+ pr_err("ACP3x power off failed\n");
+ return ret;
+ }
+
+ pr_info("ACP De-Initialized\n");
+ return 0;
+}
+
+static struct snd_pcm_ops acp3x_dma_ops = {
+ .open = NULL,
+ .close = NULL,
+ .ioctl = NULL,
+ .hw_params = NULL,
+ .hw_free = NULL,
+ .pointer = NULL,
+ .mmap = NULL,
+};
+
+static struct snd_soc_platform_driver acp3x_asoc_platform = {
+ .ops = &acp3x_dma_ops,
+ .pcm_new = NULL,
+};
+
+struct snd_soc_dai_ops acp3x_dai_i2s_ops = {
+ .hw_params = NULL,
+ .trigger = NULL,
+ .set_fmt = NULL,
+};
+
+static struct snd_soc_dai_driver acp3x_i2s_dai_driver = {
+ .playback = {
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 8,
+
+ .rate_min = 8000,
+ .rate_max = 96000,
+ },
+ .capture = {
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ },
+ .ops = &acp3x_dai_i2s_ops,
+};
+
+static const struct snd_soc_component_driver acp3x_i2s_component = {
+ .name = "acp3x_i2s",
+};
+
+static int acp3x_audio_probe(struct platform_device *pdev)
+{
+ int status;
+ struct resource *res;
+ struct i2s_dev_data *adata;
+ unsigned int irqflags;
+
+ if (pdev->dev.platform_data == NULL) {
+ dev_err(&pdev->dev, "platform_data not retrieved\n");
+ return -ENODEV;
+ }
+ irqflags = *((unsigned int *)(pdev->dev.platform_data));
+
+ adata = devm_kzalloc(&pdev->dev, sizeof(struct i2s_dev_data),
+ GFP_KERNEL);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
+ return -ENODEV;
+ }
+
+ adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+
+ adata->play_stream = NULL;
+ adata->capture_stream = NULL;
+
+ dev_set_drvdata(&pdev->dev, adata);
+ /* Initialize ACP */
+ status = acp3x_init(adata->acp3x_base);
+ if (status)
+ return -ENODEV;
+
+ status = snd_soc_register_platform(&pdev->dev, &acp3x_asoc_platform);
+ if (status != 0) {
+ dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
+ goto dev_err;
+ }
+
+ status = devm_snd_soc_register_component(&pdev->dev,
+ &acp3x_i2s_component, &acp3x_i2s_dai_driver, 1);
+ if (status != 0) {
+ dev_err(&pdev->dev, "Fail to register acp i2s dai\n");
+ snd_soc_unregister_platform(&pdev->dev);
+ goto dev_err;
+ }
+
+ return 0;
+dev_err:
+ status = acp3x_deinit(adata->acp3x_base);
+ if (status)
+ dev_err(&pdev->dev, "ACP de-init failed\n");
+ else
+ dev_info(&pdev->dev, "ACP de-initialized\n");
+ /*ignore device status and return driver probe error*/
+ return -ENODEV;
+}
+
+static int acp3x_audio_remove(struct platform_device *pdev)
+{
+ int ret;
+ struct i2s_dev_data *adata = dev_get_drvdata(&pdev->dev);
+
+ snd_soc_unregister_component(&pdev->dev);
+ snd_soc_unregister_platform(&pdev->dev);
+
+ ret = acp3x_deinit(adata->acp3x_base);
+ if (ret)
+ dev_err(&pdev->dev, "ACP de-init failed\n");
+ else
+ dev_info(&pdev->dev, "ACP de-initialized\n");
+
+ return 0;
+}
+
+static struct platform_driver acp3x_dma_driver = {
+ .probe = acp3x_audio_probe,
+ .remove = acp3x_audio_remove,
+ .driver = {
+ .name = "acp3x_rv_i2s",
+ },
+};
+
+module_platform_driver(acp3x_dma_driver);
+
+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
+MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:acp3x-i2s-audio");
diff --git a/sound/soc/amd/raven/acp3x.h b/sound/soc/amd/raven/acp3x.h
index 1996faf..b6d4659 100644
--- a/sound/soc/amd/raven/acp3x.h
+++ b/sound/soc/amd/raven/acp3x.h
@@ -4,6 +4,9 @@
#define ACP3x_I2S_MODE 0
#define ACP3x_REG_START 0x1240000
#define ACP3x_REG_END 0x1250200
+#define BT_TX_THRESHOLD 26
+#define BT_RX_THRESHOLD 25
+
static inline u32 rv_readl(void __iomem *base_addr)
{
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 005/117] ASoC: AMD: handle ACP3x i2s watermark interrupt
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 004/117] ASoC: AMD: add ACP3x PCM platform driver Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 006/117] ASoC: AMD: add ACP3x PCM driver DMA ops Alex Deucher
` (104 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
whenever audio data equal to I2S fifo watermark level is
produced/consumed, interrupt is generated. Amount of data is equal to
half of ALSA ring buffer size. Acknowledge the interrupt.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 49 +++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index 3fd9f86..0ce04f0 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -25,6 +25,7 @@
#include "acp3x.h"
struct i2s_dev_data {
+ unsigned int i2s_irq;
void __iomem *acp3x_base;
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
@@ -135,6 +136,38 @@ static int acp3x_deinit(void __iomem *acp3x_base)
return 0;
}
+static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
+{
+ u16 play_flag, cap_flag;
+ u32 val;
+ struct i2s_dev_data *rv_i2s_data = dev_id;
+
+ if (rv_i2s_data == NULL)
+ return IRQ_NONE;
+
+ play_flag = cap_flag = 0;
+
+ val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT);
+ if ((val & BIT(BT_TX_THRESHOLD)) && (rv_i2s_data->play_stream)) {
+ rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base +
+ mmACP_EXTERNAL_INTR_STAT);
+ snd_pcm_period_elapsed(rv_i2s_data->play_stream);
+ play_flag = 1;
+ }
+
+ if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) {
+ rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base +
+ mmACP_EXTERNAL_INTR_STAT);
+ snd_pcm_period_elapsed(rv_i2s_data->capture_stream);
+ cap_flag = 1;
+ }
+
+ if (play_flag | cap_flag)
+ return IRQ_HANDLED;
+ else
+ return IRQ_NONE;
+}
+
static struct snd_pcm_ops acp3x_dma_ops = {
.open = NULL,
.close = NULL,
@@ -211,6 +244,13 @@ static int acp3x_audio_probe(struct platform_device *pdev)
adata->acp3x_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
+ return -ENODEV;
+ }
+
+ adata->i2s_irq = res->start;
adata->play_stream = NULL;
adata->capture_stream = NULL;
@@ -234,6 +274,15 @@ static int acp3x_audio_probe(struct platform_device *pdev)
goto dev_err;
}
+ status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler,
+ irqflags, "ACP3x_I2S_IRQ", adata);
+ if (status) {
+ dev_err(&pdev->dev, "ACP3x I2S IRQ request failed\n");
+ snd_soc_unregister_platform(&pdev->dev);
+ snd_soc_unregister_component(&pdev->dev);
+ goto dev_err;
+ }
+
return 0;
dev_err:
status = acp3x_deinit(adata->acp3x_base);
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 006/117] ASoC: AMD: add ACP3x PCM driver DMA ops
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 005/117] ASoC: AMD: handle ACP3x i2s watermark interrupt Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 007/117] ASoC: AMD: add ACP3x i2s ops Alex Deucher
` (103 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP3x has a DMA controller to access system memory. This controller
transfers data from/to system memory to/from ACP internal fifo.
The patch adds PCM driver DMA operations.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 269 ++++++++++++++++++++++++++++++++++--
sound/soc/amd/raven/acp3x.h | 14 ++
2 files changed, 275 insertions(+), 8 deletions(-)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index 0ce04f0..346ebcb 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -31,6 +31,56 @@ struct i2s_dev_data {
struct snd_pcm_substream *capture_stream;
};
+struct i2s_stream_instance {
+ u16 num_pages;
+ u16 channels;
+ u32 xfer_resolution;
+ u32 fmt;
+ u32 val;
+ struct page *pg;
+ void __iomem *acp3x_base;
+};
+
+static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_BATCH |
+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 8,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
+ .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
+ .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
+ .periods_min = PLAYBACK_MIN_NUM_PERIODS,
+ .periods_max = PLAYBACK_MAX_NUM_PERIODS,
+};
+
+static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = {
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER |
+ SNDRV_PCM_INFO_BATCH |
+ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .rate_min = 8000,
+ .rate_max = 48000,
+ .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
+ .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
+ .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
+ .periods_min = CAPTURE_MIN_NUM_PERIODS,
+ .periods_max = CAPTURE_MAX_NUM_PERIODS,
+};
+
static int acp3x_power_on(void __iomem *acp3x_base, bool on)
{
u16 val, mask;
@@ -168,19 +218,222 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
return IRQ_NONE;
}
+static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)
+{
+ u16 page_idx;
+ u64 addr;
+ u32 low, high, val, acp_fifo_addr;
+ struct page *pg = rtd->pg;
+
+ /* 8 scratch registers used to map one 64 bit address.
+ * For 2 pages (4096 * 2 bytes), it will be 16 registers.
+ */
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK)
+ val = 0;
+ else
+ val = 16;
+
+ /* Group Enable */
+ rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +
+ mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
+ rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +
+ mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
+
+ for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
+ /* Load the low address of page int ACP SRAM through SRBM */
+ addr = page_to_phys(pg);
+ low = lower_32_bits(addr);
+ high = upper_32_bits(addr);
+
+ rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);
+ high |= BIT(31);
+ rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val
+ + 4);
+ /* Move to next physically contiguos page */
+ val += 8;
+ pg++;
+ }
+
+ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
+ /* Config ringbuffer */
+ rv_writel(MEM_WINDOW_START, rtd->acp3x_base +
+ mmACP_BT_TX_RINGBUFADDR);
+ rv_writel(MAX_BUFFER, rtd->acp3x_base +
+ mmACP_BT_TX_RINGBUFSIZE);
+ rv_writel(0x40, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE);
+
+ /* Config audio fifo */
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8)
+ + 1024;
+ rv_writel(acp_fifo_addr, rtd->acp3x_base +
+ mmACP_BT_TX_FIFOADDR);
+ rv_writel(256, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE);
+ rv_writel(PLAYBACK_MIN_PERIOD_SIZE, rtd->acp3x_base +
+ mmACP_BT_TX_INTR_WATERMARK_SIZE);
+ } else {
+ /* Config ringbuffer */
+ rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base +
+ mmACP_BT_RX_RINGBUFADDR);
+ rv_writel(MAX_BUFFER, rtd->acp3x_base +
+ mmACP_BT_RX_RINGBUFSIZE);
+ rv_writel(0x40, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE);
+
+ /* Config audio fifo */
+ acp_fifo_addr = ACP_SRAM_PTE_OFFSET +
+ (rtd->num_pages * 8) + 1024 + 256;
+ rv_writel(acp_fifo_addr, rtd->acp3x_base +
+ mmACP_BT_RX_FIFOADDR);
+ rv_writel(256, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE);
+ rv_writel(CAPTURE_MIN_PERIOD_SIZE, rtd->acp3x_base +
+ mmACP_BT_RX_INTR_WATERMARK_SIZE);
+ }
+
+ /* Enable watermark/period interrupt to host */
+ rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD),
+ rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);
+}
+
+static int acp3x_dma_open(struct snd_pcm_substream *substream)
+{
+ int ret = 0;
+
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct i2s_dev_data *adata = dev_get_drvdata(prtd->platform->dev);
+
+ struct i2s_stream_instance *i2s_data = kzalloc(sizeof(
+ struct i2s_stream_instance), GFP_KERNEL);
+ if (i2s_data == NULL)
+ return -EINVAL;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ runtime->hw = acp3x_pcm_hardware_playback;
+ else
+ runtime->hw = acp3x_pcm_hardware_capture;
+
+ ret = snd_pcm_hw_constraint_integer(runtime,
+ SNDRV_PCM_HW_PARAM_PERIODS);
+ if (ret < 0) {
+ dev_err(prtd->platform->dev, "set integer constraint failed\n");
+ return ret;
+ }
+
+ if (!adata->play_stream && !adata->capture_stream)
+ rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ adata->play_stream = substream;
+ else
+ adata->capture_stream = substream;
+
+ i2s_data->acp3x_base = adata->acp3x_base;
+ runtime->private_data = i2s_data;
+ return 0;
+}
+
+static int acp3x_dma_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ int status;
+ uint64_t size;
+ struct snd_dma_buffer *dma_buffer;
+ struct page *pg;
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+
+ if (rtd == NULL)
+ return -EINVAL;
+
+ dma_buffer = &substream->dma_buffer;
+ size = params_buffer_bytes(params);
+ status = snd_pcm_lib_malloc_pages(substream, size);
+ if (status < 0)
+ return status;
+
+ memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
+ pg = virt_to_page(substream->dma_buffer.area);
+ if (pg != NULL) {
+ rtd->pg = pg;
+ rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
+ config_acp3x_dma(rtd, substream->stream);
+ status = 0;
+ } else {
+ status = -ENOMEM;
+ }
+ return status;
+}
+
+static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream)
+{
+ u32 pos = 0;
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ pos = rv_readl(rtd->acp3x_base +
+ mmACP_BT_TX_LINKPOSITIONCNTR);
+ else
+ pos = rv_readl(rtd->acp3x_base +
+ mmACP_BT_RX_LINKPOSITIONCNTR);
+
+ if (pos >= MAX_BUFFER)
+ pos = 0;
+
+ return bytes_to_frames(substream->runtime, pos);
+}
+
+static int acp3x_dma_new(struct snd_soc_pcm_runtime *rtd)
+{
+ return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
+ SNDRV_DMA_TYPE_DEV,
+ NULL, MIN_BUFFER,
+ MAX_BUFFER);
+}
+
+static int acp3x_dma_hw_free(struct snd_pcm_substream *substream)
+{
+ return snd_pcm_lib_free_pages(substream);
+}
+
+static int acp3x_dma_mmap(struct snd_pcm_substream *substream,
+ struct vm_area_struct *vma)
+{
+ return snd_pcm_lib_default_mmap(substream, vma);
+}
+
+static int acp3x_dma_close(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *prtd = substream->private_data;
+ struct i2s_dev_data *adata = dev_get_drvdata(prtd->platform->dev);
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+
+ kfree(rtd);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ adata->play_stream = NULL;
+ else
+ adata->capture_stream = NULL;
+
+ /* Disable ACP irq, when the current stream is being closed and
+ * another stream is also not active.
+ */
+ if (!adata->play_stream && !adata->capture_stream)
+ rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
+
+ return 0;
+}
+
static struct snd_pcm_ops acp3x_dma_ops = {
- .open = NULL,
- .close = NULL,
- .ioctl = NULL,
- .hw_params = NULL,
- .hw_free = NULL,
- .pointer = NULL,
- .mmap = NULL,
+ .open = acp3x_dma_open,
+ .close = acp3x_dma_close,
+ .ioctl = snd_pcm_lib_ioctl,
+ .hw_params = acp3x_dma_hw_params,
+ .hw_free = acp3x_dma_hw_free,
+ .pointer = acp3x_dma_pointer,
+ .mmap = acp3x_dma_mmap,
};
static struct snd_soc_platform_driver acp3x_asoc_platform = {
.ops = &acp3x_dma_ops,
- .pcm_new = NULL,
+ .pcm_new = acp3x_dma_new,
};
struct snd_soc_dai_ops acp3x_dai_i2s_ops = {
diff --git a/sound/soc/amd/raven/acp3x.h b/sound/soc/amd/raven/acp3x.h
index b6d4659..d35d252 100644
--- a/sound/soc/amd/raven/acp3x.h
+++ b/sound/soc/amd/raven/acp3x.h
@@ -6,7 +6,21 @@
#define ACP3x_REG_END 0x1250200
#define BT_TX_THRESHOLD 26
#define BT_RX_THRESHOLD 25
+#define ACP_SRAM_PTE_OFFSET 0x02050000
+#define PAGE_SIZE_4K_ENABLE 0x2
+#define MEM_WINDOW_START 0x4000000
+#define PLAYBACK_MIN_NUM_PERIODS 2
+#define PLAYBACK_MAX_NUM_PERIODS 2
+#define PLAYBACK_MAX_PERIOD_SIZE 4096
+#define PLAYBACK_MIN_PERIOD_SIZE 4096
+#define CAPTURE_MIN_NUM_PERIODS 2
+#define CAPTURE_MAX_NUM_PERIODS 2
+#define CAPTURE_MAX_PERIOD_SIZE 4096
+#define CAPTURE_MIN_PERIOD_SIZE 4096
+
+#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
+#define MIN_BUFFER MAX_BUFFER
static inline u32 rv_readl(void __iomem *base_addr)
{
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 007/117] ASoC: AMD: add ACP3x i2s ops
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 006/117] ASoC: AMD: add ACP3x PCM driver DMA ops Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 008/117] ASoC: AMD: add ACP3x TDM mode support Alex Deucher
` (102 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP3x has a i2s controller block for playback and capture. This patch
adds ACP3x i2s operations.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 85 +++++++++++++++++++++++++++++++++++--
1 file changed, 82 insertions(+), 3 deletions(-)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index 346ebcb..5e589dc 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -436,10 +436,89 @@ static struct snd_soc_platform_driver acp3x_asoc_platform = {
.pcm_new = acp3x_dma_new,
};
+static int acp3x_dai_i2s_hwparams(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_U8:
+ case SNDRV_PCM_FORMAT_S8:
+ rtd->xfer_resolution = 0x0;
+ break;
+ case SNDRV_PCM_FORMAT_S16_LE:
+ rtd->xfer_resolution = 0x02;
+ break;
+
+ case SNDRV_PCM_FORMAT_S24_LE:
+ rtd->xfer_resolution = 0x04;
+ break;
+ case SNDRV_PCM_FORMAT_S32_LE:
+ rtd->xfer_resolution = 0x05;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ rv_writel((rtd->xfer_resolution << 3),
+ rtd->acp3x_base + mmACP_BTTDM_ITER);
+ else
+ rv_writel((rtd->xfer_resolution << 3),
+ rtd->acp3x_base + mmACP_BTTDM_IRER);
+
+ return 0;
+}
+
+static int acp3x_dai_i2s_trigger(struct snd_pcm_substream *substream,
+ int cmd, struct snd_soc_dai *dai)
+{
+ int ret = 0;
+ struct i2s_stream_instance *rtd = substream->runtime->private_data;
+ u32 val;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
+ val = val | BIT(0);
+ rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
+ } else {
+ val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
+ val = val | BIT(0);
+ rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
+ }
+ rv_writel(1, rtd->acp3x_base + mmACP_BTTDM_IER);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER);
+ val = val & ~BIT(0);
+ rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER);
+ } else {
+ val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER);
+ val = val & ~BIT(0);
+ rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER);
+ }
+ rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
struct snd_soc_dai_ops acp3x_dai_i2s_ops = {
- .hw_params = NULL,
- .trigger = NULL,
- .set_fmt = NULL,
+ .hw_params = acp3x_dai_i2s_hwparams,
+ .trigger = acp3x_dai_i2s_trigger,
};
static struct snd_soc_dai_driver acp3x_i2s_dai_driver = {
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 008/117] ASoC: AMD: add ACP3x TDM mode support
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 007/117] ASoC: AMD: add ACP3x i2s ops Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 009/117] ASoC: AMD: Add ACP3x runtime pm ops Alex Deucher
` (101 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP3x I2S (CPU DAI) can act in normal I2S and TDM modes. Added support
for TDM mode. Desired mode can be selected from ASoC machine driver.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 63 ++++++++++++++++++++++++++++++++++++-
sound/soc/amd/raven/acp3x.h | 1 +
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index 5e589dc..f62bb7f 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -25,7 +25,9 @@
#include "acp3x.h"
struct i2s_dev_data {
+ bool tdm_mode;
unsigned int i2s_irq;
+ u32 tdm_fmt;
void __iomem *acp3x_base;
struct snd_pcm_substream *play_stream;
struct snd_pcm_substream *capture_stream;
@@ -35,7 +37,6 @@ struct i2s_stream_instance {
u16 num_pages;
u16 channels;
u32 xfer_resolution;
- u32 fmt;
u32 val;
struct page *pg;
void __iomem *acp3x_base;
@@ -436,6 +437,64 @@ static struct snd_soc_platform_driver acp3x_asoc_platform = {
.pcm_new = acp3x_dma_new,
};
+static int acp3x_dai_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+
+ struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
+
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ adata->tdm_mode = false;
+ break;
+ case SND_SOC_DAIFMT_DSP_A:
+ adata->tdm_mode = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int acp3x_dai_set_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
+ u32 rx_mask, int slots, int slot_width)
+{
+ u32 val = 0;
+ u16 resolution;
+
+ struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
+
+ switch (slot_width) {
+ case 8:
+ resolution = 0;
+ break;
+ case 16:
+ resolution = 2;
+ break;
+ case 24:
+ resolution = 4;
+ break;
+ case 32:
+ resolution = 5;
+ break;
+ default:
+ return -EINVAL;
+ break;
+ }
+
+ val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
+ rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_ITER);
+ val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
+ rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_IRER);
+
+ val = (FRM_LEN | ((slots-1) << 15) | (resolution << 18));
+ rv_writel(val, adata->acp3x_base + mmACP_BTTDM_TXFRMT);
+ rv_writel(val, adata->acp3x_base + mmACP_BTTDM_RXFRMT);
+
+ adata->tdm_fmt = val;
+ return 0;
+}
+
static int acp3x_dai_i2s_hwparams(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -519,6 +578,8 @@ static int acp3x_dai_i2s_trigger(struct snd_pcm_substream *substream,
struct snd_soc_dai_ops acp3x_dai_i2s_ops = {
.hw_params = acp3x_dai_i2s_hwparams,
.trigger = acp3x_dai_i2s_trigger,
+ .set_fmt = acp3x_dai_i2s_set_fmt,
+ .set_tdm_slot = acp3x_dai_set_tdm_slot,
};
static struct snd_soc_dai_driver acp3x_i2s_dai_driver = {
diff --git a/sound/soc/amd/raven/acp3x.h b/sound/soc/amd/raven/acp3x.h
index d35d252..70fed97 100644
--- a/sound/soc/amd/raven/acp3x.h
+++ b/sound/soc/amd/raven/acp3x.h
@@ -9,6 +9,7 @@
#define ACP_SRAM_PTE_OFFSET 0x02050000
#define PAGE_SIZE_4K_ENABLE 0x2
#define MEM_WINDOW_START 0x4000000
+#define FRM_LEN 256
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 2
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 009/117] ASoC: AMD: Add ACP3x runtime pm ops
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 008/117] ASoC: AMD: add ACP3x TDM mode support Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 010/117] ASoC: AMD: Add ACP3x system resume pm op Alex Deucher
` (100 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
Added runtime PM operations for ACP3x PCM platform device. Device will
be powered on/off based on device is in use or not.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 39 +++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index f62bb7f..a5d3807 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/err.h>
+#include <linux/pm_runtime.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
@@ -676,6 +677,9 @@ static int acp3x_audio_probe(struct platform_device *pdev)
goto dev_err;
}
+ pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
return 0;
dev_err:
status = acp3x_deinit(adata->acp3x_base);
@@ -701,14 +705,49 @@ static int acp3x_audio_remove(struct platform_device *pdev)
else
dev_info(&pdev->dev, "ACP de-initialized\n");
+ pm_runtime_disable(&pdev->dev);
return 0;
}
+static int acp3x_pcm_runtime_suspend(struct device *dev)
+{
+ int status;
+ struct i2s_dev_data *adata = dev_get_drvdata(dev);
+
+ status = acp3x_deinit(adata->acp3x_base);
+ if (status)
+ dev_err(dev, "ACP de-init failed\n");
+ else
+ dev_info(dev, "ACP de-initialized\n");
+
+ rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
+
+ return 0;
+}
+
+static int acp3x_pcm_runtime_resume(struct device *dev)
+{
+ int status;
+ struct i2s_dev_data *adata = dev_get_drvdata(dev);
+
+ status = acp3x_init(adata->acp3x_base);
+ if (status)
+ return -ENODEV;
+ rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
+ return 0;
+}
+
+static const struct dev_pm_ops acp3x_pm_ops = {
+ .runtime_suspend = acp3x_pcm_runtime_suspend,
+ .runtime_resume = acp3x_pcm_runtime_resume,
+};
+
static struct platform_driver acp3x_dma_driver = {
.probe = acp3x_audio_probe,
.remove = acp3x_audio_remove,
.driver = {
.name = "acp3x_rv_i2s",
+ .pm = &acp3x_pm_ops,
},
};
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 010/117] ASoC: AMD: Add ACP3x system resume pm op
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 009/117] ASoC: AMD: Add ACP3x runtime pm ops Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 011/117] ASoC: AMD: enable ACP3x drivers build Alex Deucher
` (99 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
When audio usecase in progress and system wide suspend happens, ACP will
be powered off and when system resumes, for audio usecase to continue,
all the runtime configuration data needs to be programmed again. Added
'resume'pm call back to ACP pm ops.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-pcm-dma.c | 46 +++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/sound/soc/amd/raven/acp3x-pcm-dma.c b/sound/soc/amd/raven/acp3x-pcm-dma.c
index a5d3807..5246d28 100644
--- a/sound/soc/amd/raven/acp3x-pcm-dma.c
+++ b/sound/soc/amd/raven/acp3x-pcm-dma.c
@@ -709,6 +709,51 @@ static int acp3x_audio_remove(struct platform_device *pdev)
return 0;
}
+static int acp3x_resume(struct device *dev)
+{
+ int status;
+ u32 val;
+ struct i2s_dev_data *adata = dev_get_drvdata(dev);
+
+ status = acp3x_init(adata->acp3x_base);
+ if (status)
+ return -ENODEV;
+
+ if (adata->play_stream && adata->play_stream->runtime) {
+ struct i2s_stream_instance *rtd =
+ adata->play_stream->runtime->private_data;
+ config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK);
+ rv_writel((rtd->xfer_resolution << 3),
+ rtd->acp3x_base + mmACP_BTTDM_ITER);
+ if (adata->tdm_mode == true) {
+ rv_writel(adata->tdm_fmt, adata->acp3x_base +
+ mmACP_BTTDM_TXFRMT);
+ val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER);
+ rv_writel((val | 0x2), adata->acp3x_base +
+ mmACP_BTTDM_ITER);
+ }
+ }
+
+ if (adata->capture_stream && adata->capture_stream->runtime) {
+ struct i2s_stream_instance *rtd =
+ adata->capture_stream->runtime->private_data;
+ config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
+ rv_writel((rtd->xfer_resolution << 3),
+ rtd->acp3x_base + mmACP_BTTDM_IRER);
+ if (adata->tdm_mode == true) {
+ rv_writel(adata->tdm_fmt, adata->acp3x_base +
+ mmACP_BTTDM_RXFRMT);
+ val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER);
+ rv_writel((val | 0x2), adata->acp3x_base +
+ mmACP_BTTDM_IRER);
+ }
+ }
+
+ rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);
+ return 0;
+}
+
+
static int acp3x_pcm_runtime_suspend(struct device *dev)
{
int status;
@@ -740,6 +785,7 @@ static int acp3x_pcm_runtime_resume(struct device *dev)
static const struct dev_pm_ops acp3x_pm_ops = {
.runtime_suspend = acp3x_pcm_runtime_suspend,
.runtime_resume = acp3x_pcm_runtime_resume,
+ .resume = acp3x_resume,
};
static struct platform_driver acp3x_dma_driver = {
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 011/117] ASoC: AMD: enable ACP3x drivers build
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 010/117] ASoC: AMD: Add ACP3x system resume pm op Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 012/117] ASoC: AMD: create/add dummy codec and machine devices/drivers Alex Deucher
` (98 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
ACP3x drivers can be build by selecting necessary kernel config option.
The patch enables build support of the same.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/Kconfig | 4 ++++
sound/soc/amd/Makefile | 1 +
sound/soc/amd/raven/Makefile | 4 ++++
3 files changed, 9 insertions(+)
create mode 100644 sound/soc/amd/raven/Makefile
diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig
index 78187eb..dcdec36 100644
--- a/sound/soc/amd/Kconfig
+++ b/sound/soc/amd/Kconfig
@@ -2,3 +2,7 @@ config SND_SOC_AMD_ACP
tristate "AMD Audio Coprocessor support"
help
This option enables ACP DMA support on AMD platform.
+config SND_SOC_AMD_ACP3x
+ tristate "AMD Audio Coprocessor-v3.x support"
+ help
+ This option enables ACP v3.x I2S support on AMD platform.
diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile
index 1a66ec0..6a9a5ba0 100644
--- a/sound/soc/amd/Makefile
+++ b/sound/soc/amd/Makefile
@@ -1,3 +1,4 @@
snd-soc-acp-pcm-objs := acp-pcm-dma.o
obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o
+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/
diff --git a/sound/soc/amd/raven/Makefile b/sound/soc/amd/raven/Makefile
new file mode 100644
index 0000000..8c03e6f
--- /dev/null
+++ b/sound/soc/amd/raven/Makefile
@@ -0,0 +1,4 @@
+snd-pci-acp3x-objs := pci-acp3x.o
+snd-acp3x-pcm-dma-objs := acp3x-pcm-dma.o
+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-pci-acp3x.o
+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-acp3x-pcm-dma.o
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 012/117] ASoC: AMD: create/add dummy codec and machine devices/drivers
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 011/117] ASoC: AMD: enable ACP3x drivers build Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 013/117] soc/amd/raven: Disabling TDM mode flag Alex Deucher
` (97 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alex Deucher, Maruthi Bayyavarapu
From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>
Dummy codec and machine devices are created so that ASoC based
soundcard can be created. Respective drivers which bound to
these devices are added.
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/Makefile | 4 +
sound/soc/amd/raven/acp3x-dummy5102.c | 136 ++++++++++++++++++++++++++++++++++
sound/soc/amd/raven/dummy-w5102.c | 102 +++++++++++++++++++++++++
sound/soc/amd/raven/pci-acp3x.c | 34 ++++++++-
4 files changed, 272 insertions(+), 4 deletions(-)
create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
create mode 100644 sound/soc/amd/raven/dummy-w5102.c
diff --git a/sound/soc/amd/raven/Makefile b/sound/soc/amd/raven/Makefile
index 8c03e6f..5db3afc 100644
--- a/sound/soc/amd/raven/Makefile
+++ b/sound/soc/amd/raven/Makefile
@@ -1,4 +1,8 @@
snd-pci-acp3x-objs := pci-acp3x.o
snd-acp3x-pcm-dma-objs := acp3x-pcm-dma.o
+snd-soc-dummy-w5102-objs := dummy-w5102.o
+snd-soc-acp3x-mach-objs := acp3x-dummy5102.o
obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-pci-acp3x.o
obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-acp3x-pcm-dma.o
+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-soc-dummy-w5102.o
+obj-$(CONFIG_SND_SOC_AMD_ACP3x) += snd-soc-acp3x-mach.o
diff --git a/sound/soc/amd/raven/acp3x-dummy5102.c b/sound/soc/amd/raven/acp3x-dummy5102.c
new file mode 100644
index 0000000..3b2f509
--- /dev/null
+++ b/sound/soc/amd/raven/acp3x-dummy5102.c
@@ -0,0 +1,136 @@
+/*
+ * Machine driver for AMD ACP Audio engine using dummy codec
+ *
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <linux/module.h>
+
+static int acp3x_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+
+{
+ return 0;
+}
+
+static struct snd_soc_ops acp3x_wm5102_ops = {
+ .hw_params = acp3x_hw_params,
+};
+
+static int acp3x_init(struct snd_soc_pcm_runtime *rtd)
+{
+ return 0;
+}
+
+static struct snd_soc_dai_link acp3x_dai_w5102[] = {
+ {
+ .name = "RV-W5102-PLAY",
+ .stream_name = "Playback",
+ .platform_name = "acp3x_rv_i2s.0",
+ .cpu_dai_name = "acp3x_rv_i2s.0",
+ .codec_dai_name = "dummy_w5102_dai",
+ .codec_name = "dummy_w5102.0",
+ .dai_fmt = SND_SOC_DAIFMT_DSP_A /*SND_SOC_DAIFMT_I2S*/ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBM_CFM,
+ .ops = &acp3x_wm5102_ops,
+ .init = acp3x_init,
+ },
+};
+
+static const struct snd_soc_dapm_widget acp3x_widgets[] = {
+ SND_SOC_DAPM_HP("Headphones", NULL),
+ SND_SOC_DAPM_MIC("Analog Mic", NULL),
+};
+
+static const struct snd_soc_dapm_route acp3x_audio_route[] = {
+ {"Headphones", NULL, "HPO L"},
+ {"Headphones", NULL, "HPO R"},
+ {"MIC1", NULL, "Analog Mic"},
+};
+
+static struct snd_soc_card acp3x_card = {
+ .name = "acp3x",
+ .owner = THIS_MODULE,
+ .dai_link = acp3x_dai_w5102,
+ .num_links = 1,
+};
+
+static int acp3x_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct acp_wm5102 *machine = NULL;
+ struct snd_soc_card *card;
+
+ card = &acp3x_card;
+ acp3x_card.dev = &pdev->dev;
+
+ platform_set_drvdata(pdev, card);
+ snd_soc_card_set_drvdata(card, machine);
+
+ ret = snd_soc_register_card(card);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "snd_soc_register_card(%s) failed: %d\n",
+ acp3x_card.name, ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int acp3x_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card;
+
+ card = platform_get_drvdata(pdev);
+ snd_soc_unregister_card(card);
+
+ return 0;
+}
+
+static struct platform_driver acp3x_mach_driver = {
+ .driver = {
+ .name = "acp3x_w5102_mach",
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = acp3x_probe,
+ .remove = acp3x_remove,
+};
+
+static int __init acp3x_audio_init(void)
+{
+ platform_driver_register(&acp3x_mach_driver);
+ return 0;
+}
+
+static void __exit acp3x_audio_exit(void)
+{
+ platform_driver_unregister(&acp3x_mach_driver);
+}
+
+module_init(acp3x_audio_init);
+module_exit(acp3x_audio_exit);
+
+MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/amd/raven/dummy-w5102.c b/sound/soc/amd/raven/dummy-w5102.c
new file mode 100644
index 0000000..3e09e32
--- /dev/null
+++ b/sound/soc/amd/raven/dummy-w5102.c
@@ -0,0 +1,102 @@
+/*
+ * dummy audio codec driver
+ *
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+
+#include <linux/module.h>
+#include <sound/soc.h>
+
+#define W5102_RATES SNDRV_PCM_RATE_8000_96000
+#define W5102_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S32_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static const struct snd_soc_dapm_widget w5102_widgets[] = {
+ SND_SOC_DAPM_OUTPUT("dummy-w5102-out"),
+ SND_SOC_DAPM_INPUT("dummy-w5102-in"),
+};
+
+static const struct snd_soc_dapm_route w5102_routes[] = {
+ { "dummy-w5102-out", NULL, "Playback" },
+ { "Capture", NULL, "dummy-w5102-in" },
+};
+
+static struct snd_soc_codec_driver soc_codec_w5102_dummy = {
+ .component_driver = {
+ .dapm_widgets = w5102_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(w5102_widgets),
+ .dapm_routes = w5102_routes,
+ .num_dapm_routes = ARRAY_SIZE(w5102_routes),
+ },
+};
+
+static struct snd_soc_dai_driver w5102_stub_dai = {
+ .name = "dummy_w5102_dai",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = W5102_RATES,
+ .formats = W5102_FORMATS,
+ },
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = W5102_RATES,
+ .formats = W5102_FORMATS,
+ },
+
+};
+
+static int dummy_w5102_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = snd_soc_register_codec(&pdev->dev, &soc_codec_w5102_dummy,
+ &w5102_stub_dai, 1);
+ return ret;
+}
+
+static int dummy_w5102_remove(struct platform_device *pdev)
+{
+ snd_soc_unregister_codec(&pdev->dev);
+ return 0;
+}
+
+
+static struct platform_driver dummy_w5102_driver = {
+ .probe = dummy_w5102_probe,
+ .remove = dummy_w5102_remove,
+ .driver = {
+ .name = "dummy_w5102",
+ .owner = THIS_MODULE,
+ },
+};
+
+module_platform_driver(dummy_w5102_driver);
+
+MODULE_DESCRIPTION("dummy-w5102 dummy codec driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform: dummy_w5102");
diff --git a/sound/soc/amd/raven/pci-acp3x.c b/sound/soc/amd/raven/pci-acp3x.c
index a182013..5891c5b 100644
--- a/sound/soc/amd/raven/pci-acp3x.c
+++ b/sound/soc/amd/raven/pci-acp3x.c
@@ -24,7 +24,7 @@ struct acp3x_dev_data {
void __iomem *acp3x_base;
bool acp3x_audio_mode;
struct resource *res;
- struct platform_device *pdev;
+ struct platform_device *pdev[3];
};
static int snd_acp3x_probe(struct pci_dev *pci,
@@ -103,13 +103,30 @@ static int snd_acp3x_probe(struct pci_dev *pci,
pdevinfo.data = &irqflags;
pdevinfo.size_data = sizeof(irqflags);
- adata->pdev = platform_device_register_full(&pdevinfo);
- if (adata->pdev == NULL) {
+ adata->pdev[0] = platform_device_register_full(&pdevinfo);
+ if (adata->pdev[0] == NULL) {
dev_err(&pci->dev, "cannot register %s device\n",
pdevinfo.name);
ret = -ENODEV;
goto unmap_mmio;
}
+
+ /* create dummy codec device */
+ adata->pdev[1] = platform_device_register_simple("dummy_w5102",
+ 0, NULL, 0);
+ if (IS_ERR(adata->pdev[1])) {
+ dev_err(&pci->dev, "Cannot register dummy_w5102\n");
+ ret = -ENODEV;
+ goto unregister_pdev0;
+ }
+ /* create dummy mach device */
+ adata->pdev[2] = platform_device_register_simple(
+ "acp3x_w5102_mach", 0, NULL, 0);
+ if (IS_ERR(adata->pdev[2])) {
+ dev_err(&pci->dev, "Cannot register acp3x_w5102_mach\n");
+ ret = -ENODEV;
+ goto unregister_pdev1;
+ }
} else {
dev_err(&pci->dev, "Inavlid ACP audio mode : %d\n", val);
ret = -ENODEV;
@@ -118,6 +135,10 @@ static int snd_acp3x_probe(struct pci_dev *pci,
return 0;
+unregister_pdev1:
+ platform_device_unregister(adata->pdev[1]);
+unregister_pdev0:
+ platform_device_unregister(adata->pdev[0]);
unmap_mmio:
pci_disable_msi(pci);
iounmap(adata->acp3x_base);
@@ -131,9 +152,14 @@ static int snd_acp3x_probe(struct pci_dev *pci,
static void snd_acp3x_remove(struct pci_dev *pci)
{
+ int i;
struct acp3x_dev_data *adata = pci_get_drvdata(pci);
- platform_device_unregister(adata->pdev);
+ if (adata->acp3x_audio_mode == ACP3x_I2S_MODE) {
+ for (i = 2; i >= 0; i--)
+ platform_device_unregister(adata->pdev[i]);
+ }
+
iounmap(adata->acp3x_base);
pci_disable_msi(pci);
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 013/117] soc/amd/raven: Disabling TDM mode flag
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 012/117] ASoC: AMD: create/add dummy codec and machine devices/drivers Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 014/117] drm/amdgpu: add gpu_info firmware (v3) Alex Deucher
` (96 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Vijendar Mukunda
From: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
sound/soc/amd/raven/acp3x-dummy5102.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/amd/raven/acp3x-dummy5102.c b/sound/soc/amd/raven/acp3x-dummy5102.c
index 3b2f509..0282c59 100644
--- a/sound/soc/amd/raven/acp3x-dummy5102.c
+++ b/sound/soc/amd/raven/acp3x-dummy5102.c
@@ -52,7 +52,7 @@ static struct snd_soc_dai_link acp3x_dai_w5102[] = {
.cpu_dai_name = "acp3x_rv_i2s.0",
.codec_dai_name = "dummy_w5102_dai",
.codec_name = "dummy_w5102.0",
- .dai_fmt = SND_SOC_DAIFMT_DSP_A /*SND_SOC_DAIFMT_I2S*/ | SND_SOC_DAIFMT_NB_NF
+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
| SND_SOC_DAIFMT_CBM_CFM,
.ops = &acp3x_wm5102_ops,
.init = acp3x_init,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 014/117] drm/amdgpu: add gpu_info firmware (v3)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 013/117] soc/amd/raven: Disabling TDM mode flag Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 015/117] drm/amdgpu: parse the gpu_info firmware (v4) Alex Deucher
` (95 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Add a new gpu info firmware to store gpu specific configuration
data. This allows us to store hw constants in a unified place.
v2: adjust structure and elements
v3: further restructure
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 21 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index dfd1c98..38e3ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -197,6 +197,27 @@ void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
}
}
+void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
+{
+ uint16_t version_major = le16_to_cpu(hdr->header_version_major);
+ uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
+
+ DRM_DEBUG("GPU_INFO\n");
+ amdgpu_ucode_print_common_hdr(hdr);
+
+ if (version_major == 1) {
+ const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
+ container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
+
+ DRM_DEBUG("version_major: %u\n",
+ le16_to_cpu(gpu_info_hdr->version_major));
+ DRM_DEBUG("version_minor: %u\n",
+ le16_to_cpu(gpu_info_hdr->version_minor));
+ } else {
+ DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
+ }
+}
+
int amdgpu_ucode_validate(const struct firmware *fw)
{
const struct common_firmware_header *hdr =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 758f03a..9f31c9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -113,6 +113,29 @@ struct sdma_firmware_header_v1_1 {
uint32_t digest_size;
};
+/* gpu info payload */
+struct gpu_info_firmware_v1_0 {
+ uint32_t gc_num_se;
+ uint32_t gc_num_cu_per_sh;
+ uint32_t gc_num_sh_per_se;
+ uint32_t gc_num_rb_per_se;
+ uint32_t gc_num_tccs;
+ uint32_t gc_num_gprs;
+ uint32_t gc_num_max_gs_thds;
+ uint32_t gc_gs_table_depth;
+ uint32_t gc_gsprim_buff_depth;
+ uint32_t gc_parameter_cache_depth;
+ uint32_t gc_double_offchip_lds_buffer;
+ uint32_t gc_wave_size;
+};
+
+/* version_major=1, version_minor=0 */
+struct gpu_info_firmware_header_v1_0 {
+ struct common_firmware_header header;
+ uint16_t version_major; /* version */
+ uint16_t version_minor; /* version */
+};
+
/* header is fixed size */
union amdgpu_firmware_header {
struct common_firmware_header common;
@@ -124,6 +147,7 @@ union amdgpu_firmware_header {
struct rlc_firmware_header_v2_0 rlc_v2_0;
struct sdma_firmware_header_v1_0 sdma;
struct sdma_firmware_header_v1_1 sdma_v1_1;
+ struct gpu_info_firmware_header_v1_0 gpu_info;
uint8_t raw[0x100];
};
@@ -184,6 +208,7 @@ void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
+void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
int amdgpu_ucode_validate(const struct firmware *fw);
bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
uint16_t hdr_major, uint16_t hdr_minor);
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 015/117] drm/amdgpu: parse the gpu_info firmware (v4)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 014/117] drm/amdgpu: add gpu_info firmware (v3) Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 016/117] drm/amdgpu/gfx9: drop duplicate gfx info init (v3) Alex Deucher
` (94 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
And populate the gfx structures from it.
v2: update the structures updated by the table
v3: rework based on new table structure
v4: simplify things
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 98 ++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6c60728..33e0666 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -55,6 +55,8 @@
#include <linux/pci.h>
#include <linux/firmware.h>
+MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
+
static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
@@ -1392,6 +1394,98 @@ static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
}
}
+static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+{
+ const struct firmware *fw;
+ const char *chip_name;
+ char fw_name[30];
+ int err;
+ const struct gpu_info_firmware_header_v1_0 *hdr;
+
+ switch (adev->asic_type) {
+ case CHIP_TOPAZ:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+ case CHIP_POLARIS11:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS12:
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+#ifdef CONFIG_DRM_AMDGPU_SI
+ case CHIP_VERDE:
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+#endif
+ default:
+ return 0;
+ case CHIP_VEGA10:
+ chip_name = "vega10";
+ break;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
+ err = request_firmware(&fw, fw_name, adev->dev);
+ if (err) {
+ dev_err(adev->dev,
+ "Failed to load gpu_info firmware \"%s\"\n",
+ fw_name);
+ goto out;
+ }
+ err = amdgpu_ucode_validate(fw);
+ if (err) {
+ dev_err(adev->dev,
+ "Failed to validate gpu_info firmware \"%s\"\n",
+ fw_name);
+ goto out;
+ }
+
+ hdr = (const struct gpu_info_firmware_header_v1_0 *)fw->data;
+ amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
+
+ switch (hdr->version_major) {
+ case 1:
+ {
+ const struct gpu_info_firmware_v1_0 *gpu_info_fw =
+ (const struct gpu_info_firmware_v1_0 *)(fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+
+ adev->gfx.config.max_shader_engines = gpu_info_fw->gc_num_se;
+ adev->gfx.config.max_cu_per_sh = gpu_info_fw->gc_num_cu_per_sh;
+ adev->gfx.config.max_sh_per_se = gpu_info_fw->gc_num_sh_per_se;
+ adev->gfx.config.max_backends_per_se = gpu_info_fw->gc_num_rb_per_se;
+ adev->gfx.config.max_texture_channel_caches =
+ gpu_info_fw->gc_num_tccs;
+ adev->gfx.config.max_gprs = gpu_info_fw->gc_num_gprs;
+ adev->gfx.config.max_gs_threads = gpu_info_fw->gc_num_max_gs_thds;
+ adev->gfx.config.gs_vgt_table_depth = gpu_info_fw->gc_gs_table_depth;
+ adev->gfx.config.gs_prim_buffer_depth = gpu_info_fw->gc_gsprim_buff_depth;
+ adev->gfx.config.double_offchip_lds_buf =
+ gpu_info_fw->gc_double_offchip_lds_buffer;
+ adev->gfx.cu_info.wave_front_size = gpu_info_fw->gc_wave_size;
+ break;
+ }
+ default:
+ dev_err(adev->dev,
+ "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
+ err = -EINVAL;
+ goto out;
+ }
+out:
+ release_firmware(fw);
+ fw = NULL;
+
+ return err;
+}
+
static int amdgpu_early_init(struct amdgpu_device *adev)
{
int i, r;
@@ -1456,6 +1550,10 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
return -EINVAL;
}
+ r = amdgpu_device_parse_gpu_info_fw(adev);
+ if (r)
+ return r;
+
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_request_full_gpu(adev, true);
if (r)
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 016/117] drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 015/117] drm/amdgpu: parse the gpu_info firmware (v4) Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 025/117] drm/amdgpu: add RAVEN family id definition Alex Deucher
` (93 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Taken care of by gpu info firmware now.
v2: rebase
v3: rework based on latest firmware
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Tested-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5fcf236..dd1751d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -781,21 +781,11 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA10:
- adev->gfx.config.max_shader_engines = 4;
- adev->gfx.config.max_cu_per_sh = 16;
- adev->gfx.config.max_sh_per_se = 1;
- adev->gfx.config.max_backends_per_se = 4;
- adev->gfx.config.max_texture_channel_caches = 16;
- adev->gfx.config.max_gprs = 256;
- adev->gfx.config.max_gs_threads = 32;
adev->gfx.config.max_hw_contexts = 8;
-
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
- adev->gfx.config.gs_vgt_table_depth = 32;
- adev->gfx.config.gs_prim_buffer_depth = 1792;
gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
break;
default:
--
2.5.5
_______________________________________________
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 025/117] drm/amdgpu: add RAVEN family id definition
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 016/117] drm/amdgpu/gfx9: drop duplicate gfx info init (v3) Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 026/117] drm/amdgpu: add Raven ip blocks Alex Deucher
` (92 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
RAVEN is a new APU.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +++++++--
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
include/uapi/drm/amdgpu_drm.h | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 33e0666..9b64864 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,7 @@ static const char *amdgpu_asic_name[] = {
"POLARIS11",
"POLARIS12",
"VEGA10",
+ "RAVEN",
"LAST",
};
@@ -1538,8 +1539,12 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
return r;
break;
#endif
- case CHIP_VEGA10:
- adev->family = AMDGPU_FAMILY_AI;
+ case CHIP_VEGA10:
+ case CHIP_RAVEN:
+ if (adev->asic_type == CHIP_RAVEN)
+ adev->family = AMDGPU_FAMILY_RV;
+ else
+ adev->family = AMDGPU_FAMILY_AI;
r = soc15_set_ip_blocks(adev);
if (r)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 2ccf44e..f006ef6 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -48,6 +48,7 @@ enum amd_asic_type {
CHIP_POLARIS11,
CHIP_POLARIS12,
CHIP_VEGA10,
+ CHIP_RAVEN,
CHIP_LAST,
};
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 20ea895..929bc72 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -862,6 +862,7 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
+#define AMDGPU_FAMILY_RV 142 /* Raven */
/*
* Definition of free sync enter and exit signals
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 026/117] drm/amdgpu: add Raven ip blocks
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 025/117] drm/amdgpu: add RAVEN family id definition Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 027/117] drm/amdgpu/soc15: add Raven golden setting Alex Deucher
` (91 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add the IP blocks for RAVEN.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 70bd2b1..c2292ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -485,6 +485,21 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
break;
+ case CHIP_RAVEN:
+ amdgpu_ip_block_add(adev, &vega10_common_ip_block);
+ amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
+ amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
+ amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
+ amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+ if (amdgpu_device_has_dc_support(adev))
+ amdgpu_ip_block_add(adev, &dm_ip_block);
+#else
+# warning "Enable CONFIG_DRM_AMD_DC for display support on Raven."
+#endif
+ amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
+ amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
+ break;
default:
return -EINVAL;
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 027/117] drm/amdgpu/soc15: add Raven golden setting
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 026/117] drm/amdgpu: add Raven ip blocks Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 028/117] drm/amd/amdgpu: fill in raven case in soc15 early init Alex Deucher
` (90 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add the common golden settings for Raven.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c2292ad..ba40835 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -206,6 +206,10 @@ static const u32 vega10_golden_init[] =
{
};
+static const u32 raven_golden_init[] =
+{
+};
+
static void soc15_init_golden_registers(struct amdgpu_device *adev)
{
/* Some of the registers might be dependent on GRBM_GFX_INDEX */
@@ -217,6 +221,11 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
vega10_golden_init,
(const u32)ARRAY_SIZE(vega10_golden_init));
break;
+ case CHIP_RAVEN:
+ amdgpu_program_register_sequence(adev,
+ raven_golden_init,
+ (const u32)ARRAY_SIZE(raven_golden_init));
+ break;
default:
break;
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 028/117] drm/amd/amdgpu: fill in raven case in soc15 early init
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 027/117] drm/amdgpu/soc15: add Raven golden setting Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 029/117] drm/amdgpu/soc15: add clock gating functions for raven Alex Deucher
` (89 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index ba40835..4ddb55f 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -599,6 +599,11 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
+ case CHIP_RAVEN:
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = 0x1;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 029/117] drm/amdgpu/soc15: add clock gating functions for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 028/117] drm/amd/amdgpu: fill in raven case in soc15 early init Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 030/117] drm/amdgpu: enable soc15 clock gating flags " Alex Deucher
` (88 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4ddb55f..c134cf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -831,6 +831,20 @@ static int soc15_common_set_clockgating_state(void *handle,
soc15_update_df_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
+ case CHIP_RAVEN:
+ nbio_v6_1_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ nbio_v6_1_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_hdp_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_drm_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_drm_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ soc15_update_rom_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
default:
break;
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 030/117] drm/amdgpu: enable soc15 clock gating flags for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 029/117] drm/amdgpu/soc15: add clock gating functions for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 031/117] drm/amdgpu: add Raven chip id case for ucode Alex Deucher
` (87 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c134cf6..3a36968 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -600,7 +600,21 @@ static int soc15_common_early_init(void *handle)
adev->external_rev_id = 0x1;
break;
case CHIP_RAVEN:
- adev->cg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_RLC_LS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_BIF_MGCG |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_DRM_MGCG |
+ AMD_CG_SUPPORT_DRM_LS |
+ AMD_CG_SUPPORT_ROM_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 031/117] drm/amdgpu: add Raven chip id case for ucode
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 030/117] drm/amdgpu: enable soc15 clock gating flags " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 032/117] drm/amdgpu: add module firmware for raven Alex Deucher
` (86 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Set the appropriate ucode loading mechanism. Set to
direct for now.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 38e3ba6..cd6d3d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -274,6 +274,15 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
return AMDGPU_FW_LOAD_DIRECT;
else
return AMDGPU_FW_LOAD_PSP;
+ case CHIP_RAVEN:
+#if 0
+ if (!load_type)
+ return AMDGPU_FW_LOAD_DIRECT;
+ else
+ return AMDGPU_FW_LOAD_PSP;
+#else
+ return AMDGPU_FW_LOAD_DIRECT;
+#endif
default:
DRM_ERROR("Unknow firmware load type\n");
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 032/117] drm/amdgpu: add module firmware for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 031/117] drm/amdgpu: add Raven chip id case for ucode Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 033/117] drm/amdgpu: add gc9.1 golden setting (v2) Alex Deucher
` (85 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Fetch correct firmware for raven for gfx and sdma.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dd1751d..a7440c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,13 @@ MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
+MODULE_FIRMWARE("amdgpu/raven_ce.bin");
+MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
+MODULE_FIRMWARE("amdgpu/raven_me.bin");
+MODULE_FIRMWARE("amdgpu/raven_mec.bin");
+MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
+MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
+
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
{
{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ecc70a7..3c7cbe5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -42,6 +42,7 @@
MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
@@ -1074,7 +1075,10 @@ static int sdma_v4_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- adev->sdma.num_instances = 2;
+ if (adev->asic_type == CHIP_RAVEN)
+ adev->sdma.num_instances = 1;
+ else
+ adev->sdma.num_instances = 2;
sdma_v4_0_set_ring_funcs(adev);
sdma_v4_0_set_buffer_funcs(adev);
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 033/117] drm/amdgpu: add gc9.1 golden setting (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 032/117] drm/amdgpu: add module firmware for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 034/117] drm/amdgpu/gfx9: add chip name for raven when initializing microcode Alex Deucher
` (84 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add the GFX9 golden settings.
v2: squash in updates
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a7440c0..aa28873 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -116,6 +116,27 @@ static const u32 golden_settings_gc_9_0_vg10[] =
};
#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
+static const u32 golden_settings_gc_9_1[] =
+{
+ SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
+ SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
+ SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
+ SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
+ SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
+ SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
+ SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
+ SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
+ SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
+ SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff
+};
+
+static const u32 golden_settings_gc_9_1_rv1[] =
+{
+ SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x26013042,
+ SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x26013042,
+ SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x00048000,
+ SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
+};
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -138,6 +159,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_0_vg10,
(const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
break;
+ case CHIP_RAVEN:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_gc_9_1,
+ (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
+ amdgpu_program_register_sequence(adev,
+ golden_settings_gc_9_1_rv1,
+ (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ break;
default:
break;
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 034/117] drm/amdgpu/gfx9: add chip name for raven when initializing microcode
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 033/117] drm/amdgpu: add gc9.1 golden setting (v2) Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 035/117] drm/amdgpu/gfx9: add raven gfx config Alex Deucher
` (83 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Fetch the correct ucode for raven.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index aa28873..74d6eae 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -328,6 +328,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
case CHIP_VEGA10:
chip_name = "vega10";
break;
+ case CHIP_RAVEN:
+ chip_name = "raven";
+ break;
default:
BUG();
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 035/117] drm/amdgpu/gfx9: add raven gfx config
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 034/117] drm/amdgpu/gfx9: add chip name for raven when initializing microcode Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 036/117] drm/amdgpu: add gfx clock gating for raven Alex Deucher
` (82 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 74d6eae..eb6af63 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -115,7 +115,6 @@ static const u32 golden_settings_gc_9_0_vg10[] =
SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007
};
-#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
static const u32 golden_settings_gc_9_1[] =
{
SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
@@ -138,6 +137,9 @@ static const u32 golden_settings_gc_9_1_rv1[] =
SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
};
+#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
+#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x26013042
+
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
@@ -827,6 +829,14 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
break;
+ case CHIP_RAVEN:
+ adev->gfx.config.max_hw_contexts = 8;
+ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
+ break;
default:
BUG();
break;
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 036/117] drm/amdgpu: add gfx clock gating for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 035/117] drm/amdgpu/gfx9: add raven gfx config Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 037/117] drm/amdgpu/gfx9: extend rlc fw setup Alex Deucher
` (81 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index eb6af63..fefd618 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2877,6 +2877,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_RAVEN:
gfx_v9_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
@@ -3736,6 +3737,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_RAVEN:
adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
break;
default:
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 037/117] drm/amdgpu/gfx9: extend rlc fw setup
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 036/117] drm/amdgpu: add gfx clock gating for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 038/117] drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG Alex Deucher
` (80 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Required for gfx powergating.
Change-Id: I5a2f8f41253686d8bb776a92aa68bf90877ebaa8
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 46 ++++++++++++++++++++++++++++++++---
1 file changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fefd618..6bcf4b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -323,6 +323,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
struct amdgpu_firmware_info *info = NULL;
const struct common_firmware_header *header = NULL;
const struct gfx_firmware_header_v1_0 *cp_hdr;
+ const struct rlc_firmware_header_v2_0 *rlc_hdr;
+ unsigned int *tmp = NULL;
+ unsigned int i = 0;
DRM_DEBUG("\n");
@@ -375,9 +378,46 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
if (err)
goto out;
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
- cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
- adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
- adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+ rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+ adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
+ adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
+ adev->gfx.rlc.save_and_restore_offset =
+ le32_to_cpu(rlc_hdr->save_and_restore_offset);
+ adev->gfx.rlc.clear_state_descriptor_offset =
+ le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
+ adev->gfx.rlc.avail_scratch_ram_locations =
+ le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
+ adev->gfx.rlc.reg_restore_list_size =
+ le32_to_cpu(rlc_hdr->reg_restore_list_size);
+ adev->gfx.rlc.reg_list_format_start =
+ le32_to_cpu(rlc_hdr->reg_list_format_start);
+ adev->gfx.rlc.reg_list_format_separate_start =
+ le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
+ adev->gfx.rlc.starting_offsets_start =
+ le32_to_cpu(rlc_hdr->starting_offsets_start);
+ adev->gfx.rlc.reg_list_format_size_bytes =
+ le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
+ adev->gfx.rlc.reg_list_size_bytes =
+ le32_to_cpu(rlc_hdr->reg_list_size_bytes);
+ adev->gfx.rlc.register_list_format =
+ kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
+ adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
+ if (!adev->gfx.rlc.register_list_format) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+ le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
+ for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
+ adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
+
+ adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
+
+ tmp = (unsigned int *)((uintptr_t)rlc_hdr +
+ le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
+ for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
+ adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 038/117] drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 037/117] drm/amdgpu/gfx9: extend rlc fw setup Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 039/117] drm/amdgpu: correct gfx9 csb size Alex Deucher
` (79 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Required for proper handshaking between the GFX and RLC.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6bcf4b6..c8c441d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1460,9 +1460,6 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
{
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
- if (enable)
- return;
-
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 039/117] drm/amdgpu: correct gfx9 csb size
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 038/117] drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 040/117] drm/amdgpu/gfx9: add rlc bo init/fini Alex Deucher
` (78 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
programming pa_sc_raster_config/config1 reg is removed from gfx9 csb
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8c441d..e8b07c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1665,8 +1665,6 @@ static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
return 0;
}
}
- /* pa_sc_raster_config/pa_sc_raster_config1 */
- count += 4;
/* end clear state */
count += 2;
/* clear state */
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 040/117] drm/amdgpu/gfx9: add rlc bo init/fini
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 039/117] drm/amdgpu: correct gfx9 csb size Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 041/117] drm/amdgpu/gfx9: rlc save&restore list programming Alex Deucher
` (77 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
setup the save and restore buffers used for gfx
powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 236 ++++++++++++++++++++++++++++++----
1 file changed, 209 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e8b07c9..d74d3f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -529,6 +529,209 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
return err;
}
+static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
+{
+ u32 count = 0;
+ const struct cs_section_def *sect = NULL;
+ const struct cs_extent_def *ext = NULL;
+
+ /* begin clear state */
+ count += 2;
+ /* context control state */
+ count += 3;
+
+ for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
+ for (ext = sect->section; ext->extent != NULL; ++ext) {
+ if (sect->id == SECT_CONTEXT)
+ count += 2 + ext->reg_count;
+ else
+ return 0;
+ }
+ }
+
+ /* end clear state */
+ count += 2;
+ /* clear state */
+ count += 2;
+
+ return count;
+}
+
+static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
+ volatile u32 *buffer)
+{
+ u32 count = 0, i;
+ const struct cs_section_def *sect = NULL;
+ const struct cs_extent_def *ext = NULL;
+
+ if (adev->gfx.rlc.cs_data == NULL)
+ return;
+ if (buffer == NULL)
+ return;
+
+ buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+ buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
+
+ buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
+ buffer[count++] = cpu_to_le32(0x80000000);
+ buffer[count++] = cpu_to_le32(0x80000000);
+
+ for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
+ for (ext = sect->section; ext->extent != NULL; ++ext) {
+ if (sect->id == SECT_CONTEXT) {
+ buffer[count++] =
+ cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
+ buffer[count++] = cpu_to_le32(ext->reg_index -
+ PACKET3_SET_CONTEXT_REG_START);
+ for (i = 0; i < ext->reg_count; i++)
+ buffer[count++] = cpu_to_le32(ext->extent[i]);
+ } else {
+ return;
+ }
+ }
+ }
+
+ buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+ buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
+
+ buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
+ buffer[count++] = cpu_to_le32(0);
+}
+
+static void rv_init_cp_jump_table(struct amdgpu_device *adev)
+{
+ const __le32 *fw_data;
+ volatile u32 *dst_ptr;
+ int me, i, max_me = 5;
+ u32 bo_offset = 0;
+ u32 table_offset, table_size;
+
+ /* write the cp table buffer */
+ dst_ptr = adev->gfx.rlc.cp_table_ptr;
+ for (me = 0; me < max_me; me++) {
+ if (me == 0) {
+ const struct gfx_firmware_header_v1_0 *hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+ fw_data = (const __le32 *)
+ (adev->gfx.ce_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ table_offset = le32_to_cpu(hdr->jt_offset);
+ table_size = le32_to_cpu(hdr->jt_size);
+ } else if (me == 1) {
+ const struct gfx_firmware_header_v1_0 *hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+ fw_data = (const __le32 *)
+ (adev->gfx.pfp_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ table_offset = le32_to_cpu(hdr->jt_offset);
+ table_size = le32_to_cpu(hdr->jt_size);
+ } else if (me == 2) {
+ const struct gfx_firmware_header_v1_0 *hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+ fw_data = (const __le32 *)
+ (adev->gfx.me_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ table_offset = le32_to_cpu(hdr->jt_offset);
+ table_size = le32_to_cpu(hdr->jt_size);
+ } else if (me == 3) {
+ const struct gfx_firmware_header_v1_0 *hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+ fw_data = (const __le32 *)
+ (adev->gfx.mec_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ table_offset = le32_to_cpu(hdr->jt_offset);
+ table_size = le32_to_cpu(hdr->jt_size);
+ } else if (me == 4) {
+ const struct gfx_firmware_header_v1_0 *hdr =
+ (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
+ fw_data = (const __le32 *)
+ (adev->gfx.mec2_fw->data +
+ le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ table_offset = le32_to_cpu(hdr->jt_offset);
+ table_size = le32_to_cpu(hdr->jt_size);
+ }
+
+ for (i = 0; i < table_size; i ++) {
+ dst_ptr[bo_offset + i] =
+ cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
+ }
+
+ bo_offset += table_size;
+ }
+}
+
+static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
+{
+ /* clear state block */
+ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
+ &adev->gfx.rlc.clear_state_gpu_addr,
+ (void **)&adev->gfx.rlc.cs_ptr);
+
+ /* jump table block */
+ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+ &adev->gfx.rlc.cp_table_gpu_addr,
+ (void **)&adev->gfx.rlc.cp_table_ptr);
+}
+
+static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+{
+ volatile u32 *dst_ptr;
+ u32 dws;
+ const struct cs_section_def *cs_data;
+ int r;
+
+ adev->gfx.rlc.cs_data = gfx9_cs_data;
+
+ cs_data = adev->gfx.rlc.cs_data;
+
+ if (cs_data) {
+ /* clear state block */
+ adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
+ if (adev->gfx.rlc.clear_state_obj == NULL) {
+ r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->gfx.rlc.clear_state_obj,
+ &adev->gfx.rlc.clear_state_gpu_addr,
+ (void **)&adev->gfx.rlc.cs_ptr);
+ if (r) {
+ dev_err(adev->dev,
+ "(%d) failed to create rlc csb bo\n", r);
+ gfx_v9_0_rlc_fini(adev);
+ return r;
+ }
+ }
+ /* set up the cs buffer */
+ dst_ptr = adev->gfx.rlc.cs_ptr;
+ gfx_v9_0_get_csb_buffer(adev, dst_ptr);
+ amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+ }
+
+ if (adev->asic_type == CHIP_RAVEN) {
+ /* TODO: double check the cp_table_size for RV */
+ adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
+ if (adev->gfx.rlc.cp_table_obj == NULL) {
+ r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->gfx.rlc.cp_table_obj,
+ &adev->gfx.rlc.cp_table_gpu_addr,
+ (void **)&adev->gfx.rlc.cp_table_ptr);
+ if (r) {
+ dev_err(adev->dev,
+ "(%d) failed to create cp table bo\n", r);
+ gfx_v9_0_rlc_fini(adev);
+ return r;
+ }
+ }
+
+ rv_init_cp_jump_table(adev);
+ amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
+ amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
+ }
+
+ return 0;
+}
+
static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
{
int r;
@@ -1152,6 +1355,12 @@ static int gfx_v9_0_sw_init(void *handle)
return r;
}
+ r = gfx_v9_0_rlc_init(adev);
+ if (r) {
+ DRM_ERROR("Failed to init rlc BOs!\n");
+ return r;
+ }
+
r = gfx_v9_0_mec_init(adev);
if (r) {
DRM_ERROR("Failed to init MEC BOs!\n");
@@ -1646,33 +1855,6 @@ static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
return 0;
}
-static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
-{
- u32 count = 0;
- const struct cs_section_def *sect = NULL;
- const struct cs_extent_def *ext = NULL;
-
- /* begin clear state */
- count += 2;
- /* context control state */
- count += 3;
-
- for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
- for (ext = sect->section; ext->extent != NULL; ++ext) {
- if (sect->id == SECT_CONTEXT)
- count += 2 + ext->reg_count;
- else
- return 0;
- }
- }
- /* end clear state */
- count += 2;
- /* clear state */
- count += 2;
-
- return count;
-}
-
static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 041/117] drm/amdgpu/gfx9: rlc save&restore list programming
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (31 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 040/117] drm/amdgpu/gfx9: add rlc bo init/fini Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 042/117] drm/amdgpu: init gfx power gating on raven Alex Deucher
` (76 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 169 +++++++++++++++++++++++++++++++++-
1 file changed, 168 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d74d3f7..4732fc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -39,7 +39,9 @@
#define GFX9_NUM_GFX_RINGS 1
#define GFX9_NUM_COMPUTE_RINGS 8
-#define RLCG_UCODE_LOADING_START_ADDRESS 0x2000
+#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
+#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
@@ -1677,6 +1679,169 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
}
+static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
+{
+ /* csib */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
+ adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
+ adev->gfx.rlc.clear_state_size);
+}
+
+static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
+ int indirect_offset,
+ int list_size,
+ int *unique_indirect_regs,
+ int *unique_indirect_reg_count,
+ int max_indirect_reg_count,
+ int *indirect_start_offsets,
+ int *indirect_start_offsets_count,
+ int max_indirect_start_offsets_count)
+{
+ int idx;
+ bool new_entry = true;
+
+ for (; indirect_offset < list_size; indirect_offset++) {
+
+ if (new_entry) {
+ new_entry = false;
+ indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
+ *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
+ BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
+ }
+
+ if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
+ new_entry = true;
+ continue;
+ }
+
+ indirect_offset += 2;
+
+ /* look for the matching indice */
+ for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
+ if (unique_indirect_regs[idx] ==
+ register_list_format[indirect_offset])
+ break;
+ }
+
+ if (idx >= *unique_indirect_reg_count) {
+ unique_indirect_regs[*unique_indirect_reg_count] =
+ register_list_format[indirect_offset];
+ idx = *unique_indirect_reg_count;
+ *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
+ BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
+ }
+
+ register_list_format[indirect_offset] = idx;
+ }
+}
+
+static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
+{
+ int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+ int unique_indirect_reg_count = 0;
+
+ int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+ int indirect_start_offsets_count = 0;
+
+ int list_size = 0;
+ int i = 0;
+ u32 tmp = 0;
+
+ u32 *register_list_format =
+ kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
+ if (!register_list_format)
+ return -ENOMEM;
+ memcpy(register_list_format, adev->gfx.rlc.register_list_format,
+ adev->gfx.rlc.reg_list_format_size_bytes);
+
+ /* setup unique_indirect_regs array and indirect_start_offsets array */
+ gfx_v9_0_parse_ind_reg_list(register_list_format,
+ GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
+ adev->gfx.rlc.reg_list_format_size_bytes >> 2,
+ unique_indirect_regs,
+ &unique_indirect_reg_count,
+ sizeof(unique_indirect_regs)/sizeof(int),
+ indirect_start_offsets,
+ &indirect_start_offsets_count,
+ sizeof(indirect_start_offsets)/sizeof(int));
+
+ /* enable auto inc in case it is disabled */
+ tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+ tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+
+ /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
+ RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
+ for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
+ adev->gfx.rlc.register_restore[i]);
+
+ /* load direct register */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
+ for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
+ adev->gfx.rlc.register_restore[i]);
+
+ /* load indirect register */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
+ adev->gfx.rlc.reg_list_format_start);
+ for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
+ register_list_format[i]);
+
+ /* set save/restore list size */
+ list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
+ list_size = list_size >> 1;
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
+ adev->gfx.rlc.reg_restore_list_size);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
+
+ /* write the starting offsets to RLC scratch ram */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
+ adev->gfx.rlc.starting_offsets_start);
+ for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
+ indirect_start_offsets[i]);
+
+ /* load unique indirect regs*/
+ for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
+ unique_indirect_regs[i] & 0x3FFFF);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
+ unique_indirect_regs[i] >> 20);
+ }
+
+ kfree(register_list_format);
+ return 0;
+}
+
+static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
+{
+ u32 tmp = 0;
+
+ tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+ tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+}
+
+static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
+{
+ if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_GFX_SMG |
+ AMD_PG_SUPPORT_GFX_DMG |
+ AMD_PG_SUPPORT_CP |
+ AMD_PG_SUPPORT_GDS |
+ AMD_PG_SUPPORT_RLC_SMU_HS)) {
+ gfx_v9_0_init_csb(adev);
+ gfx_v9_0_init_rlc_save_restore_list(adev);
+ gfx_v9_0_enable_save_restore_machine(adev);
+ }
+}
+
void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
@@ -1770,6 +1935,8 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
gfx_v9_0_rlc_reset(adev);
+ gfx_v9_0_init_pg(adev);
+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
/* legacy rlc firmware loading */
r = gfx_v9_0_rlc_load_microcode(adev);
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 042/117] drm/amdgpu: init gfx power gating on raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (32 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 041/117] drm/amdgpu/gfx9: rlc save&restore list programming Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 043/117] drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake Alex Deucher
` (75 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 81 +++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 4732fc6..04cd04c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -43,6 +43,13 @@
#define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
+#define mmPWR_MISC_CNTL_STATUS 0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
+
MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
MODULE_FIRMWARE("amdgpu/vega10_me.bin");
@@ -1828,6 +1835,74 @@ static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
}
+static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data = 0;
+ uint32_t default_data = 0;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
+ if (enable == true) {
+ /* enable GFXIP control over CGPG */
+ data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
+
+ /* update status */
+ data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
+ data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
+ } else {
+ /* restore GFXIP control over GCPG */
+ data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
+ }
+}
+
+static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
+{
+ uint32_t data = 0;
+
+ if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_GFX_SMG |
+ AMD_PG_SUPPORT_GFX_DMG)) {
+ /* init IDLE_POLL_COUNT = 60 */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
+ data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
+ data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
+
+ /* init RLC PG Delay */
+ data = 0;
+ data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
+ data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
+ data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
+ data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
+
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
+ data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
+ data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
+
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
+ data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
+ data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
+
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
+ data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
+
+ /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
+ data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
+
+ pwr_10_0_gfxip_control_over_cgpg(adev, true);
+ }
+}
+
static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
{
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -1839,6 +1914,12 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
gfx_v9_0_init_csb(adev);
gfx_v9_0_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
+
+ if (adev->asic_type == CHIP_RAVEN) {
+ WREG32(mmRLC_JUMP_TABLE_RESTORE,
+ adev->gfx.rlc.cp_table_gpu_addr >> 8);
+ gfx_v9_0_init_gfx_power_gating(adev);
+ }
}
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 043/117] drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (33 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 042/117] drm/amdgpu: init gfx power gating on raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 044/117] drm/amdgpu/gfx9: add enable/disable funcs for cp power gating Alex Deucher
` (74 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Required for proper powergating operation.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 45 +++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 04cd04c..5be4676 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1903,6 +1903,44 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
}
}
+static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data = 0;
+ uint32_t default_data = 0;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+
+ if (enable == true) {
+ data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
+ if (default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ } else {
+ data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ }
+}
+
+static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data = 0;
+ uint32_t default_data = 0;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+
+ if (enable == true) {
+ data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ } else {
+ data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ }
+}
+
static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
{
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -1919,6 +1957,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
WREG32(mmRLC_JUMP_TABLE_RESTORE,
adev->gfx.rlc.cp_table_gpu_addr >> 8);
gfx_v9_0_init_gfx_power_gating(adev);
+ if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
+ gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
+ gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
+ } else {
+ gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
+ gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
+ }
}
}
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 044/117] drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (34 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 043/117] drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 045/117] drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state Alex Deucher
` (73 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Used to enable/disable cp powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5be4676..c8f236d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1941,6 +1941,25 @@ static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *ad
}
}
+static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data = 0;
+ uint32_t default_data = 0;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+
+ if (enable == true) {
+ data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ } else {
+ data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+ }
+}
+
static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
{
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -1957,6 +1976,7 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
WREG32(mmRLC_JUMP_TABLE_RESTORE,
adev->gfx.rlc.cp_table_gpu_addr >> 8);
gfx_v9_0_init_gfx_power_gating(adev);
+
if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
@@ -1964,6 +1984,11 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
}
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_CP)
+ gfx_v9_0_enable_cp_power_gating(adev, true);
+ else
+ gfx_v9_0_enable_cp_power_gating(adev, false);
}
}
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 045/117] drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (35 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 044/117] drm/amdgpu/gfx9: add enable/disable funcs for cp power gating Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 046/117] drm/amdgpu/gfx9: allow updating gfx cgpg state Alex Deucher
` (72 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
More stuff for gfx pg.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8f236d..8e0f7e68 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3399,6 +3399,27 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
static int gfx_v9_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
+ gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
+ gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
+ } else {
+ gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
+ gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
+ }
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_CP)
+ gfx_v9_0_enable_cp_power_gating(adev, true);
+ else
+ gfx_v9_0_enable_cp_power_gating(adev, false);
+ break;
+ default:
+ break;
+ }
+
return 0;
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 046/117] drm/amdgpu/gfx9: allow updating gfx cgpg state
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (36 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 045/117] drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 047/117] drm/amdgpu/gfx9: allow updating gfx mgpg state Alex Deucher
` (71 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Wire up the enable functions to enable coarse
grained powegating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 54 +++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8e0f7e68..bba13c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1960,6 +1960,38 @@ static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
}
}
+static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, default_data;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+ if (enable == true)
+ data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ else
+ data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+}
+
+static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, default_data;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+ if (enable == true)
+ data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
+ else
+ data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+
+ if (!enable)
+ /* read any GFX register to wake up GFX */
+ data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
+}
+
static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
{
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -3209,6 +3241,24 @@ static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
}
}
+static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ /* TODO: double check if we need to perform under safe mdoe */
+ /* gfx_v9_0_enter_rlc_safe_mode(adev); */
+
+ if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
+ gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
+ if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
+ gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
+ } else {
+ gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
+ gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
+ }
+
+ /* gfx_v9_0_exit_rlc_safe_mode(adev); */
+}
+
static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{
@@ -3400,6 +3450,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
switch (adev->asic_type) {
case CHIP_RAVEN:
@@ -3415,6 +3466,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
gfx_v9_0_enable_cp_power_gating(adev, true);
else
gfx_v9_0_enable_cp_power_gating(adev, false);
+
+ /* update gfx cgpg state */
+ gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
break;
default:
break;
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 047/117] drm/amdgpu/gfx9: allow updating gfx mgpg state
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (37 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 046/117] drm/amdgpu/gfx9: allow updating gfx cgpg state Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 048/117] drm/amdgpu: add raven case for gmc9 golden setting Alex Deucher
` (70 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Wire up the functions to control medium grained
powergating.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 50 +++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bba13c7..a1e1b7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1992,6 +1992,34 @@ static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
}
+void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, default_data;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+ if (enable == true)
+ data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+ else
+ data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+}
+
+void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t data, default_data;
+
+ default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
+ if (enable == true)
+ data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+ else
+ data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
+ if(default_data != data)
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
+}
+
static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
{
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
@@ -3259,6 +3287,25 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
/* gfx_v9_0_exit_rlc_safe_mode(adev); */
}
+static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ /* TODO: double check if we need to perform under safe mode */
+ /* gfx_v9_0_enter_rlc_safe_mode(adev); */
+
+ if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
+ gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
+ else
+ gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
+
+ if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
+ gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
+ else
+ gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
+
+ /* gfx_v9_0_exit_rlc_safe_mode(adev); */
+}
+
static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{
@@ -3469,6 +3516,9 @@ static int gfx_v9_0_set_powergating_state(void *handle,
/* update gfx cgpg state */
gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
+
+ /* update mgcg state */
+ gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
break;
default:
break;
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 048/117] drm/amdgpu: add raven case for gmc9 golden setting
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (38 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 047/117] drm/amdgpu/gfx9: allow updating gfx mgpg state Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 049/117] drm/amdgpu/gmc9: set mc vm fb offset for raven Alex Deucher
` (69 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Golden settings for GMC9.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b9f11fa..d5db654 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -686,6 +686,8 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_VEGA10:
break;
+ case CHIP_RAVEN:
+ break;
default:
break;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 049/117] drm/amdgpu/gmc9: set mc vm fb offset for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (39 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 048/117] drm/amdgpu: add raven case for gmc9 golden setting Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 050/117] drm/amdgpu/gmc9: change fb offset sequence so that used wider Alex Deucher
` (68 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
APU fb offset is set by sbios, which is different with DGPU.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +++++
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++--
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 005075f..bd1976a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -31,6 +31,11 @@
#include "soc15_common.h"
+u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
+{
+ return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
+}
+
int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
{
u32 tmp;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
index 5129a8f..1541848 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
@@ -28,7 +28,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);
void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);
void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
bool value);
-
+u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);
extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;
extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d5db654..d1e02de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -548,8 +548,10 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
amdgpu_vm_manager_init(adev);
/* base offset of vram pages */
- /*XXX This value is not zero for APU*/
- adev->vm_manager.vram_base_offset = 0;
+ if (adev->flags & AMD_IS_APU)
+ adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
+ else
+ adev->vm_manager.vram_base_offset = 0;
return 0;
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 050/117] drm/amdgpu/gmc9: change fb offset sequence so that used wider
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (40 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 049/117] drm/amdgpu/gmc9: set mc vm fb offset for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 051/117] drm/amdgpu: add raven clock gating and light sleep for mmhub Alex Deucher
` (67 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Initialize the values earlier.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index d1e02de..7a875ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -415,6 +415,11 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
amdgpu_vram_location(adev, &adev->mc, base);
adev->mc.gtt_base_align = 0;
amdgpu_gtt_location(adev, mc);
+ /* base offset of vram pages */
+ if (adev->flags & AMD_IS_APU)
+ adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
+ else
+ adev->vm_manager.vram_base_offset = 0;
}
/**
@@ -547,12 +552,6 @@ static int gmc_v9_0_vm_init(struct amdgpu_device *adev)
adev->vm_manager.num_level = 3;
amdgpu_vm_manager_init(adev);
- /* base offset of vram pages */
- if (adev->flags & AMD_IS_APU)
- adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
- else
- adev->vm_manager.vram_base_offset = 0;
-
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 051/117] drm/amdgpu: add raven clock gating and light sleep for mmhub
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (41 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 050/117] drm/amdgpu/gmc9: change fb offset sequence so that used wider Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 052/117] drm/amdgpu: enable MC MGCG and LS for raven Alex Deucher
` (66 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +++++++++++++++++++++------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index dbfe48d..ac9c95c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -34,6 +34,9 @@
#include "soc15_common.h"
+#define mmDAGB0_CNTL_MISC2_RV 0x008f
+#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
+
u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
{
u64 base = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE));
@@ -407,11 +410,15 @@ static int mmhub_v1_0_soft_reset(void *handle)
static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{
- uint32_t def, data, def1, data1, def2, data2;
+ uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
def = data = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG));
- def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2));
- def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2));
+
+ if (adev->asic_type != CHIP_RAVEN) {
+ def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2));
+ def2 = data2 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2));
+ } else
+ def1 = data1 = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
data |= ATC_L2_MISC_CG__ENABLE_MASK;
@@ -423,12 +430,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
- data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+ if (adev->asic_type != CHIP_RAVEN)
+ data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
} else {
data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
@@ -439,21 +447,26 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
- data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
- DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+ if (adev->asic_type != CHIP_RAVEN)
+ data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
}
if (def != data)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmATC_L2_MISC_CG), data);
- if (def1 != data1)
- WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1);
+ if (def1 != data1) {
+ if (adev->asic_type != CHIP_RAVEN)
+ WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2), data1);
+ else
+ WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV), data1);
+ }
- if (def2 != data2)
+ if (adev->asic_type != CHIP_RAVEN && def2 != data2)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_CNTL_MISC2), data2);
}
@@ -516,6 +529,7 @@ static int mmhub_v1_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_RAVEN:
mmhub_v1_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
athub_update_medium_grain_clock_gating(adev,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 052/117] drm/amdgpu: enable MC MGCG and LS for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (42 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 051/117] drm/amdgpu: add raven clock gating and light sleep for mmhub Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 053/117] drm/amdgpu: add Raven sdma golden setting and chip id case Alex Deucher
` (65 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 3a36968..d46dbf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -614,7 +614,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_DRM_MGCG |
AMD_CG_SUPPORT_DRM_LS |
- AMD_CG_SUPPORT_ROM_MGCG;
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS;
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 053/117] drm/amdgpu: add Raven sdma golden setting and chip id case
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (43 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 052/117] drm/amdgpu: enable MC MGCG and LS for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 054/117] drm/amdgpu: reuse sdma v4 MGCG and LS function for raven Alex Deucher
` (64 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add golden settings for SDMA.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3c7cbe5..645be90 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -83,6 +83,26 @@ static const u32 golden_settings_sdma_vg10[] = {
SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
};
+static const u32 golden_settings_sdma_4_1[] =
+{
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
+};
+
+static const u32 golden_settings_sdma_rv1[] =
+{
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00003002,
+ SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00003002
+};
+
static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
{
u32 base = 0;
@@ -113,6 +133,14 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_vg10,
(const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
break;
+ case CHIP_RAVEN:
+ amdgpu_program_register_sequence(adev,
+ golden_settings_sdma_4_1,
+ (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
+ amdgpu_program_register_sequence(adev,
+ golden_settings_sdma_rv1,
+ (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
+ break;
default:
break;
}
@@ -159,6 +187,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
case CHIP_VEGA10:
chip_name = "vega10";
break;
+ case CHIP_RAVEN:
+ chip_name = "raven";
+ break;
default:
BUG();
}
@@ -1415,6 +1446,8 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
+ case CHIP_RAVEN:
+ break;
default:
break;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 054/117] drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (44 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 053/117] drm/amdgpu: add Raven sdma golden setting and chip id case Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 055/117] drm/amdgpu: enable sdma v4 MGCG and LS " Alex Deucher
` (63 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 645be90..2afcadb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1441,13 +1441,12 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_RAVEN:
sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
sdma_v4_0_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
- case CHIP_RAVEN:
- break;
default:
break;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 055/117] drm/amdgpu: enable sdma v4 MGCG and LS for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (45 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 054/117] drm/amdgpu: reuse sdma v4 MGCG and LS function for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 056/117] drm/amdgpu: init sdma power gating " Alex Deucher
` (62 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index d46dbf3..cd0be4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -616,7 +616,9 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG |
- AMD_CG_SUPPORT_MC_LS;
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
adev->pg_flags = 0;
adev->external_rev_id = 0x1;
break;
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 056/117] drm/amdgpu: init sdma power gating for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (46 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 055/117] drm/amdgpu: enable sdma v4 MGCG and LS " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 057/117] drm/amdgpu/sdma4: add dynamic " Alex Deucher
` (61 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Initialize sdma for powergating.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 48 +++++++++++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 2afcadb..3d24e50 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,6 +35,7 @@
#include "vega10/MMHUB/mmhub_1_0_offset.h"
#include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
#include "vega10/HDP/hdp_4_0_offset.h"
+#include "raven1/SDMA0/sdma0_4_1_default.h"
#include "soc15_common.h"
#include "soc15.h"
@@ -44,6 +45,9 @@ MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
+
static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -665,6 +669,47 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
return 0;
}
+static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
+{
+ uint32_t def, data;
+
+ /* Enable HW based PG. */
+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+ data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
+ if (data != def)
+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+
+ /* enable interrupt */
+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
+ data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
+ if (data != def)
+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
+
+ /* Configure hold time to filter in-valid power on/off request. Use default right now */
+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
+ data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
+ data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
+ /* Configure switch time for hysteresis purpose. Use default right now */
+ data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
+ data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
+ if(data != def)
+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
+}
+
+static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
+{
+ if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
+ return;
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ sdma_v4_1_init_power_gating(adev);
+ break;
+ default:
+ break;
+ }
+}
+
/**
* sdma_v4_0_rlc_resume - setup and start the async dma engines
*
@@ -675,7 +720,8 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
*/
static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
{
- /* XXX todo */
+ sdma_v4_0_init_pg(adev);
+
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 057/117] drm/amdgpu/sdma4: add dynamic power gating for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (47 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 056/117] drm/amdgpu: init sdma power gating " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 058/117] drm/amdgpu: enable sdma " Alex Deucher
` (60 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add the functions to enable dynamic powergating.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3d24e50..e4825a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -669,6 +669,27 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
return 0;
}
+static void
+sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
+{
+ uint32_t def, data;
+
+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
+ /* disable idle interrupt */
+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
+ data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
+
+ if (data != def)
+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
+ } else {
+ /* disable idle interrupt */
+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
+ data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
+ if (data != def)
+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
+ }
+}
+
static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
{
uint32_t def, data;
@@ -704,6 +725,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
switch (adev->asic_type) {
case CHIP_RAVEN:
sdma_v4_1_init_power_gating(adev);
+ sdma_v4_1_update_power_gating(adev, true);
break;
default:
break;
@@ -1502,6 +1524,17 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
static int sdma_v4_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ sdma_v4_1_update_power_gating(adev,
+ state == AMD_PG_STATE_GATE ? true : false);
+ break;
+ default:
+ break;
+ }
+
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 058/117] drm/amdgpu: enable sdma power gating for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (48 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 057/117] drm/amdgpu/sdma4: add dynamic " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 059/117] drm/amdgpu: add nbio7 support Alex Deucher
` (59 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index cd0be4a..26d415c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -619,7 +619,7 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS;
- adev->pg_flags = 0;
+ adev->pg_flags = AMD_PG_SUPPORT_SDMA;
adev->external_rev_id = 0x1;
break;
default:
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 059/117] drm/amdgpu: add nbio7 support
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (49 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 058/117] drm/amdgpu: enable sdma " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 060/117] drm/amdgpu: apply nbio7 for Raven (v3) Alex Deucher
` (58 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
NBIO handles misc bus io functions on the chip. This
helper lib has the apppropriate functions for NBIO 7.0.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 ++++++++
3 files changed, 270 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index d227695..b8a94d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -40,7 +40,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
amdgpu-y += \
- vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o
+ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o
# add GMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
new file mode 100644
index 0000000..7e1206d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "nbio_v7_0.h"
+
+#include "vega10/soc15ip.h"
+#include "raven1/NBIO/nbio_7_0_default.h"
+#include "raven1/NBIO/nbio_7_0_offset.h"
+#include "raven1/NBIO/nbio_7_0_sh_mask.h"
+#include "vega10/vega10_enum.h"
+
+#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
+
+u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
+{
+ u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0));
+
+ tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+ tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+ return tmp;
+}
+
+u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
+ uint32_t idx)
+{
+ return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx);
+}
+
+void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
+ uint32_t idx, uint32_t val)
+{
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val);
+}
+
+void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+ if (enable)
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN),
+ BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
+ else
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0);
+}
+
+void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
+{
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+}
+
+u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
+{
+ return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_CONFIG_MEMSIZE));
+}
+
+static const u32 nbio_sdma_doorbell_range_reg[] =
+{
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
+ SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
+};
+
+void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index)
+{
+ u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+ } else
+ doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
+
+ WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
+}
+
+void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+ u32 tmp;
+
+ tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DOORBELL_APER_EN));
+ if (enable)
+ tmp = REG_SET_FIELD(tmp, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
+ else
+ tmp = REG_SET_FIELD(tmp, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
+
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DOORBELL_APER_EN), tmp);
+}
+
+void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index)
+{
+ u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE));
+
+ if (use_doorbell) {
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
+ } else
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
+
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range);
+}
+
+static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
+{
+ uint32_t data;
+
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
+ data = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA));
+
+ return data;
+}
+
+static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
+ uint32_t data)
+{
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_INDEX), offset);
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmSYSHUB_DATA), data);
+}
+
+void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ /* NBIF_MGCG_CTRL_LCLK */
+ def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+ data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
+ else
+ data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
+
+ if (def != data)
+ WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
+
+ /* SYSHUB_MGCG_CTRL_SOCCLK */
+ def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+ data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
+ else
+ data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
+
+ if (def != data)
+ nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
+
+ /* SYSHUB_MGCG_CTRL_SHUBCLK */
+ def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
+
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
+ data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
+ else
+ data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
+
+ if (def != data)
+ nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
+}
+
+void nbio_v7_0_ih_control(struct amdgpu_device *adev)
+{
+ u32 interrupt_cntl;
+
+ /* setup interrupt control */
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8);
+ interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL));
+ /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+ */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
+ /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
+ WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl);
+}
+
+struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
+struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+
+int nbio_v7_0_init(struct amdgpu_device *adev)
+{
+ nbio_v7_0_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
+ nbio_v7_0_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
+ nbio_v7_0_hdp_flush_reg.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
+
+ nbio_v7_0_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
+ nbio_v7_0_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
new file mode 100644
index 0000000..054ff49
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __NBIO_V7_0_H__
+#define __NBIO_V7_0_H__
+
+#include "soc15_common.h"
+
+extern struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg;
+extern struct nbio_pcie_index_data nbio_v7_0_pcie_index_data;
+int nbio_v7_0_init(struct amdgpu_device *adev);
+u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
+ uint32_t idx);
+void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
+ uint32_t idx, uint32_t val);
+void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable);
+void nbio_v7_0_hdp_flush(struct amdgpu_device *adev);
+u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev);
+void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index);
+void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable);
+void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index);
+void nbio_v7_0_ih_control(struct amdgpu_device *adev);
+u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev);
+void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable);
+#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 060/117] drm/amdgpu: apply nbio7 for Raven (v3)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (50 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 059/117] drm/amdgpu: add nbio7 support Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 061/117] drm/amdgpu: add nbio MGCG for raven Alex Deucher
` (57 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
nbio handles misc bus io operations. Handle
differences between different nbio bus versions.
v2: switch checks from RAVEN to APU (Alex)
squash in raven rev id fetch
squash in fix uninitalized hdp flush reg index for raven
v3: add some missed RAVEN to APU checks (Alex)
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 ++++++++++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 9 ++++++--
drivers/gpu/drm/amd/amdgpu/soc15.c | 38 ++++++++++++++++++++++++----------
drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +++++++--
5 files changed, 54 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7a875ff..627d442 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -33,6 +33,7 @@
#include "soc15_common.h"
#include "nbio_v6_1.h"
+#include "nbio_v7_0.h"
#include "gfxhub_v1_0.h"
#include "mmhub_v1_0.h"
@@ -215,7 +216,10 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
unsigned i, j;
/* flush hdp cache */
- nbio_v6_1_hdp_flush(adev);
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_hdp_flush(adev);
+ else
+ nbio_v6_1_hdp_flush(adev);
spin_lock(&adev->mc.invalidate_lock);
@@ -479,7 +483,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
/* size in MB on si */
adev->mc.mc_vram_size =
- nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL;
+ ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
+ nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
adev->mc.real_vram_size = adev->mc.mc_vram_size;
adev->mc.visible_vram_size = adev->mc.aper_size;
@@ -718,7 +723,10 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
return r;
/* After HDP is initialized, flush HDP.*/
- nbio_v6_1_hdp_flush(adev);
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_hdp_flush(adev);
+ else
+ nbio_v6_1_hdp_flush(adev);
r = gfxhub_v1_0_gart_enable(adev);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index e4825a3..76cb766 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -386,7 +386,9 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
u32 ref_and_mask = 0;
struct nbio_hdp_flush_reg *nbio_hf_reg;
- if (ring->adev->asic_type == CHIP_VEGA10)
+ if (ring->adev->flags & AMD_IS_APU)
+ nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
+ else
nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
if (ring == &ring->adev->sdma.instance[0].ring)
@@ -617,7 +619,10 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
}
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
- nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
+ else
+ nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
if (amdgpu_sriov_vf(adev))
sdma_v4_0_ring_set_wptr(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 26d415c..853b0e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -104,10 +104,10 @@ static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
u32 r;
struct nbio_pcie_index_data *nbio_pcie_id;
- if (adev->asic_type == CHIP_VEGA10)
- nbio_pcie_id = &nbio_v6_1_pcie_index_data;
+ if (adev->flags & AMD_IS_APU)
+ nbio_pcie_id = &nbio_v7_0_pcie_index_data;
else
- BUG();
+ nbio_pcie_id = &nbio_v6_1_pcie_index_data;
address = nbio_pcie_id->index_offset;
data = nbio_pcie_id->data_offset;
@@ -125,10 +125,10 @@ static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
unsigned long flags, address, data;
struct nbio_pcie_index_data *nbio_pcie_id;
- if (adev->asic_type == CHIP_VEGA10)
- nbio_pcie_id = &nbio_v6_1_pcie_index_data;
+ if (adev->flags & AMD_IS_APU)
+ nbio_pcie_id = &nbio_v7_0_pcie_index_data;
else
- BUG();
+ nbio_pcie_id = &nbio_v6_1_pcie_index_data;
address = nbio_pcie_id->index_offset;
data = nbio_pcie_id->data_offset;
@@ -199,7 +199,10 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
{
- return nbio_v6_1_get_memsize(adev);
+ if (adev->flags & AMD_IS_APU)
+ return nbio_v7_0_get_memsize(adev);
+ else
+ return nbio_v6_1_get_memsize(adev);
}
static const u32 vega10_golden_init[] =
@@ -376,7 +379,10 @@ static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
/* wait for asic to come out of reset */
for (i = 0; i < adev->usec_timeout; i++) {
- if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
+ u32 memsize = (adev->flags & AMD_IS_APU) ?
+ nbio_v7_0_get_memsize(adev) :
+ nbio_v6_1_get_memsize(adev);
+ if (memsize != 0xffffffff)
break;
udelay(1);
}
@@ -450,8 +456,12 @@ static void soc15_program_aspm(struct amdgpu_device *adev)
static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
bool enable)
{
- nbio_v6_1_enable_doorbell_aperture(adev, enable);
- nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
+ if (adev->flags & AMD_IS_APU) {
+ nbio_v7_0_enable_doorbell_aperture(adev, enable);
+ } else {
+ nbio_v6_1_enable_doorbell_aperture(adev, enable);
+ nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
+ }
}
static const struct amdgpu_ip_block_version vega10_common_ip_block =
@@ -518,7 +528,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
{
- return nbio_v6_1_get_rev_id(adev);
+ if (adev->flags & AMD_IS_APU)
+ return nbio_v7_0_get_rev_id(adev);
+ else
+ return nbio_v6_1_get_rev_id(adev);
}
@@ -569,6 +582,9 @@ static int soc15_common_early_init(void *handle)
case CHIP_VEGA10:
nbio_v6_1_init(adev);
break;
+ case CHIP_RAVEN:
+ nbio_v7_0_init(adev);
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index 378a46d..acb3cdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -25,6 +25,7 @@
#define __SOC15_H__
#include "nbio_v6_1.h"
+#include "nbio_v7_0.h"
extern const struct amd_ip_funcs soc15_common_ip_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 071f56e..67610f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -97,7 +97,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
/* disable irqs */
vega10_ih_disable_interrupts(adev);
- nbio_v6_1_ih_control(adev);
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_ih_control(adev);
+ else
+ nbio_v6_1_ih_control(adev);
ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
@@ -148,7 +151,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
ENABLE, 0);
}
WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr);
- nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
+ if (adev->flags & AMD_IS_APU)
+ nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
+ else
+ nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index);
tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL));
tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 061/117] drm/amdgpu: add nbio MGCG for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (51 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 060/117] drm/amdgpu: apply nbio7 for Raven (v3) Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 062/117] drm/amdgpu: add psp v10 function callback " Alex Deucher
` (56 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add medium grained nbio clockgating implementation.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 853b0e5..959ac05 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -866,7 +866,7 @@ static int soc15_common_set_clockgating_state(void *handle,
state == AMD_CG_STATE_GATE ? true : false);
break;
case CHIP_RAVEN:
- nbio_v6_1_update_medium_grain_clock_gating(adev,
+ nbio_v7_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
nbio_v6_1_update_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 062/117] drm/amdgpu: add psp v10 function callback for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (52 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 061/117] drm/amdgpu: add nbio MGCG for raven Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 063/117] drm/amdgpu: add psp v10 ip block Alex Deucher
` (55 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
PSP is the security processor. These are the support
functions.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +++++
3 files changed, 352 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index b8a94d0..2c80df0 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -60,7 +60,8 @@ amdgpu-y += \
# add PSP block
amdgpu-y += \
amdgpu_psp.o \
- psp_v3_1.o
+ psp_v3_1.o \
+ psp_v10_0.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
new file mode 100644
index 0000000..8eb21fd
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+
+#include <linux/firmware.h>
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+#include "psp_v10_0.h"
+
+#include "vega10/soc15ip.h"
+#include "raven1/MP/mp_10_0_offset.h"
+#include "raven1/GC/gc_9_1_offset.h"
+#include "raven1/SDMA0/sdma0_4_1_offset.h"
+
+static int
+psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
+{
+ switch(ucode->ucode_id) {
+ case AMDGPU_UCODE_ID_SDMA0:
+ *type = GFX_FW_TYPE_SDMA0;
+ break;
+ case AMDGPU_UCODE_ID_SDMA1:
+ *type = GFX_FW_TYPE_SDMA1;
+ break;
+ case AMDGPU_UCODE_ID_CP_CE:
+ *type = GFX_FW_TYPE_CP_CE;
+ break;
+ case AMDGPU_UCODE_ID_CP_PFP:
+ *type = GFX_FW_TYPE_CP_PFP;
+ break;
+ case AMDGPU_UCODE_ID_CP_ME:
+ *type = GFX_FW_TYPE_CP_ME;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC1:
+ *type = GFX_FW_TYPE_CP_MEC;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC1_JT:
+ *type = GFX_FW_TYPE_CP_MEC_ME1;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC2:
+ *type = GFX_FW_TYPE_CP_MEC;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC2_JT:
+ *type = GFX_FW_TYPE_CP_MEC_ME2;
+ break;
+ case AMDGPU_UCODE_ID_RLC_G:
+ *type = GFX_FW_TYPE_RLC_G;
+ break;
+ case AMDGPU_UCODE_ID_SMC:
+ *type = GFX_FW_TYPE_SMU;
+ break;
+ case AMDGPU_UCODE_ID_UVD:
+ *type = GFX_FW_TYPE_UVD;
+ break;
+ case AMDGPU_UCODE_ID_VCE:
+ *type = GFX_FW_TYPE_VCE;
+ break;
+ case AMDGPU_UCODE_ID_MAXIMUM:
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
+{
+ int ret;
+ uint64_t fw_mem_mc_addr = ucode->mc_addr;
+ struct common_firmware_header *header;
+
+ memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+ header = (struct common_firmware_header *)ucode->fw;
+
+ cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+ cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
+ cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
+ cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
+
+ ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+ if (ret)
+ DRM_ERROR("Unknown firmware type\n");
+
+ return ret;
+}
+
+int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ unsigned int psp_ring_reg = 0;
+ struct psp_ring *ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ ring = &psp->km_ring;
+
+ ring->ring_type = ring_type;
+
+ /* allocate 4k Page of Local Frame Buffer memory for ring */
+ ring->ring_size = 0x1000;
+ ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->firmware.rbuf,
+ &ring->ring_mem_mc_addr,
+ (void **)&ring->ring_mem);
+ if (ret) {
+ ring->ring_size = 0;
+ return ret;
+ }
+
+ /* Write low address of the ring to C2PMSG_69 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg);
+ /* Write high address of the ring to C2PMSG_70 */
+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+ WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg);
+ /* Write size of ring to C2PMSG_71 */
+ psp_ring_reg = ring->ring_size;
+ WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg);
+ /* Write the ring initialization command to C2PMSG_64 */
+ psp_ring_reg = ring_type;
+ psp_ring_reg = psp_ring_reg << 16;
+ WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ psp_ring_reg = 0;
+ while ((psp_ring_reg & 0x80000000) == 0) {
+ psp_ring_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64));
+ }
+
+ return 0;
+}
+
+int psp_v10_0_cmd_submit(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ int index)
+{
+ unsigned int psp_write_ptr_reg = 0;
+ struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+ struct psp_ring *ring = &psp->km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ /* KM (GPCOM) prepare write pointer */
+ psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67));
+
+ /* Update KM RB frame pointer to new frame */
+ if ((psp_write_ptr_reg % ring->ring_size) == 0)
+ write_frame = ring->ring_mem;
+ else
+ write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
+
+ /* Update KM RB frame */
+ write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
+ write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
+ write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
+ write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
+ write_frame->fence_value = index;
+
+ /* Update the write Pointer in DWORDs */
+ psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
+ psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
+ WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg);
+
+ return 0;
+}
+
+static int
+psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+ unsigned int *sram_data_reg_offset,
+ enum AMDGPU_UCODE_ID ucode_id)
+{
+ int ret = 0;
+
+ switch(ucode_id) {
+/* TODO: needs to confirm */
+#if 0
+ case AMDGPU_UCODE_ID_SMC:
+ *sram_offset = 0;
+ *sram_addr_reg_offset = 0;
+ *sram_data_reg_offset = 0;
+ break;
+#endif
+
+ case AMDGPU_UCODE_ID_CP_CE:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_PFP:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_ME:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_MEC1:
+ *sram_offset = 0x10000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_MEC2:
+ *sram_offset = 0x10000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_RLC_G:
+ *sram_offset = 0x2000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_SDMA0:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
+ break;
+
+/* TODO: needs to confirm */
+#if 0
+ case AMDGPU_UCODE_ID_SDMA1:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+
+ case AMDGPU_UCODE_ID_UVD:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+
+ case AMDGPU_UCODE_ID_VCE:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+#endif
+
+ case AMDGPU_UCODE_ID_MAXIMUM:
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+bool psp_v10_0_compare_sram_data(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type)
+{
+ int err = 0;
+ unsigned int fw_sram_reg_val = 0;
+ unsigned int fw_sram_addr_reg_offset = 0;
+ unsigned int fw_sram_data_reg_offset = 0;
+ unsigned int ucode_size;
+ uint32_t *ucode_mem = NULL;
+ struct amdgpu_device *adev = psp->adev;
+
+ err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
+ &fw_sram_data_reg_offset, ucode_type);
+ if (err)
+ return false;
+
+ WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
+
+ ucode_size = ucode->ucode_size;
+ ucode_mem = (uint32_t *)ucode->kaddr;
+ while (!ucode_size) {
+ fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
+
+ if (*ucode_mem != fw_sram_reg_val)
+ return false;
+
+ ucode_mem++;
+ /* 4 bytes */
+ ucode_size -= 4;
+ }
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
new file mode 100644
index 0000000..2022b7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+#ifndef __PSP_V10_0_H__
+#define __PSP_V10_0_H__
+
+#include "amdgpu_psp.h"
+
+extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd);
+extern int psp_v10_0_ring_init(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+extern int psp_v10_0_cmd_submit(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ int index);
+extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type);
+#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 063/117] drm/amdgpu: add psp v10 ip block
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (53 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 062/117] drm/amdgpu: add psp v10 function callback " Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 064/117] drm/amdgpu: register the psp v10 function pointers at psp sw_init Alex Deucher
` (54 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add the ip block version structure for psp 10.0.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 5041073..dfdf4fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -549,3 +549,12 @@ const struct amdgpu_ip_block_version psp_v3_1_ip_block =
.rev = 0,
.funcs = &psp_ip_funcs,
};
+
+const struct amdgpu_ip_block_version psp_v10_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_PSP,
+ .major = 10,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &psp_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 0301e4e..1a1c8b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -138,4 +138,6 @@ extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
uint32_t field_val, uint32_t mask, bool check_changed);
+extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
+
#endif
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 064/117] drm/amdgpu: register the psp v10 function pointers at psp sw_init
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (54 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 063/117] drm/amdgpu: add psp v10 ip block Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 065/117] drm/amdgpu/soc15: add psp ip block Alex Deucher
` (53 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add the psp 10.0 callbacks for PSP.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index dfdf4fd..4285f37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -30,6 +30,7 @@
#include "amdgpu_ucode.h"
#include "soc15_common.h"
#include "psp_v3_1.h"
+#include "psp_v10_0.h"
static void psp_set_funcs(struct amdgpu_device *adev);
@@ -61,6 +62,12 @@ static int psp_sw_init(void *handle)
psp->compare_sram_data = psp_v3_1_compare_sram_data;
psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
break;
+ case CHIP_RAVEN:
+ psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
+ psp->ring_init = psp_v10_0_ring_init;
+ psp->cmd_submit = psp_v10_0_cmd_submit;
+ psp->compare_sram_data = psp_v10_0_compare_sram_data;
+ break;
default:
return -EINVAL;
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 065/117] drm/amdgpu/soc15: add psp ip block
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (55 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 064/117] drm/amdgpu: register the psp v10 function pointers at psp sw_init Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 066/117] drm/amdgpu: add initial vcn support and decode tests Alex Deucher
` (52 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 959ac05..98f372b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -510,6 +510,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
+ amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 066/117] drm/amdgpu: add initial vcn support and decode tests
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (56 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 065/117] drm/amdgpu/soc15: add psp ip block Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 067/117] drm/amdgpu: add encode tests for vcn Alex Deucher
` (51 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
VCN is the new media block on Raven. Add core support
and the ring and ib tests for decode.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 40 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 425 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 35 +++
4 files changed, 500 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 2c80df0..f3c8245 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -99,6 +99,10 @@ amdgpu-y += \
vce_v3_0.o \
vce_v4_0.o
+# add VCN block
+amdgpu-y += \
+ amdgpu_vcn.o
+
# add amdkfd interfaces
amdgpu-y += \
amdgpu_amdkfd.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1fbb698..e884f5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1181,6 +1181,31 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
void amdgpu_get_pcie_info(struct amdgpu_device *adev);
/*
+ * VCN
+ */
+#define AMDGPU_VCN_STACK_SIZE (200*1024)
+#define AMDGPU_VCN_HEAP_SIZE (256*1024)
+#define AMDGPU_VCN_SESSION_SIZE (50*1024)
+#define AMDGPU_VCN_FIRMWARE_OFFSET 256
+#define AMDGPU_VCN_MAX_ENC_RINGS 3
+
+struct amdgpu_vcn {
+ struct amdgpu_bo *vcpu_bo;
+ void *cpu_addr;
+ uint64_t gpu_addr;
+ unsigned fw_version;
+ void *saved_bo;
+ struct delayed_work idle_work;
+ const struct firmware *fw; /* VCN firmware */
+ struct amdgpu_ring ring_dec;
+ struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+ struct amdgpu_irq_src irq;
+ struct amd_sched_entity entity_dec;
+ struct amd_sched_entity entity_enc;
+ uint32_t srbm_soft_reset;
+};
+
+/*
* SDMA
*/
struct amdgpu_sdma_instance {
@@ -1576,11 +1601,18 @@ struct amdgpu_device {
/* sdma */
struct amdgpu_sdma sdma;
- /* uvd */
- struct amdgpu_uvd uvd;
+ union {
+ struct {
+ /* uvd */
+ struct amdgpu_uvd uvd;
+
+ /* vce */
+ struct amdgpu_vce vce;
+ };
- /* vce */
- struct amdgpu_vce vce;
+ /* vcn */
+ struct amdgpu_vcn vcn;
+ };
/* firmwares */
struct amdgpu_firmware firmware;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
new file mode 100644
index 0000000..97b09b6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -0,0 +1,425 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+
+#include <linux/firmware.h>
+#include <linux/module.h>
+#include <drm/drmP.h>
+#include <drm/drm.h>
+
+#include "amdgpu.h"
+#include "amdgpu_pm.h"
+#include "amdgpu_vcn.h"
+#include "soc15d.h"
+#include "soc15_common.h"
+
+#include "vega10/soc15ip.h"
+#include "raven1/VCN/vcn_1_0_offset.h"
+
+/* 1 second timeout */
+#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
+
+/* Firmware Names */
+#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
+
+MODULE_FIRMWARE(FIRMWARE_RAVEN);
+
+static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
+
+int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+{
+ struct amdgpu_ring *ring;
+ struct amd_sched_rq *rq;
+ unsigned long bo_size;
+ const char *fw_name;
+ const struct common_firmware_header *hdr;
+ unsigned version_major, version_minor, family_id;
+ int r;
+
+ INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ fw_name = FIRMWARE_RAVEN;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
+ if (r) {
+ dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
+ fw_name);
+ return r;
+ }
+
+ r = amdgpu_ucode_validate(adev->vcn.fw);
+ if (r) {
+ dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
+ fw_name);
+ release_firmware(adev->vcn.fw);
+ adev->vcn.fw = NULL;
+ return r;
+ }
+
+ hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+ family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
+ version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
+ version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
+ DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
+ version_major, version_minor, family_id);
+
+
+ bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
+ + AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
+ + AMDGPU_VCN_SESSION_SIZE * 40;
+ r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
+ &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+ return r;
+ }
+
+ ring = &adev->vcn.ring_dec;
+ rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+ r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
+ rq, amdgpu_sched_jobs);
+ if (r != 0) {
+ DRM_ERROR("Failed setting up VCN dec run queue.\n");
+ return r;
+ }
+
+ return 0;
+}
+
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+{
+ kfree(adev->vcn.saved_bo);
+
+ amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
+
+ amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
+ &adev->vcn.gpu_addr,
+ (void **)&adev->vcn.cpu_addr);
+
+ amdgpu_ring_fini(&adev->vcn.ring_dec);
+
+ release_firmware(adev->vcn.fw);
+
+ return 0;
+}
+
+int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+{
+ unsigned size;
+ void *ptr;
+
+ if (adev->vcn.vcpu_bo == NULL)
+ return 0;
+
+ cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+ size = amdgpu_bo_size(adev->vcn.vcpu_bo);
+ ptr = adev->vcn.cpu_addr;
+
+ adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL);
+ if (!adev->vcn.saved_bo)
+ return -ENOMEM;
+
+ memcpy_fromio(adev->vcn.saved_bo, ptr, size);
+
+ return 0;
+}
+
+int amdgpu_vcn_resume(struct amdgpu_device *adev)
+{
+ unsigned size;
+ void *ptr;
+
+ if (adev->vcn.vcpu_bo == NULL)
+ return -EINVAL;
+
+ size = amdgpu_bo_size(adev->vcn.vcpu_bo);
+ ptr = adev->vcn.cpu_addr;
+
+ if (adev->vcn.saved_bo != NULL) {
+ memcpy_toio(ptr, adev->vcn.saved_bo, size);
+ kfree(adev->vcn.saved_bo);
+ adev->vcn.saved_bo = NULL;
+ } else {
+ const struct common_firmware_header *hdr;
+ unsigned offset;
+
+ hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+ offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+ memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
+ le32_to_cpu(hdr->ucode_size_bytes));
+ size -= le32_to_cpu(hdr->ucode_size_bytes);
+ ptr += le32_to_cpu(hdr->ucode_size_bytes);
+ memset_io(ptr, 0, size);
+ }
+
+ return 0;
+}
+
+static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
+ bool direct, struct dma_fence **fence)
+{
+ struct ttm_validate_buffer tv;
+ struct ww_acquire_ctx ticket;
+ struct list_head head;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ struct amdgpu_device *adev = ring->adev;
+ uint64_t addr;
+ int i, r;
+
+ memset(&tv, 0, sizeof(tv));
+ tv.bo = &bo->tbo;
+
+ INIT_LIST_HEAD(&head);
+ list_add(&tv.head, &head);
+
+ r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
+ if (r)
+ return r;
+
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+ if (r)
+ goto err;
+
+ r = amdgpu_job_alloc_with_ib(adev, 64, &job);
+ if (r)
+ goto err;
+
+ ib = &job->ibs[0];
+ addr = amdgpu_bo_gpu_offset(bo);
+ ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
+ ib->ptr[1] = addr;
+ ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
+ ib->ptr[3] = addr >> 32;
+ ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
+ ib->ptr[5] = 0;
+ for (i = 6; i < 16; i += 2) {
+ ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
+ ib->ptr[i+1] = 0;
+ }
+ ib->length_dw = 16;
+
+ if (direct) {
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err_free;
+
+ amdgpu_job_free(job);
+ } else {
+ r = amdgpu_job_submit(job, ring, &adev->vcn.entity_dec,
+ AMDGPU_FENCE_OWNER_UNDEFINED, &f);
+ if (r)
+ goto err_free;
+ }
+
+ ttm_eu_fence_buffer_objects(&ticket, &head, f);
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ amdgpu_bo_unref(&bo);
+ dma_fence_put(f);
+
+ return 0;
+
+err_free:
+ amdgpu_job_free(job);
+
+err:
+ ttm_eu_backoff_reservation(&ticket, &head);
+ return r;
+}
+
+static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ struct dma_fence **fence)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_bo *bo;
+ uint32_t *msg;
+ int r, i;
+
+ r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
+ NULL, NULL, &bo);
+ if (r)
+ return r;
+
+ r = amdgpu_bo_reserve(bo, false);
+ if (r) {
+ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+ r = amdgpu_bo_kmap(bo, (void **)&msg);
+ if (r) {
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+ /* stitch together an vcn create msg */
+ msg[0] = cpu_to_le32(0x00000de4);
+ msg[1] = cpu_to_le32(0x00000000);
+ msg[2] = cpu_to_le32(handle);
+ msg[3] = cpu_to_le32(0x00000000);
+ msg[4] = cpu_to_le32(0x00000000);
+ msg[5] = cpu_to_le32(0x00000000);
+ msg[6] = cpu_to_le32(0x00000000);
+ msg[7] = cpu_to_le32(0x00000780);
+ msg[8] = cpu_to_le32(0x00000440);
+ msg[9] = cpu_to_le32(0x00000000);
+ msg[10] = cpu_to_le32(0x01b37000);
+ for (i = 11; i < 1024; ++i)
+ msg[i] = cpu_to_le32(0x0);
+
+ amdgpu_bo_kunmap(bo);
+ amdgpu_bo_unreserve(bo);
+
+ return amdgpu_vcn_dec_send_msg(ring, bo, true, fence);
+}
+
+static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+ bool direct, struct dma_fence **fence)
+{
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_bo *bo;
+ uint32_t *msg;
+ int r, i;
+
+ r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
+ NULL, NULL, &bo);
+ if (r)
+ return r;
+
+ r = amdgpu_bo_reserve(bo, false);
+ if (r) {
+ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+ r = amdgpu_bo_kmap(bo, (void **)&msg);
+ if (r) {
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+ return r;
+ }
+
+ /* stitch together an vcn destroy msg */
+ msg[0] = cpu_to_le32(0x00000de4);
+ msg[1] = cpu_to_le32(0x00000002);
+ msg[2] = cpu_to_le32(handle);
+ msg[3] = cpu_to_le32(0x00000000);
+ for (i = 4; i < 1024; ++i)
+ msg[i] = cpu_to_le32(0x0);
+
+ amdgpu_bo_kunmap(bo);
+ amdgpu_bo_unreserve(bo);
+
+ return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence);
+}
+
+static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device, vcn.idle_work.work);
+ unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
+
+ if (fences == 0) {
+ if (adev->pm.dpm_enabled) {
+ amdgpu_dpm_enable_uvd(adev, false);
+ } else {
+ amdgpu_asic_set_uvd_clocks(adev, 0, 0);
+ }
+ } else {
+ schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ }
+}
+
+void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+ if (set_clocks) {
+ if (adev->pm.dpm_enabled) {
+ amdgpu_dpm_enable_uvd(adev, true);
+ } else {
+ amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
+ }
+ }
+}
+
+void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
+{
+ schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+}
+
+int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct dma_fence *fence;
+ long r;
+
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+ goto error;
+ }
+
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, true, &fence);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+ goto error;
+ }
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out.\n");
+ r = -ETIMEDOUT;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ } else {
+ DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+ r = 0;
+ }
+
+ dma_fence_put(fence);
+
+error:
+ return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
new file mode 100644
index 0000000..a32182c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __AMDGPU_VCN_H__
+#define __AMDGPU_VCN_H__
+
+int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
+int amdgpu_vcn_suspend(struct amdgpu_device *adev);
+int amdgpu_vcn_resume(struct amdgpu_device *adev);
+void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
+void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
+int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+
+#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 067/117] drm/amdgpu: add encode tests for vcn
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (57 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 066/117] drm/amdgpu: add initial vcn support and decode tests Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:46 ` [PATCH 068/117] drm/amdgpu: add vcn ip block functions (v2) Alex Deucher
` (50 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Add encode ring and ib tests.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 203 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 +
2 files changed, 206 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 97b09b6..9bb59cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -112,6 +112,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
+ ring = &adev->vcn.ring_enc[0];
+ rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
+ r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc,
+ rq, amdgpu_sched_jobs);
+ if (r != 0) {
+ DRM_ERROR("Failed setting up VCN enc run queue.\n");
+ return r;
+ }
+
return 0;
}
@@ -121,6 +130,8 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
+ amd_sched_entity_fini(&adev->vcn.ring_enc[0].sched, &adev->vcn.entity_enc);
+
amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
&adev->vcn.gpu_addr,
(void **)&adev->vcn.cpu_addr);
@@ -423,3 +434,195 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
error:
return r;
}
+
+static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
+ struct dma_fence **fence)
+{
+ const unsigned ib_size_dw = 1024;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ uint64_t dummy;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+ if (r)
+ return r;
+
+ ib = &job->ibs[0];
+
+ dummy = ib->gpu_addr + 1024;
+
+ /* stitch together an VCN enc create msg */
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
+ ib->ptr[ib->length_dw++] = handle;
+
+ ib->ptr[ib->length_dw++] = 0x00000040; /* len */
+ ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000042;
+ ib->ptr[ib->length_dw++] = 0x0000000a;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = 0x00000080;
+ ib->ptr[ib->length_dw++] = 0x00000060;
+ ib->ptr[ib->length_dw++] = 0x00000100;
+ ib->ptr[ib->length_dw++] = 0x00000100;
+ ib->ptr[ib->length_dw++] = 0x0000000c;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+
+ ib->ptr[ib->length_dw++] = 0x00000014; /* len */
+ ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
+ ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+ ib->ptr[ib->length_dw++] = dummy;
+ ib->ptr[ib->length_dw++] = 0x00000001;
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err;
+
+ amdgpu_job_free(job);
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+ return 0;
+
+err:
+ amdgpu_job_free(job);
+ return r;
+}
+
+static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
+ bool direct, struct dma_fence **fence)
+{
+ const unsigned ib_size_dw = 1024;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
+ struct dma_fence *f = NULL;
+ int i, r;
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
+ if (r)
+ return r;
+
+ ib = &job->ibs[0];
+
+ /* stitch together an VCN enc destroy msg */
+ ib->length_dw = 0;
+ ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
+ ib->ptr[ib->length_dw++] = handle;
+
+ ib->ptr[ib->length_dw++] = 0x00000020; /* len */
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+ ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
+ ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
+ ib->ptr[ib->length_dw++] = 0x00000000;
+
+ ib->ptr[ib->length_dw++] = 0x00000008; /* len */
+ ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
+
+ for (i = ib->length_dw; i < ib_size_dw; ++i)
+ ib->ptr[i] = 0x0;
+
+ if (direct) {
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err;
+
+ amdgpu_job_free(job);
+ } else {
+ r = amdgpu_job_submit(job, ring, &ring->adev->vcn.entity_enc,
+ AMDGPU_FENCE_OWNER_UNDEFINED, &f);
+ if (r)
+ goto err;
+ }
+
+ if (fence)
+ *fence = dma_fence_get(f);
+ dma_fence_put(f);
+ return 0;
+
+err:
+ amdgpu_job_free(job);
+ return r;
+}
+
+int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr = amdgpu_ring_get_rptr(ring);
+ unsigned i;
+ int r;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r) {
+ DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring, VCE_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed\n",
+ ring->idx);
+ r = -ETIMEDOUT;
+ }
+
+ return r;
+}
+
+int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
+{
+ struct dma_fence *fence = NULL;
+ long r;
+
+ r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+ goto error;
+ }
+
+ r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, true, &fence);
+ if (r) {
+ DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+ goto error;
+ }
+
+ r = dma_fence_wait_timeout(fence, false, timeout);
+ if (r == 0) {
+ DRM_ERROR("amdgpu: IB test timed out.\n");
+ r = -ETIMEDOUT;
+ } else if (r < 0) {
+ DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+ } else {
+ DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
+ r = 0;
+ }
+error:
+ dma_fence_put(fence);
+ return r;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a32182c..ec4d7ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -32,4 +32,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
+int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
+
#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 068/117] drm/amdgpu: add vcn ip block functions (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (58 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 067/117] drm/amdgpu: add encode tests for vcn Alex Deucher
@ 2017-05-10 18:46 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 069/117] drm/amdgpu: add vcn decode ring support Alex Deucher
` (49 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Fill in the core VCN 1.0 setup functionality.
v2: squash in fixup (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 417 +++++++++++++++++++++++++++++++++
3 files changed, 421 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index f3c8245..766054a 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -101,7 +101,8 @@ amdgpu-y += \
# add VCN block
amdgpu-y += \
- amdgpu_vcn.o
+ amdgpu_vcn.o \
+ vcn_v1_0.o
# add amdkfd interfaces
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index a3da1a1..3de8e74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -62,8 +62,9 @@ enum amdgpu_ih_clientid
AMDGPU_IH_CLIENTID_MP0 = 0x1e,
AMDGPU_IH_CLIENTID_MP1 = 0x1f,
- AMDGPU_IH_CLIENTID_MAX
+ AMDGPU_IH_CLIENTID_MAX,
+ AMDGPU_IH_CLIENTID_VCN = AMDGPU_IH_CLIENTID_UVD
};
#define AMDGPU_IH_CLIENTID_LEGACY 0
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
new file mode 100644
index 0000000..744268f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/firmware.h>
+#include <drm/drmP.h>
+#include "amdgpu.h"
+#include "amdgpu_vcn.h"
+#include "soc15d.h"
+#include "soc15_common.h"
+
+#include "vega10/soc15ip.h"
+#include "raven1/VCN/vcn_1_0_offset.h"
+#include "raven1/VCN/vcn_1_0_sh_mask.h"
+#include "vega10/HDP/hdp_4_0_offset.h"
+#include "raven1/MMHUB/mmhub_9_1_offset.h"
+#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
+
+static int vcn_v1_0_start(struct amdgpu_device *adev);
+static int vcn_v1_0_stop(struct amdgpu_device *adev);
+
+/**
+ * vcn_v1_0_early_init - set function pointers
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Set ring and irq function pointers
+ */
+static int vcn_v1_0_early_init(void *handle)
+{
+ return 0;
+}
+
+/**
+ * vcn_v1_0_sw_init - sw init for VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Load firmware and sw initialization
+ */
+static int vcn_v1_0_sw_init(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* VCN TRAP */
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_sw_init(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_resume(adev);
+ if (r)
+ return r;
+
+ return r;
+}
+
+/**
+ * vcn_v1_0_sw_fini - sw fini for VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * VCN suspend and free up sw allocation
+ */
+static int vcn_v1_0_sw_fini(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_vcn_suspend(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_sw_fini(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v1_0_hw_init - start and test VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Initialize the hardware, boot up the VCPU and do some testing
+ */
+static int vcn_v1_0_hw_init(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring = &adev->vcn.ring_dec;
+ int r;
+
+ r = vcn_v1_0_start(adev);
+ if (r)
+ goto done;
+
+ ring->ready = true;
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->ready = false;
+ goto done;
+ }
+
+done:
+ if (!r)
+ DRM_INFO("VCN decode initialized successfully.\n");
+
+ return r;
+}
+
+/**
+ * vcn_v1_0_hw_fini - stop the hardware block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Stop the VCN block, mark ring as not ready any more
+ */
+static int vcn_v1_0_hw_fini(void *handle)
+{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_ring *ring = &adev->vcn.ring_dec;
+ int r;
+
+ r = vcn_v1_0_stop(adev);
+ if (r)
+ return r;
+
+ ring->ready = false;
+
+ return 0;
+}
+
+/**
+ * vcn_v1_0_suspend - suspend VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * HW fini and suspend VCN block
+ */
+static int vcn_v1_0_suspend(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = vcn_v1_0_hw_fini(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_vcn_suspend(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v1_0_resume - resume VCN block
+ *
+ * @handle: amdgpu_device pointer
+ *
+ * Resume firmware and hw init VCN block
+ */
+static int vcn_v1_0_resume(void *handle)
+{
+ int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ r = amdgpu_vcn_resume(adev);
+ if (r)
+ return r;
+
+ r = vcn_v1_0_hw_init(adev);
+
+ return r;
+}
+
+/**
+ * vcn_v1_0_mc_resume - memory controller programming
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Let the VCN memory controller know it's offsets
+ */
+static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
+{
+ uint64_t offset;
+ uint32_t size;
+
+ /* programm memory controller bits 0-27 */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.gpu_addr));
+
+ /* Current FW has no signed header, but will be added later on */
+ /* offset = AMDGPU_VCN_FIRMWARE_OFFSET; */
+ offset = 0;
+ size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), offset >> 3);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
+
+ offset += size;
+ size = AMDGPU_VCN_HEAP_SIZE;
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), offset >> 3);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), size);
+
+ offset += size;
+ size = AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), offset >> 3);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), size);
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
+ adev->gfx.config.gb_addr_config);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG),
+ adev->gfx.config.gb_addr_config);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG),
+ adev->gfx.config.gb_addr_config);
+}
+
+/**
+ * vcn_v1_0_start - start VCN block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Setup and start the VCN block
+ */
+static int vcn_v1_0_start(struct amdgpu_device *adev)
+{
+ uint32_t lmi_swap_cntl;
+ int i, j, r;
+
+ /* disable byte swapping */
+ lmi_swap_cntl = 0;
+
+ vcn_v1_0_mc_resume(adev);
+
+ /* disable clock gating */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
+ ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
+
+ /* disable interupt */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* stall UMC and register bus before resetting VCPU */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
+ UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ mdelay(1);
+
+ /* put LMI, VCPU, RBC etc... into reset */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
+ UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+ mdelay(5);
+
+ /* initialize VCN memory controller */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
+ (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__REQ_MODE_MASK |
+ 0x00100000L);
+
+#ifdef __BIG_ENDIAN
+ /* swap (8 in 32) RB and IB */
+ lmi_swap_cntl = 0xa;
+#endif
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), lmi_swap_cntl);
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88);
+
+ /* take all subblocks out of reset, except VCPU */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(5);
+
+ /* enable VCPU clock */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* enable UMC */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ /* boot up the VCPU */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
+ mdelay(10);
+
+ for (i = 0; i < 10; ++i) {
+ uint32_t status;
+
+ for (j = 0; j < 100; ++j) {
+ status = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS));
+ if (status & 2)
+ break;
+ mdelay(10);
+ }
+ r = 0;
+ if (status & 2)
+ break;
+
+ DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(10);
+ r = -1;
+ }
+
+ if (r) {
+ DRM_ERROR("VCN decode not responding, giving up!!!\n");
+ return r;
+ }
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
+ (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
+ ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
+
+ /* clear the bit 4 of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+
+ return 0;
+}
+
+/**
+ * vcn_v1_0_stop - stop VCN block
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * stop the VCN block
+ */
+static int vcn_v1_0_stop(struct amdgpu_device *adev)
+{
+ /* Stall UMC and register bus before resetting VCPU */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
+ UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ mdelay(1);
+
+ /* put VCPU into reset */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+ mdelay(5);
+
+ /* disable VCPU clock */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0x0);
+
+ /* Unstall UMC and register bus */
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ return 0;
+}
+
+static int vcn_v1_0_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
+{
+ /* needed for driver unload*/
+ return 0;
+}
+
+static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
+ .name = "vcn_v1_0",
+ .early_init = vcn_v1_0_early_init,
+ .late_init = NULL,
+ .sw_init = vcn_v1_0_sw_init,
+ .sw_fini = vcn_v1_0_sw_fini,
+ .hw_init = vcn_v1_0_hw_init,
+ .hw_fini = vcn_v1_0_hw_fini,
+ .suspend = vcn_v1_0_suspend,
+ .resume = vcn_v1_0_resume,
+ .is_idle = NULL /* vcn_v1_0_is_idle */,
+ .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */,
+ .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
+ .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
+ .soft_reset = NULL /* vcn_v1_0_soft_reset */,
+ .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
+ .set_clockgating_state = vcn_v1_0_set_clockgating_state,
+ .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */,
+};
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 069/117] drm/amdgpu: add vcn decode ring support
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (59 preceding siblings ...)
2017-05-10 18:46 ` [PATCH 068/117] drm/amdgpu: add vcn ip block functions (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 070/117] drm/amdgpu: add vcn decode ring type and functions Alex Deucher
` (48 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Add the decode ring init.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 43 +++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 744268f..47bdc83 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -59,6 +59,7 @@ static int vcn_v1_0_early_init(void *handle)
*/
static int vcn_v1_0_sw_init(void *handle)
{
+ struct amdgpu_ring *ring;
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -75,6 +76,10 @@ static int vcn_v1_0_sw_init(void *handle)
if (r)
return r;
+ ring = &adev->vcn.ring_dec;
+ sprintf(ring->name, "vcn_dec");
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+
return r;
}
@@ -246,6 +251,8 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
*/
static int vcn_v1_0_start(struct amdgpu_device *adev)
{
+ struct amdgpu_ring *ring = &adev->vcn.ring_dec;
+ uint32_t rb_bufsz, tmp;
uint32_t lmi_swap_cntl;
int i, j, r;
@@ -356,6 +363,39 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
+
+ /* set the write pointer delay */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0);
+
+ /* set the wb address */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR),
+ (upper_32_bits(ring->gpu_addr) >> 2));
+
+ /* programm the RB_BASE for ring buffer */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
+ lower_32_bits(ring->gpu_addr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
+ upper_32_bits(ring->gpu_addr));
+
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR), 0);
+
+ ring->wptr = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR),
+ lower_32_bits(ring->wptr));
+
+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
+ ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+
return 0;
}
@@ -368,6 +408,9 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
*/
static int vcn_v1_0_stop(struct amdgpu_device *adev)
{
+ /* force RBC into idle state */
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0x11010101);
+
/* Stall UMC and register bus before resetting VCPU */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 070/117] drm/amdgpu: add vcn decode ring type and functions
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (60 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 069/117] drm/amdgpu: add vcn decode ring support Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 071/117] drm/amdgpu: add vcn irq functions Alex Deucher
` (47 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Add the ring function callbacks for the decode ring.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 266 +++++++++++++++++++++++++++++++
2 files changed, 268 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 2b7b3c56..b4d4ed4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -47,7 +47,8 @@ enum amdgpu_ring_type {
AMDGPU_RING_TYPE_UVD,
AMDGPU_RING_TYPE_VCE,
AMDGPU_RING_TYPE_KIQ,
- AMDGPU_RING_TYPE_UVD_ENC
+ AMDGPU_RING_TYPE_UVD_ENC,
+ AMDGPU_RING_TYPE_VCN_DEC
};
struct amdgpu_device;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 47bdc83..48aedd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -37,6 +37,7 @@
static int vcn_v1_0_start(struct amdgpu_device *adev);
static int vcn_v1_0_stop(struct amdgpu_device *adev);
+static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
/**
* vcn_v1_0_early_init - set function pointers
@@ -47,6 +48,10 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
*/
static int vcn_v1_0_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ vcn_v1_0_set_dec_ring_funcs(adev);
+
return 0;
}
@@ -439,6 +444,236 @@ static int vcn_v1_0_set_clockgating_state(void *handle,
return 0;
}
+/**
+ * vcn_v1_0_dec_ring_get_rptr - get read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware read pointer
+ */
+static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR));
+}
+
+/**
+ * vcn_v1_0_dec_ring_get_wptr - get write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware write pointer
+ */
+static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR));
+}
+
+/**
+ * vcn_v1_0_dec_ring_set_wptr - set write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the write pointer to the hardware
+ */
+static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR), lower_32_bits(ring->wptr));
+}
+
+/**
+ * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write a fence and a trap command to the ring.
+ */
+static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
+ unsigned flags)
+{
+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+ amdgpu_ring_write(ring, seq);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+ amdgpu_ring_write(ring, addr & 0xffffffff);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+ amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, 0);
+
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, 2);
+}
+
+/**
+ * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Emits an hdp invalidate.
+ */
+static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));
+ amdgpu_ring_write(ring, 1);
+}
+
+/**
+ * vcn_v1_0_dec_ring_test_ring - register write test
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Test if we can successfully write to the context register
+ */
+static int vcn_v1_0_dec_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+ amdgpu_ring_write(ring, 0xDEADBEEF);
+ amdgpu_ring_commit(ring);
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
+ ring->idx, tmp);
+ r = -EINVAL;
+ }
+ return r;
+}
+
+/**
+ * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
+ *
+ * @ring: amdgpu_ring pointer
+ * @ib: indirect buffer to execute
+ *
+ * Write ring commands to execute the indirect buffer
+ */
+static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib,
+ unsigned vm_id, bool ctx_switch)
+{
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
+ amdgpu_ring_write(ring, vm_id);
+
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
+ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
+ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
+ amdgpu_ring_write(ring, ib->length_dw);
+}
+
+static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
+ uint32_t data0, uint32_t data1)
+{
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+ amdgpu_ring_write(ring, data0);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+ amdgpu_ring_write(ring, data1);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, 8);
+}
+
+static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
+ uint32_t data0, uint32_t data1, uint32_t mask)
+{
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+ amdgpu_ring_write(ring, data0);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+ amdgpu_ring_write(ring, data1);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
+ amdgpu_ring_write(ring, mask);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, 12);
+}
+
+static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ unsigned vm_id, uint64_t pd_addr)
+{
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ uint32_t data0, data1, mask;
+ unsigned eng = ring->vm_inv_eng;
+
+ pd_addr = pd_addr | 0x1; /* valid bit */
+ /* now only use physical base address of PDE and valid */
+ BUG_ON(pd_addr & 0xFFFF00000000003EULL);
+
+ data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+ data1 = upper_32_bits(pd_addr);
+ vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+
+ data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data1 = lower_32_bits(pd_addr);
+ vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+
+ data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+ data1 = lower_32_bits(pd_addr);
+ mask = 0xffffffff;
+ vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
+
+ /* flush TLB */
+ data0 = (hub->vm_inv_eng0_req + eng) << 2;
+ data1 = req;
+ vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
+
+ /* wait for flush */
+ data0 = (hub->vm_inv_eng0_ack + eng) << 2;
+ data1 = 1 << vm_id;
+ mask = 1 << vm_id;
+ vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
+}
+
static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.name = "vcn_v1_0",
.early_init = vcn_v1_0_early_init,
@@ -458,3 +693,34 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.set_clockgating_state = vcn_v1_0_set_clockgating_state,
.set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */,
};
+
+static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_DEC,
+ .align_mask = 0xf,
+ .nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
+ .support_64bit_ptrs = false,
+ .get_rptr = vcn_v1_0_dec_ring_get_rptr,
+ .get_wptr = vcn_v1_0_dec_ring_get_wptr,
+ .set_wptr = vcn_v1_0_dec_ring_set_wptr,
+ .emit_frame_size =
+ 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
+ 34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
+ 14 + 14, /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
+ .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
+ .emit_ib = vcn_v1_0_dec_ring_emit_ib,
+ .emit_fence = vcn_v1_0_dec_ring_emit_fence,
+ .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
+ .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
+ .test_ring = vcn_v1_0_dec_ring_test_ring,
+ .test_ib = amdgpu_vcn_dec_ring_test_ib,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+};
+
+static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+{
+ adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
+ DRM_INFO("VCN decode is enabled in VM mode\n");
+}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 071/117] drm/amdgpu: add vcn irq functions
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (61 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 070/117] drm/amdgpu: add vcn decode ring type and functions Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 072/117] drm/amdgpu: add vcn ip block and type Alex Deucher
` (46 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 48aedd3..c9a6b1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -38,6 +38,7 @@
static int vcn_v1_0_start(struct amdgpu_device *adev);
static int vcn_v1_0_stop(struct amdgpu_device *adev);
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
/**
* vcn_v1_0_early_init - set function pointers
@@ -51,6 +52,7 @@ static int vcn_v1_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
vcn_v1_0_set_dec_ring_funcs(adev);
+ vcn_v1_0_set_irq_funcs(adev);
return 0;
}
@@ -674,6 +676,25 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
}
+static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ unsigned type,
+ enum amdgpu_interrupt_state state)
+{
+ return 0;
+}
+
+static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ DRM_DEBUG("IH: VCN TRAP\n");
+
+ amdgpu_fence_process(&adev->vcn.ring_dec);
+
+ return 0;
+}
+
static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
.name = "vcn_v1_0",
.early_init = vcn_v1_0_early_init,
@@ -724,3 +745,14 @@ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
DRM_INFO("VCN decode is enabled in VM mode\n");
}
+
+static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
+ .set = vcn_v1_0_set_interrupt_state,
+ .process = vcn_v1_0_process_interrupt,
+};
+
+static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
+{
+ adev->vcn.irq.num_types = 1;
+ adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
+}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 072/117] drm/amdgpu: add vcn ip block and type
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (62 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 071/117] drm/amdgpu: add vcn irq functions Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 073/117] drm/amdgpu: move amdgpu_vcn structure to vcn header Alex Deucher
` (45 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +++++++++++++++++++++++++++++
drivers/gpu/drm/amd/include/amd_shared.h | 3 ++-
3 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index c9a6b1a..7f3c078 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -756,3 +756,12 @@ static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
adev->vcn.irq.num_types = 1;
adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
}
+
+const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
+{
+ .type = AMD_IP_BLOCK_TYPE_VCN,
+ .major = 1,
+ .minor = 0,
+ .rev = 0,
+ .funcs = &vcn_v1_0_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
new file mode 100644
index 0000000..2a497a7
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VCN_V1_0_H__
+#define __VCN_V1_0_H__
+
+extern const struct amdgpu_ip_block_version vcn_v1_0_ip_block;
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index f006ef6..d2680b9 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -77,7 +77,8 @@ enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_VCE,
AMD_IP_BLOCK_TYPE_ACP,
AMD_IP_BLOCK_TYPE_GFXHUB,
- AMD_IP_BLOCK_TYPE_MMHUB
+ AMD_IP_BLOCK_TYPE_MMHUB,
+ AMD_IP_BLOCK_TYPE_VCN
};
enum amd_clockgating_state {
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 073/117] drm/amdgpu: move amdgpu_vcn structure to vcn header
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (63 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 072/117] drm/amdgpu: add vcn ip block and type Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 074/117] drm/amdgpu: re-group the functions in amdgpu_vcn.c Alex Deucher
` (44 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 26 +-------------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e884f5c..1be8aed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -62,6 +62,7 @@
#include "amdgpu_acp.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
+#include "amdgpu_vcn.h"
#include "amdgpu_dm.h"
#include "gpu_scheduler.h"
@@ -1181,31 +1182,6 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
void amdgpu_get_pcie_info(struct amdgpu_device *adev);
/*
- * VCN
- */
-#define AMDGPU_VCN_STACK_SIZE (200*1024)
-#define AMDGPU_VCN_HEAP_SIZE (256*1024)
-#define AMDGPU_VCN_SESSION_SIZE (50*1024)
-#define AMDGPU_VCN_FIRMWARE_OFFSET 256
-#define AMDGPU_VCN_MAX_ENC_RINGS 3
-
-struct amdgpu_vcn {
- struct amdgpu_bo *vcpu_bo;
- void *cpu_addr;
- uint64_t gpu_addr;
- unsigned fw_version;
- void *saved_bo;
- struct delayed_work idle_work;
- const struct firmware *fw; /* VCN firmware */
- struct amdgpu_ring ring_dec;
- struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
- struct amdgpu_irq_src irq;
- struct amd_sched_entity entity_dec;
- struct amd_sched_entity entity_enc;
- uint32_t srbm_soft_reset;
-};
-
-/*
* SDMA
*/
struct amdgpu_sdma_instance {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ec4d7ca..2fd22a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -24,6 +24,28 @@
#ifndef __AMDGPU_VCN_H__
#define __AMDGPU_VCN_H__
+#define AMDGPU_VCN_STACK_SIZE (200*1024)
+#define AMDGPU_VCN_HEAP_SIZE (256*1024)
+#define AMDGPU_VCN_SESSION_SIZE (50*1024)
+#define AMDGPU_VCN_FIRMWARE_OFFSET 256
+#define AMDGPU_VCN_MAX_ENC_RINGS 3
+
+struct amdgpu_vcn {
+ struct amdgpu_bo *vcpu_bo;
+ void *cpu_addr;
+ uint64_t gpu_addr;
+ unsigned fw_version;
+ void *saved_bo;
+ struct delayed_work idle_work;
+ const struct firmware *fw; /* VCN firmware */
+ struct amdgpu_ring ring_dec;
+ struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
+ struct amdgpu_irq_src irq;
+ struct amd_sched_entity entity_dec;
+ struct amd_sched_entity entity_enc;
+ uint32_t srbm_soft_reset;
+};
+
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 074/117] drm/amdgpu: re-group the functions in amdgpu_vcn.c
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (64 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 073/117] drm/amdgpu: move amdgpu_vcn structure to vcn header Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 075/117] drm/amdgpu: move vcn ring test to amdgpu_vcn.c Alex Deucher
` (43 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 140 ++++++++++++++++----------------
1 file changed, 70 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 9bb59cc..5decef7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -196,6 +196,42 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
return 0;
}
+static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
+{
+ struct amdgpu_device *adev =
+ container_of(work, struct amdgpu_device, vcn.idle_work.work);
+ unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
+
+ if (fences == 0) {
+ if (adev->pm.dpm_enabled) {
+ amdgpu_dpm_enable_uvd(adev, false);
+ } else {
+ amdgpu_asic_set_uvd_clocks(adev, 0, 0);
+ }
+ } else {
+ schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ }
+}
+
+void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+ if (set_clocks) {
+ if (adev->pm.dpm_enabled) {
+ amdgpu_dpm_enable_uvd(adev, true);
+ } else {
+ amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
+ }
+ }
+}
+
+void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
+{
+ schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+}
+
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
bool direct, struct dma_fence **fence)
{
@@ -365,42 +401,6 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence);
}
-static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
-{
- struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
- unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
-
- if (fences == 0) {
- if (adev->pm.dpm_enabled) {
- amdgpu_dpm_enable_uvd(adev, false);
- } else {
- amdgpu_asic_set_uvd_clocks(adev, 0, 0);
- }
- } else {
- schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
- }
-}
-
-void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
-
- if (set_clocks) {
- if (adev->pm.dpm_enabled) {
- amdgpu_dpm_enable_uvd(adev, true);
- } else {
- amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
- }
- }
-}
-
-void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
-{
- schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
-}
-
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence;
@@ -435,6 +435,40 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
return r;
}
+int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t rptr = amdgpu_ring_get_rptr(ring);
+ unsigned i;
+ int r;
+
+ r = amdgpu_ring_alloc(ring, 16);
+ if (r) {
+ DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring, VCE_CMD_END);
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if (amdgpu_ring_get_rptr(ring) != rptr)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed\n",
+ ring->idx);
+ r = -ETIMEDOUT;
+ }
+
+ return r;
+}
+
static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
struct dma_fence **fence)
{
@@ -561,40 +595,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
return r;
}
-int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t rptr = amdgpu_ring_get_rptr(ring);
- unsigned i;
- int r;
-
- r = amdgpu_ring_alloc(ring, 16);
- if (r) {
- DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
- ring->idx, r);
- return r;
- }
- amdgpu_ring_write(ring, VCE_CMD_END);
- amdgpu_ring_commit(ring);
-
- for (i = 0; i < adev->usec_timeout; i++) {
- if (amdgpu_ring_get_rptr(ring) != rptr)
- break;
- DRM_UDELAY(1);
- }
-
- if (i < adev->usec_timeout) {
- DRM_INFO("ring test on %d succeeded in %d usecs\n",
- ring->idx, i);
- } else {
- DRM_ERROR("amdgpu: ring %d test failed\n",
- ring->idx);
- r = -ETIMEDOUT;
- }
-
- return r;
-}
-
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 075/117] drm/amdgpu: move vcn ring test to amdgpu_vcn.c
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (65 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 074/117] drm/amdgpu: re-group the functions in amdgpu_vcn.c Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 076/117] drm/amdgpu: expose vcn RB command Alex Deucher
` (42 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Hope it will be generic for vcn later
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 36 ++++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 ++
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 45 +--------------------------------
3 files changed, 39 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 5decef7..e1493c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -232,6 +232,42 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
}
+int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+ r = amdgpu_ring_alloc(ring, 3);
+ if (r) {
+ DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+ ring->idx, r);
+ return r;
+ }
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+ amdgpu_ring_write(ring, 0xDEADBEEF);
+ amdgpu_ring_commit(ring);
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+
+ if (i < adev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n",
+ ring->idx, i);
+ } else {
+ DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
+ ring->idx, tmp);
+ r = -EINVAL;
+ }
+ return r;
+}
+
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
bool direct, struct dma_fence **fence)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2fd22a5..937c6d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -52,6 +52,8 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
+
+int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 7f3c078..9cd6690 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -539,49 +539,6 @@ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
}
/**
- * vcn_v1_0_dec_ring_test_ring - register write test
- *
- * @ring: amdgpu_ring pointer
- *
- * Test if we can successfully write to the context register
- */
-static int vcn_v1_0_dec_ring_test_ring(struct amdgpu_ring *ring)
-{
- struct amdgpu_device *adev = ring->adev;
- uint32_t tmp = 0;
- unsigned i;
- int r;
-
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
- r = amdgpu_ring_alloc(ring, 3);
- if (r) {
- DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
- ring->idx, r);
- return r;
- }
- amdgpu_ring_write(ring,
- PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
- amdgpu_ring_write(ring, 0xDEADBEEF);
- amdgpu_ring_commit(ring);
- for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
- if (tmp == 0xDEADBEEF)
- break;
- DRM_UDELAY(1);
- }
-
- if (i < adev->usec_timeout) {
- DRM_INFO("ring test on %d succeeded in %d usecs\n",
- ring->idx, i);
- } else {
- DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
- ring->idx, tmp);
- r = -EINVAL;
- }
- return r;
-}
-
-/**
* vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
*
* @ring: amdgpu_ring pointer
@@ -732,7 +689,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.emit_fence = vcn_v1_0_dec_ring_emit_fence,
.emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
.emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate,
- .test_ring = vcn_v1_0_dec_ring_test_ring,
+ .test_ring = amdgpu_vcn_dec_ring_test_ring,
.test_ib = amdgpu_vcn_dec_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 076/117] drm/amdgpu: expose vcn RB command
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (66 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 075/117] drm/amdgpu: move vcn ring test to amdgpu_vcn.c Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 077/117] drm/amdgpu: add a ring func for vcn start command Alex Deucher
` (41 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 7 +++++++
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 ++++----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 937c6d9..5dbc6aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -30,6 +30,13 @@
#define AMDGPU_VCN_FIRMWARE_OFFSET 256
#define AMDGPU_VCN_MAX_ENC_RINGS 3
+#define VCN_CMD_FENCE 0x00000000
+#define VCN_CMD_TRAP 0x00000001
+#define VCN_CMD_WRITE_REG 0x00000004
+#define VCN_CMD_REG_READ_COND_WAIT 0x00000006
+#define VCN_CMD_PACKET_START 0x0000000a
+#define VCN_CMD_PACKET_END 0x0000000b
+
struct amdgpu_vcn {
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 9cd6690..643e4ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
@@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 2);
+ amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);
}
/**
@@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, data1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 8);
+ amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);
}
static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
@@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, mask);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, 12);
+ amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);
}
static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 077/117] drm/amdgpu: add a ring func for vcn start command
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (67 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 076/117] drm/amdgpu: expose vcn RB command Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 078/117] drm/amdgpu: implement vcn start RB command Alex Deucher
` (40 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Needed for the proper command sequence for VCN.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 9cd363a..ef93022 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -161,6 +161,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
return r;
}
+ if (ring->funcs->insert_start)
+ ring->funcs->insert_start(ring);
+
if (vm) {
r = amdgpu_vm_flush(ring, job);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index b4d4ed4..7ee501f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -131,6 +131,7 @@ struct amdgpu_ring_funcs {
int (*test_ib)(struct amdgpu_ring *ring, long timeout);
/* insert NOP packets */
void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
+ void (*insert_start)(struct amdgpu_ring *ring);
void (*insert_end)(struct amdgpu_ring *ring);
/* pad the indirect buffer to the necessary number of dw */
void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 078/117] drm/amdgpu: implement vcn start RB command
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (68 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 077/117] drm/amdgpu: add a ring func for vcn start command Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 079/117] drm/amdgpu: implement insert end ring function for vcn decode Alex Deucher
` (39 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 643e4ce..2fd60de 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -489,6 +489,23 @@ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
/**
+ * vcn_v1_0_dec_ring_insert_start - insert a start command
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Write a start command to the ring.
+ */
+static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, VCN_CMD_PACKET_START << 1);
+}
+
+/**
* vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
*
* @ring: amdgpu_ring pointer
@@ -683,7 +700,8 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.emit_frame_size =
2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
- 14 + 14, /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
+ 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
+ 4,
.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
.emit_ib = vcn_v1_0_dec_ring_emit_ib,
.emit_fence = vcn_v1_0_dec_ring_emit_fence,
@@ -692,6 +710,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.test_ring = amdgpu_vcn_dec_ring_test_ring,
.test_ib = amdgpu_vcn_dec_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
+ .insert_start = vcn_v1_0_dec_ring_insert_start,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vcn_ring_begin_use,
.end_use = amdgpu_vcn_ring_end_use,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 079/117] drm/amdgpu: implement insert end ring function for vcn decode
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (69 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 078/117] drm/amdgpu: implement vcn start RB command Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 080/117] drm/amdgpu/vcn: implement ib tests with new message buffer interface Alex Deucher
` (38 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2fd60de..adf8e52 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -506,6 +506,20 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
}
/**
+ * vcn_v1_0_dec_ring_insert_end - insert a end command
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Write a end command to the ring.
+ */
+static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring,
+ PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+ amdgpu_ring_write(ring, VCN_CMD_PACKET_END << 1);
+}
+
+/**
* vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
*
* @ring: amdgpu_ring pointer
@@ -701,7 +715,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */
34 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_dec_ring_emit_vm_flush */
14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
- 4,
+ 6,
.emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
.emit_ib = vcn_v1_0_dec_ring_emit_ib,
.emit_fence = vcn_v1_0_dec_ring_emit_fence,
@@ -711,6 +725,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.test_ib = amdgpu_vcn_dec_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.insert_start = vcn_v1_0_dec_ring_insert_start,
+ .insert_end = vcn_v1_0_dec_ring_insert_end,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_vcn_ring_begin_use,
.end_use = amdgpu_vcn_ring_end_use,
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 080/117] drm/amdgpu/vcn: implement ib tests with new message buffer interface
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (70 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 079/117] drm/amdgpu: implement insert end ring function for vcn decode Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 081/117] uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS Alex Deucher
` (37 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 40 ++++++++++++++++++++-------------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e1493c1..14be761 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -373,19 +373,26 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
return r;
}
- /* stitch together an vcn create msg */
- msg[0] = cpu_to_le32(0x00000de4);
- msg[1] = cpu_to_le32(0x00000000);
- msg[2] = cpu_to_le32(handle);
+ msg[0] = cpu_to_le32(0x00000028);
+ msg[1] = cpu_to_le32(0x0000004c);
+ msg[2] = cpu_to_le32(0x00000001);
msg[3] = cpu_to_le32(0x00000000);
- msg[4] = cpu_to_le32(0x00000000);
+ msg[4] = cpu_to_le32(handle);
msg[5] = cpu_to_le32(0x00000000);
- msg[6] = cpu_to_le32(0x00000000);
- msg[7] = cpu_to_le32(0x00000780);
- msg[8] = cpu_to_le32(0x00000440);
+ msg[6] = cpu_to_le32(0x00000001);
+ msg[7] = cpu_to_le32(0x00000028);
+ msg[8] = cpu_to_le32(0x00000024);
msg[9] = cpu_to_le32(0x00000000);
- msg[10] = cpu_to_le32(0x01b37000);
- for (i = 11; i < 1024; ++i)
+ msg[10] = cpu_to_le32(0x00000007);
+ msg[11] = cpu_to_le32(0x00000000);
+ msg[12] = cpu_to_le32(0x00000000);
+ msg[13] = cpu_to_le32(0x00000780);
+ msg[14] = cpu_to_le32(0x00000440);
+ msg[15] = cpu_to_le32(0x00000000);
+ msg[16] = cpu_to_le32(0x01b37000);
+ msg[17] = cpu_to_le32(0x00000000);
+ msg[18] = cpu_to_le32(0x00000000);
+ for (i = 19; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
amdgpu_bo_kunmap(bo);
@@ -423,12 +430,13 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
return r;
}
- /* stitch together an vcn destroy msg */
- msg[0] = cpu_to_le32(0x00000de4);
- msg[1] = cpu_to_le32(0x00000002);
- msg[2] = cpu_to_le32(handle);
- msg[3] = cpu_to_le32(0x00000000);
- for (i = 4; i < 1024; ++i)
+ msg[0] = cpu_to_le32(0x00000028);
+ msg[1] = cpu_to_le32(0x00000018);
+ msg[2] = cpu_to_le32(0x00000000);
+ msg[3] = cpu_to_le32(0x00000002);
+ msg[4] = cpu_to_le32(handle);
+ msg[5] = cpu_to_le32(0x00000000);
+ for (i = 6; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
amdgpu_bo_kunmap(bo);
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 081/117] uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (71 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 080/117] drm/amdgpu/vcn: implement ib tests with new message buffer interface Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 082/117] uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS Alex Deucher
` (36 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 929bc72..eeaa04a 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -433,7 +433,8 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_UVD 3
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
-#define AMDGPU_HW_IP_NUM 6
+#define AMDGPU_HW_IP_VCN_DEC 6
+#define AMDGPU_HW_IP_NUM 7
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 082/117] uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (72 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 081/117] uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 083/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query Alex Deucher
` (35 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index eeaa04a..c99fe63 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -434,7 +434,8 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
-#define AMDGPU_HW_IP_NUM 7
+#define AMDGPU_HW_IP_VCN_ENC 7
+#define AMDGPU_HW_IP_NUM 8
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 083/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (73 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 082/117] uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 084/117] drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC Alex Deucher
` (34 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 585b638..8d1d8dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -318,6 +318,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
ib_size_alignment = 1;
break;
+ case AMDGPU_HW_IP_VCN_DEC:
+ type = AMD_IP_BLOCK_TYPE_VCN;
+ ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
+ ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_size_alignment = 16;
+ break;
default:
return -EINVAL;
}
@@ -360,6 +366,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
case AMDGPU_HW_IP_UVD_ENC:
type = AMD_IP_BLOCK_TYPE_UVD;
break;
+ case AMDGPU_HW_IP_VCN_DEC:
+ type = AMD_IP_BLOCK_TYPE_VCN;
+ break;
default:
return -EINVAL;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 084/117] drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (74 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 083/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 085/117] drm/amdgpu: Disable uvd and vce free handles for raven Alex Deucher
` (33 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 4e6b950..60948a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -91,6 +91,9 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
return -EINVAL;
}
break;
+ case AMDGPU_HW_IP_VCN_DEC:
+ *out_ring = &adev->vcn.ring_dec;
+ break;
}
if (!(*out_ring && (*out_ring)->adev)) {
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 085/117] drm/amdgpu: Disable uvd and vce free handles for raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (75 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 084/117] drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 086/117] drm/amdgpu: implement new vcn cache window programming Alex Deucher
` (32 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Not required on raven.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 8d1d8dd..7d2bc4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -822,8 +822,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
- amdgpu_uvd_free_handles(adev, file_priv);
- amdgpu_vce_free_handles(adev, file_priv);
+ if (adev->asic_type != CHIP_RAVEN) {
+ amdgpu_uvd_free_handles(adev, file_priv);
+ amdgpu_vce_free_handles(adev, file_priv);
+ }
amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 086/117] drm/amdgpu: implement new vcn cache window programming
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (76 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 085/117] drm/amdgpu: Disable uvd and vce free handles for raven Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 087/117] drm/amdgpu: add vcn ip block to soc15 Alex Deucher
` (31 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 34 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index adf8e52..ee27c79 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -215,31 +215,29 @@ static int vcn_v1_0_resume(void *handle)
*/
static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
{
- uint64_t offset;
- uint32_t size;
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
- /* programm memory controller bits 0-27 */
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.gpu_addr));
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.gpu_addr));
-
- /* Current FW has no signed header, but will be added later on */
- /* offset = AMDGPU_VCN_FIRMWARE_OFFSET; */
- offset = 0;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), offset >> 3);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
- offset += size;
- size = AMDGPU_VCN_HEAP_SIZE;
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), offset >> 3);
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), size);
-
- offset += size;
- size = AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40);
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), offset >> 3);
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), size);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr + size));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.gpu_addr + size));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_HEAP_SIZE);
+
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
+ AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG),
adev->gfx.config.gb_addr_config);
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 087/117] drm/amdgpu: add vcn ip block to soc15
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (77 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 086/117] drm/amdgpu: implement new vcn cache window programming Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 088/117] drm/amdgpu: change vcn dec rb command specific for decode Alex Deucher
` (30 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 98f372b..d6fa8dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -57,6 +57,7 @@
#include "sdma_v4_0.h"
#include "uvd_v7_0.h"
#include "vce_v4_0.h"
+#include "vcn_v1_0.h"
#include "amdgpu_powerplay.h"
#include "dce_virtual.h"
#include "mxgpu_ai.h"
@@ -519,6 +520,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
#endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
+ amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block);
break;
default:
return -EINVAL;
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 088/117] drm/amdgpu: change vcn dec rb command specific for decode
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (78 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 087/117] drm/amdgpu: add vcn ip block to soc15 Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 089/117] drm/amdgpu: add vcn enc rings Alex Deucher
` (29 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 5dbc6aa..5506568 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -30,12 +30,12 @@
#define AMDGPU_VCN_FIRMWARE_OFFSET 256
#define AMDGPU_VCN_MAX_ENC_RINGS 3
-#define VCN_CMD_FENCE 0x00000000
-#define VCN_CMD_TRAP 0x00000001
-#define VCN_CMD_WRITE_REG 0x00000004
-#define VCN_CMD_REG_READ_COND_WAIT 0x00000006
-#define VCN_CMD_PACKET_START 0x0000000a
-#define VCN_CMD_PACKET_END 0x0000000b
+#define VCN_DEC_CMD_FENCE 0x00000000
+#define VCN_DEC_CMD_TRAP 0x00000001
+#define VCN_DEC_CMD_WRITE_REG 0x00000004
+#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
+#define VCN_DEC_CMD_PACKET_START 0x0000000a
+#define VCN_DEC_CMD_PACKET_END 0x0000000b
struct amdgpu_vcn {
struct amdgpu_bo *vcpu_bo;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index ee27c79..2e65068 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -500,7 +500,7 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_PACKET_START << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
}
/**
@@ -514,7 +514,7 @@ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
{
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_PACKET_END << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
}
/**
@@ -541,7 +541,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
@@ -551,7 +551,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
}
/**
@@ -605,7 +605,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, data1);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
}
static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
@@ -622,7 +622,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, mask);
amdgpu_ring_write(ring,
PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
- amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);
+ amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
}
static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 089/117] drm/amdgpu: add vcn enc rings
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (79 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 088/117] drm/amdgpu: change vcn dec rb command specific for decode Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 090/117] drm/amdgpu: add vcn enc ring type and functions Alex Deucher
` (28 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 5 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +++++++++++++++++++++++++++-
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 14be761..91050ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -126,6 +126,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
{
+ int i;
+
kfree(adev->vcn.saved_bo);
amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
@@ -138,6 +140,9 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
amdgpu_ring_fini(&adev->vcn.ring_dec);
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
+
release_firmware(adev->vcn.fw);
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 5506568..444fed5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -50,7 +50,7 @@ struct amdgpu_vcn {
struct amdgpu_irq_src irq;
struct amd_sched_entity entity_dec;
struct amd_sched_entity entity_enc;
- uint32_t srbm_soft_reset;
+ unsigned num_enc_rings;
};
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2e65068..b8f4e77 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -51,6 +51,8 @@ static int vcn_v1_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ adev->vcn.num_enc_rings = 2;
+
vcn_v1_0_set_dec_ring_funcs(adev);
vcn_v1_0_set_irq_funcs(adev);
@@ -67,7 +69,7 @@ static int vcn_v1_0_early_init(void *handle)
static int vcn_v1_0_sw_init(void *handle)
{
struct amdgpu_ring *ring;
- int r;
+ int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* VCN TRAP */
@@ -86,6 +88,16 @@ static int vcn_v1_0_sw_init(void *handle)
ring = &adev->vcn.ring_dec;
sprintf(ring->name, "vcn_dec");
r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+ if (r)
+ return r;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ ring = &adev->vcn.ring_enc[i];
+ sprintf(ring->name, "vcn_enc%d", i);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+ if (r)
+ return r;
+ }
return r;
}
@@ -401,6 +413,20 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+ ring = &adev->vcn.ring_enc[0];
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
+
+ ring = &adev->vcn.ring_enc[1];
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
+
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 090/117] drm/amdgpu: add vcn enc ring type and functions
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (80 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 089/117] drm/amdgpu: add vcn enc rings Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 091/117] drm/amdgpu: add vcn enc irq support Alex Deucher
` (27 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Add the ring function callbacks for the encode rings.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 8 ++
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 170 +++++++++++++++++++++++++++++++
3 files changed, 180 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7ee501f..b6a2272 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -48,7 +48,8 @@ enum amdgpu_ring_type {
AMDGPU_RING_TYPE_VCE,
AMDGPU_RING_TYPE_KIQ,
AMDGPU_RING_TYPE_UVD_ENC,
- AMDGPU_RING_TYPE_VCN_DEC
+ AMDGPU_RING_TYPE_VCN_DEC,
+ AMDGPU_RING_TYPE_VCN_ENC
};
struct amdgpu_device;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 444fed5..d50ba06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -37,6 +37,14 @@
#define VCN_DEC_CMD_PACKET_START 0x0000000a
#define VCN_DEC_CMD_PACKET_END 0x0000000b
+#define VCN_ENC_CMD_NO_OP 0x00000000
+#define VCN_ENC_CMD_END 0x00000001
+#define VCN_ENC_CMD_IB 0x00000002
+#define VCN_ENC_CMD_FENCE 0x00000003
+#define VCN_ENC_CMD_TRAP 0x00000004
+#define VCN_ENC_CMD_REG_WRITE 0x0000000b
+#define VCN_ENC_CMD_REG_WAIT 0x0000000c
+
struct amdgpu_vcn {
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index b8f4e77..e15a81f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -38,6 +38,7 @@
static int vcn_v1_0_start(struct amdgpu_device *adev);
static int vcn_v1_0_stop(struct amdgpu_device *adev);
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
/**
@@ -54,6 +55,7 @@ static int vcn_v1_0_early_init(void *handle)
adev->vcn.num_enc_rings = 2;
vcn_v1_0_set_dec_ring_funcs(adev);
+ vcn_v1_0_set_enc_ring_funcs(adev);
vcn_v1_0_set_irq_funcs(adev);
return 0;
@@ -688,6 +690,141 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
}
+/**
+ * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc read pointer
+ */
+static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.ring_enc[0])
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR));
+ else
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2));
+}
+
+ /**
+ * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc write pointer
+ */
+static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.ring_enc[0])
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR));
+ else
+ return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2));
+}
+
+ /**
+ * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the enc write pointer to the hardware
+ */
+static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring == &adev->vcn.ring_enc[0])
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR),
+ lower_32_bits(ring->wptr));
+ else
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2),
+ lower_32_bits(ring->wptr));
+}
+
+/**
+ * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
+ *
+ * @ring: amdgpu_ring pointer
+ * @fence: fence to emit
+ *
+ * Write enc a fence and a trap command to the ring.
+ */
+static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+ u64 seq, unsigned flags)
+{
+ WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
+
+ amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
+ amdgpu_ring_write(ring, addr);
+ amdgpu_ring_write(ring, upper_32_bits(addr));
+ amdgpu_ring_write(ring, seq);
+ amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
+}
+
+static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, VCN_ENC_CMD_END);
+}
+
+/**
+ * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
+ *
+ * @ring: amdgpu_ring pointer
+ * @ib: indirect buffer to execute
+ *
+ * Write enc ring commands to execute the indirect buffer
+ */
+static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+{
+ amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
+ amdgpu_ring_write(ring, vm_id);
+ amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+ amdgpu_ring_write(ring, ib->length_dw);
+}
+
+static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
+ unsigned int vm_id, uint64_t pd_addr)
+{
+ struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
+ uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+ unsigned eng = ring->vm_inv_eng;
+
+ pd_addr = pd_addr | 0x1; /* valid bit */
+ /* now only use physical base address of PDE and valid */
+ BUG_ON(pd_addr & 0xFFFF00000000003EULL);
+
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+ amdgpu_ring_write(ring,
+ (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, upper_32_bits(pd_addr));
+
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+ amdgpu_ring_write(ring,
+ (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
+ amdgpu_ring_write(ring,
+ (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+ amdgpu_ring_write(ring, 0xffffffff);
+ amdgpu_ring_write(ring, lower_32_bits(pd_addr));
+
+ /* flush TLB */
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+ amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
+ amdgpu_ring_write(ring, req);
+
+ /* wait for flush */
+ amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
+ amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
+ amdgpu_ring_write(ring, 1 << vm_id);
+ amdgpu_ring_write(ring, 1 << vm_id);
+}
+
static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -755,12 +892,45 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
.end_use = amdgpu_vcn_ring_end_use,
};
+static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
+ .type = AMDGPU_RING_TYPE_VCN_ENC,
+ .align_mask = 0x3f,
+ .nop = VCN_ENC_CMD_NO_OP,
+ .support_64bit_ptrs = false,
+ .get_rptr = vcn_v1_0_enc_ring_get_rptr,
+ .get_wptr = vcn_v1_0_enc_ring_get_wptr,
+ .set_wptr = vcn_v1_0_enc_ring_set_wptr,
+ .emit_frame_size =
+ 17 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_enc_ring_emit_vm_flush */
+ 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
+ 1, /* vcn_v1_0_enc_ring_insert_end */
+ .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
+ .emit_ib = vcn_v1_0_enc_ring_emit_ib,
+ .emit_fence = vcn_v1_0_enc_ring_emit_fence,
+ .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
+ .insert_nop = amdgpu_ring_insert_nop,
+ .insert_end = vcn_v1_0_enc_ring_insert_end,
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_vcn_ring_begin_use,
+ .end_use = amdgpu_vcn_ring_end_use,
+};
+
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
{
adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
DRM_INFO("VCN decode is enabled in VM mode\n");
}
+static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+{
+ int i;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
+
+ DRM_INFO("VCN encode is enabled in VM mode\n");
+}
+
static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
.set = vcn_v1_0_set_interrupt_state,
.process = vcn_v1_0_process_interrupt,
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 091/117] drm/amdgpu: add vcn enc irq support
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (81 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 090/117] drm/amdgpu: add vcn enc ring type and functions Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 092/117] drm/amdgpu: enable vcn encode ring tests Alex Deucher
` (26 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index e15a81f..f09d2ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -74,11 +74,19 @@ static int vcn_v1_0_sw_init(void *handle)
int i, r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- /* VCN TRAP */
+ /* VCN DEC TRAP */
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
if (r)
return r;
+ /* VCN ENC TRAP */
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VCN, i + 119,
+ &adev->vcn.irq);
+ if (r)
+ return r;
+ }
+
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -839,7 +847,21 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
{
DRM_DEBUG("IH: VCN TRAP\n");
- amdgpu_fence_process(&adev->vcn.ring_dec);
+ switch (entry->src_id) {
+ case 124:
+ amdgpu_fence_process(&adev->vcn.ring_dec);
+ break;
+ case 119:
+ amdgpu_fence_process(&adev->vcn.ring_enc[0]);
+ break;
+ case 120:
+ amdgpu_fence_process(&adev->vcn.ring_enc[1]);
+ break;
+ default:
+ DRM_ERROR("Unhandled interrupt: %d %d\n",
+ entry->src_id, entry->src_data[0]);
+ break;
+ }
return 0;
}
@@ -938,7 +960,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
{
- adev->vcn.irq.num_types = 1;
+ adev->uvd.irq.num_types = adev->vcn.num_enc_rings + 1;
adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
}
--
2.5.5
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 092/117] drm/amdgpu: enable vcn encode ring tests
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (82 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 091/117] drm/amdgpu: add vcn enc irq support Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 093/117] drm/amdgpu: add vcn enc ib test Alex Deucher
` (25 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Wire up the callback and enable them.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 15 +++++++++++++--
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 91050ca..18fd565 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -497,7 +497,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
ring->idx, r);
return r;
}
- amdgpu_ring_write(ring, VCE_CMD_END);
+ amdgpu_ring_write(ring, VCN_ENC_CMD_END);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index f09d2ae..4ddaec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -144,7 +144,7 @@ static int vcn_v1_0_hw_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring = &adev->vcn.ring_dec;
- int r;
+ int i, r;
r = vcn_v1_0_start(adev);
if (r)
@@ -157,9 +157,19 @@ static int vcn_v1_0_hw_init(void *handle)
goto done;
}
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ ring = &adev->vcn.ring_enc[i];
+ ring->ready = true;
+ r = amdgpu_ring_test_ring(ring);
+ if (r) {
+ ring->ready = false;
+ goto done;
+ }
+ }
+
done:
if (!r)
- DRM_INFO("VCN decode initialized successfully.\n");
+ DRM_INFO("VCN decode and encode initialized successfully.\n");
return r;
}
@@ -930,6 +940,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
.emit_ib = vcn_v1_0_enc_ring_emit_ib,
.emit_fence = vcn_v1_0_enc_ring_emit_fence,
.emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
+ .test_ring = amdgpu_vcn_enc_ring_test_ring,
.insert_nop = amdgpu_ring_insert_nop,
.insert_end = vcn_v1_0_enc_ring_insert_end,
.pad_ib = amdgpu_ring_generic_pad_ib,
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 093/117] drm/amdgpu: add vcn enc ib test
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (83 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 092/117] drm/amdgpu: enable vcn encode ring tests Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 094/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query Alex Deucher
` (24 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Update and enable the vcn encode IB test.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 84 +++++++++++++--------------------
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
2 files changed, 34 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 18fd565..5c4057d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -521,7 +521,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
struct dma_fence **fence)
{
- const unsigned ib_size_dw = 1024;
+ const unsigned ib_size_dw = 16;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
@@ -533,37 +533,24 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
return r;
ib = &job->ibs[0];
-
dummy = ib->gpu_addr + 1024;
- /* stitch together an VCN enc create msg */
ib->length_dw = 0;
- ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
- ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+ ib->ptr[ib->length_dw++] = dummy;
+ ib->ptr[ib->length_dw++] = 0x0000000b;
- ib->ptr[ib->length_dw++] = 0x00000040; /* len */
- ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
- ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0x00000042;
- ib->ptr[ib->length_dw++] = 0x0000000a;
- ib->ptr[ib->length_dw++] = 0x00000001;
- ib->ptr[ib->length_dw++] = 0x00000080;
- ib->ptr[ib->length_dw++] = 0x00000060;
- ib->ptr[ib->length_dw++] = 0x00000100;
- ib->ptr[ib->length_dw++] = 0x00000100;
- ib->ptr[ib->length_dw++] = 0x0000000c;
- ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
+ ib->ptr[ib->length_dw++] = 0x0000001c;
ib->ptr[ib->length_dw++] = 0x00000000;
ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0x00000014; /* len */
- ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */
- ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
- ib->ptr[ib->length_dw++] = dummy;
- ib->ptr[ib->length_dw++] = 0x00000001;
+ ib->ptr[ib->length_dw++] = 0x00000008;
+ ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
for (i = ib->length_dw; i < ib_size_dw; ++i)
ib->ptr[i] = 0x0;
@@ -577,6 +564,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
if (fence)
*fence = dma_fence_get(f);
dma_fence_put(f);
+
return 0;
err:
@@ -585,12 +573,13 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
}
static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- bool direct, struct dma_fence **fence)
+ struct dma_fence **fence)
{
- const unsigned ib_size_dw = 1024;
+ const unsigned ib_size_dw = 16;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
+ uint64_t dummy;
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
@@ -598,45 +587,38 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
return r;
ib = &job->ibs[0];
+ dummy = ib->gpu_addr + 1024;
- /* stitch together an VCN enc destroy msg */
ib->length_dw = 0;
- ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
- ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
+ ib->ptr[ib->length_dw++] = 0x00000018;
+ ib->ptr[ib->length_dw++] = 0x00000001;
ib->ptr[ib->length_dw++] = handle;
+ ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
+ ib->ptr[ib->length_dw++] = dummy;
+ ib->ptr[ib->length_dw++] = 0x0000000b;
- ib->ptr[ib->length_dw++] = 0x00000020; /* len */
- ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
- ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
- ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */
- ib->ptr[ib->length_dw++] = 0x00000000;
+ ib->ptr[ib->length_dw++] = 0x00000014;
+ ib->ptr[ib->length_dw++] = 0x00000002;
+ ib->ptr[ib->length_dw++] = 0x0000001c;
ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
ib->ptr[ib->length_dw++] = 0x00000000;
- ib->ptr[ib->length_dw++] = 0x00000008; /* len */
- ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */
+ ib->ptr[ib->length_dw++] = 0x00000008;
+ ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
for (i = ib->length_dw; i < ib_size_dw; ++i)
ib->ptr[i] = 0x0;
- if (direct) {
- r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
- job->fence = dma_fence_get(f);
- if (r)
- goto err;
-
- amdgpu_job_free(job);
- } else {
- r = amdgpu_job_submit(job, ring, &ring->adev->vcn.entity_enc,
- AMDGPU_FENCE_OWNER_UNDEFINED, &f);
- if (r)
- goto err;
- }
+ r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+ job->fence = dma_fence_get(f);
+ if (r)
+ goto err;
+ amdgpu_job_free(job);
if (fence)
*fence = dma_fence_get(f);
dma_fence_put(f);
+
return 0;
err:
@@ -655,7 +637,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
goto error;
}
- r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, true, &fence);
+ r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
if (r) {
DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 4ddaec3..1d43d6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -941,6 +941,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
.emit_fence = vcn_v1_0_enc_ring_emit_fence,
.emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
.test_ring = amdgpu_vcn_enc_ring_test_ring,
+ .test_ib = amdgpu_vcn_enc_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.insert_end = vcn_v1_0_enc_ring_insert_end,
.pad_ib = amdgpu_ring_generic_pad_ib,
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 094/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (84 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 093/117] drm/amdgpu: add vcn enc ib test Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 095/117] drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC Alex Deucher
` (23 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7d2bc4c..77aa9f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -324,6 +324,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
ib_size_alignment = 16;
break;
+ case AMDGPU_HW_IP_VCN_ENC:
+ type = AMD_IP_BLOCK_TYPE_VCN;
+ for (i = 0; i < adev->vcn.num_enc_rings; i++)
+ ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
+ ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_size_alignment = 1;
+ break;
default:
return -EINVAL;
}
@@ -367,6 +374,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
type = AMD_IP_BLOCK_TYPE_UVD;
break;
case AMDGPU_HW_IP_VCN_DEC:
+ case AMDGPU_HW_IP_VCN_ENC:
type = AMD_IP_BLOCK_TYPE_VCN;
break;
default:
--
2.5.5
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* [PATCH 095/117] drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (85 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 094/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 096/117] drm/amdgpu: add vcn firmware header offset Alex Deucher
` (22 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 60948a7..1375a89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -94,6 +94,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
case AMDGPU_HW_IP_VCN_DEC:
*out_ring = &adev->vcn.ring_dec;
break;
+ case AMDGPU_HW_IP_VCN_ENC:
+ if (ring < adev->vcn.num_enc_rings){
+ *out_ring = &adev->vcn.ring_enc[ring];
+ } else {
+ DRM_ERROR("only %d VCN ENC rings are supported\n",
+ adev->vcn.num_enc_rings);
+ return -EINVAL;
+ }
+ break;
}
if (!(*out_ring && (*out_ring)->adev)) {
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 096/117] drm/amdgpu: add vcn firmware header offset
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (86 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 095/117] drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 097/117] drm/amdgpu: update vcn decode create msg Alex Deucher
` (21 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
New firmware add psp header.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1d43d6d..6f26a05 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -253,7 +253,8 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
lower_32_bits(adev->vcn.gpu_addr));
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.gpu_addr));
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 097/117] drm/amdgpu: update vcn decode create msg
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (87 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 096/117] drm/amdgpu: add vcn firmware header offset Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 098/117] drm/amdgpu/vcn: add sw clock gating Alex Deucher
` (20 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Leo Liu
From: Leo Liu <leo.liu@amd.com>
Based on new vcn firmware interface changes
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 5c4057d..09190fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -379,25 +379,20 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
}
msg[0] = cpu_to_le32(0x00000028);
- msg[1] = cpu_to_le32(0x0000004c);
+ msg[1] = cpu_to_le32(0x00000038);
msg[2] = cpu_to_le32(0x00000001);
msg[3] = cpu_to_le32(0x00000000);
msg[4] = cpu_to_le32(handle);
msg[5] = cpu_to_le32(0x00000000);
msg[6] = cpu_to_le32(0x00000001);
msg[7] = cpu_to_le32(0x00000028);
- msg[8] = cpu_to_le32(0x00000024);
+ msg[8] = cpu_to_le32(0x00000010);
msg[9] = cpu_to_le32(0x00000000);
msg[10] = cpu_to_le32(0x00000007);
msg[11] = cpu_to_le32(0x00000000);
- msg[12] = cpu_to_le32(0x00000000);
- msg[13] = cpu_to_le32(0x00000780);
- msg[14] = cpu_to_le32(0x00000440);
- msg[15] = cpu_to_le32(0x00000000);
- msg[16] = cpu_to_le32(0x01b37000);
- msg[17] = cpu_to_le32(0x00000000);
- msg[18] = cpu_to_le32(0x00000000);
- for (i = 19; i < 1024; ++i)
+ msg[12] = cpu_to_le32(0x00000780);
+ msg[13] = cpu_to_le32(0x00000440);
+ for (i = 14; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
amdgpu_bo_kunmap(bo);
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 098/117] drm/amdgpu/vcn: add sw clock gating
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (88 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 097/117] drm/amdgpu: update vcn decode create msg Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 099/117] drm/amdgpu: enable sw clock gating for vcn Alex Deucher
` (19 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Add sw controlled clockgating for VCN.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 207 +++++++++++++++++++++++++++++++++-
1 file changed, 205 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 6f26a05..15a2c0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -281,6 +281,207 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
}
/**
+ * vcn_v1_0_disable_clock_gating - disable VCN clock gating
+ *
+ * @adev: amdgpu_device pointer
+ * @sw: enable SW clock gating
+ *
+ * Disable clock gating for VCN block
+ */
+static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw)
+{
+ uint32_t data;
+
+ /* JPEG disable CGC */
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL));
+
+ if (sw)
+ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+
+ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE));
+ data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data);
+
+ /* UVD disable CGC */
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
+ if (sw)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE));
+ data &= ~(UVD_CGC_GATE__SYS_MASK
+ | UVD_CGC_GATE__UDEC_MASK
+ | UVD_CGC_GATE__MPEG2_MASK
+ | UVD_CGC_GATE__REGS_MASK
+ | UVD_CGC_GATE__RBC_MASK
+ | UVD_CGC_GATE__LMI_MC_MASK
+ | UVD_CGC_GATE__LMI_UMC_MASK
+ | UVD_CGC_GATE__IDCT_MASK
+ | UVD_CGC_GATE__MPRD_MASK
+ | UVD_CGC_GATE__MPC_MASK
+ | UVD_CGC_GATE__LBSI_MASK
+ | UVD_CGC_GATE__LRBBM_MASK
+ | UVD_CGC_GATE__UDEC_RE_MASK
+ | UVD_CGC_GATE__UDEC_CM_MASK
+ | UVD_CGC_GATE__UDEC_IT_MASK
+ | UVD_CGC_GATE__UDEC_DB_MASK
+ | UVD_CGC_GATE__UDEC_MP_MASK
+ | UVD_CGC_GATE__WCB_MASK
+ | UVD_CGC_GATE__VCPU_MASK
+ | UVD_CGC_GATE__SCPU_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_GATE), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK
+ | UVD_CGC_CTRL__SCPU_MODE_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
+
+ /* turn on */
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE));
+ data |= (UVD_SUVD_CGC_GATE__SRE_MASK
+ | UVD_SUVD_CGC_GATE__SIT_MASK
+ | UVD_SUVD_CGC_GATE__SMP_MASK
+ | UVD_SUVD_CGC_GATE__SCM_MASK
+ | UVD_SUVD_CGC_GATE__SDB_MASK
+ | UVD_SUVD_CGC_GATE__SRE_H264_MASK
+ | UVD_SUVD_CGC_GATE__SRE_H264_MASK
+ | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_H264_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCM_H264_MASK
+ | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_H264_MASK
+ | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCLR_MASK
+ | UVD_SUVD_CGC_GATE__UVD_SC_MASK
+ | UVD_SUVD_CGC_GATE__ENT_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
+ | UVD_SUVD_CGC_GATE__SITE_MASK
+ | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
+ | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_GATE), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL));
+ data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data);
+}
+
+/**
+ * vcn_v1_0_enable_clock_gating - enable VCN clock gating
+ *
+ * @adev: amdgpu_device pointer
+ * @sw: enable SW clock gating
+ *
+ * Enable clock gating for VCN block
+ */
+static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw)
+{
+ uint32_t data = 0;
+
+ /* enable JPEG CGC */
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL));
+ if (sw)
+ data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_CTRL), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE));
+ data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmJPEG_CGC_GATE), data);
+
+ /* enable UVD CGC */
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
+ if (sw)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL));
+ data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK
+ | UVD_CGC_CTRL__SCPU_MODE_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_CGC_CTRL), data);
+
+ data = RREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL));
+ data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+ WREG32(SOC15_REG_OFFSET(VCN, 0, mmUVD_SUVD_CGC_CTRL), data);
+}
+
+/**
* vcn_v1_0_start - start VCN block
*
* @adev: amdgpu_device pointer
@@ -300,8 +501,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
vcn_v1_0_mc_resume(adev);
/* disable clock gating */
- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
- ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
+ vcn_v1_0_disable_clock_gating(adev, false);
/* disable interupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
@@ -481,6 +681,9 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ /* enable clock gating */
+ vcn_v1_0_enable_clock_gating(adev, false);
+
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 099/117] drm/amdgpu: enable sw clock gating for vcn
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (89 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 098/117] drm/amdgpu/vcn: add sw clock gating Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 100/117] drm/amdgpu/powerplay: add header file for smu10. (v2) Alex Deucher
` (18 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 15a2c0f..61a25a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -501,7 +501,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
vcn_v1_0_mc_resume(adev);
/* disable clock gating */
- vcn_v1_0_disable_clock_gating(adev, false);
+ vcn_v1_0_disable_clock_gating(adev, true);
/* disable interupt */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
@@ -682,7 +682,7 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
/* enable clock gating */
- vcn_v1_0_enable_clock_gating(adev, false);
+ vcn_v1_0_enable_clock_gating(adev, true);
return 0;
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 100/117] drm/amdgpu/powerplay: add header file for smu10. (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (90 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 099/117] drm/amdgpu: enable sw clock gating for vcn Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 101/117] drm/amdgpu: add raven related define in pptable.h Alex Deucher
` (17 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Headers define the driver/fw interface for smu10.
v2: squash in updates (Alex)
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +++++++++++++++++++++
.../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +++++++++++++
2 files changed, 304 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10.h b/drivers/gpu/drm/amd/powerplay/inc/smu10.h
new file mode 100644
index 0000000..9e837a5
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu10.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU10_H
+#define SMU10_H
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+/* Feature Control Defines */
+#define FEATURE_CCLK_CONTROLLER_BIT 0
+#define FEATURE_FAN_CONTROLLER_BIT 1
+#define FEATURE_DATA_CALCULATION_BIT 2
+#define FEATURE_PPT_BIT 3
+#define FEATURE_TDC_BIT 4
+#define FEATURE_THERMAL_BIT 5
+#define FEATURE_FIT_BIT 6
+#define FEATURE_EDC_BIT 7
+#define FEATURE_PLL_POWER_DOWN_BIT 8
+#define FEATURE_ULV_BIT 9
+#define FEATURE_VDDOFF_BIT 10
+#define FEATURE_VCN_DPM_BIT 11
+#define FEATURE_ACP_DPM_BIT 12
+#define FEATURE_ISP_DPM_BIT 13
+#define FEATURE_FCLK_DPM_BIT 14
+#define FEATURE_SOCCLK_DPM_BIT 15
+#define FEATURE_MP0CLK_DPM_BIT 16
+#define FEATURE_LCLK_DPM_BIT 17
+#define FEATURE_SHUBCLK_DPM_BIT 18
+#define FEATURE_DCEFCLK_DPM_BIT 19
+#define FEATURE_GFX_DPM_BIT 20
+#define FEATURE_DS_GFXCLK_BIT 21
+#define FEATURE_DS_SOCCLK_BIT 22
+#define FEATURE_DS_LCLK_BIT 23
+#define FEATURE_DS_DCEFCLK_BIT 24
+#define FEATURE_DS_SHUBCLK_BIT 25
+#define FEATURE_RM_BIT 26
+#define FEATURE_S0i2_BIT 27
+#define FEATURE_WHISPER_MODE_BIT 28
+#define FEATURE_DS_FCLK_BIT 29
+#define FEATURE_DS_SMNCLK_BIT 30
+#define FEATURE_DS_MP1CLK_BIT 31
+#define FEATURE_DS_MP0CLK_BIT 32
+#define FEATURE_MGCG_BIT 33
+#define FEATURE_DS_FUSE_SRAM_BIT 34
+#define FEATURE_GFX_CKS 35
+#define FEATURE_PSI0_BIT 36
+#define FEATURE_PROCHOT_BIT 37
+#define FEATURE_CPUOFF_BIT 38
+#define FEATURE_STAPM_BIT 39
+#define FEATURE_CORE_CSTATES_BIT 40
+#define FEATURE_SPARE_41_BIT 41
+#define FEATURE_SPARE_42_BIT 42
+#define FEATURE_SPARE_43_BIT 43
+#define FEATURE_SPARE_44_BIT 44
+#define FEATURE_SPARE_45_BIT 45
+#define FEATURE_SPARE_46_BIT 46
+#define FEATURE_SPARE_47_BIT 47
+#define FEATURE_SPARE_48_BIT 48
+#define FEATURE_SPARE_49_BIT 49
+#define FEATURE_SPARE_50_BIT 50
+#define FEATURE_SPARE_51_BIT 51
+#define FEATURE_SPARE_52_BIT 52
+#define FEATURE_SPARE_53_BIT 53
+#define FEATURE_SPARE_54_BIT 54
+#define FEATURE_SPARE_55_BIT 55
+#define FEATURE_SPARE_56_BIT 56
+#define FEATURE_SPARE_57_BIT 57
+#define FEATURE_SPARE_58_BIT 58
+#define FEATURE_SPARE_59_BIT 59
+#define FEATURE_SPARE_60_BIT 60
+#define FEATURE_SPARE_61_BIT 61
+#define FEATURE_SPARE_62_BIT 62
+#define FEATURE_SPARE_63_BIT 63
+
+#define NUM_FEATURES 64
+
+#define FEATURE_CCLK_CONTROLLER_MASK (1 << FEATURE_CCLK_CONTROLLER_BIT)
+#define FEATURE_FAN_CONTROLLER_MASK (1 << FEATURE_FAN_CONTROLLER_BIT)
+#define FEATURE_DATA_CALCULATION_MASK (1 << FEATURE_DATA_CALCULATION_BIT)
+#define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT)
+#define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT)
+#define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT)
+#define FEATURE_FIT_MASK (1 << FEATURE_FIT_BIT)
+#define FEATURE_EDC_MASK (1 << FEATURE_EDC_BIT)
+#define FEATURE_PLL_POWER_DOWN_MASK (1 << FEATURE_PLL_POWER_DOWN_BIT)
+#define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT)
+#define FEATURE_VDDOFF_MASK (1 << FEATURE_VDDOFF_BIT)
+#define FEATURE_VCN_DPM_MASK (1 << FEATURE_VCN_DPM_BIT)
+#define FEATURE_ACP_DPM_MASK (1 << FEATURE_ACP_DPM_BIT)
+#define FEATURE_ISP_DPM_MASK (1 << FEATURE_ISP_DPM_BIT)
+#define FEATURE_FCLK_DPM_MASK (1 << FEATURE_FCLK_DPM_BIT)
+#define FEATURE_SOCCLK_DPM_MASK (1 << FEATURE_SOCCLK_DPM_BIT)
+#define FEATURE_MP0CLK_DPM_MASK (1 << FEATURE_MP0CLK_DPM_BIT)
+#define FEATURE_LCLK_DPM_MASK (1 << FEATURE_LCLK_DPM_BIT)
+#define FEATURE_SHUBCLK_DPM_MASK (1 << FEATURE_SHUBCLK_DPM_BIT)
+#define FEATURE_DCEFCLK_DPM_MASK (1 << FEATURE_DCEFCLK_DPM_BIT)
+#define FEATURE_GFX_DPM_MASK (1 << FEATURE_GFX_DPM_BIT)
+#define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT)
+#define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT)
+#define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT)
+#define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT)
+#define FEATURE_DS_SHUBCLK_MASK (1 << FEATURE_DS_SHUBCLK_BIT)
+#define FEATURE_RM_MASK (1 << FEATURE_RM_BIT)
+#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT)
+#define FEATURE_DS_SMNCLK_MASK (1 << FEATURE_DS_SMNCLK_BIT)
+#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT)
+#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT)
+#define FEATURE_MGCG_MASK (1 << FEATURE_MGCG_BIT)
+#define FEATURE_DS_FUSE_SRAM_MASK (1 << FEATURE_DS_FUSE_SRAM_BIT)
+#define FEATURE_PSI0_MASK (1 << FEATURE_PSI0_BIT)
+#define FEATURE_STAPM_MASK (1 << FEATURE_STAPM_BIT)
+#define FEATURE_PROCHOT_MASK (1 << FEATURE_PROCHOT_BIT)
+#define FEATURE_CPUOFF_MASK (1 << FEATURE_CPUOFF_BIT)
+#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)
+
+/* Workload bits */
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_VR_BIT 3
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5
+#define WORKLOAD_PPLIB_COUNT 6
+
+typedef struct {
+ /* MP1_EXT_SCRATCH0 */
+ uint32_t CurrLevel_ACP : 4;
+ uint32_t CurrLevel_ISP : 4;
+ uint32_t CurrLevel_VCN : 4;
+ uint32_t CurrLevel_LCLK : 4;
+ uint32_t CurrLevel_MP0CLK : 4;
+ uint32_t CurrLevel_FCLK : 4;
+ uint32_t CurrLevel_SOCCLK : 4;
+ uint32_t CurrLevel_DCEFCLK : 4;
+ /* MP1_EXT_SCRATCH1 */
+ uint32_t TargLevel_ACP : 4;
+ uint32_t TargLevel_ISP : 4;
+ uint32_t TargLevel_VCN : 4;
+ uint32_t TargLevel_LCLK : 4;
+ uint32_t TargLevel_MP0CLK : 4;
+ uint32_t TargLevel_FCLK : 4;
+ uint32_t TargLevel_SOCCLK : 4;
+ uint32_t TargLevel_DCEFCLK : 4;
+ /* MP1_EXT_SCRATCH2 */
+ uint32_t CurrLevel_SHUBCLK : 4;
+ uint32_t TargLevel_SHUBCLK : 4;
+ uint32_t InUlv : 1;
+ uint32_t InS0i2 : 1;
+ uint32_t InWhisperMode : 1;
+ uint32_t Reserved : 21;
+ /* MP1_EXT_SCRATCH3-4 */
+ uint32_t Reserved2[2];
+ /* MP1_EXT_SCRATCH5 */
+ uint32_t FeatureStatus[NUM_FEATURES / 32];
+} FwStatus_t;
+
+#define TABLE_BIOS_IF 0 /* Called by BIOS */
+#define TABLE_WATERMARKS 1 /* Called by Driver */
+#define TABLE_CUSTOM_DPM 2 /* Called by Driver */
+#define TABLE_PMSTATUSLOG 3 /* Called by Tools for Agm logging */
+#define TABLE_DPMCLOCKS 4 /* Called by Driver */
+#define TABLE_MOMENTARY_PM 5 /* Called by Tools */
+#define TABLE_COUNT 6
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
new file mode 100644
index 0000000..dea8fe9
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU10_DRIVER_IF_H
+#define SMU10_DRIVER_IF_H
+
+#define SMU10_DRIVER_IF_VERSION 0x6
+
+#define NUM_DSPCLK_LEVELS 8
+
+typedef struct {
+ int32_t value;
+ uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+ DSPCLK_DCEFCLK = 0,
+ DSPCLK_DISPCLK,
+ DSPCLK_PIXCLK,
+ DSPCLK_PHYCLK,
+ DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+ uint16_t Freq;
+ uint16_t Vid;
+} DisplayClockTable_t;
+
+
+typedef struct {
+ uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
+ uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
+ uint16_t MinMclk;
+ uint16_t MaxMclk;
+
+ uint8_t WmSetting;
+ uint8_t Padding[3];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+ WM_SOCCLK = 0,
+ WM_DCFCLK,
+ WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+ WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+ uint32_t MmHubPadding[7];
+} Watermarks_t;
+
+typedef enum {
+ CUSTOM_DPM_SETTING_GFXCLK,
+ CUSTOM_DPM_SETTING_CCLK,
+ CUSTOM_DPM_SETTING_FCLK_CCX,
+ CUSTOM_DPM_SETTING_FCLK_GFX,
+ CUSTOM_DPM_SETTING_FCLK_STALLS,
+ CUSTOM_DPM_SETTING_LCLK,
+ CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+ uint8_t ActiveHystLimit;
+ uint8_t IdleHystLimit;
+ uint8_t FPS;
+ uint8_t MinActiveFreqType;
+ FloatInIntFormat_t MinActiveFreq;
+ FloatInIntFormat_t PD_Data_limit;
+ FloatInIntFormat_t PD_Data_time_constant;
+ FloatInIntFormat_t PD_Data_error_coeff;
+ FloatInIntFormat_t PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+ DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_SOCCLK_DPM_LEVELS 8
+#define NUM_DCEFCLK_DPM_LEVELS 4
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_MEMCLK_DPM_LEVELS 4
+
+typedef struct {
+ uint32_t Freq; /* In MHz */
+ uint32_t Vol; /* Millivolts with 2 fractional bits */
+} DpmClock_t;
+
+typedef struct {
+ DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
+ DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+ DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
+ DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
+} DpmClocks_t;
+
+#endif
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 101/117] drm/amdgpu: add raven related define in pptable.h.
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (91 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 100/117] drm/amdgpu/powerplay: add header file for smu10. (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 102/117] drm/amd/powerplay: add ppt_v3 define Alex Deucher
` (16 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/pptable.h | 57 +++++++++++++++++++++++++++++++++--
1 file changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/pptable.h b/drivers/gpu/drm/amd/include/pptable.h
index ee6978b..0b6a057 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -61,13 +61,17 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
#define ATOM_PP_THERMALCONTROLLER_LM96163 17
#define ATOM_PP_THERMALCONTROLLER_CISLANDS 18
#define ATOM_PP_THERMALCONTROLLER_KAVERI 19
+#define ATOM_PP_THERMALCONTROLLER_ICELAND 20
+#define ATOM_PP_THERMALCONTROLLER_TONGA 21
+#define ATOM_PP_THERMALCONTROLLER_FIJI 22
+#define ATOM_PP_THERMALCONTROLLER_POLARIS10 23
+#define ATOM_PP_THERMALCONTROLLER_VEGA10 24
// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
// We probably should reserve the bit 0x80 for this use.
// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
// The driver can pick the correct internal controller based on the ASIC.
-
#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
@@ -104,6 +108,21 @@ typedef struct _ATOM_PPLIB_FANTABLE3
USHORT usFanOutputSensitivity;
} ATOM_PPLIB_FANTABLE3;
+typedef struct _ATOM_PPLIB_FANTABLE4
+{
+ ATOM_PPLIB_FANTABLE3 basicTable3;
+ USHORT usFanRPMMax;
+} ATOM_PPLIB_FANTABLE4;
+
+typedef struct _ATOM_PPLIB_FANTABLE5
+{
+ ATOM_PPLIB_FANTABLE4 basicTable4;
+ USHORT usFanCurrentLow;
+ USHORT usFanCurrentHigh;
+ USHORT usFanRPMLow;
+ USHORT usFanRPMHigh;
+} ATOM_PPLIB_FANTABLE5;
+
typedef struct _ATOM_PPLIB_EXTENDEDHEADER
{
USHORT usSize;
@@ -119,6 +138,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
USHORT usSclkVddgfxTableOffset;
+ USHORT usVQBudgetingTableOffset; /* points to the vqBudgetingTable; */
} ATOM_PPLIB_EXTENDEDHEADER;
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
@@ -147,8 +167,9 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
#define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature.
#define ATOM_PP_PLATFORM_CAP_EVV 0x00800000
#define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000
-#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000
-#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000
+#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000
+#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000
+#define ATOM_PP_PLATFORM_CAP_VRHOT_POLARITY_HIGH 0x08000000
typedef struct _ATOM_PPLIB_POWERPLAYTABLE
{
@@ -427,6 +448,15 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
ULONG rsv2[2];
}ATOM_PPLIB_SUMO_CLOCK_INFO;
+typedef struct _ATOM_PPLIB_KV_CLOCK_INFO {
+ USHORT usEngineClockLow;
+ UCHAR ucEngineClockHigh;
+ UCHAR vddcIndex;
+ USHORT tdpLimit;
+ USHORT rsv1;
+ ULONG rsv2[2];
+} ATOM_PPLIB_KV_CLOCK_INFO;
+
typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
UCHAR index;
UCHAR rsv[3];
@@ -697,6 +727,27 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;
+#define VQ_DisplayConfig_NoneAWD 1
+#define VQ_DisplayConfig_AWD 2
+
+typedef struct ATOM_PPLIB_VQ_Budgeting_Record{
+ ULONG ulDeviceID;
+ ULONG ulSustainableSOCPowerLimitLow; /* in mW */
+ ULONG ulSustainableSOCPowerLimitHigh; /* in mW */
+
+ ULONG ulDClk;
+ ULONG ulEClk;
+ ULONG ulDispSclk;
+ UCHAR ucDispConfig;
+
+} ATOM_PPLIB_VQ_Budgeting_Record;
+
+typedef struct ATOM_PPLIB_VQ_Budgeting_Table {
+ UCHAR revid;
+ UCHAR numEntries;
+ ATOM_PPLIB_VQ_Budgeting_Record entries[1];
+} ATOM_PPLIB_VQ_Budgeting_Table;
+
#pragma pack()
#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 102/117] drm/amd/powerplay: add ppt_v3 define
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (92 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 101/117] drm/amdgpu: add raven related define in pptable.h Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 103/117] drm/amd/powerplay: add raven support in smumgr. (v2) Alex Deucher
` (15 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
defines clock dependencies for raven.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index e4574c2..19187a9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -609,6 +609,17 @@ struct phm_ppt_v2_information {
uint8_t uc_dcef_dpm_voltage_mode;
};
+struct phm_ppt_v3_information {
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
+ struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
+};
+
+
struct phm_dynamic_state_info {
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 103/117] drm/amd/powerplay: add raven support in smumgr. (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (93 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 102/117] drm/amd/powerplay: add ppt_v3 define Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 104/117] drm/amd/powerplay: add raven support in hwmgr. (v2) Alex Deucher
` (14 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
smumgr provides the interface for interacting with the
smu firmware which handles power management.
v2: squash in updates (Alex)
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +++
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +++++
drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 352 +++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 ++++
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
7 files changed, 544 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
new file mode 100644
index 0000000..9a01493
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RAVEN_INC_H
+#define RAVEN_INC_H
+
+
+#include "asic_reg/raven1/MP/mp_10_0_default.h"
+#include "asic_reg/raven1/MP/mp_10_0_offset.h"
+#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h"
+
+#include "asic_reg/raven1/NBIO/nbio_7_0_default.h"
+#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h"
+#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h"
+
+#include "asic_reg/raven1/THM/thm_10_0_default.h"
+#include "asic_reg/raven1/THM/thm_10_0_offset.h"
+#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h"
+
+
+#define ixDDI_PHY_GEN_STATUS 0x3FCE8
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
new file mode 100644
index 0000000..65149c7
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RAVEN_PP_SMC_H
+#define RAVEN_PP_SMC_H
+
+#pragma pack(push, 1)
+
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_EnableGfxOff 0x7
+#define PPSMC_MSG_DisableGfxOff 0x8
+#define PPSMC_MSG_PowerDownIspByTile 0x9
+#define PPSMC_MSG_PowerUpIspByTile 0xA
+#define PPSMC_MSG_PowerDownVcn 0xB
+#define PPSMC_MSG_PowerUpVcn 0xC
+#define PPSMC_MSG_PowerDownSdma 0xD
+#define PPSMC_MSG_PowerUpSdma 0xE
+#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF
+#define PPSMC_MSG_SetHardMinVcn 0x10
+#define PPSMC_MSG_SetMinDisplayClock 0x11
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x12
+#define PPSMC_MSG_SetAllowFclkSwitch 0x13
+#define PPSMC_MSG_SetGfxMinActiveFreq 0x14
+#define PPSMC_MSG_ActiveProcessNotify 0x15
+#define PPSMC_MSG_SetCustomPolicy 0x16
+#define PPSMC_MSG_SetVideoFps 0x17
+#define PPSMC_MSG_SetDisplayCount 0x18
+#define PPSMC_MSG_QueryPowerLimit 0x19
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A
+#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
+#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
+#define PPSMC_MSG_TransferTableDram2Smu 0x1D
+#define PPSMC_MSG_ControlGfxRM 0x1E
+#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
+#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
+#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
+
+
+#define PPSMC_Message_Count 0x23
+
+typedef uint16_t PPSMC_Result;
+typedef int PPSMC_Msg;
+
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 37f4121..976e942 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs;
+extern const struct pp_smumgr_func rv_smu_funcs;
enum AVFS_BTC_STATUS {
AVFS_BTC_BOOT = 0,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
index 68b01b5..1703bbe 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile
@@ -4,7 +4,7 @@
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
- smu7_smumgr.o iceland_smc.o vega10_smumgr.o
+ smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
new file mode 100644
index 0000000..6b6b755
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "smumgr.h"
+#include "rv_inc.h"
+#include "pp_soc15.h"
+#include "rv_smumgr.h"
+#include "ppatomctrl.h"
+#include "rv_ppsmc.h"
+#include "smu10_driver_if.h"
+#include "smu10.h"
+#include "ppatomctrl.h"
+#include "pp_debug.h"
+#include "smu_ucode_xfer_vi.h"
+#include "smu7_smumgr.h"
+
+#define VOLTAGE_SCALE 4
+
+#define BUFFER_SIZE 80000
+#define MAX_STRING_SIZE 15
+#define BUFFER_SIZETWO 131072
+
+#define MP0_Public 0x03800000
+#define MP0_SRAM 0x03900000
+#define MP1_Public 0x03b00000
+#define MP1_SRAM 0x03c00004
+
+#define smnMP1_FIRMWARE_FLAGS 0x3010028
+
+
+bool rv_is_smc_ram_running(struct pp_smumgr *smumgr)
+{
+ uint32_t mp1_fw_flags, reg;
+
+ reg = soc15_get_register_offset(NBIF_HWID, 0,
+ mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
+
+ cgs_write_register(smumgr->device, reg,
+ (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
+
+ reg = soc15_get_register_offset(NBIF_HWID, 0,
+ mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
+
+ mp1_fw_flags = cgs_read_register(smumgr->device, reg);
+
+ if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
+ return true;
+
+ return false;
+}
+
+static uint32_t rv_wait_for_response(struct pp_smumgr *smumgr)
+{
+ uint32_t reg;
+
+ if (!rv_is_smc_ram_running(smumgr))
+ return -EINVAL;
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+
+ smum_wait_for_register_unequal(smumgr, reg,
+ 0, MP1_C2PMSG_90__CONTENT_MASK);
+
+ return cgs_read_register(smumgr->device, reg);
+}
+
+int rv_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
+ uint16_t msg)
+{
+ uint32_t reg;
+
+ if (!rv_is_smc_ram_running(smumgr))
+ return -EINVAL;
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
+ cgs_write_register(smumgr->device, reg, msg);
+
+ return 0;
+}
+
+int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
+{
+ uint32_t reg;
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+
+ *arg = cgs_read_register(smumgr->device, reg);
+
+ return 0;
+}
+
+int rv_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
+{
+ uint32_t reg;
+
+ rv_wait_for_response(smumgr);
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+ cgs_write_register(smumgr->device, reg, 0);
+
+ rv_send_msg_to_smc_without_waiting(smumgr, msg);
+
+ PP_ASSERT_WITH_CODE(rv_wait_for_response(smumgr) == 1,
+ "Failed to send Message.",
+ return -EINVAL);
+
+ return 0;
+}
+
+
+int rv_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
+ uint16_t msg, uint32_t parameter)
+{
+ uint32_t reg;
+
+ rv_wait_for_response(smumgr);
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
+ cgs_write_register(smumgr->device, reg, 0);
+
+ reg = soc15_get_register_offset(MP1_HWID, 0,
+ mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
+ cgs_write_register(smumgr->device, reg, parameter);
+
+ rv_send_msg_to_smc_without_waiting(smumgr, msg);
+
+ PP_ASSERT_WITH_CODE(rv_wait_for_response(smumgr) == 1,
+ "Failed to send Message.",
+ return -EINVAL);
+
+ return 0;
+}
+
+int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+ uint8_t *table, int16_t table_id)
+{
+ struct rv_smumgr *priv =
+ (struct rv_smumgr *)(smumgr->backend);
+
+ PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+ "Invalid SMU Table ID!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
+ "Invalid SMU Table version!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
+ "Invalid SMU Table Length!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_SetDriverDramAddrHigh,
+ priv->smu_tables.entry[table_id].table_addr_high) == 0,
+ "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_SetDriverDramAddrLow,
+ priv->smu_tables.entry[table_id].table_addr_low) == 0,
+ "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
+ return -EINVAL;);
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_TransferTableSmu2Dram,
+ priv->smu_tables.entry[table_id].table_id) == 0,
+ "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
+ return -EINVAL;);
+
+ memcpy(table, priv->smu_tables.entry[table_id].table,
+ priv->smu_tables.entry[table_id].size);
+
+ return 0;
+}
+
+int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+ uint8_t *table, int16_t table_id)
+{
+ struct rv_smumgr *priv =
+ (struct rv_smumgr *)(smumgr->backend);
+
+ PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
+ "Invalid SMU Table ID!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
+ "Invalid SMU Table version!", return -EINVAL;);
+ PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
+ "Invalid SMU Table Length!", return -EINVAL;);
+
+ memcpy(priv->smu_tables.entry[table_id].table, table,
+ priv->smu_tables.entry[table_id].size);
+
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_SetDriverDramAddrHigh,
+ priv->smu_tables.entry[table_id].table_addr_high) == 0,
+ "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
+ return -EINVAL;);
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_SetDriverDramAddrLow,
+ priv->smu_tables.entry[table_id].table_addr_low) == 0,
+ "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
+ return -EINVAL;);
+ PP_ASSERT_WITH_CODE(rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_TransferTableDram2Smu,
+ priv->smu_tables.entry[table_id].table_id) == 0,
+ "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
+ return -EINVAL;);
+
+ return 0;
+}
+
+static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
+{
+ uint32_t smc_driver_if_version;
+
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PPSMC_MSG_GetDriverIfVersion),
+ "Attempt to get SMC IF Version Number Failed!",
+ return -EINVAL);
+ PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(smumgr,
+ &smc_driver_if_version),
+ "Attempt to read SMC IF Version Number Failed!",
+ return -EINVAL);
+
+ if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION)
+ return -EINVAL;
+
+ return 0;
+}
+
+
+static int rv_smu_fini(struct pp_smumgr *smumgr)
+{
+ struct rv_smumgr *priv =
+ (struct rv_smumgr *)(smumgr->backend);
+
+ if (priv) {
+ cgs_free_gpu_mem(smumgr->device,
+ priv->smu_tables.entry[WMTABLE].handle);
+ cgs_free_gpu_mem(smumgr->device,
+ priv->smu_tables.entry[CLOCKTABLE].handle);
+ kfree(smumgr->backend);
+ smumgr->backend = NULL;
+ }
+
+ return 0;
+}
+
+static int rv_start_smu(struct pp_smumgr *smumgr)
+{
+ if (rv_verify_smc_interface(smumgr))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rv_smu_init(struct pp_smumgr *smumgr)
+{
+ struct rv_smumgr *priv;
+ uint64_t mc_addr;
+ void *kaddr = NULL;
+ unsigned long handle;
+
+ priv = kzalloc(sizeof(struct rv_smumgr), GFP_KERNEL);
+
+ if (!priv)
+ return -ENOMEM;
+
+ smumgr->backend = priv;
+
+ /* allocate space for watermarks table */
+ smu_allocate_memory(smumgr->device,
+ sizeof(Watermarks_t),
+ CGS_GPU_MEM_TYPE__GART_CACHEABLE,
+ PAGE_SIZE,
+ &mc_addr,
+ &kaddr,
+ &handle);
+
+ PP_ASSERT_WITH_CODE(kaddr,
+ "[rv_smu_init] Out of memory for wmtable.",
+ kfree(smumgr->backend);
+ smumgr->backend = NULL;
+ return -EINVAL);
+
+ priv->smu_tables.entry[WMTABLE].version = 0x01;
+ priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
+ priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
+ priv->smu_tables.entry[WMTABLE].table_addr_high =
+ smu_upper_32_bits(mc_addr);
+ priv->smu_tables.entry[WMTABLE].table_addr_low =
+ smu_lower_32_bits(mc_addr);
+ priv->smu_tables.entry[WMTABLE].table = kaddr;
+ priv->smu_tables.entry[WMTABLE].handle = handle;
+
+ /* allocate space for watermarks table */
+ smu_allocate_memory(smumgr->device,
+ sizeof(DpmClocks_t),
+ CGS_GPU_MEM_TYPE__GART_CACHEABLE,
+ PAGE_SIZE,
+ &mc_addr,
+ &kaddr,
+ &handle);
+
+ PP_ASSERT_WITH_CODE(kaddr,
+ "[rv_smu_init] Out of memory for CLOCKTABLE.",
+ cgs_free_gpu_mem(smumgr->device,
+ (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
+ kfree(smumgr->backend);
+ smumgr->backend = NULL;
+ return -EINVAL);
+
+ priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
+ priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
+ priv->smu_tables.entry[CLOCKTABLE].table_id = TABLE_DPMCLOCKS;
+ priv->smu_tables.entry[CLOCKTABLE].table_addr_high =
+ smu_upper_32_bits(mc_addr);
+ priv->smu_tables.entry[CLOCKTABLE].table_addr_low =
+ smu_lower_32_bits(mc_addr);
+ priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
+ priv->smu_tables.entry[CLOCKTABLE].handle = handle;
+
+ return 0;
+}
+
+const struct pp_smumgr_func rv_smu_funcs = {
+ .smu_init = &rv_smu_init,
+ .smu_fini = &rv_smu_fini,
+ .start_smu = &rv_start_smu,
+ .request_smu_load_specific_fw = NULL,
+ .send_msg_to_smc = &rv_send_msg_to_smc,
+ .send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter,
+ .download_pptable_settings = NULL,
+ .upload_pptable_settings = NULL,
+};
+
+
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
new file mode 100644
index 0000000..262c8de
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef PP_RAVEN_SMUMANAGER_H
+#define PP_RAVEN_SMUMANAGER_H
+
+#include "rv_ppsmc.h"
+#include "smu10_driver_if.h"
+
+enum SMU_TABLE_ID {
+ WMTABLE = 0,
+ CLOCKTABLE,
+ MAX_SMU_TABLE,
+};
+
+struct smu_table_entry {
+ uint32_t version;
+ uint32_t size;
+ uint32_t table_id;
+ uint32_t table_addr_high;
+ uint32_t table_addr_low;
+ uint8_t *table;
+ uint32_t handle;
+};
+
+struct smu_table_array {
+ struct smu_table_entry entry[MAX_SMU_TABLE];
+};
+
+struct rv_smumgr {
+ struct smu_table_array smu_tables;
+};
+
+int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
+bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
+int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
+ uint8_t *table, int16_t table_id);
+int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
+ uint8_t *table, int16_t table_id);
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index c0d7576..c234029 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -95,6 +95,15 @@ int smum_early_init(struct pp_instance *handle)
return -EINVAL;
}
break;
+ case AMDGPU_FAMILY_RV:
+ switch (smumgr->chip_id) {
+ case CHIP_RAVEN:
+ smumgr->smumgr_funcs = &rv_smu_funcs;
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
default:
kfree(smumgr);
return -EINVAL;
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 104/117] drm/amd/powerplay: add raven support in hwmgr. (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (94 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 103/117] drm/amd/powerplay: add raven support in smumgr. (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 105/117] drm/amd/powerplay/rv: power up/down sdma via the SMU Alex Deucher
` (13 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
hwmgr handles the GPU power state management.
v2: squash in updates (Alex)
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
.../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +++++++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 18 +-
8 files changed, 1291 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
index 781e53d..3e3ca03 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c
@@ -42,8 +42,8 @@ static int pem_init(struct pp_eventmgr *eventmgr)
/* Call initialization event */
result = pem_handle_event(eventmgr, AMD_PP_EVENT_INITIALIZE, &event_data);
- if (0 != result)
- return result;
+ /* if (0 != result)
+ return result; */
/* Register interrupt callback functions */
result = pem_register_interrupts(eventmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index 27db2b7..d9bab85 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -9,7 +9,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
smu7_hwmgr.o smu7_powertune.o smu7_thermal.o \
smu7_clockpowergating.o \
vega10_processpptables.o vega10_hwmgr.o vega10_powertune.o \
- vega10_thermal.o
+ vega10_thermal.o rv_hwmgr.o
AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index ff4ae3d..27fe108 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -115,6 +115,15 @@ int hwmgr_early_init(struct pp_instance *handle)
return -EINVAL;
}
break;
+ case AMDGPU_FAMILY_RV:
+ switch (hwmgr->chip_id) {
+ case CHIP_RAVEN:
+ rv_init_function_pointers(hwmgr);
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index ed6c934..7138cf9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1015,6 +1015,10 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;
hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
+ hwmgr->platform_descriptor.overdriveVDDCStep = 0;
+
+ if (hwmgr->chip_id == CHIP_RAVEN)
+ return 0;
/* We assume here that fw_info is unchanged if this call fails.*/
fw_info = cgs_atom_get_data_table(hwmgr->device,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
new file mode 100644
index 0000000..fe7082a
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -0,0 +1,974 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "pp_debug.h"
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include "atom-types.h"
+#include "atombios.h"
+#include "processpptables.h"
+#include "cgs_common.h"
+#include "smumgr.h"
+#include "hwmgr.h"
+#include "hardwaremanager.h"
+#include "rv_ppsmc.h"
+#include "rv_hwmgr.h"
+#include "power_state.h"
+#include "rv_smumgr.h"
+
+#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5
+#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip
+#define SCLK_MIN_DIV_INTV_SHIFT 12
+#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz
+#define SMC_RAM_END 0x40000
+
+
+static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Cz_Magic;
+
+struct phm_vq_budgeting_record rv_vqtable[] = {
+ /* _TBD
+ * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
+ { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
+};
+
+static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
+{
+ if (PhwRaven_Magic != hw_ps->magic)
+ return NULL;
+
+ return (struct rv_power_state *)hw_ps;
+}
+
+static const struct rv_power_state *cast_const_rv_ps(
+ const struct pp_hw_power_state *hw_ps)
+{
+ if (PhwRaven_Magic != hw_ps->magic)
+ return NULL;
+
+ return (struct rv_power_state *)hw_ps;
+}
+
+static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
+{
+ uint32_t table_size, i;
+ struct phm_vq_budgeting_table *ptable;
+ uint32_t num_entries = (sizeof(rv_vqtable) / sizeof(*rv_vqtable));
+
+ if (hwmgr->dyn_state.vq_budgeting_table != NULL)
+ return 0;
+
+ table_size = sizeof(struct phm_vq_budgeting_table) +
+ sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
+
+ ptable = kzalloc(table_size, GFP_KERNEL);
+ if (NULL == ptable)
+ return -ENOMEM;
+
+ ptable->numEntries = (uint8_t) num_entries;
+
+ for (i = 0; i < ptable->numEntries; i++) {
+ ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
+ ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
+ ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
+ ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
+ ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
+ ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
+ ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
+ ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
+ ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
+ ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
+ }
+
+ hwmgr->dyn_state.vq_budgeting_table = ptable;
+
+ return 0;
+}
+
+static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
+{
+ struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
+ struct cgs_system_info sys_info = {0};
+ int result;
+
+ rv_hwmgr->ddi_power_gating_disabled = 0;
+ rv_hwmgr->bapm_enabled = 1;
+ rv_hwmgr->dce_slow_sclk_threshold = 30000;
+ rv_hwmgr->disable_driver_thermal_policy = 1;
+ rv_hwmgr->thermal_auto_throttling_treshold = 0;
+ rv_hwmgr->is_nb_dpm_enabled = 1;
+ rv_hwmgr->dpm_flags = 1;
+ rv_hwmgr->disable_smu_acp_s3_handshake = 1;
+ rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
+ rv_hwmgr->gfx_off_controled_by_driver = false;
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicM3Arbiter);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDPowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UVDDynamicPowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_VCEPowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SamuPowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ACP);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkDeepSleep);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_GFXDynamicMGPowerGating);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_SclkThrottleLowNotification);
+
+ phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DisableVoltageIsland);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicUVDState);
+
+ sys_info.size = sizeof(struct cgs_system_info);
+ sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
+ result = cgs_query_system_info(hwmgr->device, &sys_info);
+ if (!result) {
+ if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_GFXDynamicMGPowerGating);
+ }
+
+ return 0;
+}
+
+static int rv_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
+ struct phm_clock_and_voltage_limits *table)
+{
+ return 0;
+}
+
+static int rv_init_dynamic_state_adjustment_rule_settings(
+ struct pp_hwmgr *hwmgr)
+{
+ uint32_t table_size =
+ sizeof(struct phm_clock_voltage_dependency_table) +
+ (7 * sizeof(struct phm_clock_voltage_dependency_record));
+
+ struct phm_clock_voltage_dependency_table *table_clk_vlt =
+ kzalloc(table_size, GFP_KERNEL);
+
+ if (NULL == table_clk_vlt) {
+ pr_err("Can not allocate memory!\n");
+ return -ENOMEM;
+ }
+
+ table_clk_vlt->count = 8;
+ table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
+ table_clk_vlt->entries[0].v = 0;
+ table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
+ table_clk_vlt->entries[1].v = 1;
+ table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
+ table_clk_vlt->entries[2].v = 2;
+ table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
+ table_clk_vlt->entries[3].v = 3;
+ table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
+ table_clk_vlt->entries[4].v = 4;
+ table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
+ table_clk_vlt->entries[5].v = 5;
+ table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
+ table_clk_vlt->entries[6].v = 6;
+ table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
+ table_clk_vlt->entries[7].v = 7;
+ hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
+
+ return 0;
+}
+
+static int rv_get_system_info_data(struct pp_hwmgr *hwmgr)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)hwmgr->backend;
+
+ rv_data->sys_info.htc_hyst_lmt = 5;
+ rv_data->sys_info.htc_tmp_lmt = 203;
+
+ if (rv_data->thermal_auto_throttling_treshold == 0)
+ rv_data->thermal_auto_throttling_treshold = 203;
+
+ rv_construct_max_power_limits_table (hwmgr,
+ &hwmgr->dyn_state.max_clock_voltage_on_ac);
+
+ rv_init_dynamic_state_adjustment_rule_settings(hwmgr);
+
+ return 0;
+}
+
+static int rv_construct_boot_state(struct pp_hwmgr *hwmgr)
+{
+ return 0;
+}
+
+static int rv_tf_set_isp_clock_limit(struct pp_hwmgr *hwmgr, void *input,
+ void *output, void *storage, int result)
+{
+ return 0;
+}
+
+static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
+ void *output, void *storage, int result)
+{
+ uint32_t num_of_active_displays = 0;
+ struct cgs_display_info info = {0};
+
+ cgs_get_active_displays_info(hwmgr->device, &info);
+ num_of_active_displays = info.display_count;
+
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_SetDisplayCount,
+ num_of_active_displays);
+ return 0;
+}
+
+static const struct phm_master_table_item rv_set_power_state_list[] = {
+ { NULL, rv_tf_set_isp_clock_limit },
+ { NULL, rv_tf_set_num_active_display },
+ { }
+};
+
+static const struct phm_master_table_header rv_set_power_state_master = {
+ 0,
+ PHM_MasterTableFlag_None,
+ rv_set_power_state_list
+};
+
+static int rv_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
+ void *output, void *storage, int result)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ rv_data->vcn_power_gated = true;
+ rv_data->isp_tileA_power_gated = true;
+ rv_data->isp_tileB_power_gated = true;
+
+ return 0;
+}
+
+static const struct phm_master_table_item rv_setup_asic_list[] = {
+ { .tableFunction = rv_tf_init_power_gate_state },
+ { }
+};
+
+static const struct phm_master_table_header rv_setup_asic_master = {
+ 0,
+ PHM_MasterTableFlag_None,
+ rv_setup_asic_list
+};
+
+static int rv_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
+ void *input, void *output,
+ void *storage, int result)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ rv_data->separation_time = 0;
+ rv_data->cc6_disable = false;
+ rv_data->pstate_disable = false;
+ rv_data->cc6_setting_changed = false;
+
+ return 0;
+}
+
+static const struct phm_master_table_item rv_power_down_asic_list[] = {
+ { .tableFunction = rv_tf_reset_cc6_data },
+ { }
+};
+
+static const struct phm_master_table_header rv_power_down_asic_master = {
+ 0,
+ PHM_MasterTableFlag_None,
+ rv_power_down_asic_list
+};
+
+
+static int rv_tf_disable_gfx_off(struct pp_hwmgr *hwmgr,
+ void *input, void *output,
+ void *storage, int result)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ if (rv_data->gfx_off_controled_by_driver)
+ smum_send_msg_to_smc(hwmgr->smumgr,
+ PPSMC_MSG_DisableGfxOff);
+
+ return 0;
+}
+
+static const struct phm_master_table_item rv_disable_dpm_list[] = {
+ {NULL, rv_tf_disable_gfx_off},
+ { },
+};
+
+
+static const struct phm_master_table_header rv_disable_dpm_master = {
+ 0,
+ PHM_MasterTableFlag_None,
+ rv_disable_dpm_list
+};
+
+static int rv_tf_enable_gfx_off(struct pp_hwmgr *hwmgr,
+ void *input, void *output,
+ void *storage, int result)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+
+ if (rv_data->gfx_off_controled_by_driver)
+ smum_send_msg_to_smc(hwmgr->smumgr,
+ PPSMC_MSG_EnableGfxOff);
+
+ return 0;
+}
+
+static const struct phm_master_table_item rv_enable_dpm_list[] = {
+ {NULL, rv_tf_enable_gfx_off},
+ { },
+};
+
+static const struct phm_master_table_header rv_enable_dpm_master = {
+ 0,
+ PHM_MasterTableFlag_None,
+ rv_enable_dpm_list
+};
+
+static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+ struct pp_power_state *prequest_ps,
+ const struct pp_power_state *pcurrent_ps)
+{
+ return 0;
+}
+
+/* temporary hardcoded clock voltage breakdown tables */
+DpmClock_t VddDcfClk[]= {
+ { 300, 2600},
+ { 600, 3200},
+ { 600, 3600},
+};
+
+DpmClock_t VddSocClk[]= {
+ { 478, 2600},
+ { 722, 3200},
+ { 722, 3600},
+};
+
+DpmClock_t VddFClk[]= {
+ { 400, 2600},
+ {1200, 3200},
+ {1200, 3600},
+};
+
+DpmClock_t VddDispClk[]= {
+ { 435, 2600},
+ { 661, 3200},
+ {1086, 3600},
+};
+
+DpmClock_t VddDppClk[]= {
+ { 435, 2600},
+ { 661, 3200},
+ { 661, 3600},
+};
+
+DpmClock_t VddPhyClk[]= {
+ { 540, 2600},
+ { 810, 3200},
+ { 810, 3600},
+};
+
+static int rv_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
+ struct rv_voltage_dependency_table **pptable,
+ uint32_t num_entry, DpmClock_t *pclk_dependency_table)
+{
+ uint32_t table_size, i;
+ struct rv_voltage_dependency_table *ptable;
+
+ table_size = sizeof(uint32_t) + sizeof(struct rv_voltage_dependency_table) * num_entry;
+ ptable = kzalloc(table_size, GFP_KERNEL);
+
+ if (NULL == ptable)
+ return -ENOMEM;
+
+ ptable->count = num_entry;
+
+ for (i = 0; i < ptable->count; i++) {
+ ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
+ ptable->entries[i].vol = pclk_dependency_table->Vol;
+ pclk_dependency_table++;
+ }
+
+ *pptable = ptable;
+
+ return 0;
+}
+
+
+static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
+{
+ int result;
+
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ DpmClocks_t *table = &(rv_data->clock_table);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+
+ result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE);
+
+ PP_ASSERT_WITH_CODE((0 == result),
+ "Attempt to copy clock table from smc failed",
+ return result);
+
+ if (0 == result && table->DcefClocks[0].Freq != 0) {
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
+ NUM_DCEFCLK_DPM_LEVELS,
+ &rv_data->clock_table.DcefClocks[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
+ NUM_SOCCLK_DPM_LEVELS,
+ &rv_data->clock_table.SocClocks[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
+ NUM_FCLK_DPM_LEVELS,
+ &rv_data->clock_table.FClocks[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
+ NUM_MEMCLK_DPM_LEVELS,
+ &rv_data->clock_table.MemClocks[0]);
+ } else {
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
+ sizeof(VddDcfClk)/sizeof(*VddDcfClk), &VddDcfClk[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
+ sizeof(VddSocClk)/sizeof(*VddSocClk), &VddSocClk[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
+ sizeof(VddFClk)/sizeof(*VddFClk), &VddFClk[0]);
+ }
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
+ sizeof(VddDispClk)/sizeof(*VddDispClk), &VddDispClk[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
+ sizeof(VddDppClk)/sizeof(*VddDppClk), &VddDppClk[0]);
+ rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
+ sizeof(VddPhyClk)/sizeof(*VddPhyClk), &VddPhyClk[0]);
+
+ return 0;
+}
+
+static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
+{
+ int result = 0;
+ struct rv_hwmgr *data;
+
+ data = kzalloc(sizeof(struct rv_hwmgr), GFP_KERNEL);
+ if (data == NULL)
+ return -ENOMEM;
+
+ hwmgr->backend = data;
+
+ result = rv_initialize_dpm_defaults(hwmgr);
+ if (result != 0) {
+ pr_err("rv_initialize_dpm_defaults failed\n");
+ return result;
+ }
+
+ rv_populate_clock_table(hwmgr);
+
+ result = rv_get_system_info_data(hwmgr);
+ if (result != 0) {
+ pr_err("rv_get_system_info_data failed\n");
+ return result;
+ }
+
+ rv_construct_boot_state(hwmgr);
+
+ result = phm_construct_table(hwmgr, &rv_setup_asic_master,
+ &(hwmgr->setup_asic));
+ if (result != 0) {
+ pr_err("Fail to construct setup ASIC\n");
+ return result;
+ }
+
+ result = phm_construct_table(hwmgr, &rv_power_down_asic_master,
+ &(hwmgr->power_down_asic));
+ if (result != 0) {
+ pr_err("Fail to construct power down ASIC\n");
+ return result;
+ }
+
+ result = phm_construct_table(hwmgr, &rv_set_power_state_master,
+ &(hwmgr->set_power_state));
+ if (result != 0) {
+ pr_err("Fail to construct set_power_state\n");
+ return result;
+ }
+
+ result = phm_construct_table(hwmgr, &rv_disable_dpm_master,
+ &(hwmgr->disable_dynamic_state_management));
+ if (result != 0) {
+ pr_err("Fail to disable_dynamic_state\n");
+ return result;
+ }
+ result = phm_construct_table(hwmgr, &rv_enable_dpm_master,
+ &(hwmgr->enable_dynamic_state_management));
+ if (result != 0) {
+ pr_err("Fail to enable_dynamic_state\n");
+ return result;
+ }
+
+ hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
+ RAVEN_MAX_HARDWARE_POWERLEVELS;
+
+ hwmgr->platform_descriptor.hardwarePerformanceLevels =
+ RAVEN_MAX_HARDWARE_POWERLEVELS;
+
+ hwmgr->platform_descriptor.vbiosInterruptId = 0;
+
+ hwmgr->platform_descriptor.clockStep.engineClock = 500;
+
+ hwmgr->platform_descriptor.clockStep.memoryClock = 500;
+
+ hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
+
+ rv_init_vq_budget_table(hwmgr);
+ return result;
+}
+
+static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+
+ phm_destroy_table(hwmgr, &(hwmgr->set_power_state));
+ phm_destroy_table(hwmgr, &(hwmgr->enable_dynamic_state_management));
+ phm_destroy_table(hwmgr, &(hwmgr->disable_dynamic_state_management));
+ phm_destroy_table(hwmgr, &(hwmgr->power_down_asic));
+ phm_destroy_table(hwmgr, &(hwmgr->setup_asic));
+
+ if (pinfo->vdd_dep_on_dcefclk) {
+ kfree(pinfo->vdd_dep_on_dcefclk);
+ pinfo->vdd_dep_on_dcefclk = NULL;
+ }
+ if (pinfo->vdd_dep_on_socclk) {
+ kfree(pinfo->vdd_dep_on_socclk);
+ pinfo->vdd_dep_on_socclk = NULL;
+ }
+ if (pinfo->vdd_dep_on_fclk) {
+ kfree(pinfo->vdd_dep_on_fclk);
+ pinfo->vdd_dep_on_fclk = NULL;
+ }
+ if (pinfo->vdd_dep_on_dispclk) {
+ kfree(pinfo->vdd_dep_on_dispclk);
+ pinfo->vdd_dep_on_dispclk = NULL;
+ }
+ if (pinfo->vdd_dep_on_dppclk) {
+ kfree(pinfo->vdd_dep_on_dppclk);
+ pinfo->vdd_dep_on_dppclk = NULL;
+ }
+ if (pinfo->vdd_dep_on_phyclk) {
+ kfree(pinfo->vdd_dep_on_phyclk);
+ pinfo->vdd_dep_on_phyclk = NULL;
+ }
+
+ kfree(hwmgr->backend);
+ hwmgr->backend = NULL;
+
+ return 0;
+}
+
+static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
+ enum amd_dpm_forced_level level)
+{
+ return 0;
+}
+
+static int rv_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
+{
+ return 0;
+}
+
+static int rv_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
+{
+ return 0;
+}
+
+static int rv_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
+ struct pp_hw_power_state *hw_ps)
+{
+ return 0;
+}
+
+static int rv_dpm_get_pp_table_entry_callback(
+ struct pp_hwmgr *hwmgr,
+ struct pp_hw_power_state *hw_ps,
+ unsigned int index,
+ const void *clock_info)
+{
+ struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
+
+ const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info;
+
+ struct phm_clock_voltage_dependency_table *table =
+ hwmgr->dyn_state.vddc_dependency_on_sclk;
+ uint8_t clock_info_index = rv_clock_info->index;
+
+ if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
+ clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
+
+ rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk;
+ rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v;
+
+ rv_ps->level = index + 1;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+ rv_ps->levels[index].ds_divider_index = 5;
+ rv_ps->levels[index].ss_divider_index = 5;
+ }
+
+ return 0;
+}
+
+static int rv_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
+{
+ int result;
+ unsigned long ret = 0;
+
+ result = pp_tables_get_num_of_entries(hwmgr, &ret);
+
+ return result ? 0 : ret;
+}
+
+static int rv_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
+ unsigned long entry, struct pp_power_state *ps)
+{
+ int result;
+ struct rv_power_state *rv_ps;
+
+ ps->hardware.magic = PhwRaven_Magic;
+
+ rv_ps = cast_rv_ps(&(ps->hardware));
+
+ result = pp_tables_get_entry(hwmgr, entry, ps,
+ rv_dpm_get_pp_table_entry_callback);
+
+ rv_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
+ rv_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
+
+ return result;
+}
+
+static int rv_get_power_state_size(struct pp_hwmgr *hwmgr)
+{
+ return sizeof(struct rv_power_state);
+}
+
+static int rv_set_cpu_power_state(struct pp_hwmgr *hwmgr)
+{
+ return 0;
+}
+
+
+static int rv_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
+ bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
+{
+ return 0;
+}
+
+static int rv_get_dal_power_level(struct pp_hwmgr *hwmgr,
+ struct amd_pp_simple_clock_info *info)
+{
+ return -EINVAL;
+}
+
+static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
+ enum pp_clock_type type, uint32_t mask)
+{
+ return 0;
+}
+
+static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
+ enum pp_clock_type type, char *buf)
+{
+ return 0;
+}
+
+static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
+ PHM_PerformanceLevelDesignation designation, uint32_t index,
+ PHM_PerformanceLevel *level)
+{
+ const struct rv_power_state *ps;
+ struct rv_hwmgr *data;
+ uint32_t level_index;
+ uint32_t i;
+
+ if (level == NULL || hwmgr == NULL || state == NULL)
+ return -EINVAL;
+
+ data = (struct rv_hwmgr *)(hwmgr->backend);
+ ps = cast_const_rv_ps(state);
+
+ level_index = index > ps->level - 1 ? ps->level - 1 : index;
+ level->coreClock = ps->levels[level_index].engine_clock;
+
+ if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
+ for (i = 1; i < ps->level; i++) {
+ if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
+ level->coreClock = ps->levels[i].engine_clock;
+ break;
+ }
+ }
+ }
+
+ level->nonLocalMemoryFreq = 0;
+ level->nonLocalMemoryWidth = 0;
+
+ return 0;
+}
+
+static int rv_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
+ const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
+{
+ const struct rv_power_state *ps = cast_const_rv_ps(state);
+
+ clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
+ clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
+
+ return 0;
+}
+
+#define MEM_FREQ_LOW_LATENCY 25000
+#define MEM_FREQ_HIGH_LATENCY 80000
+#define MEM_LATENCY_HIGH 245
+#define MEM_LATENCY_LOW 35
+#define MEM_LATENCY_ERR 0xFFFF
+
+
+static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr,
+ uint32_t clock)
+{
+ if (clock >= MEM_FREQ_LOW_LATENCY &&
+ clock < MEM_FREQ_HIGH_LATENCY)
+ return MEM_LATENCY_HIGH;
+ else if (clock >= MEM_FREQ_HIGH_LATENCY)
+ return MEM_LATENCY_LOW;
+ else
+ return MEM_LATENCY_ERR;
+}
+
+static void rv_get_memclocks(struct pp_hwmgr *hwmgr,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct rv_voltage_dependency_table *pmclk_table;
+ uint32_t i;
+
+ pmclk_table = pinfo->vdd_dep_on_mclk;
+ clocks->num_levels = 0;
+
+ for (i = 0; i < pmclk_table->count; i++) {
+ if (pmclk_table->entries[i].clk) {
+ clocks->data[clocks->num_levels].clocks_in_khz =
+ pmclk_table->entries[i].clk;
+ clocks->data[clocks->num_levels].latency_in_us =
+ rv_get_mem_latency(hwmgr,
+ pmclk_table->entries[i].clk);
+ clocks->num_levels++;
+ }
+ }
+}
+
+static void rv_get_dcefclocks(struct pp_hwmgr *hwmgr,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct rv_voltage_dependency_table *pdcef_table;
+ uint32_t i;
+
+ pdcef_table = pinfo->vdd_dep_on_dcefclk;
+ for (i = 0; i < pdcef_table->count; i++) {
+ clocks->data[i].clocks_in_khz = pdcef_table->entries[i].clk;
+ clocks->data[i].latency_in_us = 0;
+ }
+ clocks->num_levels = pdcef_table->count;
+}
+
+static void rv_get_socclocks(struct pp_hwmgr *hwmgr,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct rv_voltage_dependency_table *psoc_table;
+ uint32_t i;
+
+ psoc_table = pinfo->vdd_dep_on_socclk;
+
+ for (i = 0; i < psoc_table->count; i++) {
+ clocks->data[i].clocks_in_khz = psoc_table->entries[i].clk;
+ clocks->data[i].latency_in_us = 0;
+ }
+ clocks->num_levels = psoc_table->count;
+}
+
+static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_latency *clocks)
+{
+ switch (type) {
+ case amd_pp_mem_clock:
+ rv_get_memclocks(hwmgr, clocks);
+ break;
+ case amd_pp_dcef_clock:
+ rv_get_dcefclocks(hwmgr, clocks);
+ break;
+ case amd_pp_soc_clock:
+ rv_get_socclocks(hwmgr, clocks);
+ break;
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+ enum amd_pp_clock_type type,
+ struct pp_clock_levels_with_voltage *clocks)
+{
+ uint32_t i;
+ struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
+ struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
+ struct rv_voltage_dependency_table *pclk_vol_table;
+
+ switch (type) {
+ case amd_pp_mem_clock:
+ pclk_vol_table = pinfo->vdd_dep_on_mclk;
+ break;
+ case amd_pp_dcef_clock:
+ pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
+ break;
+ case amd_pp_disp_clock:
+ pclk_vol_table = pinfo->vdd_dep_on_dispclk;
+ break;
+ case amd_pp_phy_clock:
+ pclk_vol_table = pinfo->vdd_dep_on_phyclk;
+ break;
+ case amd_pp_dpp_clock:
+ pclk_vol_table = pinfo->vdd_dep_on_dppclk;
+ default:
+ return -EINVAL;
+ }
+
+ if (pclk_vol_table->count == 0)
+ return -EINVAL;
+
+ for (i = 0; i < pclk_vol_table->count; i++) {
+ clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
+ clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
+ clocks->num_levels++;
+ }
+
+ clocks->num_levels = pclk_vol_table->count;
+
+ return 0;
+}
+
+int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+ struct pp_display_clock_request *clock_req)
+{
+ int result = 0;
+ enum amd_pp_clock_type clk_type = clock_req->clock_type;
+ uint32_t clk_freq = clock_req->clock_freq_in_khz / 100;
+ PPSMC_Msg msg;
+
+ switch (clk_type) {
+ case amd_pp_dcef_clock:
+ msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
+ break;
+ case amd_pp_soc_clock:
+ msg = PPSMC_MSG_SetHardMinSocclkByFreq;
+ break;
+ case amd_pp_mem_clock:
+ msg = PPSMC_MSG_SetHardMinFclkByFreq;
+ break;
+ default:
+ pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
+ return -EINVAL;
+ }
+
+ result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg,
+ clk_freq);
+
+ return result;
+}
+
+static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
+{
+ return -EINVAL;
+}
+
+static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+ void *value, int *size)
+{
+ return -EINVAL;
+}
+
+static const struct pp_hwmgr_func rv_hwmgr_funcs = {
+ .backend_init = rv_hwmgr_backend_init,
+ .backend_fini = rv_hwmgr_backend_fini,
+ .asic_setup = NULL,
+ .apply_state_adjust_rules = rv_apply_state_adjust_rules,
+ .force_dpm_level = rv_dpm_force_dpm_level,
+ .get_power_state_size = rv_get_power_state_size,
+ .powerdown_uvd = NULL,
+ .powergate_uvd = NULL,
+ .powergate_vce = NULL,
+ .get_mclk = rv_dpm_get_mclk,
+ .get_sclk = rv_dpm_get_sclk,
+ .patch_boot_state = rv_dpm_patch_boot_state,
+ .get_pp_table_entry = rv_dpm_get_pp_table_entry,
+ .get_num_of_pp_table_entries = rv_dpm_get_num_of_pp_table_entries,
+ .set_cpu_power_state = rv_set_cpu_power_state,
+ .store_cc6_data = rv_store_cc6_data,
+ .force_clock_level = rv_force_clock_level,
+ .print_clock_levels = rv_print_clock_levels,
+ .get_dal_power_level = rv_get_dal_power_level,
+ .get_performance_level = rv_get_performance_level,
+ .get_current_shallow_sleep_clocks = rv_get_current_shallow_sleep_clocks,
+ .get_clock_by_type_with_latency = rv_get_clock_by_type_with_latency,
+ .get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
+ .get_max_high_clocks = rv_get_max_high_clocks,
+ .read_sensor = rv_read_sensor,
+};
+
+int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
+{
+ hwmgr->hwmgr_func = &rv_hwmgr_funcs;
+ hwmgr->pptable_func = &pptable_funcs;
+ return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
new file mode 100644
index 0000000..6733691
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RAVEN_HWMGR_H
+#define RAVEN_HWMGR_H
+
+#include "hwmgr.h"
+#include "rv_inc.h"
+#include "smu10_driver_if.h"
+#include "rv_ppsmc.h"
+
+
+#define RAVEN_MAX_HARDWARE_POWERLEVELS 8
+#define PHMRAVEN_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
+
+#define DPMFlags_SCLK_Enabled 0x00000001
+#define DPMFlags_UVD_Enabled 0x00000002
+#define DPMFlags_VCE_Enabled 0x00000004
+#define DPMFlags_ACP_Enabled 0x00000008
+#define DPMFlags_ForceHighestValid 0x40000000
+
+/* Do not change the following, it is also defined in SMU8.h */
+#define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001
+#define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000
+#define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x01000000
+#define SMU_EnabledFeatureScoreboard_VceDpmOn 0x02000000
+
+#define SMU_PHYID_SHIFT 8
+
+#define RAVEN_PCIE_POWERGATING_TARGET_GFX 0
+#define RAVEN_PCIE_POWERGATING_TARGET_DDI 1
+#define RAVEN_PCIE_POWERGATING_TARGET_PLLCASCADE 2
+#define RAVEN_PCIE_POWERGATING_TARGET_PHY 3
+
+enum VQ_TYPE {
+ CLOCK_TYPE_DCLK = 0L,
+ CLOCK_TYPE_ECLK,
+ CLOCK_TYPE_SCLK,
+ CLOCK_TYPE_CCLK,
+ VQ_GFX_CU
+};
+
+#define SUSTAINABLE_SCLK_MASK 0x00ffffff
+#define SUSTAINABLE_SCLK_SHIFT 0
+#define SUSTAINABLE_CU_MASK 0xff000000
+#define SUSTAINABLE_CU_SHIFT 24
+
+struct rv_dpm_entry {
+ uint32_t soft_min_clk;
+ uint32_t hard_min_clk;
+ uint32_t soft_max_clk;
+ uint32_t hard_max_clk;
+};
+
+struct rv_power_level {
+ uint32_t engine_clock;
+ uint8_t vddc_index;
+ uint8_t ds_divider_index;
+ uint8_t ss_divider_index;
+ uint8_t allow_gnb_slow;
+ uint8_t force_nbp_state;
+ uint8_t display_wm;
+ uint8_t vce_wm;
+ uint8_t num_simd_to_powerdown;
+ uint8_t hysteresis_up;
+ uint8_t rsv[3];
+};
+
+/*used for the nbpsFlags field in rv_power state*/
+#define RAVEN_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
+#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
+#define RAVEN_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
+
+#define RAVEN_POWERSTATE_FLAGS_BAPM_DISABLE (1<<0)
+
+struct rv_uvd_clocks {
+ uint32_t vclk;
+ uint32_t dclk;
+ uint32_t vclk_low_divider;
+ uint32_t vclk_high_divider;
+ uint32_t dclk_low_divider;
+ uint32_t dclk_high_divider;
+};
+
+struct pp_disable_nbpslo_flags {
+ union {
+ struct {
+ uint32_t entry : 1;
+ uint32_t display : 1;
+ uint32_t driver: 1;
+ uint32_t vce : 1;
+ uint32_t uvd : 1;
+ uint32_t acp : 1;
+ uint32_t reserved: 26;
+ } bits;
+ uint32_t u32All;
+ };
+};
+
+
+enum rv_pstate_previous_action {
+ DO_NOTHING = 1,
+ FORCE_HIGH,
+ CANCEL_FORCE_HIGH
+};
+
+struct rv_power_state {
+ unsigned int magic;
+ uint32_t level;
+ struct rv_uvd_clocks uvd_clocks;
+ uint32_t evclk;
+ uint32_t ecclk;
+ uint32_t samclk;
+ uint32_t acpclk;
+ bool need_dfs_bypass;
+
+ uint32_t nbps_flags;
+ uint32_t bapm_flags;
+ uint8_t dpm0_pg_nbps_low;
+ uint8_t dpm0_pg_nbps_high;
+ uint8_t dpm_x_nbps_low;
+ uint8_t dpm_x_nbps_high;
+
+ enum rv_pstate_previous_action action;
+
+ struct rv_power_level levels[RAVEN_MAX_HARDWARE_POWERLEVELS];
+ struct pp_disable_nbpslo_flags nbpslo_flags;
+};
+
+#define RAVEN_NUM_NBPSTATES 4
+#define RAVEN_NUM_NBPMEMORYCLOCK 2
+
+
+struct rv_display_phy_info_entry {
+ uint8_t phy_present;
+ uint8_t active_lane_mapping;
+ uint8_t display_config_type;
+ uint8_t active_num_of_lanes;
+};
+
+#define RAVEN_MAX_DISPLAYPHY_IDS 10
+
+struct rv_display_phy_info {
+ bool display_phy_access_initialized;
+ struct rv_display_phy_info_entry entries[RAVEN_MAX_DISPLAYPHY_IDS];
+};
+
+#define MAX_DISPLAY_CLOCK_LEVEL 8
+
+struct rv_system_info{
+ uint8_t htc_tmp_lmt;
+ uint8_t htc_hyst_lmt;
+};
+
+#define MAX_REGULAR_DPM_NUMBER 8
+
+struct rv_mclk_latency_entries {
+ uint32_t frequency;
+ uint32_t latency;
+};
+
+struct rv_mclk_latency_table {
+ uint32_t count;
+ struct rv_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct rv_clock_voltage_dependency_record {
+ uint32_t clk;
+ uint32_t vol;
+};
+
+
+struct rv_voltage_dependency_table {
+ uint32_t count;
+ struct rv_clock_voltage_dependency_record entries[1];
+};
+
+struct rv_clock_voltage_information {
+ struct rv_voltage_dependency_table *vdd_dep_on_dcefclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_socclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_fclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_mclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_dispclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_dppclk;
+ struct rv_voltage_dependency_table *vdd_dep_on_phyclk;
+};
+
+struct rv_hwmgr {
+ uint32_t disable_driver_thermal_policy;
+ uint32_t thermal_auto_throttling_treshold;
+ struct rv_system_info sys_info;
+ struct rv_mclk_latency_table mclk_latency_table;
+
+ uint32_t ddi_power_gating_disabled;
+
+ struct rv_display_phy_info_entry display_phy_info;
+ uint32_t dce_slow_sclk_threshold;
+
+ bool disp_clk_bypass;
+ bool disp_clk_bypass_pending;
+ uint32_t bapm_enabled;
+
+ bool video_start;
+ bool battery_state;
+
+ uint32_t is_nb_dpm_enabled;
+ uint32_t is_voltage_island_enabled;
+ uint32_t disable_smu_acp_s3_handshake;
+ uint32_t disable_notify_smu_vpu_recovery;
+ bool in_vpu_recovery;
+ bool pg_acp_init;
+ uint8_t disp_config;
+
+ /* PowerTune */
+ uint32_t power_containment_features;
+ bool cac_enabled;
+ bool disable_uvd_power_tune_feature;
+ bool enable_bapm_feature;
+ bool enable_tdc_limit_feature;
+
+
+ /* SMC SRAM Address of firmware header tables */
+ uint32_t sram_end;
+ uint32_t dpm_table_start;
+ uint32_t soft_regs_start;
+
+ /* start of SMU7_Fusion_DpmTable */
+
+ uint8_t uvd_level_count;
+ uint8_t vce_level_count;
+ uint8_t acp_level_count;
+ uint8_t samu_level_count;
+
+ uint32_t fps_high_threshold;
+ uint32_t fps_low_threshold;
+
+ uint32_t dpm_flags;
+ struct rv_dpm_entry sclk_dpm;
+ struct rv_dpm_entry uvd_dpm;
+ struct rv_dpm_entry vce_dpm;
+ struct rv_dpm_entry acp_dpm;
+ bool acp_power_up_no_dsp;
+
+ uint32_t max_sclk_level;
+ uint32_t num_of_clk_entries;
+
+ /* CPU Power State */
+ uint32_t separation_time;
+ bool cc6_disable;
+ bool pstate_disable;
+ bool cc6_setting_changed;
+
+ uint32_t ulTotalActiveCUs;
+
+ bool isp_tileA_power_gated;
+ bool isp_tileB_power_gated;
+ uint32_t isp_actual_hard_min_freq;
+ uint32_t soc_actual_hard_min_freq;
+
+ bool vcn_power_gated;
+ bool vcn_dpg_mode;
+
+ bool gfx_off_controled_by_driver;
+ Watermarks_t water_marks_table;
+ struct rv_clock_voltage_information clock_vol_info;
+ DpmClocks_t clock_table;
+
+ uint32_t active_process_mask;
+};
+
+struct pp_hwmgr;
+
+int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
+
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 4e39f35..a62948b8 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -273,7 +273,8 @@ enum amd_pp_clock_type {
amd_pp_dcef_clock,
amd_pp_soc_clock,
amd_pp_pixel_clock,
- amd_pp_phy_clock
+ amd_pp_phy_clock,
+ amd_pp_dpp_clock
};
#define MAX_NUM_CLOCKS 16
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 19187a9..e5c3d28 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -609,17 +609,6 @@ struct phm_ppt_v2_information {
uint8_t uc_dcef_dpm_voltage_mode;
};
-struct phm_ppt_v3_information {
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
- struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
-};
-
-
struct phm_dynamic_state_info {
struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
@@ -635,7 +624,7 @@ struct phm_dynamic_state_info {
uint32_t vddc_vddci_delta;
uint32_t min_vddc_for_pcie_gen2;
struct phm_cac_leakage_table *cac_leakage_table;
- struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
+ struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
struct phm_vce_clock_voltage_dependency_table
*vce_clock_voltage_dependency_table;
@@ -648,8 +637,8 @@ struct phm_dynamic_state_info {
struct phm_ppm_table *ppm_parameter_table;
struct phm_cac_tdp_table *cac_dtp_table;
- struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
- struct phm_vq_budgeting_table *vq_budgeting_table;
+ struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
+ struct phm_vq_budgeting_table *vq_budgeting_table;
};
struct pp_fan_info {
@@ -832,6 +821,7 @@ extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
uint32_t sclk, uint16_t id, uint16_t *voltage);
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 105/117] drm/amd/powerplay/rv: power up/down sdma via the SMU
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (95 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 104/117] drm/amd/powerplay: add raven support in hwmgr. (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 106/117] drm/amdgpu/raven: power up/down VCN via the SMU (v2) Alex Deucher
` (12 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
sdma is powered down by default in vbios,
need to power up in driver init. Power it down
again on driver tear down.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index 6b6b755..6c931ba 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -243,6 +243,26 @@ static int rv_verify_smc_interface(struct pp_smumgr *smumgr)
return 0;
}
+/* sdma is disabled by default in vbios, need to re-enable in driver */
+static int rv_smc_enable_sdma(struct pp_smumgr *smumgr)
+{
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PPSMC_MSG_PowerUpSdma),
+ "Attempt to power up sdma Failed!",
+ return -EINVAL);
+
+ return 0;
+}
+
+static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
+{
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc(smumgr,
+ PPSMC_MSG_PowerDownSdma),
+ "Attempt to power down sdma Failed!",
+ return -EINVAL);
+
+ return 0;
+}
static int rv_smu_fini(struct pp_smumgr *smumgr)
{
@@ -250,6 +270,7 @@ static int rv_smu_fini(struct pp_smumgr *smumgr)
(struct rv_smumgr *)(smumgr->backend);
if (priv) {
+ rv_smc_disable_sdma(smumgr);
cgs_free_gpu_mem(smumgr->device,
priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device,
@@ -265,6 +286,8 @@ static int rv_start_smu(struct pp_smumgr *smumgr)
{
if (rv_verify_smc_interface(smumgr))
return -EINVAL;
+ if (rv_smc_enable_sdma(smumgr))
+ return -EINVAL;
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 106/117] drm/amdgpu/raven: power up/down VCN via the SMU (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (96 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 105/117] drm/amd/powerplay/rv: power up/down sdma via the SMU Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 107/117] drm/amdgpu/powerplay/raven: add smu block and enable powerplay Alex Deucher
` (11 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Huang Rui
By default VCN is powered down like SDMA, power it up/down
on driver load/unload.
[Rui: Fix to add the parameter 0 to un-gate VCN] v2
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index 6c931ba..b69dcb9 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -264,6 +264,27 @@ static int rv_smc_disable_sdma(struct pp_smumgr *smumgr)
return 0;
}
+/* vcn is disabled by default in vbios, need to re-enable in driver */
+static int rv_smc_enable_vcn(struct pp_smumgr *smumgr)
+{
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_PowerUpVcn, 0),
+ "Attempt to power up vcn Failed!",
+ return -EINVAL);
+
+ return 0;
+}
+
+static int rv_smc_disable_vcn(struct pp_smumgr *smumgr)
+{
+ PP_ASSERT_WITH_CODE(!rv_send_msg_to_smc_with_parameter(smumgr,
+ PPSMC_MSG_PowerDownVcn, 0),
+ "Attempt to power down vcn Failed!",
+ return -EINVAL);
+
+ return 0;
+}
+
static int rv_smu_fini(struct pp_smumgr *smumgr)
{
struct rv_smumgr *priv =
@@ -271,6 +292,7 @@ static int rv_smu_fini(struct pp_smumgr *smumgr)
if (priv) {
rv_smc_disable_sdma(smumgr);
+ rv_smc_disable_vcn(smumgr);
cgs_free_gpu_mem(smumgr->device,
priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device,
@@ -288,6 +310,8 @@ static int rv_start_smu(struct pp_smumgr *smumgr)
return -EINVAL;
if (rv_smc_enable_sdma(smumgr))
return -EINVAL;
+ if (rv_smc_enable_vcn(smumgr))
+ return -EINVAL;
return 0;
}
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 107/117] drm/amdgpu/powerplay/raven: add smu block and enable powerplay
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (97 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 106/117] drm/amdgpu/raven: power up/down VCN via the SMU (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 108/117] drm/amd: Add DCN ivsrcids (v2) Alex Deucher
` (10 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add the ip block and enable powerplay on raven.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index f5ae871..72c03c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -72,6 +72,7 @@ static int amdgpu_pp_early_init(void *handle)
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_VEGA10:
+ case CHIP_RAVEN:
adev->pp_enabled = true;
if (amdgpu_create_pp_handle(adev))
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index d6fa8dc..3b7f449 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -512,6 +512,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
amdgpu_ip_block_add(adev, &psp_v10_0_ip_block);
+ amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
#if defined(CONFIG_DRM_AMD_DC)
if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block);
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 108/117] drm/amd: Add DCN ivsrcids (v2)
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (98 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 107/117] drm/amdgpu/powerplay/raven: add smu block and enable powerplay Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 109/117] drm/amdgpu/display: Add calcs code for DCN Alex Deucher
` (9 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
v2: squash in some updates (Alex)
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 ++++++++++++++++++++
1 file changed, 1134 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
new file mode 100644
index 0000000..ac9fa3a
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
@@ -0,0 +1,1134 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __IRQSRCS_DCN_1_0_H__
+#define __IRQSRCS_DCN_1_0_H__
+
+
+#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_I2C_SW_DONE 0
+
+#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1
+
+#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2
+
+#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3
+
+#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4
+
+#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5
+
+#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6
+
+#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7
+
+#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8
+
+#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9
+
+#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10
+
+#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11
+
+#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12
+
+#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13
+
+#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14
+
+#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15
+
+#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse
+#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7
+
+#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level
+#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8
+
+#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse
+#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7
+
+#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level
+#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8
+
+#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse
+#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7
+
+#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level
+#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8
+
+#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12
+
+#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13
+
+#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DMCU_SCP_INT 14
+
+#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0
+
+#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1
+
+#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2
+
+#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3
+
+#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4
+
+#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5
+
+#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse
+#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6
+
+#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level
+#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7
+
+#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
+#define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5
+
+#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6
+
+#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7
+
+#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_HPD1_INT 0
+
+#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_HPD2_INT 1
+
+#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_HPD3_INT 2
+
+#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_HPD4_INT 3
+
+#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_HPD5_INT 4
+
+#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_HPD6_INT 5
+
+#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_HPD1_RX_INT 6
+
+#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_HPD2_RX_INT 7
+
+#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_HPD3_RX_INT 8
+
+#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_HPD4_RX_INT 9
+
+#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_HPD5_RX_INT 10
+
+#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_HPD6_RX_INT 11
+
+#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6
+
+#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse
+#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7
+
+#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0
+
+#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1
+
+#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2
+
+#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3
+
+#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4
+
+#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5
+
+#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0
+
+#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1
+
+#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2
+
+#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3
+
+#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4
+
+#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5
+
+#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level
+#define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6
+
+#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7
+
+#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0
+
+#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1
+
+#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2
+
+#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3
+
+#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4
+
+#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5
+
+#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level
+#define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6
+
+#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
+#define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7
+
+#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0
+
+#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1
+
+#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2
+
+#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3
+
+#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4
+
+#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5
+
+#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6
+
+#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7
+
+#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8
+
+#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9
+
+#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10
+
+#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level
+#define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11
+
+#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__VGA_CRT_INT 12
+
+#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0
+
+#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1
+
+#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2
+
+#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3
+
+#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4
+
+#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5
+
+#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level
+#define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6
+
+#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level
+#define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7
+
+#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0
+
+#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1
+
+#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2
+
+#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3
+
+#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4
+
+#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level
+#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5
+
+#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0
+
+#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1
+
+#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2
+
+#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3
+
+#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4
+
+#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5
+
+#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6
+
+#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7
+
+#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8
+
+#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9
+
+#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10
+
+#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11
+
+#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12
+
+#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13
+
+#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14
+
+#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4
+
+#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level
+#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5
+
+#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level
+#define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6
+
+#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level
+#define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7
+
+#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level
+#define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8
+
+#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level
+#define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9
+
+#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10
+
+#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level
+#define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11
+
+#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0
+
+#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1
+
+#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2
+
+#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3
+
+#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4
+
+#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5
+
+#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6
+
+#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7
+
+#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0
+
+#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1
+
+#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2
+
+#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3
+
+#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4
+
+#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5
+
+#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6
+
+#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7
+
+#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8
+
+#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9
+
+#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10
+
+#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11
+
+#define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+
+#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_VBLANK 0
+
+#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_VLINE1 1
+
+#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse
+#define DCN_1_0__CTXID__DC_D1_VLINE2 2
+
+#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_VBLANK 3
+
+#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_VLINE1 4
+
+#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__DC_D2_VLINE2 5
+
+#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6
+
+#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level
+#define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7
+
+#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level
+#define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8
+
+#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9
+
+#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10
+
+#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11
+
+#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12
+
+#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13
+
+#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse
+#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level
+#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_VBLANK 9
+
+#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_VLINE1 10
+
+#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__DC_D3_VLINE2 11
+
+#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_VBLANK 12
+
+#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_VLINE1 13
+
+#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D4_VLINE2 14
+
+#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse
+#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level
+#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_VBLANK 9
+
+#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_VLINE1 10
+
+#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D5_VLINE2 11
+
+#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_VBLANK 12
+
+#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_VLINE1 13
+
+#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_VLINE2 14
+
+#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse
+#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level
+#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D7_VBLANK 9
+
+#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D7_VLINE1 10
+
+#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D7_VLINE2 11
+
+#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D8_VBLANK 12
+
+#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D8_VLINE1 13
+
+#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__DC_D8_VLINE2 14
+
+#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse
+#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level
+#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse
+#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level
+#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse
+#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level
+#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse
+#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level
+#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse
+#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level
+#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse
+#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level
+#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level
+#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse
+#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level
+#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level
+#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level
+#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse
+#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level
+#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse
+#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level
+#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse
+#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level
+#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse
+#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level
+#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse
+#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level
+#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level
+#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0
+
+#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1
+
+#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2
+
+#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3
+
+#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4
+
+#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5
+
+#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6
+
+#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7
+
+#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8
+
+#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9
+
+#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10
+
+#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11
+
+#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+#define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12
+
+#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level
+#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level
+#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse
+#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0
+
+#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level
+#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1
+
+#define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+
+#define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+#define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse
+
+#define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse
+#define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse
+#define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse
+#define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse
+#define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse
+#define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse
+
+#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0
+
+#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1
+
+#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2
+
+#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3
+
+#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4
+
+#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5
+
+#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6
+
+#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7
+
+#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8
+
+#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9
+
+#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10
+
+#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11
+
+#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12
+
+#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13
+
+#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14
+
+#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level
+#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15
+
+#define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+
+#define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+#define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+#define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+#define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+#define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+#define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse
+
+#define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse
+
+
+#endif // __IRQSRCS_DCN_1_0_H__
--
2.5.5
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 109/117] drm/amdgpu/display: Add calcs code for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (99 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 108/117] drm/amd: Add DCN ivsrcids (v2) Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 110/117] drm/amdgpu/display: Add core dc support " Alex Deucher
` (8 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
Bandwidth and scaling calculations for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 ++++++++++++++++++++
.../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
.../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 ++++++++
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 ++++
6 files changed, 5805 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
new file mode 100644
index 0000000..21b83e4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -0,0 +1,3629 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn_calc_auto.h"
+#include "dcn_calc_math.h"
+
+/*REVISION#247*/
+void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
+{
+ int k;
+ /*scaler settings calculation*/
+
+ /*scale ratio calculation*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->allow_different_hratio_vratio == dcn_bw_yes) {
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
+ v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
+ } else {
+ v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
+ v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
+ }
+ } else {
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->h_ratio[k] = dcn_bw_max2(
+ v->viewport_width[k] / v->scaler_rec_out_width[k],
+ v->viewport_height[k] / v->scaler_recout_height[k]);
+ } else {
+ v->h_ratio[k] = dcn_bw_max2(
+ v->viewport_height[k] / v->scaler_rec_out_width[k],
+ v->viewport_width[k] / v->scaler_recout_height[k]);
+ }
+ v->v_ratio[k] = v->h_ratio[k];
+ }
+ if (v->interlace_output[k] == 1.0) {
+ v->v_ratio[k] = 2.0 * v->v_ratio[k];
+ }
+ if ((v->underscan_output[k] == 1.0)) {
+ v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
+ v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
+ }
+ }
+ /*scaler taps calculation*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->h_ratio[k] > 1.0) {
+ v->acceptable_quality_hta_ps = dcn_bw_min2(
+ v->max_hscl_taps,
+ 2.0 * dcn_bw_ceil2(v->h_ratio[k], 1.0));
+ } else if (v->h_ratio[k] < 1.0) {
+ v->acceptable_quality_hta_ps = 4.0;
+ } else {
+ v->acceptable_quality_hta_ps = 1.0;
+ }
+ if (v->ta_pscalculation == dcn_bw_override) {
+ v->htaps[k] = v->override_hta_ps[k];
+ } else {
+ v->htaps[k] = v->acceptable_quality_hta_ps;
+ }
+ if (v->v_ratio[k] > 1.0) {
+ v->acceptable_quality_vta_ps = dcn_bw_min2(
+ v->max_vscl_taps,
+ 2.0 * dcn_bw_ceil2(v->v_ratio[k], 1.0));
+ } else if (v->v_ratio[k] < 1.0) {
+ v->acceptable_quality_vta_ps = 4.0;
+ } else {
+ v->acceptable_quality_vta_ps = 1.0;
+ }
+ if (v->ta_pscalculation == dcn_bw_override) {
+ v->vtaps[k] = v->override_vta_ps[k];
+ } else {
+ v->vtaps[k] = v->acceptable_quality_vta_ps;
+ }
+ if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
+ v->vta_pschroma[k] = 0.0;
+ v->hta_pschroma[k] = 0.0;
+ } else {
+ if (v->ta_pscalculation == dcn_bw_override) {
+ v->vta_pschroma[k] = v->override_vta_pschroma[k];
+ v->hta_pschroma[k] = v->override_hta_pschroma[k];
+ } else {
+ v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
+ v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
+ }
+ }
+ }
+}
+void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
+{
+ int i, j, k;
+ /*mode support, voltage state and soc configuration*/
+
+ /*scale ratio support check*/
+
+ v->scale_ratio_support = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio
+ || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k]
+ || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_32
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_16
+ && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k]
+ || v->v_ratio[k] / 2.0
+ > v->vta_pschroma[k]))) {
+ v->scale_ratio_support = dcn_bw_no;
+ }
+ }
+ /*source format, pixel format and scan support check*/
+
+ v->source_format_pixel_and_scan_support = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->source_surface_mode[k] == dcn_bw_sw_linear
+ && v->source_scan[k] != dcn_bw_hor)
+ || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x
+ || v->source_surface_mode[k] == dcn_bw_sw_var_d
+ || v->source_surface_mode[k] == dcn_bw_sw_var_d_x)
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
+ v->source_format_pixel_and_scan_support = dcn_bw_no;
+ }
+ }
+ /*bandwidth support check*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
+ } else {
+ v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
+ }
+ if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->byte_per_pixel_in_dety[k] = 8.0;
+ v->byte_per_pixel_in_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
+ v->byte_per_pixel_in_dety[k] = 4.0;
+ v->byte_per_pixel_in_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
+ v->byte_per_pixel_in_dety[k] = 2.0;
+ v->byte_per_pixel_in_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->byte_per_pixel_in_dety[k] = 1.0;
+ v->byte_per_pixel_in_detc[k] = 2.0;
+ } else {
+ v->byte_per_pixel_in_dety[k] = 4.0f / 3;
+ v->byte_per_pixel_in_detc[k] = 8.0f / 3;
+ }
+ }
+ v->total_read_bandwidth_consumed_gbyte_per_second = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k]
+ * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k]
+ + dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0
+ * v->v_ratio[k] / 2)
+ / (v->htotal[k] / v->pixel_clock[k]);
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
+ }
+ if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor
+ && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
+ v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
+ } else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor
+ && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32)
+ && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
+ v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
+ } else if (v->pte_enable == dcn_bw_yes) {
+ v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
+ }
+ v->total_read_bandwidth_consumed_gbyte_per_second =
+ v->total_read_bandwidth_consumed_gbyte_per_second
+ + v->read_bandwidth[k] / 1000.0;
+ }
+ v->total_write_bandwidth_consumed_gbyte_per_second = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
+ v->write_bandwidth[k] = v->scaler_rec_out_width[k]
+ / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
+ } else if (v->output[k] == dcn_bw_writeback) {
+ v->write_bandwidth[k] = v->scaler_rec_out_width[k]
+ / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
+ } else {
+ v->write_bandwidth[k] = 0.0;
+ }
+ v->total_write_bandwidth_consumed_gbyte_per_second =
+ v->total_write_bandwidth_consumed_gbyte_per_second
+ + v->write_bandwidth[k] / 1000.0;
+ }
+ v->total_bandwidth_consumed_gbyte_per_second =
+ v->total_read_bandwidth_consumed_gbyte_per_second
+ + v->total_write_bandwidth_consumed_gbyte_per_second;
+ v->dcc_enabled_in_any_plane = dcn_bw_no;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->dcc_enabled_in_any_plane = dcn_bw_yes;
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ v->return_bw_todcn_per_state =
+ dcn_bw_min2(
+ v->return_bus_width * v->dcfclk_per_state[i],
+ v->fabric_and_dram_bandwidth_per_state[i] * 1000.0
+ * v->percent_of_ideal_drambw_received_after_urg_latency
+ / 100.0);
+ v->return_bw_per_state[i] = v->return_bw_todcn_per_state;
+ if (v->dcc_enabled_in_any_plane == dcn_bw_yes
+ && v->return_bw_todcn_per_state
+ > v->dcfclk_per_state[i] * v->return_bus_width
+ / 4.0) {
+ v->return_bw_per_state[i] =
+ dcn_bw_min2(
+ v->return_bw_per_state[i],
+ v->return_bw_todcn_per_state * 4.0
+ * (1.0
+ - v->urgent_latency
+ / ((v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ / (v->return_bw_todcn_per_state
+ - v->dcfclk_per_state[i]
+ * v->return_bus_width
+ / 4.0)
+ + v->urgent_latency)));
+ }
+ v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i]
+ * v->urgent_latency
+ / (v->return_bw_todcn_per_state * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0);
+ if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0
+ && v->critical_point < 4.0) {
+ v->return_bw_per_state[i] =
+ dcn_bw_min2(
+ v->return_bw_per_state[i],
+ dcn_bw_pow(
+ 4.0
+ * v->return_bw_todcn_per_state
+ * (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ * v->return_bus_width
+ * v->dcfclk_per_state[i]
+ * v->urgent_latency
+ / (v->return_bw_todcn_per_state
+ * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0),
+ 2));
+ }
+ v->return_bw_todcn_per_state = dcn_bw_min2(
+ v->return_bus_width * v->dcfclk_per_state[i],
+ v->fabric_and_dram_bandwidth_per_state[i] * 1000.0);
+ if (v->dcc_enabled_in_any_plane == dcn_bw_yes
+ && v->return_bw_todcn_per_state
+ > v->dcfclk_per_state[i] * v->return_bus_width
+ / 4.0) {
+ v->return_bw_per_state[i] =
+ dcn_bw_min2(
+ v->return_bw_per_state[i],
+ v->return_bw_todcn_per_state * 4.0
+ * (1.0
+ - v->urgent_latency
+ / ((v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ / (v->return_bw_todcn_per_state
+ - v->dcfclk_per_state[i]
+ * v->return_bus_width
+ / 4.0)
+ + v->urgent_latency)));
+ }
+ v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i]
+ * v->urgent_latency
+ / (v->return_bw_todcn_per_state * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0);
+ if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0
+ && v->critical_point < 4.0) {
+ v->return_bw_per_state[i] =
+ dcn_bw_min2(
+ v->return_bw_per_state[i],
+ dcn_bw_pow(
+ 4.0
+ * v->return_bw_todcn_per_state
+ * (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ * v->return_bus_width
+ * v->dcfclk_per_state[i]
+ * v->urgent_latency
+ / (v->return_bw_todcn_per_state
+ * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0),
+ 2));
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0
+ <= v->return_bw_per_state[i])
+ && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0
+ <= v->fabric_and_dram_bandwidth_per_state[i]
+ * 1000.0
+ * v->percent_of_ideal_drambw_received_after_urg_latency
+ / 100.0)) {
+ v->bandwidth_support[i] = dcn_bw_yes;
+ } else {
+ v->bandwidth_support[i] = dcn_bw_no;
+ }
+ }
+ /*writeback latency support check*/
+
+ v->writeback_latency_support = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444
+ && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])
+ * 4.0
+ > (v->writeback_luma_buffer_size
+ + v->writeback_chroma_buffer_size)
+ * 1024.0 / v->write_back_latency) {
+ v->writeback_latency_support = dcn_bw_no;
+ } else if (v->output[k] == dcn_bw_writeback
+ && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])
+ > dcn_bw_min2(
+ v->writeback_luma_buffer_size,
+ 2.0
+ * v->writeback_chroma_buffer_size)
+ * 1024.0 / v->write_back_latency) {
+ v->writeback_latency_support = dcn_bw_no;
+ }
+ }
+ /*re-ordering buffer support check*/
+
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ v->urgent_round_trip_and_out_of_order_latency_per_state[i] =
+ (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i]
+ + v->urgent_out_of_order_return_per_channel
+ * v->number_of_channels
+ / v->return_bw_per_state[i];
+ if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0
+ / v->return_bw_per_state[i]
+ > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) {
+ v->rob_support[i] = dcn_bw_yes;
+ } else {
+ v->rob_support[i] = dcn_bw_no;
+ }
+ }
+ /*display io support check*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
+ if (v->output_format[k] == dcn_bw_420) {
+ v->required_output_bw = v->pixel_clock[k] / 2.0;
+ } else {
+ v->required_output_bw = v->pixel_clock[k];
+ }
+ } else if (v->output_format[k] == dcn_bw_420) {
+ v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
+ } else {
+ v->required_output_bw = v->pixel_clock[k] * 3.0;
+ }
+ if (v->output[k] == dcn_bw_hdmi) {
+ v->required_phyclk[k] = v->required_output_bw / 3.0;
+ } else if (v->output[k] == dcn_bw_dp) {
+ v->required_phyclk[k] = v->required_output_bw / 4.0;
+ } else {
+ v->required_phyclk[k] = 0.0;
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ v->dio_support[i] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->required_phyclk[k] > v->phyclk_per_state[i]
+ || (v->output[k] == dcn_bw_hdmi
+ && v->required_phyclk[k] > 600.0)) {
+ v->dio_support[i] = dcn_bw_no;
+ }
+ }
+ }
+ /*total available writeback support check*/
+
+ v->total_number_of_active_writeback = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_writeback) {
+ v->total_number_of_active_writeback = v->total_number_of_active_writeback
+ + 1.0;
+ }
+ }
+ if (v->total_number_of_active_writeback <= v->max_num_writeback) {
+ v->total_available_writeback_support = dcn_bw_yes;
+ } else {
+ v->total_available_writeback_support = dcn_bw_no;
+ }
+ /*maximum dispclk/dppclk support check*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->h_ratio[k] > 1.0) {
+ v->pscl_factor[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput * v->h_ratio[k]
+ / dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
+ } else {
+ v->pscl_factor[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput);
+ }
+ if (v->byte_per_pixel_in_detc[k] == 0.0) {
+ v->pscl_factor_chroma[k] = 0.0;
+ v->min_dppclk_using_single_dpp[k] =
+ v->pixel_clock[k]
+ * dcn_bw_max3(
+ v->vtaps[k] / 6.0
+ * dcn_bw_min2(
+ 1.0,
+ v->h_ratio[k]),
+ v->h_ratio[k]
+ * v->v_ratio[k]
+ / v->pscl_factor[k],
+ 1.0);
+ } else {
+ if (v->h_ratio[k] / 2.0 > 1.0) {
+ v->pscl_factor_chroma[k] =
+ dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput
+ * v->h_ratio[k]
+ / 2.0
+ / dcn_bw_ceil2(
+ v->hta_pschroma[k]
+ / 6.0,
+ 1.0));
+ } else {
+ v->pscl_factor_chroma[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput);
+ }
+ v->min_dppclk_using_single_dpp[k] =
+ v->pixel_clock[k]
+ * dcn_bw_max5(
+ v->vtaps[k] / 6.0
+ * dcn_bw_min2(
+ 1.0,
+ v->h_ratio[k]),
+ v->h_ratio[k]
+ * v->v_ratio[k]
+ / v->pscl_factor[k],
+ v->vta_pschroma[k] / 6.0
+ * dcn_bw_min2(
+ 1.0,
+ v->h_ratio[k]
+ / 2.0),
+ v->h_ratio[k]
+ * v->v_ratio[k]
+ / 4.0
+ / v->pscl_factor_chroma[k],
+ 1.0);
+ }
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->read256_block_height_y[k] = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->read256_block_height_y[k] = 4.0;
+ } else {
+ v->read256_block_height_y[k] = 8.0;
+ }
+ v->read256_block_width_y[k] = 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
+ / v->read256_block_height_y[k];
+ v->read256_block_height_c[k] = 0.0;
+ v->read256_block_width_c[k] = 0.0;
+ } else {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->read256_block_height_y[k] = 1.0;
+ v->read256_block_height_c[k] = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->read256_block_height_y[k] = 16.0;
+ v->read256_block_height_c[k] = 8.0;
+ } else {
+ v->read256_block_height_y[k] = 8.0;
+ v->read256_block_height_c[k] = 8.0;
+ }
+ v->read256_block_width_y[k] = 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
+ / v->read256_block_height_y[k];
+ v->read256_block_width_c[k] = 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)
+ / v->read256_block_height_c[k];
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->max_swath_height_y[k] = v->read256_block_height_y[k];
+ v->max_swath_height_c[k] = v->read256_block_height_c[k];
+ } else {
+ v->max_swath_height_y[k] = v->read256_block_width_y[k];
+ v->max_swath_height_c[k] = v->read256_block_width_c[k];
+ }
+ if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear
+ || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ && (v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_var_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_var_s_x)
+ && v->source_scan[k] == dcn_bw_hor)) {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k];
+ } else {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
+ }
+ v->min_swath_height_c[k] = v->max_swath_height_c[k];
+ } else {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k];
+ v->min_swath_height_c[k] = v->max_swath_height_c[k];
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8
+ && v->source_scan[k] == dcn_bw_hor) {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
+ if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
+ == dcn_bw_yes) {
+ v->min_swath_height_c[k] = v->max_swath_height_c[k];
+ } else {
+ v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
+ }
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10
+ && v->source_scan[k] == dcn_bw_hor) {
+ v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
+ if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
+ == dcn_bw_yes) {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k];
+ } else {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
+ }
+ } else {
+ v->min_swath_height_y[k] = v->max_swath_height_y[k];
+ v->min_swath_height_c[k] = v->max_swath_height_c[k];
+ }
+ }
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->maximum_swath_width = 8192.0;
+ } else {
+ v->maximum_swath_width = 5120.0;
+ }
+ v->number_of_dpp_required_for_det_size =
+ dcn_bw_ceil2(
+ v->swath_width_ysingle_dpp[k]
+ / dcn_bw_min2(
+ v->maximum_swath_width,
+ v->det_buffer_size_in_kbyte
+ * 1024.0
+ / 2.0
+ / (v->byte_per_pixel_in_dety[k]
+ * v->min_swath_height_y[k]
+ + v->byte_per_pixel_in_detc[k]
+ / 2.0
+ * v->min_swath_height_c[k])),
+ 1.0);
+ if (v->byte_per_pixel_in_detc[k] == 0.0) {
+ v->number_of_dpp_required_for_lb_size = dcn_bw_ceil2(
+ (v->vtaps[k]
+ + dcn_bw_max2(
+ dcn_bw_ceil2(v->v_ratio[k], 1.0)
+ - 2,
+ 0.0))
+ * v->swath_width_ysingle_dpp[k]
+ / dcn_bw_max2(v->h_ratio[k], 1.0)
+ * v->lb_bit_per_pixel[k]
+ / v->line_buffer_size,
+ 1.0);
+ } else {
+ v->number_of_dpp_required_for_lb_size =
+ dcn_bw_max2(
+ dcn_bw_ceil2(
+ (v->vtaps[k]
+ + dcn_bw_max2(
+ dcn_bw_ceil2(
+ v->v_ratio[k],
+ 1.0)
+ - 2,
+ 0.0))
+ * v->swath_width_ysingle_dpp[k]
+ / dcn_bw_max2(
+ v->h_ratio[k],
+ 1.0)
+ * v->lb_bit_per_pixel[k]
+ / v->line_buffer_size,
+ 1.0),
+ dcn_bw_ceil2(
+ (v->vta_pschroma[k]
+ + dcn_bw_max2(
+ dcn_bw_ceil2(
+ v->v_ratio[k]
+ / 2.0,
+ 1.0)
+ - 2,
+ 0.0))
+ * v->swath_width_ysingle_dpp[k]
+ / 2.0
+ / dcn_bw_max2(
+ v->h_ratio[k]
+ / 2.0,
+ 1.0)
+ * v->lb_bit_per_pixel[k]
+ / v->line_buffer_size,
+ 1.0));
+ }
+ v->number_of_dpp_required_for_det_and_lb_size[k] = dcn_bw_max2(
+ v->number_of_dpp_required_for_det_size,
+ v->number_of_dpp_required_for_lb_size);
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->total_number_of_active_dpp[i][j] = 0.0;
+ v->required_dispclk[i][j] = 0.0;
+ v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->min_dispclk_using_single_dpp = dcn_bw_max2(
+ v->pixel_clock[k],
+ v->min_dppclk_using_single_dpp[k] * (j + 1))
+ * (1.0 + v->downspreading / 100.0);
+ if (v->odm_capability == dcn_bw_yes) {
+ v->min_dispclk_using_dual_dpp = dcn_bw_max2(
+ v->pixel_clock[k] / 2.0,
+ v->min_dppclk_using_single_dpp[k] / 2.0
+ * (j + 1))
+ * (1.0 + v->downspreading / 100.0);
+ } else {
+ v->min_dispclk_using_dual_dpp = dcn_bw_max2(
+ v->pixel_clock[k],
+ v->min_dppclk_using_single_dpp[k] / 2.0
+ * (j + 1))
+ * (1.0 + v->downspreading / 100.0);
+ }
+ if (i < number_of_states) {
+ v->min_dispclk_using_single_dpp =
+ v->min_dispclk_using_single_dpp
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0);
+ v->min_dispclk_using_dual_dpp =
+ v->min_dispclk_using_dual_dpp
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0);
+ }
+ if (v->min_dispclk_using_single_dpp
+ <= dcn_bw_min2(
+ v->max_dispclk[i],
+ (j + 1) * v->max_dppclk[i])
+ && v->number_of_dpp_required_for_det_and_lb_size[k]
+ <= 1.0) {
+ v->no_of_dpp[i][j][k] = 1.0;
+ v->required_dispclk[i][j] = dcn_bw_max2(
+ v->required_dispclk[i][j],
+ v->min_dispclk_using_single_dpp);
+ } else if (v->min_dispclk_using_dual_dpp
+ <= dcn_bw_min2(
+ v->max_dispclk[i],
+ (j + 1) * v->max_dppclk[i])) {
+ v->no_of_dpp[i][j][k] = 2.0;
+ v->required_dispclk[i][j] = dcn_bw_max2(
+ v->required_dispclk[i][j],
+ v->min_dispclk_using_dual_dpp);
+ } else {
+ v->no_of_dpp[i][j][k] = 2.0;
+ v->required_dispclk[i][j] = dcn_bw_max2(
+ v->required_dispclk[i][j],
+ v->min_dispclk_using_dual_dpp);
+ v->dispclk_dppclk_support[i][j] = dcn_bw_no;
+ }
+ v->total_number_of_active_dpp[i][j] =
+ v->total_number_of_active_dpp[i][j]
+ + v->no_of_dpp[i][j][k];
+ }
+ if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) {
+ v->total_number_of_active_dpp[i][j] = 0.0;
+ v->required_dispclk[i][j] = 0.0;
+ v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->min_dispclk_using_single_dpp = dcn_bw_max2(
+ v->pixel_clock[k],
+ v->min_dppclk_using_single_dpp[k] * (j + 1))
+ * (1.0 + v->downspreading / 100.0);
+ v->min_dispclk_using_dual_dpp = dcn_bw_max2(
+ v->pixel_clock[k],
+ v->min_dppclk_using_single_dpp[k] / 2.0
+ * (j + 1))
+ * (1.0 + v->downspreading / 100.0);
+ if (i < number_of_states) {
+ v->min_dispclk_using_single_dpp =
+ v->min_dispclk_using_single_dpp
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0);
+ v->min_dispclk_using_dual_dpp =
+ v->min_dispclk_using_dual_dpp
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0);
+ }
+ if (v->number_of_dpp_required_for_det_and_lb_size[k]
+ <= 1.0) {
+ v->no_of_dpp[i][j][k] = 1.0;
+ v->required_dispclk[i][j] = dcn_bw_max2(
+ v->required_dispclk[i][j],
+ v->min_dispclk_using_single_dpp);
+ if (v->min_dispclk_using_single_dpp
+ > dcn_bw_min2(
+ v->max_dispclk[i],
+ (j + 1)
+ * v->max_dppclk[i])) {
+ v->dispclk_dppclk_support[i][j] = dcn_bw_no;
+ }
+ } else {
+ v->no_of_dpp[i][j][k] = 2.0;
+ v->required_dispclk[i][j] = dcn_bw_max2(
+ v->required_dispclk[i][j],
+ v->min_dispclk_using_dual_dpp);
+ if (v->min_dispclk_using_dual_dpp
+ > dcn_bw_min2(
+ v->max_dispclk[i],
+ (j + 1)
+ * v->max_dppclk[i])) {
+ v->dispclk_dppclk_support[i][j] = dcn_bw_no;
+ }
+ }
+ v->total_number_of_active_dpp[i][j] =
+ v->total_number_of_active_dpp[i][j]
+ + v->no_of_dpp[i][j][k];
+ }
+ }
+ }
+ }
+ /*viewport size check*/
+
+ v->viewport_size_support = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
+ v->viewport_size_support = dcn_bw_no;
+ }
+ }
+ /*total available pipes support check*/
+
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) {
+ v->total_available_pipes_support[i][j] = dcn_bw_yes;
+ } else {
+ v->total_available_pipes_support[i][j] = dcn_bw_no;
+ }
+ }
+ }
+ /*urgent latency support check*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k]
+ / v->no_of_dpp[i][j][k];
+ v->swath_width_granularity_y = 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0)
+ / v->max_swath_height_y[k];
+ v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(
+ v->swath_width_yper_state[i][j][k] - 1.0,
+ v->swath_width_granularity_y)
+ + v->swath_width_granularity_y)
+ * v->byte_per_pixel_in_dety[k]
+ * v->max_swath_height_y[k];
+ if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
+ v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(
+ v->rounded_up_max_swath_size_bytes_y,
+ 256.0) + 256;
+ }
+ if (v->max_swath_height_c[k] > 0.0) {
+ v->swath_width_granularity_c =
+ 256.0
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / v->max_swath_height_c[k];
+ }
+ v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(
+ v->swath_width_yper_state[i][j][k] / 2.0 - 1.0,
+ v->swath_width_granularity_c)
+ + v->swath_width_granularity_c)
+ * v->byte_per_pixel_in_detc[k]
+ * v->max_swath_height_c[k];
+ if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
+ v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(
+ v->rounded_up_max_swath_size_bytes_c,
+ 256.0) + 256;
+ }
+ if (v->rounded_up_max_swath_size_bytes_y
+ + v->rounded_up_max_swath_size_bytes_c
+ <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
+ v->swath_height_yper_state[i][j][k] =
+ v->max_swath_height_y[k];
+ v->swath_height_cper_state[i][j][k] =
+ v->max_swath_height_c[k];
+ } else {
+ v->swath_height_yper_state[i][j][k] =
+ v->min_swath_height_y[k];
+ v->swath_height_cper_state[i][j][k] =
+ v->min_swath_height_c[k];
+ }
+ if (v->byte_per_pixel_in_detc[k] == 0.0) {
+ v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
+ / v->byte_per_pixel_in_dety[k]
+ / v->swath_width_yper_state[i][j][k];
+ v->lines_in_det_chroma = 0.0;
+ } else if (v->swath_height_yper_state[i][j][k]
+ <= v->swath_height_cper_state[i][j][k]) {
+ v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
+ / 2.0 / v->byte_per_pixel_in_dety[k]
+ / v->swath_width_yper_state[i][j][k];
+ v->lines_in_det_chroma =
+ v->det_buffer_size_in_kbyte * 1024.0 / 2.0
+ / v->byte_per_pixel_in_detc[k]
+ / (v->swath_width_yper_state[i][j][k]
+ / 2.0);
+ } else {
+ v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0
+ * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k]
+ / v->swath_width_yper_state[i][j][k];
+ v->lines_in_det_chroma =
+ v->det_buffer_size_in_kbyte * 1024.0 / 3.0
+ / v->byte_per_pixel_in_dety[k]
+ / (v->swath_width_yper_state[i][j][k]
+ / 2.0);
+ }
+ v->effective_lb_latency_hiding_source_lines_luma =
+ dcn_bw_min2(
+ v->max_line_buffer_lines,
+ dcn_bw_floor2(
+ v->line_buffer_size
+ / v->lb_bit_per_pixel[k]
+ / (v->swath_width_yper_state[i][j][k]
+ / dcn_bw_max2(
+ v->h_ratio[k],
+ 1.0)),
+ 1.0))
+ - (v->vtaps[k] - 1.0);
+ v->effective_lb_latency_hiding_source_lines_chroma =
+ dcn_bw_min2(
+ v->max_line_buffer_lines,
+ dcn_bw_floor2(
+ v->line_buffer_size
+ / v->lb_bit_per_pixel[k]
+ / (v->swath_width_yper_state[i][j][k]
+ / 2.0
+ / dcn_bw_max2(
+ v->h_ratio[k]
+ / 2.0,
+ 1.0)),
+ 1.0))
+ - (v->vta_pschroma[k] - 1.0);
+ v->effective_detlb_lines_luma =
+ dcn_bw_floor2(
+ v->lines_in_det_luma
+ + dcn_bw_min2(
+ v->lines_in_det_luma
+ * v->required_dispclk[i][j]
+ * v->byte_per_pixel_in_dety[k]
+ * v->pscl_factor[k]
+ / v->return_bw_per_state[i],
+ v->effective_lb_latency_hiding_source_lines_luma),
+ v->swath_height_yper_state[i][j][k]);
+ v->effective_detlb_lines_chroma =
+ dcn_bw_floor2(
+ v->lines_in_det_chroma
+ + dcn_bw_min2(
+ v->lines_in_det_chroma
+ * v->required_dispclk[i][j]
+ * v->byte_per_pixel_in_detc[k]
+ * v->pscl_factor_chroma[k]
+ / v->return_bw_per_state[i],
+ v->effective_lb_latency_hiding_source_lines_chroma),
+ v->swath_height_cper_state[i][j][k]);
+ if (v->byte_per_pixel_in_detc[k] == 0.0) {
+ v->urgent_latency_support_us_per_state[i][j][k] =
+ v->effective_detlb_lines_luma
+ * (v->htotal[k]
+ / v->pixel_clock[k])
+ / v->v_ratio[k]
+ - v->effective_detlb_lines_luma
+ * v->swath_width_yper_state[i][j][k]
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / (v->return_bw_per_state[i]
+ / v->no_of_dpp[i][j][k]);
+ } else {
+ v->urgent_latency_support_us_per_state[i][j][k] =
+ dcn_bw_min2(
+ v->effective_detlb_lines_luma
+ * (v->htotal[k]
+ / v->pixel_clock[k])
+ / v->v_ratio[k]
+ - v->effective_detlb_lines_luma
+ * v->swath_width_yper_state[i][j][k]
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / (v->return_bw_per_state[i]
+ / v->no_of_dpp[i][j][k]),
+ v->effective_detlb_lines_chroma
+ * (v->htotal[k]
+ / v->pixel_clock[k])
+ / (v->v_ratio[k]
+ / 2.0)
+ - v->effective_detlb_lines_chroma
+ * v->swath_width_yper_state[i][j][k]
+ / 2.0
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / (v->return_bw_per_state[i]
+ / v->no_of_dpp[i][j][k]));
+ }
+ }
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->urgent_latency_support[i][j] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->urgent_latency_support_us_per_state[i][j][k]
+ < v->urgent_latency / 1.0) {
+ v->urgent_latency_support[i][j] = dcn_bw_no;
+ }
+ }
+ }
+ }
+ /*prefetch check*/
+
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->total_number_of_dcc_active_dpp[i][j] = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->total_number_of_dcc_active_dpp[i][j] =
+ v->total_number_of_dcc_active_dpp[i][j]
+ + v->no_of_dpp[i][j][k];
+ }
+ }
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->projected_dcfclk_deep_sleep = 8.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->projected_dcfclk_deep_sleep = dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ v->pixel_clock[k] / 16.0);
+ if (v->byte_per_pixel_in_detc[k] == 0.0) {
+ if (v->v_ratio[k] <= 1.0) {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 64.0
+ * v->h_ratio[k]
+ * v->pixel_clock[k]
+ / v->no_of_dpp[i][j][k]);
+ } else {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 64.0
+ * v->pscl_factor[k]
+ * v->required_dispclk[i][j]
+ / (1
+ + j));
+ }
+ } else {
+ if (v->v_ratio[k] <= 1.0) {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 32.0
+ * v->h_ratio[k]
+ * v->pixel_clock[k]
+ / v->no_of_dpp[i][j][k]);
+ } else {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 32.0
+ * v->pscl_factor[k]
+ * v->required_dispclk[i][j]
+ / (1
+ + j));
+ }
+ if (v->v_ratio[k] / 2.0 <= 1.0) {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 32.0
+ * v->h_ratio[k]
+ / 2.0
+ * v->pixel_clock[k]
+ / v->no_of_dpp[i][j][k]);
+ } else {
+ v->projected_dcfclk_deep_sleep =
+ dcn_bw_max2(
+ v->projected_dcfclk_deep_sleep,
+ 1.1
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 32.0
+ * v->pscl_factor_chroma[k]
+ * v->required_dispclk[i][j]
+ / (1
+ + j));
+ }
+ }
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
+ v->meta_req_width_y =
+ 64.0 * 256.0
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / v->meta_req_height_y;
+ v->meta_surface_width_y = dcn_bw_ceil2(
+ v->viewport_width[k] / v->no_of_dpp[i][j][k]
+ - 1.0,
+ v->meta_req_width_y) + v->meta_req_width_y;
+ v->meta_surface_height_y = dcn_bw_ceil2(
+ v->viewport_height[k] - 1.0,
+ v->meta_req_height_y)
+ + v->meta_req_height_y;
+ if (v->pte_enable == dcn_bw_yes) {
+ v->meta_pte_bytes_per_frame_y =
+ (dcn_bw_ceil2(
+ (v->meta_surface_width_y
+ * v->meta_surface_height_y
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 256.0
+ - 4096.0)
+ / 8.0
+ / 4096.0,
+ 1.0) + 1) * 64.0;
+ } else {
+ v->meta_pte_bytes_per_frame_y = 0.0;
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->meta_row_bytes_y =
+ v->meta_surface_width_y
+ * v->meta_req_height_y
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 256.0;
+ } else {
+ v->meta_row_bytes_y =
+ v->meta_surface_height_y
+ * v->meta_req_width_y
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / 256.0;
+ }
+ } else {
+ v->meta_pte_bytes_per_frame_y = 0.0;
+ v->meta_row_bytes_y = 0.0;
+ }
+ if (v->pte_enable == dcn_bw_yes) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->macro_tile_block_size_bytes_y = 256.0;
+ v->macro_tile_block_height_y = 1.0;
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_d_x) {
+ v->macro_tile_block_size_bytes_y = 4096.0;
+ v->macro_tile_block_height_y = 4.0
+ * v->read256_block_height_y[k];
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d_x) {
+ v->macro_tile_block_size_bytes_y = 64.0 * 1024;
+ v->macro_tile_block_height_y = 16.0
+ * v->read256_block_height_y[k];
+ } else {
+ v->macro_tile_block_size_bytes_y = 256.0 * 1024;
+ v->macro_tile_block_height_y = 32.0
+ * v->read256_block_height_y[k];
+ }
+ if (v->macro_tile_block_size_bytes_y <= 65536.0) {
+ v->data_pte_req_height_y =
+ v->macro_tile_block_height_y;
+ } else {
+ v->data_pte_req_height_y = 16.0
+ * v->read256_block_height_y[k];
+ }
+ v->data_pte_req_width_y =
+ 4096.0
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ / v->data_pte_req_height_y
+ * 8;
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->dpte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ * dcn_bw_min2(
+ 128.0,
+ dcn_bw_pow(
+ 2.0,
+ dcn_bw_floor2(
+ dcn_bw_log(
+ v->pte_buffer_size_in_requests
+ * v->data_pte_req_width_y
+ / (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]),
+ 2.0),
+ 1.0)))
+ - 1.0)
+ / v->data_pte_req_width_y,
+ 1.0)
+ + 1);
+ } else if (v->source_scan[k] == dcn_bw_hor) {
+ v->dpte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ - 1.0)
+ / v->data_pte_req_width_y,
+ 1.0)
+ + 1);
+ } else {
+ v->dpte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_height[k]
+ - 1.0)
+ / v->data_pte_req_height_y,
+ 1.0)
+ + 1);
+ }
+ } else {
+ v->dpte_bytes_per_row_y = 0.0;
+ }
+ if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_32
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->meta_req_height_c = 8.0
+ * v->read256_block_height_c[k];
+ v->meta_req_width_c =
+ 64.0 * 256.0
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / v->meta_req_height_c;
+ v->meta_surface_width_c =
+ dcn_bw_ceil2(
+ v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ / 2.0
+ - 1.0,
+ v->meta_req_width_c)
+ + v->meta_req_width_c;
+ v->meta_surface_height_c = dcn_bw_ceil2(
+ v->viewport_height[k] / 2.0 - 1.0,
+ v->meta_req_height_c)
+ + v->meta_req_height_c;
+ if (v->pte_enable == dcn_bw_yes) {
+ v->meta_pte_bytes_per_frame_c =
+ (dcn_bw_ceil2(
+ (v->meta_surface_width_c
+ * v->meta_surface_height_c
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 256.0
+ - 4096.0)
+ / 8.0
+ / 4096.0,
+ 1.0) + 1)
+ * 64.0;
+ } else {
+ v->meta_pte_bytes_per_frame_c = 0.0;
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->meta_row_bytes_c =
+ v->meta_surface_width_c
+ * v->meta_req_height_c
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 256.0;
+ } else {
+ v->meta_row_bytes_c =
+ v->meta_surface_height_c
+ * v->meta_req_width_c
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 256.0;
+ }
+ } else {
+ v->meta_pte_bytes_per_frame_c = 0.0;
+ v->meta_row_bytes_c = 0.0;
+ }
+ if (v->pte_enable == dcn_bw_yes) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->macro_tile_block_size_bytes_c = 256.0;
+ v->macro_tile_block_height_c = 1.0;
+ } else if (v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_d_x) {
+ v->macro_tile_block_size_bytes_c = 4096.0;
+ v->macro_tile_block_height_c =
+ 4.0
+ * v->read256_block_height_c[k];
+ } else if (v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d_x) {
+ v->macro_tile_block_size_bytes_c = 64.0
+ * 1024;
+ v->macro_tile_block_height_c =
+ 16.0
+ * v->read256_block_height_c[k];
+ } else {
+ v->macro_tile_block_size_bytes_c = 256.0
+ * 1024;
+ v->macro_tile_block_height_c =
+ 32.0
+ * v->read256_block_height_c[k];
+ }
+ v->macro_tile_block_width_c =
+ v->macro_tile_block_size_bytes_c
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / v->macro_tile_block_height_c;
+ if (v->macro_tile_block_size_bytes_c <= 65536.0) {
+ v->data_pte_req_height_c =
+ v->macro_tile_block_height_c;
+ } else {
+ v->data_pte_req_height_c =
+ 16.0
+ * v->read256_block_height_c[k];
+ }
+ v->data_pte_req_width_c =
+ 4096.0
+ / dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / v->data_pte_req_height_c
+ * 8;
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->dpte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ / 2.0
+ * dcn_bw_min2(
+ 128.0,
+ dcn_bw_pow(
+ 2.0,
+ dcn_bw_floor2(
+ dcn_bw_log(
+ v->pte_buffer_size_in_requests
+ * v->data_pte_req_width_c
+ / (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ / 2.0),
+ 2.0),
+ 1.0)))
+ - 1.0)
+ / v->data_pte_req_width_c,
+ 1.0)
+ + 1);
+ } else if (v->source_scan[k] == dcn_bw_hor) {
+ v->dpte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_width[k]
+ / v->no_of_dpp[i][j][k]
+ / 2.0
+ - 1.0)
+ / v->data_pte_req_width_c,
+ 1.0)
+ + 1);
+ } else {
+ v->dpte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_height[k]
+ / 2.0
+ - 1.0)
+ / v->data_pte_req_height_c,
+ 1.0)
+ + 1);
+ }
+ } else {
+ v->dpte_bytes_per_row_c = 0.0;
+ }
+ } else {
+ v->dpte_bytes_per_row_c = 0.0;
+ v->meta_pte_bytes_per_frame_c = 0.0;
+ v->meta_row_bytes_c = 0.0;
+ }
+ v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y
+ + v->dpte_bytes_per_row_c;
+ v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y
+ + v->meta_pte_bytes_per_frame_c;
+ v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
+ v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0
+ + v->interlace_output[k] * 0.5 * v->v_ratio[k])
+ / 2.0;
+ v->prefill_y[k] = dcn_bw_floor2(v->v_init_y, 1.0);
+ v->max_num_sw_y[k] =
+ dcn_bw_ceil2(
+ (v->prefill_y[k] - 1.0)
+ / v->swath_height_yper_state[i][j][k],
+ 1.0) + 1;
+ if (v->prefill_y[k] > 1.0) {
+ v->max_partial_sw_y = dcn_bw_mod(
+ (v->prefill_y[k] - 2.0),
+ v->swath_height_yper_state[i][j][k]);
+ } else {
+ v->max_partial_sw_y =
+ dcn_bw_mod(
+ (v->prefill_y[k]
+ + v->swath_height_yper_state[i][j][k]
+ - 2.0),
+ v->swath_height_yper_state[i][j][k]);
+ }
+ v->max_partial_sw_y = dcn_bw_max2(1.0, v->max_partial_sw_y);
+ v->prefetch_lines_y[k] = v->max_num_sw_y[k]
+ * v->swath_height_yper_state[i][j][k]
+ + v->max_partial_sw_y;
+ if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_32
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
+ v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0
+ + v->interlace_output[k] * 0.5
+ * v->v_ratio[k] / 2.0)
+ / 2.0;
+ v->prefill_c[k] = dcn_bw_floor2(v->v_init_c, 1.0);
+ v->max_num_sw_c[k] =
+ dcn_bw_ceil2(
+ (v->prefill_c[k] - 1.0)
+ / v->swath_height_cper_state[i][j][k],
+ 1.0) + 1;
+ if (v->prefill_c[k] > 1.0) {
+ v->max_partial_sw_c =
+ dcn_bw_mod(
+ (v->prefill_c[k]
+ - 2.0),
+ v->swath_height_cper_state[i][j][k]);
+ } else {
+ v->max_partial_sw_c =
+ dcn_bw_mod(
+ (v->prefill_c[k]
+ + v->swath_height_cper_state[i][j][k]
+ - 2.0),
+ v->swath_height_cper_state[i][j][k]);
+ }
+ v->max_partial_sw_c = dcn_bw_max2(1.0, v->max_partial_sw_c);
+ v->prefetch_lines_c[k] = v->max_num_sw_c[k]
+ * v->swath_height_cper_state[i][j][k]
+ + v->max_partial_sw_c;
+ } else {
+ v->prefetch_lines_c[k] = 0.0;
+ }
+ v->dst_x_after_scaler = 90.0 * v->pixel_clock[k]
+ / (v->required_dispclk[i][j] / (j + 1))
+ + 42.0 * v->pixel_clock[k]
+ / v->required_dispclk[i][j];
+ if (v->no_of_dpp[i][j][k] > 1.0) {
+ v->dst_x_after_scaler = v->dst_x_after_scaler
+ + v->scaler_rec_out_width[k] / 2.0;
+ }
+ if (v->output_format[k] == dcn_bw_420) {
+ v->dst_y_after_scaler = 1.0;
+ } else {
+ v->dst_y_after_scaler = 0.0;
+ }
+ v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep;
+ v->v_update_offset[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
+ v->total_repeater_delay = v->max_inter_dcn_tile_repeaters
+ * (2.0 / (v->required_dispclk[i][j] / (j + 1))
+ + 3.0 / v->required_dispclk[i][j]);
+ v->v_update_width[k] = (14.0 / v->projected_dcfclk_deep_sleep
+ + 12.0 / (v->required_dispclk[i][j] / (j + 1))
+ + v->total_repeater_delay) * v->pixel_clock[k];
+ v->v_ready_offset[k] =
+ dcn_bw_max2(
+ 150.0
+ / (v->required_dispclk[i][j]
+ / (j
+ + 1)),
+ v->total_repeater_delay
+ + 20.0
+ / v->projected_dcfclk_deep_sleep
+ + 10.0
+ / (v->required_dispclk[i][j]
+ / (j
+ + 1)))
+ * v->pixel_clock[k];
+ v->time_setup = (v->v_update_offset[k] + v->v_update_width[k]
+ + v->v_ready_offset[k]) / v->pixel_clock[k];
+ v->extra_latency =
+ v->urgent_round_trip_and_out_of_order_latency_per_state[i]
+ + (v->total_number_of_active_dpp[i][j]
+ * v->pixel_chunk_size_in_kbyte
+ + v->total_number_of_dcc_active_dpp[i][j]
+ * v->meta_chunk_size)
+ * 1024.0
+ / v->return_bw_per_state[i];
+ if (v->pte_enable == dcn_bw_yes) {
+ v->extra_latency = v->extra_latency
+ + v->total_number_of_active_dpp[i][j]
+ * v->pte_chunk_size * 1024.0
+ / v->return_bw_per_state[i];
+ }
+ if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
+ == dcn_bw_yes) {
+ v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
+ } else {
+ v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
+ }
+ v->line_times_for_prefetch[k] = v->maximum_vstartup
+ - v->urgent_latency
+ / (v->htotal[k] / v->pixel_clock[k])
+ - (v->time_calc + v->time_setup)
+ / (v->htotal[k] / v->pixel_clock[k])
+ - (v->dst_y_after_scaler
+ + v->dst_x_after_scaler
+ / v->htotal[k]);
+ v->line_times_for_prefetch[k] = dcn_bw_floor2(
+ 4.0 * (v->line_times_for_prefetch[k] + 0.125),
+ 1.0) / 4;
+ v->prefetch_bw[k] =
+ (v->meta_pte_bytes_per_frame[k]
+ + 2.0 * v->meta_row_bytes[k]
+ + 2.0 * v->dpte_bytes_per_row[k]
+ + v->prefetch_lines_y[k]
+ * v->swath_width_yper_state[i][j][k]
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ + v->prefetch_lines_c[k]
+ * v->swath_width_yper_state[i][j][k]
+ / 2.0
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0))
+ / (v->line_times_for_prefetch[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]);
+ }
+ v->bw_available_for_immediate_flip = v->return_bw_per_state[i];
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->bw_available_for_immediate_flip =
+ v->bw_available_for_immediate_flip
+ - dcn_bw_max2(
+ v->read_bandwidth[k],
+ v->prefetch_bw[k]);
+ }
+ v->total_immediate_flip_bytes[k] = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
+ v->total_immediate_flip_bytes[k] =
+ v->total_immediate_flip_bytes[k]
+ + v->meta_pte_bytes_per_frame[k]
+ + v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k];
+ }
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
+ v->time_for_meta_pte_with_immediate_flip =
+ dcn_bw_max5(
+ v->meta_pte_bytes_per_frame[k]
+ / v->prefetch_bw[k],
+ v->meta_pte_bytes_per_frame[k]
+ * v->total_immediate_flip_bytes[k]
+ / (v->bw_available_for_immediate_flip
+ * (v->meta_pte_bytes_per_frame[k]
+ + v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])),
+ v->extra_latency,
+ v->urgent_latency,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ / 4.0);
+ v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
+ v->meta_pte_bytes_per_frame[k]
+ / v->prefetch_bw[k],
+ v->extra_latency,
+ v->htotal[k] / v->pixel_clock[k] / 4.0);
+ } else {
+ v->time_for_meta_pte_with_immediate_flip = v->htotal[k]
+ / v->pixel_clock[k] / 4.0;
+ v->time_for_meta_pte_without_immediate_flip = v->htotal[k]
+ / v->pixel_clock[k] / 4.0;
+ }
+ if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
+ v->time_for_meta_and_dpte_row_with_immediate_flip =
+ dcn_bw_max5(
+ (v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])
+ / v->prefetch_bw[k],
+ (v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])
+ * v->total_immediate_flip_bytes[k]
+ / (v->bw_available_for_immediate_flip
+ * (v->meta_pte_bytes_per_frame[k]
+ + v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])),
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_meta_pte_with_immediate_flip,
+ v->extra_latency,
+ 2.0 * v->urgent_latency);
+ v->time_for_meta_and_dpte_row_without_immediate_flip =
+ dcn_bw_max3(
+ (v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])
+ / v->prefetch_bw[k],
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_meta_pte_without_immediate_flip,
+ v->extra_latency);
+ } else {
+ v->time_for_meta_and_dpte_row_with_immediate_flip =
+ dcn_bw_max2(
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_meta_pte_with_immediate_flip,
+ v->extra_latency
+ - v->time_for_meta_pte_with_immediate_flip);
+ v->time_for_meta_and_dpte_row_without_immediate_flip =
+ dcn_bw_max2(
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_meta_pte_without_immediate_flip,
+ v->extra_latency
+ - v->time_for_meta_pte_without_immediate_flip);
+ }
+ v->lines_for_meta_pte_with_immediate_flip[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_meta_pte_with_immediate_flip
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ v->lines_for_meta_pte_without_immediate_flip[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_meta_pte_without_immediate_flip
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_meta_and_dpte_row_with_immediate_flip
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_meta_and_dpte_row_without_immediate_flip
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ v->line_times_to_request_prefetch_pixel_data_with_immediate_flip =
+ v->line_times_for_prefetch[k]
+ - v->lines_for_meta_pte_with_immediate_flip[k]
+ - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
+ v->line_times_to_request_prefetch_pixel_data_without_immediate_flip =
+ v->line_times_for_prefetch[k]
+ - v->lines_for_meta_pte_without_immediate_flip[k]
+ - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
+ if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ > 0.0) {
+ v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
+ v->prefetch_lines_y[k]
+ / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
+ if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
+ if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ - (v->prefill_y[k] - 3.0) / 2.0
+ > 0.0) {
+ v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
+ dcn_bw_max2(
+ v->v_ratio_pre_ywith_immediate_flip[i][j][k],
+ (v->max_num_sw_y[k]
+ * v->swath_height_yper_state[i][j][k])
+ / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ - (v->prefill_y[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_pre_ywith_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ }
+ v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
+ v->prefetch_lines_c[k]
+ / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
+ if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
+ if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ - (v->prefill_c[k] - 3.0) / 2.0
+ > 0.0) {
+ v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
+ dcn_bw_max2(
+ v->v_ratio_pre_cwith_immediate_flip[i][j][k],
+ (v->max_num_sw_c[k]
+ * v->swath_height_cper_state[i][j][k])
+ / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ - (v->prefill_c[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_pre_cwith_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ }
+ v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] =
+ v->no_of_dpp[i][j][k]
+ * (v->prefetch_lines_y[k]
+ / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ + v->prefetch_lines_c[k]
+ / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 2.0)
+ * v->swath_width_yper_state[i][j][k]
+ / (v->htotal[k]
+ / v->pixel_clock[k]);
+ } else {
+ v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
+ v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
+ v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ > 0.0) {
+ v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
+ v->prefetch_lines_y[k]
+ / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
+ if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
+ if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ - (v->prefill_y[k] - 3.0) / 2.0
+ > 0.0) {
+ v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
+ dcn_bw_max2(
+ v->v_ratio_pre_ywithout_immediate_flip[i][j][k],
+ (v->max_num_sw_y[k]
+ * v->swath_height_yper_state[i][j][k])
+ / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ - (v->prefill_y[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ }
+ v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
+ v->prefetch_lines_c[k]
+ / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
+ if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
+ if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ - (v->prefill_c[k] - 3.0) / 2.0
+ > 0.0) {
+ v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
+ dcn_bw_max2(
+ v->v_ratio_pre_cwithout_immediate_flip[i][j][k],
+ (v->max_num_sw_c[k]
+ * v->swath_height_cper_state[i][j][k])
+ / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ - (v->prefill_c[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ }
+ v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] =
+ v->no_of_dpp[i][j][k]
+ * (v->prefetch_lines_y[k]
+ / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_dety[k],
+ 1.0)
+ + v->prefetch_lines_c[k]
+ / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_in_detc[k],
+ 2.0)
+ / 2.0)
+ * v->swath_width_yper_state[i][j][k]
+ / (v->htotal[k]
+ / v->pixel_clock[k]);
+ } else {
+ v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
+ v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
+ v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] =
+ 999999.0;
+ }
+ }
+ v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
+ v->maximum_read_bandwidth_with_prefetch_with_immediate_flip =
+ v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
+ + dcn_bw_max2(
+ v->read_bandwidth[k],
+ v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k])
+ + dcn_bw_max2(
+ v->meta_pte_bytes_per_frame[k]
+ / (v->lines_for_meta_pte_with_immediate_flip[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]),
+ (v->meta_row_bytes[k]
+ + v->dpte_bytes_per_row[k])
+ / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]));
+ } else {
+ v->maximum_read_bandwidth_with_prefetch_with_immediate_flip =
+ v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
+ + dcn_bw_max2(
+ v->read_bandwidth[k],
+ v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
+ }
+ }
+ v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->maximum_read_bandwidth_with_prefetch_without_immediate_flip =
+ v->maximum_read_bandwidth_with_prefetch_without_immediate_flip
+ + dcn_bw_max2(
+ v->read_bandwidth[k],
+ v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
+ }
+ v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
+ if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip
+ > v->return_bw_per_state[i]) {
+ v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->line_times_for_prefetch[k] < 2.0
+ || v->lines_for_meta_pte_with_immediate_flip[k]
+ >= 8.0
+ || v->lines_for_meta_and_dpte_row_with_immediate_flip[k]
+ >= 16.0) {
+ v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
+ }
+ }
+ v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
+ if (v->maximum_read_bandwidth_with_prefetch_without_immediate_flip
+ > v->return_bw_per_state[i]) {
+ v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->line_times_for_prefetch[k] < 2.0
+ || v->lines_for_meta_pte_without_immediate_flip[k]
+ >= 8.0
+ || v->lines_for_meta_and_dpte_row_without_immediate_flip[k]
+ >= 16.0) {
+ v->prefetch_supported_without_immediate_flip[i][j] =
+ dcn_bw_no;
+ }
+ }
+ }
+ }
+ for (i = 0; i <= number_of_states_plus_one; i++) {
+ for (j = 0; j <= 1; j++) {
+ v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)
+ && (v->v_ratio_pre_ywith_immediate_flip[i][j][k]
+ > 4.0
+ || v->v_ratio_pre_cwith_immediate_flip[i][j][k]
+ > 4.0))
+ || ((v->source_pixel_format[k]
+ == dcn_bw_yuv420_sub_8
+ || v->source_pixel_format[k]
+ == dcn_bw_yuv420_sub_10)
+ && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k]
+ > 4.0
+ || v->v_ratio_pre_cwithout_immediate_flip[i][j][k]
+ > 4.0)))) {
+ v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] =
+ dcn_bw_no;
+ }
+ }
+ v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0
+ || v->v_ratio_pre_cwithout_immediate_flip[i][j][k]
+ > 4.0)) {
+ v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] =
+ dcn_bw_no;
+ }
+ }
+ }
+ }
+ /*mode support, voltage state and soc configuration*/
+
+ for (i = number_of_states_plus_one; i >= 0; i--) {
+ for (j = 0; j <= 1; j++) {
+ if (v->scale_ratio_support == dcn_bw_yes
+ && v->source_format_pixel_and_scan_support == dcn_bw_yes
+ && v->viewport_size_support == dcn_bw_yes
+ && v->bandwidth_support[i] == dcn_bw_yes
+ && v->dio_support[i] == dcn_bw_yes
+ && v->urgent_latency_support[i][j] == dcn_bw_yes
+ && v->rob_support[i] == dcn_bw_yes
+ && v->dispclk_dppclk_support[i][j] == dcn_bw_yes
+ && v->total_available_pipes_support[i][j] == dcn_bw_yes
+ && v->total_available_writeback_support == dcn_bw_yes
+ && v->writeback_latency_support == dcn_bw_yes) {
+ if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes
+ && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j]
+ == dcn_bw_yes) {
+ v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes;
+ } else {
+ v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
+ }
+ if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes
+ && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j]
+ == dcn_bw_yes) {
+ v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes;
+ } else {
+ v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
+ }
+ } else {
+ v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
+ v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
+ }
+ }
+ }
+ for (i = number_of_states_plus_one; i >= 0; i--) {
+ if ((i == number_of_states_plus_one
+ || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes
+ || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes)
+ && i >= v->voltage_override_level) {
+ v->voltage_level_with_immediate_flip = i;
+ }
+ }
+ for (i = number_of_states_plus_one; i >= 0; i--) {
+ if ((i == number_of_states_plus_one
+ || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes
+ || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes)
+ && i >= v->voltage_override_level) {
+ v->voltage_level_without_immediate_flip = i;
+ }
+ }
+ if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) {
+ v->immediate_flip_supported = dcn_bw_no;
+ v->voltage_level = v->voltage_level_without_immediate_flip;
+ } else {
+ v->immediate_flip_supported = dcn_bw_yes;
+ v->voltage_level = v->voltage_level_with_immediate_flip;
+ }
+ v->dcfclk = v->dcfclk_per_state[v->voltage_level];
+ v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
+ for (j = 0; j <= 1; j++) {
+ v->required_dispclk_per_ratio[j] = v->required_dispclk[v->voltage_level][j];
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
+ }
+ v->dispclk_dppclk_support_per_ratio[j] =
+ v->dispclk_dppclk_support[v->voltage_level][j];
+ }
+ v->max_phyclk = v->phyclk_per_state[v->voltage_level];
+}
+void display_pipe_configuration(struct dcn_bw_internal_vars *v)
+{
+ int j, k;
+ /*display pipe configuration*/
+
+ for (j = 0; j <= 1; j++) {
+ v->total_number_of_active_dpp_per_ratio[j] = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->total_number_of_active_dpp_per_ratio[j] =
+ v->total_number_of_active_dpp_per_ratio[j]
+ + v->dpp_per_plane_per_ratio[j][k];
+ }
+ }
+ if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes
+ && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no)
+ || (v->dispclk_dppclk_support_per_ratio[0]
+ == v->dispclk_dppclk_support_per_ratio[1]
+ && (v->total_number_of_active_dpp_per_ratio[0]
+ < v->total_number_of_active_dpp_per_ratio[1]
+ || (((v->total_number_of_active_dpp_per_ratio[0]
+ == v->total_number_of_active_dpp_per_ratio[1])
+ && v->required_dispclk_per_ratio[0]
+ <= 0.5
+ * v->required_dispclk_per_ratio[1]))))) {
+ v->dispclk_dppclk_ratio = 1;
+ v->final_error_message = v->error_message[0];
+ } else {
+ v->dispclk_dppclk_ratio = 2;
+ v->final_error_message = v->error_message[1];
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->byte_per_pix_dety = 8.0;
+ v->byte_per_pix_detc = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
+ v->byte_per_pix_dety = 4.0;
+ v->byte_per_pix_detc = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
+ v->byte_per_pix_dety = 2.0;
+ v->byte_per_pix_detc = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->byte_per_pix_dety = 1.0;
+ v->byte_per_pix_detc = 2.0;
+ } else {
+ v->byte_per_pix_dety = 4.0f / 3;
+ v->byte_per_pix_detc = 8.0f / 3;
+ }
+ if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->read256_bytes_block_height_y = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->read256_bytes_block_height_y = 4.0;
+ } else {
+ v->read256_bytes_block_height_y = 8.0;
+ }
+ v->read256_bytes_block_width_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
+ / v->read256_bytes_block_height_y;
+ v->read256_bytes_block_height_c = 0.0;
+ v->read256_bytes_block_width_c = 0.0;
+ } else {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->read256_bytes_block_height_y = 1.0;
+ v->read256_bytes_block_height_c = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->read256_bytes_block_height_y = 16.0;
+ v->read256_bytes_block_height_c = 8.0;
+ } else {
+ v->read256_bytes_block_height_y = 8.0;
+ v->read256_bytes_block_height_c = 8.0;
+ }
+ v->read256_bytes_block_width_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
+ / v->read256_bytes_block_height_y;
+ v->read256_bytes_block_width_c = 256.0 / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0)
+ / v->read256_bytes_block_height_c;
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->maximum_swath_height_y = v->read256_bytes_block_height_y;
+ v->maximum_swath_height_c = v->read256_bytes_block_height_c;
+ } else {
+ v->maximum_swath_height_y = v->read256_bytes_block_width_y;
+ v->maximum_swath_height_c = v->read256_bytes_block_width_c;
+ }
+ if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear
+ || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ && (v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_var_s
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_var_s_x)
+ && v->source_scan[k] == dcn_bw_hor)) {
+ v->minimum_swath_height_y = v->maximum_swath_height_y;
+ } else {
+ v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
+ }
+ v->minimum_swath_height_c = v->maximum_swath_height_c;
+ } else {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->minimum_swath_height_y = v->maximum_swath_height_y;
+ v->minimum_swath_height_c = v->maximum_swath_height_c;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8
+ && v->source_scan[k] == dcn_bw_hor) {
+ v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
+ if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
+ == dcn_bw_yes) {
+ v->minimum_swath_height_c = v->maximum_swath_height_c;
+ } else {
+ v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
+ }
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10
+ && v->source_scan[k] == dcn_bw_hor) {
+ v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
+ if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed
+ == dcn_bw_yes) {
+ v->minimum_swath_height_y = v->maximum_swath_height_y;
+ } else {
+ v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
+ }
+ } else {
+ v->minimum_swath_height_y = v->maximum_swath_height_y;
+ v->minimum_swath_height_c = v->maximum_swath_height_c;
+ }
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
+ } else {
+ v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
+ }
+ v->swath_width_granularity_y = 256.0 / dcn_bw_ceil2(v->byte_per_pix_dety, 1.0)
+ / v->maximum_swath_height_y;
+ v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(
+ v->swath_width - 1.0,
+ v->swath_width_granularity_y) + v->swath_width_granularity_y)
+ * v->byte_per_pix_dety * v->maximum_swath_height_y;
+ if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
+ v->rounded_up_max_swath_size_bytes_y = dcn_bw_ceil2(
+ v->rounded_up_max_swath_size_bytes_y,
+ 256.0) + 256;
+ }
+ if (v->maximum_swath_height_c > 0.0) {
+ v->swath_width_granularity_c = 256.0 / dcn_bw_ceil2(v->byte_per_pix_detc, 2.0)
+ / v->maximum_swath_height_c;
+ }
+ v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(
+ v->swath_width / 2.0 - 1.0,
+ v->swath_width_granularity_c) + v->swath_width_granularity_c)
+ * v->byte_per_pix_detc * v->maximum_swath_height_c;
+ if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
+ v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(
+ v->rounded_up_max_swath_size_bytes_c,
+ 256.0) + 256;
+ }
+ if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c
+ <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
+ v->swath_height_y[k] = v->maximum_swath_height_y;
+ v->swath_height_c[k] = v->maximum_swath_height_c;
+ } else {
+ v->swath_height_y[k] = v->minimum_swath_height_y;
+ v->swath_height_c[k] = v->minimum_swath_height_c;
+ }
+ if (v->swath_height_c[k] == 0.0) {
+ v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
+ v->det_buffer_size_c[k] = 0.0;
+ } else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
+ v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
+ v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
+ } else {
+ v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
+ v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
+ }
+ }
+}
+void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
+ struct dcn_bw_internal_vars *v)
+{
+ int k;
+ /*dispclk and dppclk calculation*/
+
+ v->dispclk_with_ramping = 0.0;
+ v->dispclk_without_ramping = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->h_ratio[k] > 1.0) {
+ v->pscl_throughput[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput * v->h_ratio[k]
+ / dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
+ } else {
+ v->pscl_throughput[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput);
+ }
+ v->dppclk_using_single_dpp_luma = v->pixel_clock[k]
+ * dcn_bw_max3(
+ v->vtaps[k] / 6.0 * dcn_bw_min2(1.0, v->h_ratio[k]),
+ v->h_ratio[k] * v->v_ratio[k]
+ / v->pscl_throughput[k],
+ 1.0);
+ if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
+ v->pscl_throughput_chroma[k] = 0.0;
+ v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma;
+ } else {
+ if (v->h_ratio[k] > 1.0) {
+ v->pscl_throughput_chroma[k] =
+ dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput
+ * v->h_ratio[k]
+ / 2.0
+ / dcn_bw_ceil2(
+ v->hta_pschroma[k]
+ / 6.0,
+ 1.0));
+ } else {
+ v->pscl_throughput_chroma[k] = dcn_bw_min2(
+ v->max_dchub_topscl_throughput,
+ v->max_pscl_tolb_throughput);
+ }
+ v->dppclk_using_single_dpp_chroma =
+ v->pixel_clock[k]
+ * dcn_bw_max3(
+ v->vta_pschroma[k] / 6.0
+ * dcn_bw_min2(
+ 1.0,
+ v->h_ratio[k]
+ / 2.0),
+ v->h_ratio[k]
+ * v->v_ratio[k]
+ / 4.0
+ / v->pscl_throughput_chroma[k],
+ 1.0);
+ v->dppclk_using_single_dpp = dcn_bw_max2(
+ v->dppclk_using_single_dpp_luma,
+ v->dppclk_using_single_dpp_chroma);
+ }
+ if (v->odm_capable == dcn_bw_yes) {
+ v->dispclk_with_ramping =
+ dcn_bw_max2(
+ v->dispclk_with_ramping,
+ dcn_bw_max2(
+ v->dppclk_using_single_dpp
+ / v->dpp_per_plane[k]
+ * v->dispclk_dppclk_ratio,
+ v->pixel_clock[k]
+ / v->dpp_per_plane[k])
+ * (1.0
+ + v->downspreading
+ / 100.0)
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0));
+ v->dispclk_without_ramping = dcn_bw_max2(
+ v->dispclk_without_ramping,
+ dcn_bw_max2(
+ v->dppclk_using_single_dpp
+ / v->dpp_per_plane[k]
+ * v->dispclk_dppclk_ratio,
+ v->pixel_clock[k] / v->dpp_per_plane[k])
+ * (1.0 + v->downspreading / 100.0));
+ } else {
+ v->dispclk_with_ramping =
+ dcn_bw_max2(
+ v->dispclk_with_ramping,
+ dcn_bw_max2(
+ v->dppclk_using_single_dpp
+ / v->dpp_per_plane[k]
+ * v->dispclk_dppclk_ratio,
+ v->pixel_clock[k])
+ * (1.0
+ + v->downspreading
+ / 100.0)
+ * (1.0
+ + v->dispclk_ramping_margin
+ / 100.0));
+ v->dispclk_without_ramping = dcn_bw_max2(
+ v->dispclk_without_ramping,
+ dcn_bw_max2(
+ v->dppclk_using_single_dpp
+ / v->dpp_per_plane[k]
+ * v->dispclk_dppclk_ratio,
+ v->pixel_clock[k])
+ * (1.0 + v->downspreading / 100.0));
+ }
+ }
+ if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) {
+ v->dispclk = v->dispclk_without_ramping;
+ } else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) {
+ v->dispclk = v->max_dispclk[number_of_states];
+ } else {
+ v->dispclk = v->dispclk_with_ramping;
+ }
+ v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
+ /*urgent watermark*/
+
+ v->return_bandwidth_to_dcn = dcn_bw_min2(
+ v->return_bus_width * v->dcfclk,
+ v->fabric_and_dram_bandwidth * 1000.0
+ * v->percent_of_ideal_drambw_received_after_urg_latency
+ / 100.0);
+ v->dcc_enabled_any_plane = dcn_bw_no;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->dcc_enabled_any_plane = dcn_bw_yes;
+ }
+ }
+ v->return_bw = v->return_bandwidth_to_dcn;
+ if (v->dcc_enabled_any_plane == dcn_bw_yes
+ && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
+ v->return_bw =
+ dcn_bw_min2(
+ v->return_bw,
+ v->return_bandwidth_to_dcn * 4.0
+ * (1.0
+ - v->urgent_latency
+ / ((v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ / (v->return_bandwidth_to_dcn
+ - v->dcfclk
+ * v->return_bus_width
+ / 4.0)
+ + v->urgent_latency)));
+ }
+ v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency
+ / (v->return_bandwidth_to_dcn * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte) * 1024.0);
+ if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0
+ && v->critical_compression < 4.0) {
+ v->return_bw =
+ dcn_bw_min2(
+ v->return_bw,
+ dcn_bw_pow(
+ 4.0 * v->return_bandwidth_to_dcn
+ * (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ * v->return_bus_width
+ * v->dcfclk
+ * v->urgent_latency
+ / (v->return_bandwidth_to_dcn
+ * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0),
+ 2));
+ }
+ v->return_bandwidth_to_dcn = dcn_bw_min2(
+ v->return_bus_width * v->dcfclk,
+ v->fabric_and_dram_bandwidth * 1000.0);
+ if (v->dcc_enabled_any_plane == dcn_bw_yes
+ && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
+ v->return_bw =
+ dcn_bw_min2(
+ v->return_bw,
+ v->return_bandwidth_to_dcn * 4.0
+ * (1.0
+ - v->urgent_latency
+ / ((v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ / (v->return_bandwidth_to_dcn
+ - v->dcfclk
+ * v->return_bus_width
+ / 4.0)
+ + v->urgent_latency)));
+ }
+ v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency
+ / (v->return_bandwidth_to_dcn * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte) * 1024.0);
+ if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0
+ && v->critical_compression < 4.0) {
+ v->return_bw =
+ dcn_bw_min2(
+ v->return_bw,
+ dcn_bw_pow(
+ 4.0 * v->return_bandwidth_to_dcn
+ * (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0
+ * v->return_bus_width
+ * v->dcfclk
+ * v->urgent_latency
+ / (v->return_bandwidth_to_dcn
+ * v->urgent_latency
+ + (v->rob_buffer_size_in_kbyte
+ - v->pixel_chunk_size_in_kbyte)
+ * 1024.0),
+ 2));
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
+ } else {
+ v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
+ }
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->byte_per_pixel_dety[k] = 8.0;
+ v->byte_per_pixel_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
+ v->byte_per_pixel_dety[k] = 4.0;
+ v->byte_per_pixel_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
+ v->byte_per_pixel_dety[k] = 2.0;
+ v->byte_per_pixel_detc[k] = 0.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->byte_per_pixel_dety[k] = 1.0;
+ v->byte_per_pixel_detc[k] = 2.0;
+ } else {
+ v->byte_per_pixel_dety[k] = 4.0f / 3;
+ v->byte_per_pixel_detc[k] = 8.0f / 3;
+ }
+ }
+ v->total_data_read_bandwidth = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k]
+ * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
+ / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
+ v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k]
+ * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
+ v->total_data_read_bandwidth = v->total_data_read_bandwidth
+ + v->read_bandwidth_plane_luma[k]
+ + v->read_bandwidth_plane_chroma[k];
+ }
+ v->total_active_dpp = 0.0;
+ v->total_dcc_active_dpp = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
+ }
+ }
+ v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0)
+ / v->dcfclk
+ + v->urgent_out_of_order_return_per_channel * v->number_of_channels
+ / v->return_bw;
+ v->last_pixel_of_line_extra_watermark = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->v_ratio[k] <= 1.0) {
+ v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k]
+ * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
+ } else {
+ v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k]
+ / v->pscl_throughput[k] / v->dppclk;
+ }
+ v->data_fabric_line_delivery_time_luma =
+ v->swath_width_y[k] * v->swath_height_y[k]
+ * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
+ / (v->return_bw * v->read_bandwidth_plane_luma[k]
+ / v->dpp_per_plane[k]
+ / v->total_data_read_bandwidth);
+ v->last_pixel_of_line_extra_watermark = dcn_bw_max2(
+ v->last_pixel_of_line_extra_watermark,
+ v->data_fabric_line_delivery_time_luma
+ - v->display_pipe_line_delivery_time_luma[k]);
+ if (v->byte_per_pixel_detc[k] == 0.0) {
+ v->display_pipe_line_delivery_time_chroma[k] = 0.0;
+ } else {
+ if (v->v_ratio[k] / 2.0 <= 1.0) {
+ v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k]
+ / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0)
+ / v->pixel_clock[k];
+ } else {
+ v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k]
+ / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
+ }
+ v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0
+ * v->swath_height_c[k]
+ * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / (v->return_bw * v->read_bandwidth_plane_chroma[k]
+ / v->dpp_per_plane[k]
+ / v->total_data_read_bandwidth);
+ v->last_pixel_of_line_extra_watermark =
+ dcn_bw_max2(
+ v->last_pixel_of_line_extra_watermark,
+ v->data_fabric_line_delivery_time_chroma
+ - v->display_pipe_line_delivery_time_chroma[k]);
+ }
+ }
+ v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency
+ + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte
+ + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0
+ / v->return_bw;
+ if (v->pte_enable == dcn_bw_yes) {
+ v->urgent_extra_latency = v->urgent_extra_latency
+ + v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw;
+ }
+ v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark
+ + v->urgent_extra_latency;
+ v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency;
+ /*nb p-state/dram clock change watermark*/
+
+ v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark;
+ v->total_active_writeback = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_writeback) {
+ v->total_active_writeback = v->total_active_writeback + 1.0;
+ }
+ }
+ if (v->total_active_writeback <= 1.0) {
+ v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency
+ + v->write_back_latency;
+ } else {
+ v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency
+ + v->write_back_latency
+ + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
+ }
+ /*stutter efficiency*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k]
+ / v->swath_width_y[k];
+ v->lines_in_dety_rounded_down_to_swath[k] = dcn_bw_floor2(
+ v->lines_in_dety[k],
+ v->swath_height_y[k]);
+ v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k]
+ * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
+ if (v->byte_per_pixel_detc[k] > 0.0) {
+ v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k]
+ / (v->swath_width_y[k] / 2.0);
+ v->lines_in_detc_rounded_down_to_swath[k] = dcn_bw_floor2(
+ v->lines_in_detc[k],
+ v->swath_height_c[k]);
+ v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k]
+ * (v->htotal[k] / v->pixel_clock[k])
+ / (v->v_ratio[k] / 2.0);
+ } else {
+ v->lines_in_detc[k] = 0.0;
+ v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
+ v->full_det_buffering_time_c[k] = 999999.0;
+ }
+ }
+ v->min_full_det_buffering_time = 999999.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
+ v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
+ v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k]
+ / v->pixel_clock[k];
+ }
+ if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
+ v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
+ v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k]
+ / v->pixel_clock[k];
+ }
+ }
+ v->average_read_bandwidth_gbyte_per_second = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->average_read_bandwidth_gbyte_per_second =
+ v->average_read_bandwidth_gbyte_per_second
+ + v->read_bandwidth_plane_luma[k]
+ / v->dcc_rate[k] / 1000.0
+ + v->read_bandwidth_plane_chroma[k]
+ / v->dcc_rate[k] / 1000.0;
+ } else {
+ v->average_read_bandwidth_gbyte_per_second =
+ v->average_read_bandwidth_gbyte_per_second
+ + v->read_bandwidth_plane_luma[k] / 1000.0
+ + v->read_bandwidth_plane_chroma[k]
+ / 1000.0;
+ }
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->average_read_bandwidth_gbyte_per_second =
+ v->average_read_bandwidth_gbyte_per_second
+ + v->read_bandwidth_plane_luma[k] / 1000.0
+ / 256.0
+ + v->read_bandwidth_plane_chroma[k] / 1000.0
+ / 256.0;
+ }
+ if (v->pte_enable == dcn_bw_yes) {
+ v->average_read_bandwidth_gbyte_per_second =
+ v->average_read_bandwidth_gbyte_per_second
+ + v->read_bandwidth_plane_luma[k] / 1000.0
+ / 512.0
+ + v->read_bandwidth_plane_chroma[k] / 1000.0
+ / 512.0;
+ }
+ }
+ v->part_of_burst_that_fits_in_rob = dcn_bw_min2(
+ v->min_full_det_buffering_time * v->total_data_read_bandwidth,
+ v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth
+ / (v->average_read_bandwidth_gbyte_per_second * 1000.0));
+ v->stutter_burst_time = v->part_of_burst_that_fits_in_rob
+ * (v->average_read_bandwidth_gbyte_per_second * 1000.0)
+ / v->total_data_read_bandwidth / v->return_bw
+ + (v->min_full_det_buffering_time * v->total_data_read_bandwidth
+ - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0);
+ if (v->total_active_writeback == 0.0) {
+ v->stutter_efficiency_not_including_vblank = (1.0
+ - (v->sr_exit_time + v->stutter_burst_time)
+ / v->min_full_det_buffering_time) * 100.0;
+ } else {
+ v->stutter_efficiency_not_including_vblank = 0.0;
+ }
+ v->smallest_vblank = 999999.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
+ v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k]
+ / v->pixel_clock[k];
+ } else {
+ v->v_blank_time = 0.0;
+ }
+ v->smallest_vblank = dcn_bw_min2(v->smallest_vblank, v->v_blank_time);
+ }
+ v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0
+ * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank)
+ + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time
+ * 100.0;
+ /*dcfclk deep sleep*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->byte_per_pixel_detc[k] > 0.0) {
+ v->dcfclk_deep_sleep_per_plane[k] =
+ dcn_bw_max2(
+ 1.1 * v->swath_width_y[k]
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_dety[k],
+ 1.0) / 32.0
+ / v->display_pipe_line_delivery_time_luma[k],
+ 1.1 * v->swath_width_y[k] / 2.0
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_detc[k],
+ 2.0) / 32.0
+ / v->display_pipe_line_delivery_time_chroma[k]);
+ } else {
+ v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k]
+ * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0
+ / v->display_pipe_line_delivery_time_luma[k];
+ }
+ v->dcfclk_deep_sleep_per_plane[k] = dcn_bw_max2(
+ v->dcfclk_deep_sleep_per_plane[k],
+ v->pixel_clock[k] / 16.0);
+ }
+ v->dcf_clk_deep_sleep = 8.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->dcf_clk_deep_sleep = dcn_bw_max2(
+ v->dcf_clk_deep_sleep,
+ v->dcfclk_deep_sleep_per_plane[k]);
+ }
+ /*stutter watermark*/
+
+ v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark
+ + v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep;
+ v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time
+ + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
+ /*urgent latency supported*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->effective_det_plus_lb_lines_luma =
+ dcn_bw_floor2(
+ v->lines_in_dety[k]
+ + dcn_bw_min2(
+ v->lines_in_dety[k]
+ * v->dppclk
+ * v->byte_per_pixel_dety[k]
+ * v->pscl_throughput[k]
+ / (v->return_bw
+ / v->dpp_per_plane[k]),
+ v->effective_lb_latency_hiding_source_lines_luma),
+ v->swath_height_y[k]);
+ v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma
+ * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k]
+ - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k]
+ * v->byte_per_pixel_dety[k]
+ / (v->return_bw / v->dpp_per_plane[k]);
+ if (v->byte_per_pixel_detc[k] > 0.0) {
+ v->effective_det_plus_lb_lines_chroma =
+ dcn_bw_floor2(
+ v->lines_in_detc[k]
+ + dcn_bw_min2(
+ v->lines_in_detc[k]
+ * v->dppclk
+ * v->byte_per_pixel_detc[k]
+ * v->pscl_throughput_chroma[k]
+ / (v->return_bw
+ / v->dpp_per_plane[k]),
+ v->effective_lb_latency_hiding_source_lines_chroma),
+ v->swath_height_c[k]);
+ v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma
+ * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0)
+ - v->effective_det_plus_lb_lines_chroma
+ * (v->swath_width_y[k] / 2.0)
+ * v->byte_per_pixel_detc[k]
+ / (v->return_bw / v->dpp_per_plane[k]);
+ v->urgent_latency_support_us[k] = dcn_bw_min2(
+ v->urgent_latency_support_us_luma,
+ v->urgent_latency_support_us_chroma);
+ } else {
+ v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
+ }
+ }
+ v->min_urgent_latency_support_us = 999999.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->min_urgent_latency_support_us = dcn_bw_min2(
+ v->min_urgent_latency_support_us,
+ v->urgent_latency_support_us[k]);
+ }
+ /*non-urgent latency tolerance*/
+
+ v->non_urgent_latency_tolerance = v->min_urgent_latency_support_us - v->urgent_watermark;
+ /*prefetch*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_32
+ || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->block_height256_bytes_y = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
+ v->block_height256_bytes_y = 4.0;
+ } else {
+ v->block_height256_bytes_y = 8.0;
+ }
+ v->block_height256_bytes_c = 0.0;
+ } else {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->block_height256_bytes_y = 1.0;
+ v->block_height256_bytes_c = 1.0;
+ } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
+ v->block_height256_bytes_y = 16.0;
+ v->block_height256_bytes_c = 8.0;
+ } else {
+ v->block_height256_bytes_y = 8.0;
+ v->block_height256_bytes_c = 8.0;
+ }
+ }
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->meta_request_width_y = 64.0 * 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
+ / (8.0 * v->block_height256_bytes_y);
+ v->meta_surf_width_y = dcn_bw_ceil2(
+ v->swath_width_y[k] - 1.0,
+ v->meta_request_width_y) + v->meta_request_width_y;
+ v->meta_surf_height_y = dcn_bw_ceil2(
+ v->viewport_height[k] - 1.0,
+ 8.0 * v->block_height256_bytes_y)
+ + 8.0 * v->block_height256_bytes_y;
+ if (v->pte_enable == dcn_bw_yes) {
+ v->meta_pte_bytes_frame_y =
+ (dcn_bw_ceil2(
+ (v->meta_surf_width_y
+ * v->meta_surf_height_y
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_dety[k],
+ 1.0)
+ / 256.0 - 4096.0)
+ / 8.0 / 4096.0,
+ 1.0) + 1) * 64.0;
+ } else {
+ v->meta_pte_bytes_frame_y = 0.0;
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->meta_row_byte_y = v->meta_surf_width_y * 8.0
+ * v->block_height256_bytes_y
+ * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
+ } else {
+ v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y
+ * dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
+ }
+ } else {
+ v->meta_pte_bytes_frame_y = 0.0;
+ v->meta_row_byte_y = 0.0;
+ }
+ if (v->pte_enable == dcn_bw_yes) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->macro_tile_size_byte_y = 256.0;
+ v->macro_tile_height_y = 1.0;
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
+ v->macro_tile_size_byte_y = 4096.0;
+ v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y;
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
+ v->macro_tile_size_byte_y = 64.0 * 1024;
+ v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y;
+ } else {
+ v->macro_tile_size_byte_y = 256.0 * 1024;
+ v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y;
+ }
+ if (v->macro_tile_size_byte_y <= 65536.0) {
+ v->pixel_pte_req_height_y = v->macro_tile_height_y;
+ } else {
+ v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y;
+ }
+ v->pixel_pte_req_width_y = 4096.0 / dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0)
+ / v->pixel_pte_req_height_y * 8;
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->pixel_pte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->swath_width_y[k]
+ * dcn_bw_min2(
+ 128.0,
+ dcn_bw_pow(
+ 2.0,
+ dcn_bw_floor2(
+ dcn_bw_log(
+ v->pte_buffer_size_in_requests
+ * v->pixel_pte_req_width_y
+ / v->swath_width_y[k],
+ 2.0),
+ 1.0)))
+ - 1.0)
+ / v->pixel_pte_req_width_y,
+ 1.0) + 1);
+ } else if (v->source_scan[k] == dcn_bw_hor) {
+ v->pixel_pte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->swath_width_y[k]
+ - 1.0)
+ / v->pixel_pte_req_width_y,
+ 1.0) + 1);
+ } else {
+ v->pixel_pte_bytes_per_row_y =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_height[k]
+ - 1.0)
+ / v->pixel_pte_req_height_y,
+ 1.0) + 1);
+ }
+ } else {
+ v->pixel_pte_bytes_per_row_y = 0.0;
+ }
+ if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_32
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
+ if (v->dcc_enable[k] == dcn_bw_yes) {
+ v->meta_request_width_c = 64.0 * 256.0
+ / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / (8.0 * v->block_height256_bytes_c);
+ v->meta_surf_width_c = dcn_bw_ceil2(
+ v->swath_width_y[k] / 2.0 - 1.0,
+ v->meta_request_width_c) + v->meta_request_width_c;
+ v->meta_surf_height_c = dcn_bw_ceil2(
+ v->viewport_height[k] / 2.0 - 1.0,
+ 8.0 * v->block_height256_bytes_c)
+ + 8.0 * v->block_height256_bytes_c;
+ if (v->pte_enable == dcn_bw_yes) {
+ v->meta_pte_bytes_frame_c =
+ (dcn_bw_ceil2(
+ (v->meta_surf_width_c
+ * v->meta_surf_height_c
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_detc[k],
+ 2.0)
+ / 256.0
+ - 4096.0)
+ / 8.0
+ / 4096.0,
+ 1.0) + 1) * 64.0;
+ } else {
+ v->meta_pte_bytes_frame_c = 0.0;
+ }
+ if (v->source_scan[k] == dcn_bw_hor) {
+ v->meta_row_byte_c = v->meta_surf_width_c * 8.0
+ * v->block_height256_bytes_c
+ * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / 256.0;
+ } else {
+ v->meta_row_byte_c = v->meta_surf_height_c
+ * v->meta_request_width_c
+ * dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / 256.0;
+ }
+ } else {
+ v->meta_pte_bytes_frame_c = 0.0;
+ v->meta_row_byte_c = 0.0;
+ }
+ if (v->pte_enable == dcn_bw_yes) {
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->macro_tile_size_bytes_c = 256.0;
+ v->macro_tile_height_c = 1.0;
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_4_kb_d_x) {
+ v->macro_tile_size_bytes_c = 4096.0;
+ v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c;
+ } else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d
+ || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t
+ || v->source_surface_mode[k]
+ == dcn_bw_sw_64_kb_d_x) {
+ v->macro_tile_size_bytes_c = 64.0 * 1024;
+ v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c;
+ } else {
+ v->macro_tile_size_bytes_c = 256.0 * 1024;
+ v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c;
+ }
+ if (v->macro_tile_size_bytes_c <= 65536.0) {
+ v->pixel_pte_req_height_c = v->macro_tile_height_c;
+ } else {
+ v->pixel_pte_req_height_c = 16.0
+ * v->block_height256_bytes_c;
+ }
+ v->pixel_pte_req_width_c = 4096.0
+ / dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)
+ / v->pixel_pte_req_height_c * 8;
+ if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
+ v->pixel_pte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->swath_width_y[k]
+ / 2.0
+ * dcn_bw_min2(
+ 128.0,
+ dcn_bw_pow(
+ 2.0,
+ dcn_bw_floor2(
+ dcn_bw_log(
+ v->pte_buffer_size_in_requests
+ * v->pixel_pte_req_width_c
+ / (v->swath_width_y[k]
+ / 2.0),
+ 2.0),
+ 1.0)))
+ - 1.0)
+ / v->pixel_pte_req_width_c,
+ 1.0) + 1);
+ } else if (v->source_scan[k] == dcn_bw_hor) {
+ v->pixel_pte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->swath_width_y[k]
+ / 2.0
+ - 1.0)
+ / v->pixel_pte_req_width_c,
+ 1.0) + 1);
+ } else {
+ v->pixel_pte_bytes_per_row_c =
+ 64.0
+ * (dcn_bw_ceil2(
+ (v->viewport_height[k]
+ / 2.0
+ - 1.0)
+ / v->pixel_pte_req_height_c,
+ 1.0) + 1);
+ }
+ } else {
+ v->pixel_pte_bytes_per_row_c = 0.0;
+ }
+ } else {
+ v->pixel_pte_bytes_per_row_c = 0.0;
+ v->meta_pte_bytes_frame_c = 0.0;
+ v->meta_row_byte_c = 0.0;
+ }
+ v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y
+ + v->pixel_pte_bytes_per_row_c;
+ v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
+ v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
+ v->v_init_pre_fill_y[k] = dcn_bw_floor2(
+ (v->v_ratio[k] + v->vtaps[k] + 1.0
+ + v->interlace_output[k] * 0.5 * v->v_ratio[k])
+ / 2.0,
+ 1.0);
+ v->max_num_swath_y[k] = dcn_bw_ceil2(
+ (v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k],
+ 1.0) + 1;
+ if (v->v_init_pre_fill_y[k] > 1.0) {
+ v->max_partial_swath_y = dcn_bw_mod(
+ (v->v_init_pre_fill_y[k] - 2.0),
+ v->swath_height_y[k]);
+ } else {
+ v->max_partial_swath_y = dcn_bw_mod(
+ (v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0),
+ v->swath_height_y[k]);
+ }
+ v->max_partial_swath_y = dcn_bw_max2(1.0, v->max_partial_swath_y);
+ v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k]
+ + v->max_partial_swath_y;
+ if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_32
+ && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
+ v->v_init_pre_fill_c[k] = dcn_bw_floor2(
+ (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0
+ + v->interlace_output[k] * 0.5
+ * v->v_ratio[k] / 2.0)
+ / 2.0,
+ 1.0);
+ v->max_num_swath_c[k] = dcn_bw_ceil2(
+ (v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k],
+ 1.0) + 1;
+ if (v->v_init_pre_fill_c[k] > 1.0) {
+ v->max_partial_swath_c = dcn_bw_mod(
+ (v->v_init_pre_fill_c[k] - 2.0),
+ v->swath_height_c[k]);
+ } else {
+ v->max_partial_swath_c = dcn_bw_mod(
+ (v->v_init_pre_fill_c[k] + v->swath_height_c[k]
+ - 2.0),
+ v->swath_height_c[k]);
+ }
+ v->max_partial_swath_c = dcn_bw_max2(1.0, v->max_partial_swath_c);
+ } else {
+ v->max_num_swath_c[k] = 0.0;
+ v->max_partial_swath_c = 0.0;
+ }
+ v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k]
+ + v->max_partial_swath_c;
+ }
+ v->t_calc = 24.0 / v->dcf_clk_deep_sleep;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
+ == dcn_bw_yes) {
+ v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
+ } else {
+ v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
+ }
+ }
+ v->next_prefetch_mode = 0.0;
+ do {
+ v->v_startup_lines = 13.0;
+ do {
+ v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw =
+ dcn_bw_yes;
+ v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 =
+ dcn_bw_no;
+ v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 =
+ dcn_bw_no;
+ v->v_ratio_prefetch_more_than4 = dcn_bw_no;
+ v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
+ v->prefetch_mode = v->next_prefetch_mode;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk
+ + 42.0 * v->pixel_clock[k] / v->dispclk;
+ if (v->dpp_per_plane[k] > 1.0) {
+ v->dstx_after_scaler = v->dstx_after_scaler
+ + v->scaler_rec_out_width[k] / 2.0;
+ }
+ if (v->output_format[k] == dcn_bw_420) {
+ v->dsty_after_scaler = 1.0;
+ } else {
+ v->dsty_after_scaler = 0.0;
+ }
+ v->v_update_offset_pix = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
+ v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters
+ * (2.0 / v->dppclk + 3.0 / v->dispclk);
+ v->v_update_width_pix = (14.0 / v->dcf_clk_deep_sleep
+ + 12.0 / v->dppclk + v->total_repeater_delay_time)
+ * v->pixel_clock[k];
+ v->v_ready_offset_pix = dcn_bw_max2(
+ 150.0 / v->dppclk,
+ v->total_repeater_delay_time
+ + 20.0 / v->dcf_clk_deep_sleep
+ + 10.0 / v->dppclk)
+ * v->pixel_clock[k];
+ v->t_setup = (v->v_update_offset_pix + v->v_update_width_pix
+ + v->v_ready_offset_pix) / v->pixel_clock[k];
+ v->v_startup[k] = dcn_bw_min2(
+ v->v_startup_lines,
+ v->max_vstartup_lines[k]);
+ if (v->prefetch_mode == 0.0) {
+ v->t_wait = dcn_bw_max3(
+ v->dram_clock_change_latency
+ + v->urgent_latency,
+ v->sr_enter_plus_exit_time,
+ v->urgent_latency);
+ } else if (v->prefetch_mode == 1.0) {
+ v->t_wait = dcn_bw_max2(
+ v->sr_enter_plus_exit_time,
+ v->urgent_latency);
+ } else {
+ v->t_wait = v->urgent_latency;
+ }
+ v->destination_lines_for_prefetch[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->v_startup[k]
+ - v->t_wait
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ - (v->t_calc
+ + v->t_setup)
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ - (v->dsty_after_scaler
+ + v->dstx_after_scaler
+ / v->htotal[k])
+ + 0.125),
+ 1.0) / 4;
+ if (v->destination_lines_for_prefetch[k] > 0.0) {
+ v->prefetch_bandwidth[k] =
+ (v->meta_pte_bytes_frame[k]
+ + 2.0 * v->meta_row_byte[k]
+ + 2.0
+ * v->pixel_pte_bytes_per_row[k]
+ + v->prefetch_source_lines_y[k]
+ * v->swath_width_y[k]
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_dety[k],
+ 1.0)
+ + v->prefetch_source_lines_c[k]
+ * v->swath_width_y[k]
+ / 2.0
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_detc[k],
+ 2.0))
+ / (v->destination_lines_for_prefetch[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]);
+ } else {
+ v->prefetch_bandwidth[k] = 999999.0;
+ }
+ }
+ v->bandwidth_available_for_immediate_flip = v->return_bw;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->bandwidth_available_for_immediate_flip =
+ v->bandwidth_available_for_immediate_flip
+ - dcn_bw_max2(
+ v->read_bandwidth_plane_luma[k]
+ + v->read_bandwidth_plane_chroma[k],
+ v->prefetch_bandwidth[k]);
+ }
+ v->tot_immediate_flip_bytes = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->immediate_flip_supported == dcn_bw_yes
+ && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_10)) {
+ v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes
+ + v->meta_pte_bytes_frame[k]
+ + v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k];
+ }
+ }
+ v->max_rd_bandwidth = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
+ if (v->immediate_flip_supported == dcn_bw_yes
+ && (v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_10)) {
+ v->time_for_fetching_meta_pte =
+ dcn_bw_max5(
+ v->meta_pte_bytes_frame[k]
+ / v->prefetch_bandwidth[k],
+ v->meta_pte_bytes_frame[k]
+ * v->tot_immediate_flip_bytes
+ / (v->bandwidth_available_for_immediate_flip
+ * (v->meta_pte_bytes_frame[k]
+ + v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])),
+ v->urgent_extra_latency,
+ v->urgent_latency,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ / 4.0);
+ } else {
+ v->time_for_fetching_meta_pte =
+ dcn_bw_max3(
+ v->meta_pte_bytes_frame[k]
+ / v->prefetch_bandwidth[k],
+ v->urgent_extra_latency,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ / 4.0);
+ }
+ } else {
+ v->time_for_fetching_meta_pte = v->htotal[k]
+ / v->pixel_clock[k] / 4.0;
+ }
+ v->destination_lines_to_request_vm_inv_blank[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_fetching_meta_pte
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
+ if (v->immediate_flip_supported == dcn_bw_yes
+ && (v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_10)) {
+ v->time_for_fetching_row_in_vblank =
+ dcn_bw_max5(
+ (v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])
+ / v->prefetch_bandwidth[k],
+ (v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])
+ * v->tot_immediate_flip_bytes
+ / (v->bandwidth_available_for_immediate_flip
+ * (v->meta_pte_bytes_frame[k]
+ + v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])),
+ v->urgent_extra_latency,
+ 2.0
+ * v->urgent_latency,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_fetching_meta_pte);
+ } else {
+ v->time_for_fetching_row_in_vblank =
+ dcn_bw_max3(
+ (v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])
+ / v->prefetch_bandwidth[k],
+ v->urgent_extra_latency,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_fetching_meta_pte);
+ }
+ } else {
+ v->time_for_fetching_row_in_vblank =
+ dcn_bw_max2(
+ v->urgent_extra_latency
+ - v->time_for_fetching_meta_pte,
+ v->htotal[k]
+ / v->pixel_clock[k]
+ - v->time_for_fetching_meta_pte);
+ }
+ v->destination_lines_to_request_row_in_vblank[k] =
+ dcn_bw_floor2(
+ 4.0
+ * (v->time_for_fetching_row_in_vblank
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ + 0.125),
+ 1.0) / 4;
+ v->lines_to_request_prefetch_pixel_data =
+ v->destination_lines_for_prefetch[k]
+ - v->destination_lines_to_request_vm_inv_blank[k]
+ - v->destination_lines_to_request_row_in_vblank[k];
+ if (v->lines_to_request_prefetch_pixel_data > 0.0) {
+ v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k]
+ / v->lines_to_request_prefetch_pixel_data;
+ if ((v->swath_height_y[k] > 4.0)) {
+ if (v->lines_to_request_prefetch_pixel_data
+ > (v->v_init_pre_fill_y[k] - 3.0)
+ / 2.0) {
+ v->v_ratio_prefetch_y[k] =
+ dcn_bw_max2(
+ v->v_ratio_prefetch_y[k],
+ v->max_num_swath_y[k]
+ * v->swath_height_y[k]
+ / (v->lines_to_request_prefetch_pixel_data
+ - (v->v_init_pre_fill_y[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_prefetch_y[k] = 999999.0;
+ }
+ }
+ } else {
+ v->v_ratio_prefetch_y[k] = 999999.0;
+ }
+ v->v_ratio_prefetch_y[k] = dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
+ if (v->lines_to_request_prefetch_pixel_data > 0.0) {
+ v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k]
+ / v->lines_to_request_prefetch_pixel_data;
+ if ((v->swath_height_c[k] > 4.0)) {
+ if (v->lines_to_request_prefetch_pixel_data
+ > (v->v_init_pre_fill_c[k] - 3.0)
+ / 2.0) {
+ v->v_ratio_prefetch_c[k] =
+ dcn_bw_max2(
+ v->v_ratio_prefetch_c[k],
+ v->max_num_swath_c[k]
+ * v->swath_height_c[k]
+ / (v->lines_to_request_prefetch_pixel_data
+ - (v->v_init_pre_fill_c[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->v_ratio_prefetch_c[k] = 999999.0;
+ }
+ }
+ } else {
+ v->v_ratio_prefetch_c[k] = 999999.0;
+ }
+ v->v_ratio_prefetch_c[k] = dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
+ if (v->lines_to_request_prefetch_pixel_data > 0.0) {
+ v->required_prefetch_pix_data_bw =
+ v->dpp_per_plane[k]
+ * (v->prefetch_source_lines_y[k]
+ / v->lines_to_request_prefetch_pixel_data
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_dety[k],
+ 1.0)
+ + v->prefetch_source_lines_c[k]
+ / v->lines_to_request_prefetch_pixel_data
+ * dcn_bw_ceil2(
+ v->byte_per_pixel_detc[k],
+ 2.0)
+ / 2.0)
+ * v->swath_width_y[k]
+ / (v->htotal[k]
+ / v->pixel_clock[k]);
+ } else {
+ v->required_prefetch_pix_data_bw = 999999.0;
+ }
+ v->max_rd_bandwidth =
+ v->max_rd_bandwidth
+ + dcn_bw_max2(
+ v->read_bandwidth_plane_luma[k]
+ + v->read_bandwidth_plane_chroma[k],
+ v->required_prefetch_pix_data_bw);
+ if (v->immediate_flip_supported == dcn_bw_yes
+ && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8
+ && v->source_pixel_format[k]
+ != dcn_bw_yuv420_sub_10)) {
+ v->max_rd_bandwidth =
+ v->max_rd_bandwidth
+ + dcn_bw_max2(
+ v->meta_pte_bytes_frame[k]
+ / (v->destination_lines_to_request_vm_inv_blank[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]),
+ (v->meta_row_byte[k]
+ + v->pixel_pte_bytes_per_row[k])
+ / (v->destination_lines_to_request_row_in_vblank[k]
+ * v->htotal[k]
+ / v->pixel_clock[k]));
+ }
+ if (v->v_ratio_prefetch_y[k] > 4.0
+ || v->v_ratio_prefetch_c[k] > 4.0) {
+ v->v_ratio_prefetch_more_than4 = dcn_bw_yes;
+ }
+ if (v->destination_lines_for_prefetch[k] < 2.0) {
+ v->destination_line_times_for_prefetch_less_than2 =
+ dcn_bw_yes;
+ }
+ if (v->max_vstartup_lines[k] > v->v_startup_lines) {
+ if (v->required_prefetch_pix_data_bw
+ > (v->read_bandwidth_plane_luma[k]
+ + v->read_bandwidth_plane_chroma[k])) {
+ v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw =
+ dcn_bw_no;
+ }
+ if (v->v_ratio_prefetch_y[k] > 4.0
+ || v->v_ratio_prefetch_c[k] > 4.0) {
+ v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 =
+ dcn_bw_yes;
+ }
+ if (v->destination_lines_for_prefetch[k] < 2.0) {
+ v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 =
+ dcn_bw_yes;
+ }
+ }
+ }
+ if (v->max_rd_bandwidth <= v->return_bw
+ && v->v_ratio_prefetch_more_than4 == dcn_bw_no
+ && v->destination_line_times_for_prefetch_less_than2
+ == dcn_bw_no) {
+ v->prefetch_mode_supported = dcn_bw_yes;
+ } else {
+ v->prefetch_mode_supported = dcn_bw_no;
+ }
+ v->v_startup_lines = v->v_startup_lines + 1.0;
+ } while (!(v->prefetch_mode_supported == dcn_bw_yes
+ || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw
+ == dcn_bw_yes
+ && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4
+ == dcn_bw_no
+ && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2
+ == dcn_bw_no)));
+ v->next_prefetch_mode = v->next_prefetch_mode + 1.0;
+ } while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0));
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->v_ratio_prefetch_y[k] <= 1.0) {
+ v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k]
+ * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
+ } else {
+ v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k]
+ / v->pscl_throughput[k] / v->dppclk;
+ }
+ if (v->byte_per_pixel_detc[k] == 0.0) {
+ v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
+ } else {
+ if (v->v_ratio_prefetch_c[k] <= 1.0) {
+ v->display_pipe_line_delivery_time_chroma_prefetch[k] =
+ v->swath_width_y[k] * v->dpp_per_plane[k]
+ / v->h_ratio[k] / v->pixel_clock[k];
+ } else {
+ v->display_pipe_line_delivery_time_chroma_prefetch[k] =
+ v->swath_width_y[k] / v->pscl_throughput[k]
+ / v->dppclk;
+ }
+ }
+ }
+ /*min ttuv_blank*/
+
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->prefetch_mode == 0.0) {
+ v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
+ v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
+ v->min_ttuv_blank[k] = v->t_calc
+ + dcn_bw_max3(
+ v->dram_clock_change_watermark,
+ v->stutter_enter_plus_exit_watermark,
+ v->urgent_watermark);
+ } else if (v->prefetch_mode == 1.0) {
+ v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
+ v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
+ v->min_ttuv_blank[k] = v->t_calc
+ + dcn_bw_max2(
+ v->stutter_enter_plus_exit_watermark,
+ v->urgent_watermark);
+ } else {
+ v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
+ v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
+ v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
+ }
+ }
+ /*nb p-state/dram clock change support*/
+
+ v->active_dp_ps = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ v->lb_latency_hiding_source_lines_y =
+ dcn_bw_min2(
+ v->max_line_buffer_lines,
+ dcn_bw_floor2(
+ v->line_buffer_size
+ / v->lb_bit_per_pixel[k]
+ / (v->swath_width_y[k]
+ / dcn_bw_max2(
+ v->h_ratio[k],
+ 1.0)),
+ 1.0)) - (v->vtaps[k] - 1.0);
+ v->lb_latency_hiding_source_lines_c =
+ dcn_bw_min2(
+ v->max_line_buffer_lines,
+ dcn_bw_floor2(
+ v->line_buffer_size
+ / v->lb_bit_per_pixel[k]
+ / (v->swath_width_y[k]
+ / 2.0
+ / dcn_bw_max2(
+ v->h_ratio[k]
+ / 2.0,
+ 1.0)),
+ 1.0)) - (v->vta_pschroma[k] - 1.0);
+ v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y
+ / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
+ v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c
+ / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
+ if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
+ v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels
+ / v->swath_width_y[k];
+ } else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
+ v->dpp_output_buffer_lines_y = 0.5;
+ } else {
+ v->dpp_output_buffer_lines_y = 1.0;
+ }
+ if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
+ v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels
+ / (v->swath_width_y[k] / 2.0);
+ } else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
+ v->dpp_output_buffer_lines_c = 0.5;
+ } else {
+ v->dpp_output_buffer_lines_c = 1.0;
+ }
+ v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k])
+ * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
+ v->max_det_buffering_time_y = v->full_det_buffering_time_y[k]
+ + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k])
+ / v->swath_height_y[k]
+ * (v->htotal[k] / v->pixel_clock[k]);
+ v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y
+ + v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y
+ - v->dram_clock_change_watermark;
+ if (v->active_dp_ps > 1.0) {
+ v->active_dram_clock_change_latency_margin_y =
+ v->active_dram_clock_change_latency_margin_y
+ - (1.0 - 1.0 / (v->active_dp_ps - 1.0))
+ * v->swath_height_y[k]
+ * (v->htotal[k]
+ / v->pixel_clock[k]);
+ }
+ if (v->byte_per_pixel_detc[k] > 0.0) {
+ v->dppopp_buffering_c =
+ (v->htotal[k] / v->pixel_clock[k])
+ * (v->dpp_output_buffer_lines_c
+ + v->opp_output_buffer_lines);
+ v->max_det_buffering_time_c = v->full_det_buffering_time_c[k]
+ + (v->lines_in_detc[k]
+ - v->lines_in_detc_rounded_down_to_swath[k])
+ / v->swath_height_c[k]
+ * (v->htotal[k] / v->pixel_clock[k]);
+ v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c
+ + v->effective_lb_latency_hiding_c
+ + v->max_det_buffering_time_c
+ - v->dram_clock_change_watermark;
+ if (v->active_dp_ps > 1.0) {
+ v->active_dram_clock_change_latency_margin_c =
+ v->active_dram_clock_change_latency_margin_c
+ - (1.0
+ - 1.0
+ / (v->active_dp_ps
+ - 1.0))
+ * v->swath_height_c[k]
+ * (v->htotal[k]
+ / v->pixel_clock[k]);
+ }
+ v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(
+ v->active_dram_clock_change_latency_margin_y,
+ v->active_dram_clock_change_latency_margin_c);
+ } else {
+ v->active_dram_clock_change_latency_margin[k] =
+ v->active_dram_clock_change_latency_margin_y;
+ }
+ if (v->output_format[k] == dcn_bw_444) {
+ v->writeback_dram_clock_change_latency_margin =
+ (v->writeback_luma_buffer_size
+ + v->writeback_chroma_buffer_size) * 1024.0
+ / (v->scaler_rec_out_width[k]
+ / (v->htotal[k]
+ / v->pixel_clock[k])
+ * 4.0)
+ - v->writeback_dram_clock_change_watermark;
+ } else {
+ v->writeback_dram_clock_change_latency_margin = dcn_bw_min2(
+ v->writeback_luma_buffer_size,
+ 2.0 * v->writeback_chroma_buffer_size) * 1024.0
+ / (v->scaler_rec_out_width[k]
+ / (v->htotal[k] / v->pixel_clock[k]))
+ - v->writeback_dram_clock_change_watermark;
+ }
+ if (v->output[k] == dcn_bw_writeback) {
+ v->active_dram_clock_change_latency_margin[k] = dcn_bw_min2(
+ v->active_dram_clock_change_latency_margin[k],
+ v->writeback_dram_clock_change_latency_margin);
+ }
+ }
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
+ v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k]
+ - v->scaler_recout_height[k])
+ * (v->htotal[k] / v->pixel_clock[k])
+ - dcn_bw_max2(
+ v->dram_clock_change_watermark,
+ v->writeback_dram_clock_change_watermark);
+ } else {
+ v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
+ }
+ }
+ v->min_active_dram_clock_change_margin = 999999.0;
+ v->v_blank_of_min_active_dram_clock_change_margin = 999999.0;
+ v->second_min_active_dram_clock_change_margin = 999999.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->active_dram_clock_change_latency_margin[k]
+ < v->min_active_dram_clock_change_margin) {
+ v->second_min_active_dram_clock_change_margin =
+ v->min_active_dram_clock_change_margin;
+ v->min_active_dram_clock_change_margin =
+ v->active_dram_clock_change_latency_margin[k];
+ v->v_blank_of_min_active_dram_clock_change_margin =
+ v->v_blank_dram_clock_change_latency_margin[k];
+ } else if (v->active_dram_clock_change_latency_margin[k]
+ < v->second_min_active_dram_clock_change_margin) {
+ v->second_min_active_dram_clock_change_margin =
+ v->active_dram_clock_change_latency_margin[k];
+ }
+ }
+ v->min_vblank_dram_clock_change_margin = 999999.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->min_vblank_dram_clock_change_margin
+ > v->v_blank_dram_clock_change_latency_margin[k]) {
+ v->min_vblank_dram_clock_change_margin =
+ v->v_blank_dram_clock_change_latency_margin[k];
+ }
+ }
+ if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
+ v->dram_clock_change_margin = dcn_bw_max2(
+ v->min_active_dram_clock_change_margin,
+ v->min_vblank_dram_clock_change_margin);
+ } else if (v->v_blank_of_min_active_dram_clock_change_margin
+ > v->min_active_dram_clock_change_margin) {
+ v->dram_clock_change_margin = dcn_bw_min2(
+ v->second_min_active_dram_clock_change_margin,
+ v->v_blank_of_min_active_dram_clock_change_margin);
+ } else {
+ v->dram_clock_change_margin = v->min_active_dram_clock_change_margin;
+ }
+ if (v->min_active_dram_clock_change_margin > 0.0) {
+ v->dram_clock_change_support = dcn_bw_supported_in_v_active;
+ } else if (v->dram_clock_change_margin > 0.0) {
+ v->dram_clock_change_support = dcn_bw_supported_in_v_blank;
+ } else {
+ v->dram_clock_change_support = dcn_bw_not_supported;
+ }
+ /*maximum bandwidth used*/
+
+ v->wr_bandwidth = 0.0;
+ for (k = 0; k <= v->number_of_active_planes - 1; k++) {
+ if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
+ v->wr_bandwidth = v->wr_bandwidth
+ + v->scaler_rec_out_width[k]
+ / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
+ } else if (v->output[k] == dcn_bw_writeback) {
+ v->wr_bandwidth = v->wr_bandwidth
+ + v->scaler_rec_out_width[k]
+ / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
+ }
+ }
+ v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
new file mode 100644
index 0000000..03f06f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN_CALC_AUTO_H_
+#define _DCN_CALC_AUTO_H_
+
+#include "dcn_calcs.h"
+
+void scaler_settings_calculation(struct dcn_bw_internal_vars *v);
+void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v);
+void display_pipe_configuration(struct dcn_bw_internal_vars *v);
+void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(
+ struct dcn_bw_internal_vars *v);
+
+#endif /* _DCN_CALC_AUTO_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
new file mode 100644
index 0000000..a184744
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn_calc_math.h"
+
+float dcn_bw_mod(const float arg1, const float arg2)
+{
+ return arg1 - arg1 * ((int) (arg1 / arg2));
+}
+
+float dcn_bw_min2(const float arg1, const float arg2)
+{
+ return arg1 < arg2 ? arg1 : arg2;
+}
+
+unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2)
+{
+ return arg1 > arg2 ? arg1 : arg2;
+}
+float dcn_bw_max2(const float arg1, const float arg2)
+{
+ return arg1 > arg2 ? arg1 : arg2;
+}
+
+float dcn_bw_floor2(const float arg, const float significance)
+{
+ if (significance == 0)
+ return 0;
+ return ((int) (arg / significance)) * significance;
+}
+
+float dcn_bw_ceil2(const float arg, const float significance)
+{
+ float flr = dcn_bw_floor2(arg, significance);
+ if (significance == 0)
+ return 0;
+ return flr + 0.00001 >= arg ? arg : flr + significance;
+}
+
+float dcn_bw_max3(float v1, float v2, float v3)
+{
+ return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2);
+}
+
+float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)
+{
+ return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);
+}
+
+float dcn_bw_pow(float a, float exp)
+{
+ float temp;
+ /*ASSERT(exp == (int)exp);*/
+ if ((int)exp == 0)
+ return 1;
+ temp = dcn_bw_pow(a, (int)(exp / 2));
+ if (((int)exp % 2) == 0) {
+ return temp * temp;
+ } else {
+ if ((int)exp > 0)
+ return a * temp * temp;
+ else
+ return (temp * temp) / a;
+ }
+}
+
+float dcn_bw_log(float a, float b)
+{
+ int * const exp_ptr = (int *)(&a);
+ int x = *exp_ptr;
+ const int log_2 = ((x >> 23) & 255) - 128;
+ x &= ~(255 << 23);
+ x += 127 << 23;
+ *exp_ptr = x;
+
+ a = ((-1.0f / 3) * a + 2) * a - 2.0f / 3;
+
+ if (b > 2.00001 || b < 1.99999)
+ return (a + log_2) / dcn_bw_log(b, 2);
+ else
+ return (a + log_2);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
new file mode 100644
index 0000000..f46ab0e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN_CALC_MATH_H_
+#define _DCN_CALC_MATH_H_
+
+float dcn_bw_mod(const float arg1, const float arg2);
+float dcn_bw_min2(const float arg1, const float arg2);
+unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2);
+float dcn_bw_max2(const float arg1, const float arg2);
+float dcn_bw_floor2(const float arg, const float significance);
+float dcn_bw_ceil2(const float arg, const float significance);
+float dcn_bw_max3(float v1, float v2, float v3);
+float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
+float dcn_bw_pow(float a, float exp);
+float dcn_bw_log(float a, float b);
+
+#endif /* _DCN_CALC_MATH_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
new file mode 100644
index 0000000..eb81edf
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -0,0 +1,1366 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn_calcs.h"
+#include "dcn_calc_auto.h"
+#include "dc.h"
+#include "core_dc.h"
+#include "dal_asic_id.h"
+
+#include "resource.h"
+#include "dcn10/dcn10_resource.h"
+#include "dcn_calc_math.h"
+
+/* Defaults from spreadsheet rev#247 */
+const struct dcn_soc_bounding_box dcn10_soc_defaults = {
+ .sr_exit_time = 17, /*us*/ /*update based on HW Request for 118773*/
+ .sr_enter_plus_exit_time = 19, /*us*/
+ .urgent_latency = 4, /*us*/
+ .write_back_latency = 12, /*us*/
+ .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
+ .max_request_size = 256, /*bytes*/
+ .dcfclkv_max0p9 = 600, /*MHz*/
+ .dcfclkv_nom0p8 = 600, /*MHz*/
+ .dcfclkv_mid0p72 = 300, /*MHz*/
+ .dcfclkv_min0p65 = 300, /*MHz*/
+ .max_dispclk_vmax0p9 = 1086, /*MHz*/
+ .max_dispclk_vnom0p8 = 661, /*MHz*/
+ .max_dispclk_vmid0p72 = 608, /*MHz*/
+ .max_dispclk_vmin0p65 = 608, /*MHz*/
+ .max_dppclk_vmax0p9 = 661, /*MHz*/
+ .max_dppclk_vnom0p8 = 661, /*MHz*/
+ .max_dppclk_vmid0p72 = 435, /*MHz*/
+ .max_dppclk_vmin0p65 = 435, /*MHz*/
+ .socclk = 208, /*MHz*/
+ .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
+ .fabric_and_dram_bandwidth_vnom0p8 = 34.1f, /*GB/s*/
+ .fabric_and_dram_bandwidth_vmid0p72 = 29.8f, /*GB/s*/
+ .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
+ .phyclkv_max0p9 = 810, /*MHz*/
+ .phyclkv_nom0p8 = 810, /*MHz*/
+ .phyclkv_mid0p72 = 540, /*MHz*/
+ .phyclkv_min0p65 = 540, /*MHz*/
+ .downspreading = 0.5f, /*%*/
+ .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
+ .urgent_out_of_order_return_per_channel = 256, /*bytes*/
+ .number_of_channels = 2,
+ .vmm_page_size = 4096, /*bytes*/
+ .dram_clock_change_latency = 17, /*us*/
+ .return_bus_width = 64, /*bytes*/
+};
+
+const struct dcn_ip_params dcn10_ip_defaults = {
+ .rob_buffer_size_in_kbyte = 64,
+ .det_buffer_size_in_kbyte = 164,
+ .dpp_output_buffer_pixels = 2560,
+ .opp_output_buffer_lines = 1,
+ .pixel_chunk_size_in_kbyte = 8,
+ .pte_enable = dcn_bw_yes,
+ .pte_chunk_size = 2, /*kbytes*/
+ .meta_chunk_size = 2, /*kbytes*/
+ .writeback_chunk_size = 2, /*kbytes*/
+ .odm_capability = dcn_bw_no,
+ .dsc_capability = dcn_bw_no,
+ .line_buffer_size = 589824, /*bit*/
+ .max_line_buffer_lines = 12,
+ .is_line_buffer_bpp_fixed = dcn_bw_no,
+ .line_buffer_fixed_bpp = dcn_bw_na,
+ .writeback_luma_buffer_size = 12, /*kbytes*/
+ .writeback_chroma_buffer_size = 8, /*kbytes*/
+ .max_num_dpp = 4,
+ .max_num_writeback = 2,
+ .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
+ .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
+ .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
+ .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
+ .max_hscl_ratio = 4,
+ .max_vscl_ratio = 4,
+ .max_hscl_taps = 8,
+ .max_vscl_taps = 8,
+ .pte_buffer_size_in_requests = 42,
+ .dispclk_ramping_margin = 1, /*%*/
+ .under_scan_factor = 1.11f,
+ .max_inter_dcn_tile_repeaters = 8,
+ .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
+ .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
+ .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
+};
+
+static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
+{
+ switch (sw_mode) {
+ case DC_SW_LINEAR:
+ return dcn_bw_sw_linear;
+ case DC_SW_4KB_S:
+ return dcn_bw_sw_4_kb_s;
+ case DC_SW_4KB_D:
+ return dcn_bw_sw_4_kb_d;
+ case DC_SW_64KB_S:
+ return dcn_bw_sw_64_kb_s;
+ case DC_SW_64KB_D:
+ return dcn_bw_sw_64_kb_d;
+ case DC_SW_VAR_S:
+ return dcn_bw_sw_var_s;
+ case DC_SW_VAR_D:
+ return dcn_bw_sw_var_d;
+ case DC_SW_64KB_S_T:
+ return dcn_bw_sw_64_kb_s_t;
+ case DC_SW_64KB_D_T:
+ return dcn_bw_sw_64_kb_d_t;
+ case DC_SW_4KB_S_X:
+ return dcn_bw_sw_4_kb_s_x;
+ case DC_SW_4KB_D_X:
+ return dcn_bw_sw_4_kb_d_x;
+ case DC_SW_64KB_S_X:
+ return dcn_bw_sw_64_kb_s_x;
+ case DC_SW_64KB_D_X:
+ return dcn_bw_sw_64_kb_d_x;
+ case DC_SW_VAR_S_X:
+ return dcn_bw_sw_var_s_x;
+ case DC_SW_VAR_D_X:
+ return dcn_bw_sw_var_d_x;
+ case DC_SW_256B_S:
+ case DC_SW_256_D:
+ case DC_SW_256_R:
+ case DC_SW_4KB_R:
+ case DC_SW_64KB_R:
+ case DC_SW_VAR_R:
+ case DC_SW_4KB_R_X:
+ case DC_SW_64KB_R_X:
+ case DC_SW_VAR_R_X:
+ default:
+ BREAK_TO_DEBUGGER(); /*not in formula*/
+ return dcn_bw_sw_4_kb_s;
+ }
+}
+
+static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
+{
+ switch (depth) {
+ case LB_PIXEL_DEPTH_18BPP:
+ return 18;
+ case LB_PIXEL_DEPTH_24BPP:
+ return 24;
+ case LB_PIXEL_DEPTH_30BPP:
+ return 30;
+ case LB_PIXEL_DEPTH_36BPP:
+ return 36;
+ default:
+ return 30;
+ }
+}
+
+static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
+{
+ switch (format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+ return dcn_bw_rgb_sub_16;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
+ return dcn_bw_rgb_sub_32;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+ return dcn_bw_rgb_sub_64;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
+ return dcn_bw_yuv420_sub_8;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
+ return dcn_bw_yuv420_sub_10;
+ default:
+ return dcn_bw_rgb_sub_32;
+ }
+}
+
+static void pipe_ctx_to_e2e_pipe_params (
+ const struct pipe_ctx *pipe,
+ struct _vcs_dpi_display_pipe_params_st *input)
+{
+ input->src.is_hsplit = false;
+ if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface)
+ input->src.is_hsplit = true;
+ else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface)
+ input->src.is_hsplit = true;
+
+ input->src.dcc = pipe->surface->public.dcc.enable;
+ input->src.dcc_rate = 1;
+ input->src.meta_pitch = pipe->surface->public.dcc.grph.meta_pitch;
+ input->src.source_scan = dm_horz;
+ input->src.sw_mode = pipe->surface->public.tiling_info.gfx9.swizzle;
+
+ input->src.viewport_width = pipe->scl_data.viewport.width;
+ input->src.viewport_height = pipe->scl_data.viewport.height;
+ input->src.data_pitch = pipe->scl_data.viewport.width;
+ input->src.data_pitch_c = pipe->scl_data.viewport.width;
+ input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
+ input->src.cur0_bpp = 32;
+
+ switch (pipe->surface->public.tiling_info.gfx9.swizzle) {
+ /* for 4/8/16 high tiles */
+ case DC_SW_LINEAR:
+ input->src.is_display_sw = 1;
+ input->src.macro_tile_size = dm_4k_tile;
+ break;
+ case DC_SW_4KB_S:
+ case DC_SW_4KB_S_X:
+ input->src.is_display_sw = 0;
+ input->src.macro_tile_size = dm_4k_tile;
+ break;
+ case DC_SW_64KB_S:
+ case DC_SW_64KB_S_X:
+ input->src.is_display_sw = 0;
+ input->src.macro_tile_size = dm_64k_tile;
+ break;
+ case DC_SW_VAR_S:
+ case DC_SW_VAR_S_X:
+ input->src.is_display_sw = 0;
+ input->src.macro_tile_size = dm_256k_tile;
+ break;
+
+ /* For 64bpp 2 high tiles */
+ case DC_SW_4KB_D:
+ case DC_SW_4KB_D_X:
+ input->src.is_display_sw = 1;
+ input->src.macro_tile_size = dm_4k_tile;
+ break;
+ case DC_SW_64KB_D:
+ case DC_SW_64KB_D_X:
+ input->src.is_display_sw = 1;
+ input->src.macro_tile_size = dm_64k_tile;
+ break;
+ case DC_SW_VAR_D:
+ case DC_SW_VAR_D_X:
+ input->src.is_display_sw = 1;
+ input->src.macro_tile_size = dm_256k_tile;
+ break;
+
+ /* Unsupported swizzle modes for dcn */
+ case DC_SW_256B_S:
+ default:
+ ASSERT(0); /* Not supported */
+ break;
+ }
+
+ switch (pipe->surface->public.rotation) {
+ case ROTATION_ANGLE_0:
+ case ROTATION_ANGLE_180:
+ input->src.source_scan = dm_horz;
+ break;
+ case ROTATION_ANGLE_90:
+ case ROTATION_ANGLE_270:
+ input->src.source_scan = dm_vert;
+ break;
+ default:
+ ASSERT(0); /* Not supported */
+ break;
+ }
+
+ /* TODO: Fix pixel format mappings */
+ switch (pipe->surface->public.format) {
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
+ input->src.source_format = dm_420_8;
+ input->src.viewport_width_c = input->src.viewport_width / 2;
+ input->src.viewport_height_c = input->src.viewport_height / 2;
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
+ input->src.source_format = dm_420_10;
+ input->src.viewport_width_c = input->src.viewport_width / 2;
+ input->src.viewport_height_c = input->src.viewport_height / 2;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+ input->src.source_format = dm_444_64;
+ input->src.viewport_width_c = input->src.viewport_width;
+ input->src.viewport_height_c = input->src.viewport_height;
+ break;
+ default:
+ input->src.source_format = dm_444_32;
+ input->src.viewport_width_c = input->src.viewport_width;
+ input->src.viewport_height_c = input->src.viewport_height;
+ break;
+ }
+
+ input->scale_taps.htaps = pipe->scl_data.taps.h_taps;
+ input->scale_ratio_depth.hscl_ratio = pipe->scl_data.ratios.horz.value/4294967296.0;
+ input->scale_ratio_depth.vscl_ratio = pipe->scl_data.ratios.vert.value/4294967296.0;
+ input->scale_ratio_depth.vinit = pipe->scl_data.inits.v.value/4294967296.0;
+ if (input->scale_ratio_depth.vinit < 1.0)
+ input->scale_ratio_depth.vinit = 1;
+ input->scale_taps.vtaps = pipe->scl_data.taps.v_taps;
+ input->scale_taps.vtaps_c = pipe->scl_data.taps.v_taps_c;
+ input->scale_taps.htaps_c = pipe->scl_data.taps.h_taps_c;
+ input->scale_ratio_depth.hscl_ratio_c = pipe->scl_data.ratios.horz_c.value/4294967296.0;
+ input->scale_ratio_depth.vscl_ratio_c = pipe->scl_data.ratios.vert_c.value/4294967296.0;
+ input->scale_ratio_depth.vinit_c = pipe->scl_data.inits.v_c.value/4294967296.0;
+ if (input->scale_ratio_depth.vinit_c < 1.0)
+ input->scale_ratio_depth.vinit_c = 1;
+ switch (pipe->scl_data.lb_params.depth) {
+ case LB_PIXEL_DEPTH_30BPP:
+ input->scale_ratio_depth.lb_depth = 30; break;
+ case LB_PIXEL_DEPTH_36BPP:
+ input->scale_ratio_depth.lb_depth = 36; break;
+ default:
+ input->scale_ratio_depth.lb_depth = 24; break;
+ }
+
+
+ input->dest.vactive = pipe->stream->public.timing.v_addressable;
+
+ input->dest.recout_width = pipe->scl_data.recout.width;
+ input->dest.recout_height = pipe->scl_data.recout.height;
+
+ input->dest.full_recout_width = pipe->scl_data.recout.width;
+ input->dest.full_recout_height = pipe->scl_data.recout.height;
+
+ input->dest.htotal = pipe->stream->public.timing.h_total;
+ input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch;
+ input->dest.hblank_end = input->dest.hblank_start
+ - pipe->stream->public.timing.h_addressable
+ - pipe->stream->public.timing.h_border_left
+ - pipe->stream->public.timing.h_border_right;
+
+ input->dest.vtotal = pipe->stream->public.timing.v_total;
+ input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch;
+ input->dest.vblank_end = input->dest.vblank_start
+ - pipe->stream->public.timing.v_addressable
+ - pipe->stream->public.timing.v_border_bottom
+ - pipe->stream->public.timing.v_border_top;
+
+ input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total
+ - pipe->stream->public.timing.v_addressable
+ - pipe->stream->public.timing.v_front_porch;
+ input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0;
+ input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
+ input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
+ input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
+ input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
+
+}
+
+static void dcn_bw_calc_rq_dlg_ttu(
+ const struct core_dc *dc,
+ const struct dcn_bw_internal_vars *v,
+ struct pipe_ctx *pipe)
+{
+ struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
+ struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
+ struct _vcs_dpi_display_rq_params_st rq_param = {0};
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
+ struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
+ float total_active_bw = 0;
+ float total_prefetch_bw = 0;
+ int total_flip_bytes = 0;
+ int i;
+
+ for (i = 0; i < number_of_planes; i++) {
+ total_active_bw += v->read_bandwidth[i];
+ total_prefetch_bw += v->prefetch_bandwidth[i];
+ total_flip_bytes += v->total_immediate_flip_bytes[i];
+ }
+ dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
+ if (dlg_sys_param.total_flip_bw < 0.0)
+ dlg_sys_param.total_flip_bw = 0;
+
+ dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
+ dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
+ dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
+ dlg_sys_param.t_extra_us = v->urgent_extra_latency;
+ dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
+ dlg_sys_param.total_flip_bytes = total_flip_bytes;
+
+ pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
+ input.clks_cfg.dcfclk_mhz = v->dcfclk;
+ input.clks_cfg.dispclk_mhz = v->dispclk;
+ input.clks_cfg.dppclk_mhz = v->dppclk;
+ input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+ input.clks_cfg.socclk_mhz = v->socclk;
+ input.clks_cfg.voltage = v->voltage_level;
+// dc->dml.logger = pool->base.logger;
+
+ /*todo: soc->sr_enter_plus_exit_time??*/
+ dlg_sys_param.t_srx_delay_us = dc->dcn_ip.dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
+
+ dml_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
+ extract_rq_regs(dml, rq_regs, rq_param);
+ dml_rq_dlg_get_dlg_params(
+ dml,
+ dlg_regs,
+ ttu_regs,
+ rq_param.dlg,
+ dlg_sys_param,
+ input,
+ true,
+ true,
+ v->pte_enable == dcn_bw_yes,
+ pipe->surface->public.flip_immediate);
+}
+
+static void dcn_dml_wm_override(
+ const struct dcn_bw_internal_vars *v,
+ struct display_mode_lib *dml,
+ struct validate_context *context,
+ const struct resource_pool *pool)
+{
+ int i, in_idx, active_count;
+
+ struct _vcs_dpi_display_e2e_pipe_params_st *input = dm_alloc(pool->pipe_count *
+ sizeof(struct _vcs_dpi_display_e2e_pipe_params_st));
+ struct wm {
+ double urgent;
+ struct _vcs_dpi_cstate_pstate_watermarks_st cpstate;
+ double pte_meta_urgent;
+ } a;
+
+
+ for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream || !pipe->surface)
+ continue;
+
+ input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk;
+ input[in_idx].clks_cfg.dispclk_mhz = v->dispclk;
+ input[in_idx].clks_cfg.dppclk_mhz = v->dppclk;
+ input[in_idx].clks_cfg.refclk_mhz = pool->ref_clock_inKhz / 1000;
+ input[in_idx].clks_cfg.socclk_mhz = v->socclk;
+ input[in_idx].clks_cfg.voltage = v->voltage_level;
+ pipe_ctx_to_e2e_pipe_params(pipe, &input[in_idx].pipe);
+ dml_rq_dlg_get_rq_reg(
+ dml,
+ &pipe->rq_regs,
+ input[in_idx].pipe.src);
+ in_idx++;
+ }
+ active_count = in_idx;
+
+ a.urgent = dml_wm_urgent_e2e(dml, input, active_count);
+ a.cpstate = dml_wm_cstate_pstate_e2e(dml, input, active_count);
+ a.pte_meta_urgent = dml_wm_pte_meta_urgent(dml, a.urgent);
+
+ context->watermarks.a.cstate_pstate.cstate_exit_ns =
+ a.cpstate.cstate_exit_us * 1000;
+ context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ a.cpstate.cstate_enter_plus_exit_us * 1000;
+ context->watermarks.a.cstate_pstate.pstate_change_ns =
+ a.cpstate.pstate_change_us * 1000;
+ context->watermarks.a.pte_meta_urgent_ns = a.pte_meta_urgent * 1000;
+ context->watermarks.a.urgent_ns = a.urgent * 1000;
+ context->watermarks.b = context->watermarks.a;
+ context->watermarks.c = context->watermarks.a;
+ context->watermarks.d = context->watermarks.a;
+
+
+ for (i = 0, in_idx = 0; i < pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream || !pipe->surface)
+ continue;
+
+ dml_rq_dlg_get_dlg_reg(dml,
+ &pipe->dlg_regs,
+ &pipe->ttu_regs,
+ input, active_count,
+ in_idx,
+ true,
+ true,
+ v->pte_enable == dcn_bw_yes,
+ pipe->surface->public.flip_immediate);
+ in_idx++;
+ }
+ dm_free(input);
+}
+
+static void split_stream_across_pipes(
+ struct resource_context *res_ctx,
+ const struct resource_pool *pool,
+ struct pipe_ctx *primary_pipe,
+ struct pipe_ctx *secondary_pipe)
+{
+ if (!primary_pipe->surface)
+ return;
+
+ secondary_pipe->stream = primary_pipe->stream;
+ secondary_pipe->tg = primary_pipe->tg;
+
+ secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx];
+ secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx];
+ secondary_pipe->xfm = pool->transforms[secondary_pipe->pipe_idx];
+ secondary_pipe->opp = pool->opps[secondary_pipe->pipe_idx];
+ if (primary_pipe->bottom_pipe) {
+ secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
+ secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
+ }
+ primary_pipe->bottom_pipe = secondary_pipe;
+ secondary_pipe->top_pipe = primary_pipe;
+ secondary_pipe->surface = primary_pipe->surface;
+ secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param;
+
+ resource_build_scaling_params(primary_pipe);
+ resource_build_scaling_params(secondary_pipe);
+}
+
+static void calc_wm_sets_and_perf_params(
+ struct validate_context *context,
+ struct dcn_bw_internal_vars *v)
+{
+ /* Calculate set A last to keep internal var state consistent for required config */
+ if (v->voltage_level < 2) {
+ v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
+ v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
+ v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+ context->watermarks.b.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+ context->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+ context->watermarks.b.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+ context->watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->watermarks.b.urgent_ns = v->urgent_watermark * 1000;
+
+ v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
+ v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
+ v->dcfclk = v->dcfclkv_nom0p8;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+ context->watermarks.c.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+ context->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+ context->watermarks.c.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+ context->watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->watermarks.c.urgent_ns = v->urgent_watermark * 1000;
+ }
+
+ if (v->voltage_level < 3) {
+ v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
+ v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
+ v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
+ v->dcfclk = v->dcfclkv_max0p9;
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+ context->watermarks.d.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+ context->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+ context->watermarks.d.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+ context->watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->watermarks.d.urgent_ns = v->urgent_watermark * 1000;
+ }
+
+ v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
+ v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
+ v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
+ v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
+ v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
+ v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
+ v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
+ v->dcfclk = v->dcfclk_per_state[v->voltage_level];
+ dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
+
+ context->watermarks.a.cstate_pstate.cstate_exit_ns =
+ v->stutter_exit_watermark * 1000;
+ context->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+ v->stutter_enter_plus_exit_watermark * 1000;
+ context->watermarks.a.cstate_pstate.pstate_change_ns =
+ v->dram_clock_change_watermark * 1000;
+ context->watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
+ context->watermarks.a.urgent_ns = v->urgent_watermark * 1000;
+ if (v->voltage_level >= 2) {
+ context->watermarks.b = context->watermarks.a;
+ context->watermarks.c = context->watermarks.a;
+ }
+ if (v->voltage_level >= 3)
+ context->watermarks.d = context->watermarks.a;
+}
+
+static void dcn_bw_apply_registry_override(struct core_dc *dc)
+{
+ kernel_fpu_begin();
+ if (dc->public.debug.sr_exit_time_ns)
+ dc->dcn_soc.sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0;
+ if (dc->public.debug.sr_enter_plus_exit_time_ns)
+ dc->dcn_soc.sr_enter_plus_exit_time =
+ dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0;
+ if (dc->public.debug.urgent_latency_ns)
+ dc->dcn_soc.urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0;
+ if (dc->public.debug.percent_of_ideal_drambw)
+ dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency =
+ dc->public.debug.percent_of_ideal_drambw;
+ if (dc->public.debug.dram_clock_change_latency_ns)
+ dc->dcn_soc.dram_clock_change_latency =
+ dc->public.debug.dram_clock_change_latency_ns / 1000.0;
+ kernel_fpu_end();
+}
+
+bool dcn_validate_bandwidth(
+ const struct core_dc *dc,
+ struct validate_context *context)
+{
+ const struct resource_pool *pool = dc->res_pool;
+ struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
+ int i, input_idx;
+ int vesa_sync_start, asic_blank_end, asic_blank_start;
+
+ dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public));
+
+ memset(v, 0, sizeof(*v));
+ kernel_fpu_begin();
+ v->sr_exit_time = dc->dcn_soc.sr_exit_time;
+ v->sr_enter_plus_exit_time = dc->dcn_soc.sr_enter_plus_exit_time;
+ v->urgent_latency = dc->dcn_soc.urgent_latency;
+ v->write_back_latency = dc->dcn_soc.write_back_latency;
+ v->percent_of_ideal_drambw_received_after_urg_latency =
+ dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency;
+
+ v->dcfclkv_min0p65 = dc->dcn_soc.dcfclkv_min0p65;
+ v->dcfclkv_mid0p72 = dc->dcn_soc.dcfclkv_mid0p72;
+ v->dcfclkv_nom0p8 = dc->dcn_soc.dcfclkv_nom0p8;
+ v->dcfclkv_max0p9 = dc->dcn_soc.dcfclkv_max0p9;
+
+ v->max_dispclk_vmin0p65 = dc->dcn_soc.max_dispclk_vmin0p65;
+ v->max_dispclk_vmid0p72 = dc->dcn_soc.max_dispclk_vmid0p72;
+ v->max_dispclk_vnom0p8 = dc->dcn_soc.max_dispclk_vnom0p8;
+ v->max_dispclk_vmax0p9 = dc->dcn_soc.max_dispclk_vmax0p9;
+
+ v->max_dppclk_vmin0p65 = dc->dcn_soc.max_dppclk_vmin0p65;
+ v->max_dppclk_vmid0p72 = dc->dcn_soc.max_dppclk_vmid0p72;
+ v->max_dppclk_vnom0p8 = dc->dcn_soc.max_dppclk_vnom0p8;
+ v->max_dppclk_vmax0p9 = dc->dcn_soc.max_dppclk_vmax0p9;
+
+ v->socclk = dc->dcn_soc.socclk;
+
+ v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65;
+ v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72;
+ v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8;
+ v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9;
+
+ v->phyclkv_min0p65 = dc->dcn_soc.phyclkv_min0p65;
+ v->phyclkv_mid0p72 = dc->dcn_soc.phyclkv_mid0p72;
+ v->phyclkv_nom0p8 = dc->dcn_soc.phyclkv_nom0p8;
+ v->phyclkv_max0p9 = dc->dcn_soc.phyclkv_max0p9;
+
+ v->downspreading = dc->dcn_soc.downspreading;
+ v->round_trip_ping_latency_cycles = dc->dcn_soc.round_trip_ping_latency_cycles;
+ v->urgent_out_of_order_return_per_channel = dc->dcn_soc.urgent_out_of_order_return_per_channel;
+ v->number_of_channels = dc->dcn_soc.number_of_channels;
+ v->vmm_page_size = dc->dcn_soc.vmm_page_size;
+ v->dram_clock_change_latency = dc->dcn_soc.dram_clock_change_latency;
+ v->return_bus_width = dc->dcn_soc.return_bus_width;
+
+ v->rob_buffer_size_in_kbyte = dc->dcn_ip.rob_buffer_size_in_kbyte;
+ v->det_buffer_size_in_kbyte = dc->dcn_ip.det_buffer_size_in_kbyte;
+ v->dpp_output_buffer_pixels = dc->dcn_ip.dpp_output_buffer_pixels;
+ v->opp_output_buffer_lines = dc->dcn_ip.opp_output_buffer_lines;
+ v->pixel_chunk_size_in_kbyte = dc->dcn_ip.pixel_chunk_size_in_kbyte;
+ v->pte_enable = dc->dcn_ip.pte_enable;
+ v->pte_chunk_size = dc->dcn_ip.pte_chunk_size;
+ v->meta_chunk_size = dc->dcn_ip.meta_chunk_size;
+ v->writeback_chunk_size = dc->dcn_ip.writeback_chunk_size;
+ v->odm_capability = dc->dcn_ip.odm_capability;
+ v->dsc_capability = dc->dcn_ip.dsc_capability;
+ v->line_buffer_size = dc->dcn_ip.line_buffer_size;
+ v->is_line_buffer_bpp_fixed = dc->dcn_ip.is_line_buffer_bpp_fixed;
+ v->line_buffer_fixed_bpp = dc->dcn_ip.line_buffer_fixed_bpp;
+ v->max_line_buffer_lines = dc->dcn_ip.max_line_buffer_lines;
+ v->writeback_luma_buffer_size = dc->dcn_ip.writeback_luma_buffer_size;
+ v->writeback_chroma_buffer_size = dc->dcn_ip.writeback_chroma_buffer_size;
+ v->max_num_dpp = dc->dcn_ip.max_num_dpp;
+ v->max_num_writeback = dc->dcn_ip.max_num_writeback;
+ v->max_dchub_topscl_throughput = dc->dcn_ip.max_dchub_topscl_throughput;
+ v->max_pscl_tolb_throughput = dc->dcn_ip.max_pscl_tolb_throughput;
+ v->max_lb_tovscl_throughput = dc->dcn_ip.max_lb_tovscl_throughput;
+ v->max_vscl_tohscl_throughput = dc->dcn_ip.max_vscl_tohscl_throughput;
+ v->max_hscl_ratio = dc->dcn_ip.max_hscl_ratio;
+ v->max_vscl_ratio = dc->dcn_ip.max_vscl_ratio;
+ v->max_hscl_taps = dc->dcn_ip.max_hscl_taps;
+ v->max_vscl_taps = dc->dcn_ip.max_vscl_taps;
+ v->under_scan_factor = dc->dcn_ip.under_scan_factor;
+ v->pte_buffer_size_in_requests = dc->dcn_ip.pte_buffer_size_in_requests;
+ v->dispclk_ramping_margin = dc->dcn_ip.dispclk_ramping_margin;
+ v->max_inter_dcn_tile_repeaters = dc->dcn_ip.max_inter_dcn_tile_repeaters;
+ v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
+ dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
+ v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
+ dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed;
+
+ v->voltage[5] = dcn_bw_no_support;
+ v->voltage[4] = dcn_bw_v_max0p9;
+ v->voltage[3] = dcn_bw_v_max0p9;
+ v->voltage[2] = dcn_bw_v_nom0p8;
+ v->voltage[1] = dcn_bw_v_mid0p72;
+ v->voltage[0] = dcn_bw_v_min0p65;
+ v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
+ v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
+ v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
+ v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
+ v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
+ v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
+ v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
+ v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
+ v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
+ v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
+ v->max_dispclk[5] = v->max_dispclk_vmax0p9;
+ v->max_dispclk[4] = v->max_dispclk_vmax0p9;
+ v->max_dispclk[3] = v->max_dispclk_vmax0p9;
+ v->max_dispclk[2] = v->max_dispclk_vnom0p8;
+ v->max_dispclk[1] = v->max_dispclk_vmid0p72;
+ v->max_dispclk[0] = v->max_dispclk_vmin0p65;
+ v->max_dppclk[5] = v->max_dppclk_vmax0p9;
+ v->max_dppclk[4] = v->max_dppclk_vmax0p9;
+ v->max_dppclk[3] = v->max_dppclk_vmax0p9;
+ v->max_dppclk[2] = v->max_dppclk_vnom0p8;
+ v->max_dppclk[1] = v->max_dppclk_vmid0p72;
+ v->max_dppclk[0] = v->max_dppclk_vmin0p65;
+ v->phyclk_per_state[5] = v->phyclkv_max0p9;
+ v->phyclk_per_state[4] = v->phyclkv_max0p9;
+ v->phyclk_per_state[3] = v->phyclkv_max0p9;
+ v->phyclk_per_state[2] = v->phyclkv_nom0p8;
+ v->phyclk_per_state[1] = v->phyclkv_mid0p72;
+ v->phyclk_per_state[0] = v->phyclkv_min0p65;
+
+ if (dc->public.debug.use_max_voltage) {
+ v->max_dppclk[1] = v->max_dppclk_vnom0p8;
+ v->max_dppclk[0] = v->max_dppclk_vnom0p8;
+ }
+
+ if (v->voltage_override == dcn_bw_v_max0p9) {
+ v->voltage_override_level = number_of_states - 1;
+ } else if (v->voltage_override == dcn_bw_v_nom0p8) {
+ v->voltage_override_level = number_of_states - 2;
+ } else if (v->voltage_override == dcn_bw_v_mid0p72) {
+ v->voltage_override_level = number_of_states - 3;
+ } else {
+ v->voltage_override_level = 0;
+ }
+ v->synchronized_vblank = dcn_bw_no;
+ v->ta_pscalculation = dcn_bw_override;
+ v->allow_different_hratio_vratio = dcn_bw_yes;
+
+
+ for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe->stream)
+ continue;
+ /* skip all but first of split pipes */
+ if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+ continue;
+
+ v->underscan_output[input_idx] = false; /* taken care of in recout already*/
+ v->interlace_output[input_idx] = false;
+
+ v->htotal[input_idx] = pipe->stream->public.timing.h_total;
+ v->vtotal[input_idx] = pipe->stream->public.timing.v_total;
+ v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total
+ - pipe->stream->public.timing.v_addressable
+ - pipe->stream->public.timing.v_front_porch;
+ v->vactive[input_idx] = pipe->stream->public.timing.v_addressable;
+ v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f;
+
+
+ if (!pipe->surface){
+ v->dcc_enable[input_idx] = dcn_bw_yes;
+ v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
+ v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
+ v->lb_bit_per_pixel[input_idx] = 30;
+ v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable;
+ v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable;
+ v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable;
+ v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable;
+ v->override_hta_ps[input_idx] = 1;
+ v->override_vta_ps[input_idx] = 1;
+ v->override_hta_pschroma[input_idx] = 1;
+ v->override_vta_pschroma[input_idx] = 1;
+ v->source_scan[input_idx] = dcn_bw_hor;
+
+ } else {
+ v->viewport_height[input_idx] = pipe->scl_data.viewport.height;
+ v->viewport_width[input_idx] = pipe->scl_data.viewport.width;
+ v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width;
+ v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height;
+ if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) {
+ if (pipe->surface->public.rotation % 2 == 0) {
+ int viewport_end = pipe->scl_data.viewport.width
+ + pipe->scl_data.viewport.x;
+ int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width
+ + pipe->bottom_pipe->scl_data.viewport.x;
+
+ if (viewport_end > viewport_b_end)
+ v->viewport_width[input_idx] = viewport_end
+ - pipe->bottom_pipe->scl_data.viewport.x;
+ else
+ v->viewport_width[input_idx] = viewport_b_end
+ - pipe->scl_data.viewport.x;
+ } else {
+ int viewport_end = pipe->scl_data.viewport.height
+ + pipe->scl_data.viewport.y;
+ int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.height
+ + pipe->bottom_pipe->scl_data.viewport.y;
+
+ if (viewport_end > viewport_b_end)
+ v->viewport_height[input_idx] = viewport_end
+ - pipe->bottom_pipe->scl_data.viewport.y;
+ else
+ v->viewport_height[input_idx] = viewport_b_end
+ - pipe->scl_data.viewport.y;
+ }
+ v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width
+ + pipe->bottom_pipe->scl_data.recout.width;
+ }
+
+ v->dcc_enable[input_idx] = pipe->surface->public.dcc.enable ? dcn_bw_yes : dcn_bw_no;
+ v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
+ pipe->surface->public.format);
+ v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
+ pipe->surface->public.tiling_info.gfx9.swizzle);
+ v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth);
+ v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps;
+ v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps;
+ v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c;
+ v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c;
+ v->source_scan[input_idx] = (pipe->surface->public.rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
+ }
+ if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
+ v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
+ v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
+ v->output_format[input_idx] = dcn_bw_444;
+ v->output[input_idx] = dcn_bw_dp;
+
+ input_idx++;
+ }
+ v->number_of_active_planes = input_idx;
+
+ scaler_settings_calculation(v);
+ mode_support_and_system_configuration(v);
+
+ if (v->voltage_level != 5) {
+ float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
+ if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
+ bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
+ else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
+ bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
+ else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
+ bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
+ else
+ bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
+
+ display_pipe_configuration(v);
+ calc_wm_sets_and_perf_params(context, v);
+ context->fclk_khz = (int)(bw_consumed * 1000000 /
+ (ddr4_dram_factor_single_Channel * v->number_of_channels));
+ context->dram_ccm_us = (int)(v->dram_clock_change_margin);
+ context->min_active_dram_ccm_us = (int)(v->min_active_dram_clock_change_margin);
+ context->dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
+ context->dcfclk_khz = (int)(v->dcfclk * 1000);
+ context->dispclk_khz = (int)(v->dispclk * 1000);
+ if (dc->public.debug.max_disp_clk == true)
+ context->dispclk_khz = (int)(dc->dcn_soc.max_dispclk_vmax0p9 * 1000);
+ context->dppclk_khz = (int)(v->dppclk * 1000);
+ context->dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
+
+ for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+
+ /* skip inactive pipe */
+ if (!pipe->stream)
+ continue;
+ /* skip all but first of split pipes */
+ if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface)
+ continue;
+
+ pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
+ pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
+ pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
+ pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
+
+ pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
+ pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
+ vesa_sync_start = pipe->stream->public.timing.v_addressable +
+ pipe->stream->public.timing.v_border_bottom +
+ pipe->stream->public.timing.v_front_porch;
+
+ asic_blank_end = (pipe->stream->public.timing.v_total -
+ vesa_sync_start -
+ pipe->stream->public.timing.v_border_top)
+ * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+
+ asic_blank_start = asic_blank_end +
+ (pipe->stream->public.timing.v_border_top +
+ pipe->stream->public.timing.v_addressable +
+ pipe->stream->public.timing.v_border_bottom)
+ * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+
+ pipe->pipe_dlg_param.vblank_start = asic_blank_start;
+ pipe->pipe_dlg_param.vblank_end = asic_blank_end;
+
+ if (pipe->surface) {
+ struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+
+ if (v->dpp_per_plane[input_idx] == 2 ||
+ (pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+ pipe->stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE)) {
+ if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+ /* update previously split pipe */
+ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
+ hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx];
+ hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
+ hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
+
+ hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
+ hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
+ hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
+ hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
+ } else {
+ /* pipe not split previously needs split */
+ hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool);
+ ASSERT(hsplit_pipe);
+ split_stream_across_pipes(
+ &context->res_ctx, pool,
+ pipe, hsplit_pipe);
+ }
+
+ dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe);
+ } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
+ /* merge previously split pipe */
+ if (pipe->bottom_pipe->bottom_pipe)
+ pipe->bottom_pipe->bottom_pipe->top_pipe = pipe;
+ memset(pipe->bottom_pipe, 0, sizeof(*pipe->bottom_pipe));
+ pipe->bottom_pipe = pipe->bottom_pipe->bottom_pipe;
+ resource_build_scaling_params(pipe);
+ }
+ /* for now important to do this after pipe split for building e2e params */
+ dcn_bw_calc_rq_dlg_ttu(dc, v, pipe);
+ }
+
+ input_idx++;
+ }
+ if (dc->public.debug.use_dml_wm)
+ dcn_dml_wm_override(v, (struct display_mode_lib *)
+ &dc->dml, context, pool);
+ }
+
+ kernel_fpu_end();
+ return v->voltage_level != 5;
+}
+
+unsigned int dcn_find_normalized_clock_vdd_Level(
+ const struct core_dc *dc,
+ enum dm_pp_clock_type clocks_type,
+ int clocks_in_khz)
+{
+ int vdd_level = dcn_bw_v_min0p65;
+
+ if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
+ return vdd_level;
+
+ switch (clocks_type) {
+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
+ if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmax0p9*1000) {
+ vdd_level = dcn_bw_v_max0p91;
+ BREAK_TO_DEBUGGER();
+ } else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vnom0p8*1000) {
+ vdd_level = dcn_bw_v_max0p9;
+ } else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmid0p72*1000) {
+ vdd_level = dcn_bw_v_nom0p8;
+ } else if (clocks_in_khz > dc->dcn_soc.max_dispclk_vmin0p65*1000) {
+ vdd_level = dcn_bw_v_mid0p72;
+ } else
+ vdd_level = dcn_bw_v_min0p65;
+ break;
+ case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
+ if (clocks_in_khz > dc->dcn_soc.phyclkv_max0p9*1000) {
+ vdd_level = dcn_bw_v_max0p91;
+ BREAK_TO_DEBUGGER();
+ } else if (clocks_in_khz > dc->dcn_soc.phyclkv_nom0p8*1000) {
+ vdd_level = dcn_bw_v_max0p9;
+ } else if (clocks_in_khz > dc->dcn_soc.phyclkv_mid0p72*1000) {
+ vdd_level = dcn_bw_v_nom0p8;
+ } else if (clocks_in_khz > dc->dcn_soc.phyclkv_min0p65*1000) {
+ vdd_level = dcn_bw_v_mid0p72;
+ } else
+ vdd_level = dcn_bw_v_min0p65;
+ break;
+
+ case DM_PP_CLOCK_TYPE_DPPCLK:
+ if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmax0p9*1000) {
+ vdd_level = dcn_bw_v_max0p91;
+ BREAK_TO_DEBUGGER();
+ } else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vnom0p8*1000) {
+ vdd_level = dcn_bw_v_max0p9;
+ } else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmid0p72*1000) {
+ vdd_level = dcn_bw_v_nom0p8;
+ } else if (clocks_in_khz > dc->dcn_soc.max_dppclk_vmin0p65*1000) {
+ vdd_level = dcn_bw_v_mid0p72;
+ } else
+ vdd_level = dcn_bw_v_min0p65;
+ break;
+
+ case DM_PP_CLOCK_TYPE_MEMORY_CLK:
+ {
+ unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc.number_of_channels);
+ if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
+ vdd_level = dcn_bw_v_max0p91;
+ BREAK_TO_DEBUGGER();
+ } else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
+ vdd_level = dcn_bw_v_max0p9;
+ } else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
+ vdd_level = dcn_bw_v_nom0p8;
+ } else if (clocks_in_khz > dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
+ vdd_level = dcn_bw_v_mid0p72;
+ } else
+ vdd_level = dcn_bw_v_min0p65;
+ }
+ break;
+
+ case DM_PP_CLOCK_TYPE_DCFCLK:
+ if (clocks_in_khz > dc->dcn_soc.dcfclkv_max0p9*1000) {
+ vdd_level = dcn_bw_v_max0p91;
+ BREAK_TO_DEBUGGER();
+ } else if (clocks_in_khz > dc->dcn_soc.dcfclkv_nom0p8*1000) {
+ vdd_level = dcn_bw_v_max0p9;
+ } else if (clocks_in_khz > dc->dcn_soc.dcfclkv_mid0p72*1000) {
+ vdd_level = dcn_bw_v_nom0p8;
+ } else if (clocks_in_khz > dc->dcn_soc.dcfclkv_min0p65*1000) {
+ vdd_level = dcn_bw_v_mid0p72;
+ } else
+ vdd_level = dcn_bw_v_min0p65;
+ break;
+
+ default:
+ break;
+ }
+ return vdd_level;
+}
+
+unsigned int dcn_find_dcfclk_suits_all(
+ const struct core_dc *dc,
+ struct clocks_value *clocks)
+{
+ unsigned vdd_level, vdd_level_temp;
+ unsigned dcf_clk;
+
+ /*find a common supported voltage level*/
+ vdd_level = dcn_find_normalized_clock_vdd_Level(
+ dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
+ vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
+ dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
+
+ vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
+ vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
+ dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
+ vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
+
+ vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
+ dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
+ vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
+ vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
+ dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
+
+ /*find that level conresponding dcfclk*/
+ vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
+ if (vdd_level == dcn_bw_v_max0p91) {
+ BREAK_TO_DEBUGGER();
+ dcf_clk = dc->dcn_soc.dcfclkv_max0p9*1000;
+ } else if (vdd_level == dcn_bw_v_max0p9)
+ dcf_clk = dc->dcn_soc.dcfclkv_max0p9*1000;
+ else if (vdd_level == dcn_bw_v_nom0p8)
+ dcf_clk = dc->dcn_soc.dcfclkv_nom0p8*1000;
+ else if (vdd_level == dcn_bw_v_mid0p72)
+ dcf_clk = dc->dcn_soc.dcfclkv_mid0p72*1000;
+ else
+ dcf_clk = dc->dcn_soc.dcfclkv_min0p65*1000;
+
+ dm_logger_write(dc->ctx->logger, LOG_HW_MARKS,
+ "\tdcf_clk for voltage = %d\n", dcf_clk);
+ return dcf_clk;
+}
+
+void dcn_bw_update_from_pplib(struct core_dc *dc)
+{
+ struct dc_context *ctx = dc->ctx;
+ struct dm_pp_clock_levels_with_latency clks = {0};
+ struct dm_pp_clock_levels_with_voltage clks2 = {0};
+
+ kernel_fpu_begin();
+ dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
+ ASSERT(dc->dcn_soc.number_of_channels && dc->dcn_soc.number_of_channels < 3);
+ if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
+ dc->dcn_soc.number_of_channels = 2;
+
+ if (dm_pp_get_clock_levels_by_type_with_voltage(
+ ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clks2) &&
+ clks2.num_levels >= 3) {
+ dc->dcn_soc.max_dispclk_vmin0p65 = clks2.data[0].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dispclk_vmid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dispclk_vnom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dispclk_vmax0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
+ } else
+ BREAK_TO_DEBUGGER();
+/*
+ if (dm_pp_get_clock_levels_by_type_with_latency(
+ ctx, DM_PP_CLOCK_TYPE_MEMORY_CLK, &clks) &&
+ clks.num_levels != 0) {
+ //this is to get DRAM data_rate
+ //FabricAndDRAMBandwidth = min(64*FCLK , Data rate * single_Channel_Width * number of channels);
+ }*/
+ if (dm_pp_get_clock_levels_by_type_with_latency(
+ ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) &&
+ clks.num_levels != 0) {
+ ASSERT(clks.num_levels >= 3);
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc.number_of_channels *
+ (clks.data[0].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ if (clks.num_levels > 2) {
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
+ (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ } else {
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc.number_of_channels *
+ (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ }
+ dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc.number_of_channels *
+ (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc.number_of_channels *
+ (clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
+ } else
+ BREAK_TO_DEBUGGER();
+ if (dm_pp_get_clock_levels_by_type_with_latency(
+ ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) &&
+ clks.num_levels >= 3) {
+ dc->dcn_soc.dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0;
+ dc->dcn_soc.dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
+ dc->dcn_soc.dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
+ dc->dcn_soc.dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
+ } else
+ BREAK_TO_DEBUGGER();
+ if (dm_pp_get_clock_levels_by_type_with_voltage(
+ ctx, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, &clks2) &&
+ clks2.num_levels >= 3) {
+ dc->dcn_soc.phyclkv_min0p65 = clks2.data[0].clocks_in_khz / 1000.0;
+ dc->dcn_soc.phyclkv_mid0p72 = clks2.data[clks2.num_levels - 3].clocks_in_khz / 1000.0;
+ dc->dcn_soc.phyclkv_nom0p8 = clks2.data[clks2.num_levels - 2].clocks_in_khz / 1000.0;
+ dc->dcn_soc.phyclkv_max0p9 = clks2.data[clks2.num_levels - 1].clocks_in_khz / 1000.0;
+ } else
+ BREAK_TO_DEBUGGER();
+ if (dm_pp_get_clock_levels_by_type_with_latency(
+ ctx, DM_PP_CLOCK_TYPE_DPPCLK, &clks) &&
+ clks.num_levels >= 3) {
+ dc->dcn_soc.max_dppclk_vmin0p65 = clks.data[0].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dppclk_vmid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dppclk_vnom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0;
+ dc->dcn_soc.max_dppclk_vmax0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0;
+ }
+
+ if (dm_pp_get_clock_levels_by_type_with_latency(
+ ctx, DM_PP_CLOCK_TYPE_SOCCLK, &clks) &&
+ clks.num_levels >= 3) {
+ dc->dcn_soc.socclk = clks.data[0].clocks_in_khz / 1000.0;
+ } else
+ BREAK_TO_DEBUGGER();
+ kernel_fpu_end();
+}
+
+void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
+{
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0};
+ int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz,
+ nom_dcfclk_khz, min_dcfclk_khz, socclk_khz;
+ const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
+ unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc.number_of_channels);
+
+ kernel_fpu_begin();
+ max_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
+ nom_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
+ min_fclk_khz = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 * 1000000 / factor;
+ max_dcfclk_khz = dc->dcn_soc.dcfclkv_max0p9 * 1000;
+ nom_dcfclk_khz = dc->dcn_soc.dcfclkv_nom0p8 * 1000;
+ min_dcfclk_khz = dc->dcn_soc.dcfclkv_min0p65 * 1000;
+ socclk_khz = dc->dcn_soc.socclk * 1000;
+ kernel_fpu_end();
+
+ /* Now notify PPLib/SMU about which Watermarks sets they should select
+ * depending on DPM state they are in. And update BW MGR GFX Engine and
+ * Memory clock member variables for Watermarks calculations for each
+ * Watermark Set
+ */
+ /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
+ * care what the value is, hence min to overdrive level
+ */
+ clk_ranges.num_wm_dmif_sets = 4;
+ clk_ranges.num_wm_mcif_sets = 4;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_set_id = WM_SET_A;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_set_id = WM_SET_A;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_min_socclk_clk_in_khz = socclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_max_socclk_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_min_memg_clk_in_khz = min_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[0].wm_max_mem_clk_in_khz = nom_fclk_khz - 1;
+
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_set_id = WM_SET_B;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_min_dcfclk_clk_in_khz = min_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_max_dcfclk_clk_in_khz = nom_dcfclk_khz - 1;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_set_id = WM_SET_B;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_min_socclk_clk_in_khz = socclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_max_socclk_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_min_memg_clk_in_khz = nom_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[1].wm_max_mem_clk_in_khz = max_fclk_khz;
+
+
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_set_id = WM_SET_C;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_min_dcfclk_clk_in_khz = nom_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_max_dcfclk_clk_in_khz = max_dcfclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
+ clk_ranges.wm_dmif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_set_id = WM_SET_C;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_min_socclk_clk_in_khz = socclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_max_socclk_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_min_memg_clk_in_khz = nom_fclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[2].wm_max_mem_clk_in_khz = max_fclk_khz;
+
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_set_id = WM_SET_D;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_min_dcfclk_clk_in_khz = max_dcfclk_khz + 1;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_max_dcfclk_clk_in_khz = overdrive;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
+ clk_ranges.wm_dmif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_set_id = WM_SET_D;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_min_socclk_clk_in_khz = socclk_khz;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_max_socclk_clk_in_khz = overdrive;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_min_memg_clk_in_khz = max_fclk_khz + 1;
+ clk_ranges.wm_mcif_clocks_ranges[3].wm_max_mem_clk_in_khz = overdrive;
+
+ /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+ dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges);
+}
+
+void dcn_bw_sync_calcs_and_dml(struct core_dc *dc)
+{
+ kernel_fpu_begin();
+ dc->dml.soc.vmin.socclk_mhz = dc->dcn_soc.socclk;
+ dc->dml.soc.vmid.socclk_mhz = dc->dcn_soc.socclk;
+ dc->dml.soc.vnom.socclk_mhz = dc->dcn_soc.socclk;
+ dc->dml.soc.vmax.socclk_mhz = dc->dcn_soc.socclk;
+
+ dc->dml.soc.vmin.dcfclk_mhz = dc->dcn_soc.dcfclkv_min0p65;
+ dc->dml.soc.vmid.dcfclk_mhz = dc->dcn_soc.dcfclkv_mid0p72;
+ dc->dml.soc.vnom.dcfclk_mhz = dc->dcn_soc.dcfclkv_nom0p8;
+ dc->dml.soc.vmax.dcfclk_mhz = dc->dcn_soc.dcfclkv_max0p9;
+
+ dc->dml.soc.vmin.dispclk_mhz = dc->dcn_soc.max_dispclk_vmin0p65;
+ dc->dml.soc.vmid.dispclk_mhz = dc->dcn_soc.max_dispclk_vmid0p72;
+ dc->dml.soc.vnom.dispclk_mhz = dc->dcn_soc.max_dispclk_vnom0p8;
+ dc->dml.soc.vmax.dispclk_mhz = dc->dcn_soc.max_dispclk_vmax0p9;
+
+ dc->dml.soc.vmin.dppclk_mhz = dc->dcn_soc.max_dppclk_vmin0p65;
+ dc->dml.soc.vmid.dppclk_mhz = dc->dcn_soc.max_dppclk_vmid0p72;
+ dc->dml.soc.vnom.dppclk_mhz = dc->dcn_soc.max_dppclk_vnom0p8;
+ dc->dml.soc.vmax.dppclk_mhz = dc->dcn_soc.max_dppclk_vmax0p9;
+
+ dc->dml.soc.vmin.phyclk_mhz = dc->dcn_soc.phyclkv_min0p65;
+ dc->dml.soc.vmid.phyclk_mhz = dc->dcn_soc.phyclkv_mid0p72;
+ dc->dml.soc.vnom.phyclk_mhz = dc->dcn_soc.phyclkv_nom0p8;
+ dc->dml.soc.vmax.phyclk_mhz = dc->dcn_soc.phyclkv_max0p9;
+
+ dc->dml.soc.vmin.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65;
+ dc->dml.soc.vmid.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72;
+ dc->dml.soc.vnom.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8;
+ dc->dml.soc.vmax.dram_bw_per_chan_gbps = dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9;
+
+ dc->dml.soc.sr_exit_time_us = dc->dcn_soc.sr_exit_time;
+ dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc.sr_enter_plus_exit_time;
+ dc->dml.soc.urgent_latency_us = dc->dcn_soc.urgent_latency;
+ dc->dml.soc.writeback_latency_us = dc->dcn_soc.write_back_latency;
+ dc->dml.soc.ideal_dram_bw_after_urgent_percent =
+ dc->dcn_soc.percent_of_ideal_drambw_received_after_urg_latency;
+ dc->dml.soc.max_request_size_bytes = dc->dcn_soc.max_request_size;
+ dc->dml.soc.downspread_percent = dc->dcn_soc.downspreading;
+ dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
+ dc->dcn_soc.round_trip_ping_latency_cycles;
+ dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
+ dc->dcn_soc.urgent_out_of_order_return_per_channel;
+ dc->dml.soc.num_chans = dc->dcn_soc.number_of_channels;
+ dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc.vmm_page_size;
+ dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc.dram_clock_change_latency;
+ dc->dml.soc.return_bus_width_bytes = dc->dcn_soc.return_bus_width;
+
+ dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip.rob_buffer_size_in_kbyte;
+ dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip.det_buffer_size_in_kbyte;
+ dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip.dpp_output_buffer_pixels;
+ dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip.opp_output_buffer_lines;
+ dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip.pixel_chunk_size_in_kbyte;
+ dc->dml.ip.pte_enable = dc->dcn_ip.pte_enable == dcn_bw_yes;
+ dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip.pte_chunk_size;
+ dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip.meta_chunk_size;
+ dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip.writeback_chunk_size;
+ dc->dml.ip.line_buffer_size_bits = dc->dcn_ip.line_buffer_size;
+ dc->dml.ip.max_line_buffer_lines = dc->dcn_ip.max_line_buffer_lines;
+ dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip.is_line_buffer_bpp_fixed == dcn_bw_yes;
+ dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip.line_buffer_fixed_bpp;
+ dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip.writeback_luma_buffer_size;
+ dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip.writeback_chroma_buffer_size;
+ dc->dml.ip.max_num_dpp = dc->dcn_ip.max_num_dpp;
+ dc->dml.ip.max_num_wb = dc->dcn_ip.max_num_writeback;
+ dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip.max_dchub_topscl_throughput;
+ dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip.max_pscl_tolb_throughput;
+ dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip.max_lb_tovscl_throughput;
+ dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip.max_vscl_tohscl_throughput;
+ dc->dml.ip.max_hscl_ratio = dc->dcn_ip.max_hscl_ratio;
+ dc->dml.ip.max_vscl_ratio = dc->dcn_ip.max_vscl_ratio;
+ dc->dml.ip.max_hscl_taps = dc->dcn_ip.max_hscl_taps;
+ dc->dml.ip.max_vscl_taps = dc->dcn_ip.max_vscl_taps;
+ /*pte_buffer_size_in_requests missing in dml*/
+ dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip.dispclk_ramping_margin;
+ dc->dml.ip.underscan_factor = dc->dcn_ip.under_scan_factor;
+ dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip.max_inter_dcn_tile_repeaters;
+ dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
+ dc->dcn_ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
+ dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
+ dc->dcn_ip.bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
+ dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip.dcfclk_cstate_latency;
+ kernel_fpu_end();
+}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
new file mode 100644
index 0000000..499bc11
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -0,0 +1,629 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/**
+ * Bandwidth and Watermark calculations interface.
+ * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
+ */
+#ifndef __DCN_CALCS_H__
+#define __DCN_CALCS_H__
+
+#include "bw_fixed.h"
+#include "display_clock.h"
+#include "../dml/display_mode_lib.h"
+
+struct core_dc;
+struct validate_context;
+
+/*******************************************************************************
+ * DCN data structures.
+ ******************************************************************************/
+
+#define number_of_planes 6
+#define number_of_planes_minus_one 5
+#define number_of_states 4
+#define number_of_states_plus_one 5
+
+#define ddr4_dram_width 64
+#define ddr4_dram_factor_single_Channel 16
+enum dcn_bw_defs {
+ dcn_bw_v_min0p65,
+ dcn_bw_v_mid0p72,
+ dcn_bw_v_nom0p8,
+ dcn_bw_v_max0p9,
+ dcn_bw_v_max0p91,
+ dcn_bw_no_support = 5,
+ dcn_bw_yes,
+ dcn_bw_hor,
+ dcn_bw_vert,
+ dcn_bw_override,
+ dcn_bw_rgb_sub_64,
+ dcn_bw_rgb_sub_32,
+ dcn_bw_rgb_sub_16,
+ dcn_bw_no,
+ dcn_bw_sw_linear,
+ dcn_bw_sw_4_kb_d,
+ dcn_bw_sw_4_kb_d_x,
+ dcn_bw_sw_64_kb_d,
+ dcn_bw_sw_64_kb_d_t,
+ dcn_bw_sw_64_kb_d_x,
+ dcn_bw_sw_var_d,
+ dcn_bw_sw_var_d_x,
+ dcn_bw_yuv420_sub_8,
+ dcn_bw_sw_4_kb_s,
+ dcn_bw_sw_4_kb_s_x,
+ dcn_bw_sw_64_kb_s,
+ dcn_bw_sw_64_kb_s_t,
+ dcn_bw_sw_64_kb_s_x,
+ dcn_bw_writeback,
+ dcn_bw_444,
+ dcn_bw_dp,
+ dcn_bw_420,
+ dcn_bw_hdmi,
+ dcn_bw_sw_var_s,
+ dcn_bw_sw_var_s_x,
+ dcn_bw_yuv420_sub_10,
+ dcn_bw_supported_in_v_active,
+ dcn_bw_supported_in_v_blank,
+ dcn_bw_not_supported,
+ dcn_bw_na,
+};
+
+/*bounding box parameters*/
+/*mode parameters*/
+/*system configuration*/
+/* display configuration*/
+struct dcn_bw_internal_vars {
+ float voltage[number_of_states_plus_one + 1];
+ float max_dispclk[number_of_states_plus_one + 1];
+ float max_dppclk[number_of_states_plus_one + 1];
+ float dcfclk_per_state[number_of_states_plus_one + 1];
+ float phyclk_per_state[number_of_states_plus_one + 1];
+ float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1];
+ float sr_exit_time;
+ float sr_enter_plus_exit_time;
+ float dram_clock_change_latency;
+ float urgent_latency;
+ float write_back_latency;
+ float percent_of_ideal_drambw_received_after_urg_latency;
+ float dcfclkv_max0p9;
+ float dcfclkv_nom0p8;
+ float dcfclkv_mid0p72;
+ float dcfclkv_min0p65;
+ float max_dispclk_vmax0p9;
+ float max_dppclk_vmax0p9;
+ float max_dispclk_vnom0p8;
+ float max_dppclk_vnom0p8;
+ float max_dispclk_vmid0p72;
+ float max_dppclk_vmid0p72;
+ float max_dispclk_vmin0p65;
+ float max_dppclk_vmin0p65;
+ float socclk;
+ float fabric_and_dram_bandwidth_vmax0p9;
+ float fabric_and_dram_bandwidth_vnom0p8;
+ float fabric_and_dram_bandwidth_vmid0p72;
+ float fabric_and_dram_bandwidth_vmin0p65;
+ float round_trip_ping_latency_cycles;
+ float urgent_out_of_order_return_per_channel;
+ float number_of_channels;
+ float vmm_page_size;
+ float return_bus_width;
+ float rob_buffer_size_in_kbyte;
+ float det_buffer_size_in_kbyte;
+ float dpp_output_buffer_pixels;
+ float opp_output_buffer_lines;
+ float pixel_chunk_size_in_kbyte;
+ float pte_chunk_size;
+ float meta_chunk_size;
+ float writeback_chunk_size;
+ enum dcn_bw_defs odm_capability;
+ enum dcn_bw_defs dsc_capability;
+ float line_buffer_size;
+ enum dcn_bw_defs is_line_buffer_bpp_fixed;
+ float line_buffer_fixed_bpp;
+ float max_line_buffer_lines;
+ float writeback_luma_buffer_size;
+ float writeback_chroma_buffer_size;
+ float max_num_dpp;
+ float max_num_writeback;
+ float max_dchub_topscl_throughput;
+ float max_pscl_tolb_throughput;
+ float max_lb_tovscl_throughput;
+ float max_vscl_tohscl_throughput;
+ float max_hscl_ratio;
+ float max_vscl_ratio;
+ float max_hscl_taps;
+ float max_vscl_taps;
+ float under_scan_factor;
+ float phyclkv_max0p9;
+ float phyclkv_nom0p8;
+ float phyclkv_mid0p72;
+ float phyclkv_min0p65;
+ float pte_buffer_size_in_requests;
+ float dispclk_ramping_margin;
+ float downspreading;
+ float max_inter_dcn_tile_repeaters;
+ enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
+ enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
+ int mode;
+ float viewport_width[number_of_planes_minus_one + 1];
+ float htotal[number_of_planes_minus_one + 1];
+ float vtotal[number_of_planes_minus_one + 1];
+ float v_sync_plus_back_porch[number_of_planes_minus_one + 1];
+ float vactive[number_of_planes_minus_one + 1];
+ float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/
+ float viewport_height[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1];
+ float dcc_rate[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1];
+ float lb_bit_per_pixel[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs output_format[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs output[number_of_planes_minus_one + 1];
+ float scaler_rec_out_width[number_of_planes_minus_one + 1];
+ float scaler_recout_height[number_of_planes_minus_one + 1];
+ float underscan_output[number_of_planes_minus_one + 1];
+ float interlace_output[number_of_planes_minus_one + 1];
+ float override_hta_ps[number_of_planes_minus_one + 1];
+ float override_vta_ps[number_of_planes_minus_one + 1];
+ float override_hta_pschroma[number_of_planes_minus_one + 1];
+ float override_vta_pschroma[number_of_planes_minus_one + 1];
+ float urgent_latency_support_us[number_of_planes_minus_one + 1];
+ float h_ratio[number_of_planes_minus_one + 1];
+ float v_ratio[number_of_planes_minus_one + 1];
+ float htaps[number_of_planes_minus_one + 1];
+ float vtaps[number_of_planes_minus_one + 1];
+ float hta_pschroma[number_of_planes_minus_one + 1];
+ float vta_pschroma[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs pte_enable;
+ enum dcn_bw_defs synchronized_vblank;
+ enum dcn_bw_defs ta_pscalculation;
+ int voltage_override_level;
+ int number_of_active_planes;
+ int voltage_level;
+ enum dcn_bw_defs immediate_flip_supported;
+ float dcfclk;
+ float max_phyclk;
+ float fabric_and_dram_bandwidth;
+ float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1];
+ enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1];
+ float required_dispclk_per_ratio[1 + 1];
+ enum dcn_bw_defs error_message[1 + 1];
+ int dispclk_dppclk_ratio;
+ float dpp_per_plane[number_of_planes_minus_one + 1];
+ float det_buffer_size_y[number_of_planes_minus_one + 1];
+ float det_buffer_size_c[number_of_planes_minus_one + 1];
+ float swath_height_y[number_of_planes_minus_one + 1];
+ float swath_height_c[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs final_error_message;
+ float frequency;
+ float header_line;
+ float header;
+ enum dcn_bw_defs voltage_override;
+ enum dcn_bw_defs allow_different_hratio_vratio;
+ float acceptable_quality_hta_ps;
+ float acceptable_quality_vta_ps;
+ float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1];
+ enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ float required_dispclk[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1];
+ float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1];
+ float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1];
+ float return_bw_per_state[number_of_states_plus_one + 1];
+ enum dcn_bw_defs dio_support[number_of_states_plus_one + 1];
+ float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1];
+ enum dcn_bw_defs rob_support[number_of_states_plus_one + 1];
+ enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1];
+ float prefetch_bw[number_of_planes_minus_one + 1];
+ float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1];
+ float meta_row_bytes[number_of_planes_minus_one + 1];
+ float dpte_bytes_per_row[number_of_planes_minus_one + 1];
+ float prefetch_lines_y[number_of_planes_minus_one + 1];
+ float prefetch_lines_c[number_of_planes_minus_one + 1];
+ float max_num_sw_y[number_of_planes_minus_one + 1];
+ float max_num_sw_c[number_of_planes_minus_one + 1];
+ float line_times_for_prefetch[number_of_planes_minus_one + 1];
+ float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1];
+ float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1];
+ float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1];
+ float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1];
+ float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1];
+ float swath_width_ysingle_dpp[number_of_planes_minus_one + 1];
+ float byte_per_pixel_in_dety[number_of_planes_minus_one + 1];
+ float byte_per_pixel_in_detc[number_of_planes_minus_one + 1];
+ float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1];
+ float required_phyclk[number_of_planes_minus_one + 1];
+ float read256_block_height_y[number_of_planes_minus_one + 1];
+ float read256_block_width_y[number_of_planes_minus_one + 1];
+ float read256_block_height_c[number_of_planes_minus_one + 1];
+ float read256_block_width_c[number_of_planes_minus_one + 1];
+ float max_swath_height_y[number_of_planes_minus_one + 1];
+ float max_swath_height_c[number_of_planes_minus_one + 1];
+ float min_swath_height_y[number_of_planes_minus_one + 1];
+ float min_swath_height_c[number_of_planes_minus_one + 1];
+ float read_bandwidth[number_of_planes_minus_one + 1];
+ float write_bandwidth[number_of_planes_minus_one + 1];
+ float pscl_factor[number_of_planes_minus_one + 1];
+ float pscl_factor_chroma[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs scale_ratio_support;
+ enum dcn_bw_defs source_format_pixel_and_scan_support;
+ float total_read_bandwidth_consumed_gbyte_per_second;
+ float total_write_bandwidth_consumed_gbyte_per_second;
+ float total_bandwidth_consumed_gbyte_per_second;
+ enum dcn_bw_defs dcc_enabled_in_any_plane;
+ float return_bw_todcn_per_state;
+ float critical_point;
+ enum dcn_bw_defs writeback_latency_support;
+ float required_output_bw;
+ float total_number_of_active_writeback;
+ enum dcn_bw_defs total_available_writeback_support;
+ float maximum_swath_width;
+ float number_of_dpp_required_for_det_size;
+ float number_of_dpp_required_for_lb_size;
+ float min_dispclk_using_single_dpp;
+ float min_dispclk_using_dual_dpp;
+ enum dcn_bw_defs viewport_size_support;
+ float swath_width_granularity_y;
+ float rounded_up_max_swath_size_bytes_y;
+ float swath_width_granularity_c;
+ float rounded_up_max_swath_size_bytes_c;
+ float lines_in_det_luma;
+ float lines_in_det_chroma;
+ float effective_lb_latency_hiding_source_lines_luma;
+ float effective_lb_latency_hiding_source_lines_chroma;
+ float effective_detlb_lines_luma;
+ float effective_detlb_lines_chroma;
+ float projected_dcfclk_deep_sleep;
+ float meta_req_height_y;
+ float meta_req_width_y;
+ float meta_surface_width_y;
+ float meta_surface_height_y;
+ float meta_pte_bytes_per_frame_y;
+ float meta_row_bytes_y;
+ float macro_tile_block_size_bytes_y;
+ float macro_tile_block_height_y;
+ float data_pte_req_height_y;
+ float data_pte_req_width_y;
+ float dpte_bytes_per_row_y;
+ float meta_req_height_c;
+ float meta_req_width_c;
+ float meta_surface_width_c;
+ float meta_surface_height_c;
+ float meta_pte_bytes_per_frame_c;
+ float meta_row_bytes_c;
+ float macro_tile_block_size_bytes_c;
+ float macro_tile_block_height_c;
+ float macro_tile_block_width_c;
+ float data_pte_req_height_c;
+ float data_pte_req_width_c;
+ float dpte_bytes_per_row_c;
+ float v_init_y;
+ float max_partial_sw_y;
+ float v_init_c;
+ float max_partial_sw_c;
+ float dst_x_after_scaler;
+ float dst_y_after_scaler;
+ float time_calc;
+ float v_update_offset[number_of_planes_minus_one + 1];
+ float total_repeater_delay;
+ float v_update_width[number_of_planes_minus_one + 1];
+ float v_ready_offset[number_of_planes_minus_one + 1];
+ float time_setup;
+ float extra_latency;
+ float maximum_vstartup;
+ float bw_available_for_immediate_flip;
+ float total_immediate_flip_bytes[number_of_planes_minus_one + 1];
+ float time_for_meta_pte_with_immediate_flip;
+ float time_for_meta_pte_without_immediate_flip;
+ float time_for_meta_and_dpte_row_with_immediate_flip;
+ float time_for_meta_and_dpte_row_without_immediate_flip;
+ float line_times_to_request_prefetch_pixel_data_with_immediate_flip;
+ float line_times_to_request_prefetch_pixel_data_without_immediate_flip;
+ float maximum_read_bandwidth_with_prefetch_with_immediate_flip;
+ float maximum_read_bandwidth_with_prefetch_without_immediate_flip;
+ float voltage_level_with_immediate_flip;
+ float voltage_level_without_immediate_flip;
+ float total_number_of_active_dpp_per_ratio[1 + 1];
+ float byte_per_pix_dety;
+ float byte_per_pix_detc;
+ float read256_bytes_block_height_y;
+ float read256_bytes_block_width_y;
+ float read256_bytes_block_height_c;
+ float read256_bytes_block_width_c;
+ float maximum_swath_height_y;
+ float maximum_swath_height_c;
+ float minimum_swath_height_y;
+ float minimum_swath_height_c;
+ float swath_width;
+ float prefetch_bandwidth[number_of_planes_minus_one + 1];
+ float v_init_pre_fill_y[number_of_planes_minus_one + 1];
+ float v_init_pre_fill_c[number_of_planes_minus_one + 1];
+ float max_num_swath_y[number_of_planes_minus_one + 1];
+ float max_num_swath_c[number_of_planes_minus_one + 1];
+ float prefill_y[number_of_planes_minus_one + 1];
+ float prefill_c[number_of_planes_minus_one + 1];
+ float v_startup[number_of_planes_minus_one + 1];
+ enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1];
+ float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1];
+ float v_ratio_prefetch_y[number_of_planes_minus_one + 1];
+ float v_ratio_prefetch_c[number_of_planes_minus_one + 1];
+ float destination_lines_for_prefetch[number_of_planes_minus_one + 1];
+ float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1];
+ float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1];
+ float min_ttuv_blank[number_of_planes_minus_one + 1];
+ float byte_per_pixel_dety[number_of_planes_minus_one + 1];
+ float byte_per_pixel_detc[number_of_planes_minus_one + 1];
+ float swath_width_y[number_of_planes_minus_one + 1];
+ float lines_in_dety[number_of_planes_minus_one + 1];
+ float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1];
+ float lines_in_detc[number_of_planes_minus_one + 1];
+ float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1];
+ float full_det_buffering_time_y[number_of_planes_minus_one + 1];
+ float full_det_buffering_time_c[number_of_planes_minus_one + 1];
+ float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
+ float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1];
+ float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1];
+ float read_bandwidth_plane_luma[number_of_planes_minus_one + 1];
+ float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1];
+ float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1];
+ float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1];
+ float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1];
+ float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1];
+ float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1];
+ float meta_pte_bytes_frame[number_of_planes_minus_one + 1];
+ float meta_row_byte[number_of_planes_minus_one + 1];
+ float prefetch_source_lines_y[number_of_planes_minus_one + 1];
+ float prefetch_source_lines_c[number_of_planes_minus_one + 1];
+ float pscl_throughput[number_of_planes_minus_one + 1];
+ float pscl_throughput_chroma[number_of_planes_minus_one + 1];
+ float output_bpphdmi[number_of_planes_minus_one + 1];
+ float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1];
+ float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1];
+ float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1];
+ float max_vstartup_lines[number_of_planes_minus_one + 1];
+ float dispclk_with_ramping;
+ float dispclk_without_ramping;
+ float dppclk_using_single_dpp_luma;
+ float dppclk_using_single_dpp;
+ float dppclk_using_single_dpp_chroma;
+ enum dcn_bw_defs odm_capable;
+ float dispclk;
+ float dppclk;
+ float return_bandwidth_to_dcn;
+ enum dcn_bw_defs dcc_enabled_any_plane;
+ float return_bw;
+ float critical_compression;
+ float total_data_read_bandwidth;
+ float total_active_dpp;
+ float total_dcc_active_dpp;
+ float urgent_round_trip_and_out_of_order_latency;
+ float last_pixel_of_line_extra_watermark;
+ float data_fabric_line_delivery_time_luma;
+ float data_fabric_line_delivery_time_chroma;
+ float urgent_extra_latency;
+ float urgent_watermark;
+ float ptemeta_urgent_watermark;
+ float dram_clock_change_watermark;
+ float total_active_writeback;
+ float writeback_dram_clock_change_watermark;
+ float min_full_det_buffering_time;
+ float frame_time_for_min_full_det_buffering_time;
+ float average_read_bandwidth_gbyte_per_second;
+ float part_of_burst_that_fits_in_rob;
+ float stutter_burst_time;
+ float stutter_efficiency_not_including_vblank;
+ float smallest_vblank;
+ float v_blank_time;
+ float stutter_efficiency;
+ float dcf_clk_deep_sleep;
+ float stutter_exit_watermark;
+ float stutter_enter_plus_exit_watermark;
+ float effective_det_plus_lb_lines_luma;
+ float urgent_latency_support_us_luma;
+ float effective_det_plus_lb_lines_chroma;
+ float urgent_latency_support_us_chroma;
+ float min_urgent_latency_support_us;
+ float non_urgent_latency_tolerance;
+ float block_height256_bytes_y;
+ float block_height256_bytes_c;
+ float meta_request_width_y;
+ float meta_surf_width_y;
+ float meta_surf_height_y;
+ float meta_pte_bytes_frame_y;
+ float meta_row_byte_y;
+ float macro_tile_size_byte_y;
+ float macro_tile_height_y;
+ float pixel_pte_req_height_y;
+ float pixel_pte_req_width_y;
+ float pixel_pte_bytes_per_row_y;
+ float meta_request_width_c;
+ float meta_surf_width_c;
+ float meta_surf_height_c;
+ float meta_pte_bytes_frame_c;
+ float meta_row_byte_c;
+ float macro_tile_size_bytes_c;
+ float macro_tile_height_c;
+ float pixel_pte_req_height_c;
+ float pixel_pte_req_width_c;
+ float pixel_pte_bytes_per_row_c;
+ float max_partial_swath_y;
+ float max_partial_swath_c;
+ float t_calc;
+ float next_prefetch_mode;
+ float v_startup_lines;
+ enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw;
+ enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4;
+ enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2;
+ enum dcn_bw_defs v_ratio_prefetch_more_than4;
+ enum dcn_bw_defs destination_line_times_for_prefetch_less_than2;
+ float prefetch_mode;
+ float dstx_after_scaler;
+ float dsty_after_scaler;
+ float v_update_offset_pix;
+ float total_repeater_delay_time;
+ float v_update_width_pix;
+ float v_ready_offset_pix;
+ float t_setup;
+ float t_wait;
+ float bandwidth_available_for_immediate_flip;
+ float tot_immediate_flip_bytes;
+ float max_rd_bandwidth;
+ float time_for_fetching_meta_pte;
+ float time_for_fetching_row_in_vblank;
+ float lines_to_request_prefetch_pixel_data;
+ float required_prefetch_pix_data_bw;
+ enum dcn_bw_defs prefetch_mode_supported;
+ float active_dp_ps;
+ float lb_latency_hiding_source_lines_y;
+ float lb_latency_hiding_source_lines_c;
+ float effective_lb_latency_hiding_y;
+ float effective_lb_latency_hiding_c;
+ float dpp_output_buffer_lines_y;
+ float dpp_output_buffer_lines_c;
+ float dppopp_buffering_y;
+ float max_det_buffering_time_y;
+ float active_dram_clock_change_latency_margin_y;
+ float dppopp_buffering_c;
+ float max_det_buffering_time_c;
+ float active_dram_clock_change_latency_margin_c;
+ float writeback_dram_clock_change_latency_margin;
+ float min_active_dram_clock_change_margin;
+ float v_blank_of_min_active_dram_clock_change_margin;
+ float second_min_active_dram_clock_change_margin;
+ float min_vblank_dram_clock_change_margin;
+ float dram_clock_change_margin;
+ float dram_clock_change_support;
+ float wr_bandwidth;
+ float max_used_bw;
+};
+
+struct dcn_soc_bounding_box {
+ float sr_exit_time; /*us*/
+ float sr_enter_plus_exit_time; /*us*/
+ float urgent_latency; /*us*/
+ float write_back_latency; /*us*/
+ float percent_of_ideal_drambw_received_after_urg_latency; /*%*/
+ int max_request_size; /*bytes*/
+ float dcfclkv_max0p9; /*MHz*/
+ float dcfclkv_nom0p8; /*MHz*/
+ float dcfclkv_mid0p72; /*MHz*/
+ float dcfclkv_min0p65; /*MHz*/
+ float max_dispclk_vmax0p9; /*MHz*/
+ float max_dispclk_vmid0p72; /*MHz*/
+ float max_dispclk_vnom0p8; /*MHz*/
+ float max_dispclk_vmin0p65; /*MHz*/
+ float max_dppclk_vmax0p9; /*MHz*/
+ float max_dppclk_vnom0p8; /*MHz*/
+ float max_dppclk_vmid0p72; /*MHz*/
+ float max_dppclk_vmin0p65; /*MHz*/
+ float socclk; /*MHz*/
+ float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/
+ float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/
+ float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/
+ float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/
+ float phyclkv_max0p9; /*MHz*/
+ float phyclkv_nom0p8; /*MHz*/
+ float phyclkv_mid0p72; /*MHz*/
+ float phyclkv_min0p65; /*MHz*/
+ float downspreading; /*%*/
+ int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/
+ int urgent_out_of_order_return_per_channel; /*bytes*/
+ int number_of_channels;
+ int vmm_page_size; /*bytes*/
+ float dram_clock_change_latency; /*us*/
+ int return_bus_width; /*bytes*/
+};
+extern const struct dcn_soc_bounding_box dcn10_soc_defaults;
+
+struct dcn_ip_params {
+ float rob_buffer_size_in_kbyte;
+ float det_buffer_size_in_kbyte;
+ float dpp_output_buffer_pixels;
+ float opp_output_buffer_lines;
+ float pixel_chunk_size_in_kbyte;
+ enum dcn_bw_defs pte_enable;
+ int pte_chunk_size; /*kbytes*/
+ int meta_chunk_size; /*kbytes*/
+ int writeback_chunk_size; /*kbytes*/
+ enum dcn_bw_defs odm_capability;
+ enum dcn_bw_defs dsc_capability;
+ int line_buffer_size; /*bit*/
+ int max_line_buffer_lines;
+ enum dcn_bw_defs is_line_buffer_bpp_fixed;
+ int line_buffer_fixed_bpp;
+ int writeback_luma_buffer_size; /*kbytes*/
+ int writeback_chroma_buffer_size; /*kbytes*/
+ int max_num_dpp;
+ int max_num_writeback;
+ int max_dchub_topscl_throughput; /*pixels/dppclk*/
+ int max_pscl_tolb_throughput; /*pixels/dppclk*/
+ int max_lb_tovscl_throughput; /*pixels/dppclk*/
+ int max_vscl_tohscl_throughput; /*pixels/dppclk*/
+ float max_hscl_ratio;
+ float max_vscl_ratio;
+ int max_hscl_taps;
+ int max_vscl_taps;
+ int pte_buffer_size_in_requests;
+ float dispclk_ramping_margin; /*%*/
+ float under_scan_factor;
+ int max_inter_dcn_tile_repeaters;
+ enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
+ enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed;
+ int dcfclk_cstate_latency;
+};
+extern const struct dcn_ip_params dcn10_ip_defaults;
+
+bool dcn_validate_bandwidth(
+ const struct core_dc *dc,
+ struct validate_context *context);
+
+unsigned int dcn_find_dcfclk_suits_all(
+ const struct core_dc *dc,
+ struct clocks_value *clocks);
+
+void dcn_bw_update_from_pplib(struct core_dc *dc);
+void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc);
+void dcn_bw_sync_calcs_and_dml(struct core_dc *dc);
+
+#endif /* __DCN_CALCS_H__ */
+
--
2.5.5
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 110/117] drm/amdgpu/display: Add core dc support for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (100 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 109/117] drm/amdgpu/display: Add calcs code for DCN Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 111/117] drm/amdgpu/display: Add dml " Alex Deucher
` (7 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
Core display support for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 ++++++++++++++++++++
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +++++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 ++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 ++++++++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 ++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 ++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 ++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +++++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 ++++++++++++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
.../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +++++++++++++
.../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 ++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +++++++++++
.../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +++++
17 files changed, 11467 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
new file mode 100644
index 0000000..2c43ad7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for DCN.
+
+DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
+ dcn10_transform.o dcn10_opp.o dcn10_timing_generator.o \
+ dcn10_mem_input.o dcn10_mpc.o
+
+AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
new file mode 100644
index 0000000..fb4eb43
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -0,0 +1,1866 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+#include "core_dc.h"
+#include "core_types.h"
+#include "core_status.h"
+#include "resource.h"
+#include "hw_sequencer.h"
+#include "dcn10_hw_sequencer.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "abm.h"
+
+#include "dcn10/dcn10_transform.h"
+#include "dcn10/dcn10_mpc.h"
+#include "dcn10/dcn10_timing_generator.h"
+
+#include "mem_input.h"
+#include "timing_generator.h"
+#include "opp.h"
+#include "ipp.h"
+
+#include "dc_bios_types.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#include "custom_float.h"
+
+
+struct dcn10_hwseq_reg_offsets {
+ uint32_t dchubp;
+ uint32_t dpp;
+ uint32_t otg;
+ uint32_t vtg;
+ uint32_t fmt;
+};
+
+/* TODO: move to resource */
+static const struct dcn10_hwseq_reg_offsets reg_offsets[] = {
+ {
+ .dchubp = (mmHUBP0_DCHUBP_CNTL - mmHUBP0_DCHUBP_CNTL),
+ .dpp = (mmCM0_CM_DGAM_CONTROL - mmCM0_CM_DGAM_CONTROL),
+ .otg = (mmOTG0_OTG_CONTROL - mmOTG0_OTG_CONTROL),
+ .vtg = (mmVTG0_CONTROL - mmVTG0_CONTROL),
+ .fmt = (mmFMT0_FMT_BIT_DEPTH_CONTROL -
+ mmFMT0_FMT_BIT_DEPTH_CONTROL),
+ },
+ {
+ .dchubp = (mmHUBP1_DCHUBP_CNTL - mmHUBP0_DCHUBP_CNTL),
+ .dpp = (mmCM1_CM_DGAM_CONTROL - mmCM0_CM_DGAM_CONTROL),
+ .otg = (mmOTG1_OTG_CONTROL - mmOTG0_OTG_CONTROL),
+ .vtg = (mmVTG1_CONTROL - mmVTG0_CONTROL),
+ .fmt = (mmFMT1_FMT_BIT_DEPTH_CONTROL -
+ mmFMT0_FMT_BIT_DEPTH_CONTROL),
+ },
+ {
+ .dchubp = (mmHUBP2_DCHUBP_CNTL - mmHUBP0_DCHUBP_CNTL),
+ .dpp = (mmCM2_CM_DGAM_CONTROL - mmCM0_CM_DGAM_CONTROL),
+ .otg = (mmOTG2_OTG_CONTROL - mmOTG0_OTG_CONTROL),
+ .vtg = (mmVTG2_CONTROL - mmVTG0_CONTROL),
+ .fmt = (mmFMT2_FMT_BIT_DEPTH_CONTROL -
+ mmFMT0_FMT_BIT_DEPTH_CONTROL),
+ },
+ {
+ .dchubp = (mmHUBP3_DCHUBP_CNTL - mmHUBP0_DCHUBP_CNTL),
+ .dpp = (mmCM3_CM_DGAM_CONTROL - mmCM0_CM_DGAM_CONTROL),
+ .otg = (mmOTG3_OTG_CONTROL - mmOTG0_OTG_CONTROL),
+ .vtg = (mmVTG3_CONTROL - mmVTG0_CONTROL),
+ .fmt = (mmFMT3_FMT_BIT_DEPTH_CONTROL -
+ mmFMT0_FMT_BIT_DEPTH_CONTROL),
+ }
+};
+
+#define HWSEQ_REG_UPDATE_N(reg_name, n, ...) \
+ generic_reg_update_soc15(ctx, inst_offset, reg_name, n, __VA_ARGS__)
+
+#define HWSEQ_REG_SET_N(reg_name, n, ...) \
+ generic_reg_set_soc15(ctx, inst_offset, reg_name, n, __VA_ARGS__)
+
+#define HWSEQ_REG_UPDATE(reg, field, val) \
+ HWSEQ_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
+
+#define HWSEQ_REG_UPDATE_2(reg, field1, val1, field2, val2) \
+ HWSEQ_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
+
+#define HWSEQ_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \
+ HWSEQ_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
+
+
+#define HWSEQ_REG_SET(reg, field, val) \
+ HWSEQ_REG_SET_N(reg, 1, FD(reg##__##field), val)
+
+/* TODO should be moved to OTG */
+static void lock_otg_master_update(
+ struct dc_context *ctx,
+ uint8_t inst)
+{
+ uint32_t inst_offset = reg_offsets[inst].otg;
+
+ HWSEQ_REG_UPDATE(OTG0_OTG_GLOBAL_CONTROL0,
+ OTG_MASTER_UPDATE_LOCK_SEL, inst);
+
+ /* unlock master locker */
+ HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK,
+ OTG_MASTER_UPDATE_LOCK, 1);
+
+ /* wait for unlock happens */
+ if (!wait_reg(ctx, inst_offset, OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1))
+ BREAK_TO_DEBUGGER();
+
+}
+
+static bool unlock_master_tg_and_wait(
+ struct dc_context *ctx,
+ uint8_t inst)
+{
+ uint32_t inst_offset = reg_offsets[inst].otg;
+
+ HWSEQ_REG_UPDATE(OTG0_OTG_GLOBAL_SYNC_STATUS,
+ VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
+ HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, 0);
+
+ if (!wait_reg(ctx, inst_offset, OTG0_OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, 1)) {
+ dm_logger_write(ctx->logger, LOG_ERROR,
+ "wait for VUPDATE_NO_LOCK_EVENT_OCCURRED failed\n");
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+ return true;
+}
+
+/* TODO: should be moved to OTG ? */
+static void unlock_otg_master(
+ struct dc_context *ctx,
+ uint8_t inst)
+{
+ uint32_t inst_offset = reg_offsets[inst].otg;
+
+ /* unlock master locker */
+ HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK,
+ OTG_MASTER_UPDATE_LOCK, 0);
+}
+
+
+static void wait_no_outstanding_request(
+ struct dc_context *ctx,
+ uint8_t plane_id)
+{
+ uint32_t inst_offset = reg_offsets[plane_id].dchubp;
+
+ if (!wait_reg(ctx, inst_offset, HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, 1))
+ BREAK_TO_DEBUGGER();
+}
+
+static void disable_clocks(
+ struct dc_context *ctx,
+ uint8_t plane_id)
+{
+ uint32_t inst_offset = reg_offsets[plane_id].dchubp;
+
+ generic_reg_update_soc15(ctx, inst_offset, HUBP0_HUBP_CLK_CNTL, 1,
+ FD(HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE), 0);
+
+ inst_offset = reg_offsets[plane_id].dpp;
+ generic_reg_update_soc15(ctx, inst_offset, DPP_TOP0_DPP_CONTROL, 1,
+ FD(DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE), 0);
+}
+
+/* TODO: This is one time program during system boot up,
+ * this should be done within BIOS or CAIL
+ */
+static void dchubp_map_fb_to_mc(struct dc_context *ctx)
+{
+ /* TODO: do not know where to program
+ * DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB
+ */
+ /*
+ * TODO: For real ASIC, FB_OFFSET may be need change to the same value
+ * as FB_BASE. Need re-visit this for real ASIC.
+ */
+ dm_write_reg_soc15(ctx, mmDCHUBBUB_SDPIF_FB_BASE, 0, 0x80);
+ dm_write_reg_soc15(ctx, mmDCHUBBUB_SDPIF_FB_OFFSET, 0, 0);
+ dm_write_reg_soc15(ctx, mmDCHUBBUB_SDPIF_FB_TOP, 0, 0xFF);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_CFG0, 7,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_CLEAR), 0,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR), 0,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN), 0,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN), 0,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL), 1,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_UNIT_ID_BITMASK), 0xd3,
+ FD(DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY), 0xc);
+
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_CFG1, 4,
+ FD(DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_IO), 0,
+ FD(DCHUBBUB_SDPIF_CFG1__SDPIF_INSIDE_FB_VC), 6,
+ FD(DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_IO), 1,
+ FD(DCHUBBUB_SDPIF_CFG1__SDPIF_OUTSIDE_FB_VC), 6);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_FB_BASE, 1,
+ FD(DCHUBBUB_SDPIF_FB_BASE__SDPIF_FB_BASE), 0x000080);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_FB_TOP, 1,
+ FD(DCHUBBUB_SDPIF_FB_TOP__SDPIF_FB_TOP), 0x0000ff);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_AGP_BOT, 1,
+ FD(DCHUBBUB_SDPIF_AGP_BOT__SDPIF_AGP_BOT), 0x0000040);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_AGP_TOP, 1,
+ FD(DCHUBBUB_SDPIF_AGP_TOP__SDPIF_AGP_TOP), 0x00001ff);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_AGP_BASE, 1,
+ FD(DCHUBBUB_SDPIF_AGP_BASE__SDPIF_AGP_BASE), 0x0000080);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_APER_TOP, 1,
+ FD(DCHUBBUB_SDPIF_APER_TOP__SDPIF_APER_TOP), 0x00007ff);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_APER_DEF_0, 1,
+ FD(DCHUBBUB_SDPIF_APER_DEF_0__SDPIF_APER_DEF_0), 0xdeadbeef);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_RELOC_LO_0, 2,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_EN_0), 0,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_0__SDPIF_MARC_RELOC_LO_0), 0x90000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_LENGTH_LO_0, 1,
+ FD(DCHUBBUB_SDPIF_MARC_LENGTH_LO_0__SDPIF_MARC_LENGTH_LO_0), 0x10000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_BASE_LO_1, 1,
+ FD(DCHUBBUB_SDPIF_MARC_BASE_LO_1__SDPIF_MARC_BASE_LO_1), 0x10000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_RELOC_LO_1, 2,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_EN_1), 0,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_1__SDPIF_MARC_RELOC_LO_1), 0xa0000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_LENGTH_LO_1, 1,
+ FD(DCHUBBUB_SDPIF_MARC_LENGTH_LO_1__SDPIF_MARC_LENGTH_LO_1), 0x10000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_BASE_LO_2, 1,
+ FD(DCHUBBUB_SDPIF_MARC_BASE_LO_2__SDPIF_MARC_BASE_LO_2), 0x20000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_RELOC_LO_2, 2,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_EN_2), 0,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_2__SDPIF_MARC_RELOC_LO_2), 0xb0000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_LENGTH_LO_2, 1,
+ FD(DCHUBBUB_SDPIF_MARC_LENGTH_LO_2__SDPIF_MARC_LENGTH_LO_2), 0x10000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_BASE_LO_3, 1,
+ FD(DCHUBBUB_SDPIF_MARC_BASE_LO_3__SDPIF_MARC_BASE_LO_3), 0x30000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_RELOC_LO_3, 2,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_EN_3), 0,
+ FD(DCHUBBUB_SDPIF_MARC_RELOC_LO_3__SDPIF_MARC_RELOC_LO_3), 0xc0000);
+
+ generic_reg_set_soc15(ctx, 0, DCHUBBUB_SDPIF_MARC_LENGTH_LO_3, 1,
+ FD(DCHUBBUB_SDPIF_MARC_LENGTH_LO_3__SDPIF_MARC_LENGTH_LO_3), 0x10000);
+
+ /* TODO: Is DCN_VM_SYSTEM_APERTURE address one time programming?
+ * Are all 4 hubp programmed with the same address?
+ */
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 0x100000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0);
+
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 0x100000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0);
+
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 0x100000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0);
+
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0, 0x100000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0, 0);
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x80000);
+ dm_write_reg_soc15(ctx, mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0);
+}
+
+/* TODO: This is one time program during system boot up,
+ * this should be done within BIOS
+ */
+static void dchubup_setup_timer(struct dc_context *ctx)
+{
+ dm_write_reg_soc15(ctx, mmREFCLK_CNTL, 0, 0);
+
+ generic_reg_update_soc15(ctx, 0, DCHUBBUB_GLOBAL_TIMER_CNTL, 1,
+ FD(DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE), 1);
+}
+
+/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
+ * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
+ * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
+ */
+static void select_vtg(
+ struct dc_context *ctx,
+ uint8_t plane_id,
+ uint8_t inst)
+{
+ uint32_t inst_offset = reg_offsets[plane_id].dchubp;
+
+ HWSEQ_REG_UPDATE(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, inst);
+}
+
+static void enable_dcfclk(
+ struct dc_context *ctx,
+ uint8_t plane_id,
+ uint32_t requested_pix_clk,
+ bool dppclk_div)
+{
+ uint32_t inst_offset = reg_offsets[plane_id].dchubp;
+
+ HWSEQ_REG_UPDATE(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, 1);
+}
+
+static void enable_dppclk(
+ struct dc_context *ctx,
+ uint8_t plane_id,
+ uint32_t requested_pix_clk,
+ bool dppclk_div)
+{
+ uint32_t inst_offset = reg_offsets[plane_id].dpp;
+
+ dm_logger_write(ctx->logger, LOG_SURFACE,
+ "dppclk_rate_control for pipe %d programed to %d\n",
+ plane_id,
+ dppclk_div);
+
+ /* TODO: find condition for DPP clock to DISPCLK or 1/2 DISPCLK */
+ if (dppclk_div) {
+ /* 1/2 DISPCLK*/
+ HWSEQ_REG_UPDATE_2(DPP_TOP0_DPP_CONTROL,
+ DPPCLK_RATE_CONTROL, 1,
+ DPP_CLOCK_ENABLE, 1);
+ } else {
+ /* DISPCLK */
+ HWSEQ_REG_UPDATE_2(DPP_TOP0_DPP_CONTROL,
+ DPPCLK_RATE_CONTROL, 0,
+ DPP_CLOCK_ENABLE, 1);
+ }
+}
+
+static void enable_power_gating_plane(
+ struct dc_context *ctx,
+ bool enable)
+{
+ uint32_t inst_offset = 0; /* each register only has one instance */
+ bool force_on = 1; /* disable power gating */
+
+ if (enable)
+ force_on = 0;
+
+ /* DCHUBP0/1/2/3 */
+ HWSEQ_REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
+
+ /* DPP0/1/2/3 */
+ HWSEQ_REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
+ HWSEQ_REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
+
+ if (ctx->dc->debug.disable_clock_gate) {
+ /* probably better to just write entire register to 0xffff to
+ * ensure all clock gating is disabled
+ */
+ HWSEQ_REG_UPDATE_3(DCCG_GATE_DISABLE_CNTL,
+ DISPCLK_R_DCCG_GATE_DISABLE, 1,
+ DPREFCLK_R_DCCG_GATE_DISABLE, 1,
+ REFCLK_R_DIG_GATE_DISABLE, 1);
+ HWSEQ_REG_UPDATE(DCFCLK_CNTL,
+ DCFCLK_GATE_DIS, 1);
+ }
+
+}
+
+static void dpp_pg_control(
+ struct dc_context *ctx,
+ unsigned int dpp_inst,
+ bool power_on)
+{
+ uint32_t inst_offset = 0;
+ uint32_t power_gate = power_on ? 0 : 1;
+ uint32_t pwr_status = power_on ? 0 : 2;
+
+ if (ctx->dc->debug.disable_dpp_power_gate)
+ return;
+
+ switch (dpp_inst) {
+ case 0: /* DPP0 */
+ HWSEQ_REG_UPDATE(DOMAIN1_PG_CONFIG,
+ DOMAIN1_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN1_PG_STATUS,
+ DOMAIN1_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 1: /* DPP1 */
+ HWSEQ_REG_UPDATE(DOMAIN3_PG_CONFIG,
+ DOMAIN3_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN3_PG_STATUS,
+ DOMAIN3_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 2: /* DPP2 */
+ HWSEQ_REG_UPDATE(DOMAIN5_PG_CONFIG,
+ DOMAIN5_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN5_PG_STATUS,
+ DOMAIN5_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 3: /* DPP3 */
+ HWSEQ_REG_UPDATE(DOMAIN7_PG_CONFIG,
+ DOMAIN7_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN7_PG_STATUS,
+ DOMAIN7_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+}
+
+static void hubp_pg_control(
+ struct dc_context *ctx,
+ unsigned int hubp_inst,
+ bool power_on)
+{
+ uint32_t inst_offset = 0;
+ uint32_t power_gate = power_on ? 0 : 1;
+ uint32_t pwr_status = power_on ? 0 : 2;
+
+ if (ctx->dc->debug.disable_hubp_power_gate)
+ return;
+
+ switch (hubp_inst) {
+ case 0: /* DCHUBP0 */
+ HWSEQ_REG_UPDATE(DOMAIN0_PG_CONFIG,
+ DOMAIN0_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN0_PG_STATUS,
+ DOMAIN0_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 1: /* DCHUBP1 */
+ HWSEQ_REG_UPDATE(DOMAIN2_PG_CONFIG,
+ DOMAIN2_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN2_PG_STATUS,
+ DOMAIN2_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 2: /* DCHUBP2 */
+ HWSEQ_REG_UPDATE(DOMAIN4_PG_CONFIG,
+ DOMAIN4_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN4_PG_STATUS,
+ DOMAIN4_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ case 3: /* DCHUBP3 */
+ HWSEQ_REG_UPDATE(DOMAIN6_PG_CONFIG,
+ DOMAIN6_POWER_GATE, power_gate);
+
+ wait_reg(ctx, 0, DOMAIN6_PG_STATUS,
+ DOMAIN6_PGFSM_PWR_STATUS, pwr_status);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+}
+
+static void power_on_plane(
+ struct dc_context *ctx,
+ uint8_t plane_id,
+ uint8_t inst)
+{
+ uint32_t inst_offset = 0;
+
+ /* disable clock power gating */
+
+ /* DCCG_GATE_DISABLE_CNTL only has one instance */
+ HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
+ DISPCLK_DCCG_GATE_DISABLE, 1,
+ DPPCLK_GATE_DISABLE, 1);
+ /* DCFCLK_CNTL only has one instance */
+ HWSEQ_REG_UPDATE(DCFCLK_CNTL,
+ DCFCLK_GATE_DIS, 1);
+
+ HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
+ IP_REQUEST_EN, 1);
+ dpp_pg_control(ctx, plane_id, true);
+ hubp_pg_control(ctx, plane_id, true);
+ HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
+ IP_REQUEST_EN, 0);
+
+ if (ctx->dc->debug.disable_clock_gate) {
+ HWSEQ_REG_UPDATE(DCCG_GATE_DISABLE_CNTL,
+ DISPCLK_DCCG_GATE_DISABLE, 0);
+ } else {
+ /* DCCG_GATE_DISABLE_CNTL only has one instance. inst_offset = 0 */
+ HWSEQ_REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL,
+ DISPCLK_DCCG_GATE_DISABLE, 0,
+ DPPCLK_GATE_DISABLE, 0);
+ /* DCFCLK_CNTL only has one instance. inst_offset = 0 */
+ HWSEQ_REG_UPDATE(DCFCLK_CNTL,
+ DCFCLK_GATE_DIS, 0);
+ }
+}
+
+/* fully check bios enabledisplaypowergating table. dal only need dce init
+ * other power, clock gate register will be handle by dal itself.
+ * further may be put within init_hw
+ */
+static bool dcn10_enable_display_power_gating(
+ struct core_dc *dc,
+ uint8_t controller_id,
+ struct dc_bios *dcb,
+ enum pipe_gating_control power_gating)
+{
+ /* TODOFPGA */
+#if 0
+ if (power_gating != PIPE_GATING_CONTROL_ENABLE)
+ dce110_init_pte(ctx);
+#endif
+
+ return true;
+}
+
+static void bios_golden_init(struct core_dc *dc)
+{
+ struct dc_bios *bp = dc->ctx->dc_bios;
+ int i;
+
+ /* initialize dcn global */
+ bp->funcs->enable_disp_power_gating(bp,
+ CONTROLLER_ID_D0, ASIC_PIPE_INIT);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ /* initialize dcn per pipe */
+ bp->funcs->enable_disp_power_gating(bp,
+ CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
+ }
+}
+
+static void init_hw(struct core_dc *dc)
+{
+ int i;
+ struct dc_bios *bp;
+ struct transform *xfm;
+ struct abm *abm;
+
+ bp = dc->ctx->dc_bios;
+
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ /* TODO: this will be moved to Diag or BIOS */
+ dchubup_setup_timer(dc->ctx);
+
+ /* TODO: dchubp_map_fb_to_mc will be moved to dchub interface
+ * between dc and kmd
+ */
+ dchubp_map_fb_to_mc(dc->ctx);
+
+ enable_power_gating_plane(dc->ctx, true);
+ return;
+ }
+ /* end of FPGA. Below if real ASIC */
+
+ bios_golden_init(dc);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ xfm = dc->res_pool->transforms[i];
+ xfm->funcs->transform_reset(xfm);
+
+ /* TODOFPGA: may need later */
+#if 0
+ xfm->funcs->transform_power_up(xfm);
+ dc->hwss.enable_display_pipe_clock_gating(
+ dc->ctx,
+ true);
+#endif
+ }
+ /* TODOFPGA: light sleep */
+#if 0
+ dc->hwss.clock_gating_power_up(dc->ctx, false);
+#endif
+
+ for (i = 0; i < dc->link_count; i++) {
+ /* Power up AND update implementation according to the
+ * required signal (which may be different from the
+ * default signal on connector).
+ */
+ struct core_link *link = dc->links[i];
+
+ link->link_enc->funcs->hw_init(link->link_enc);
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct timing_generator *tg =
+ dc->res_pool->timing_generators[i];
+
+ tg->funcs->disable_vga(tg);
+
+ /* Blank controller using driver code instead of
+ * command table.
+ */
+ tg->funcs->set_blank(tg, true);
+ hwss_wait_for_blank_complete(tg);
+ }
+
+ for (i = 0; i < dc->res_pool->audio_count; i++) {
+ struct audio *audio = dc->res_pool->audios[i];
+
+ audio->funcs->hw_init(audio);
+ }
+
+ abm = dc->res_pool->abm;
+ if (abm != NULL) {
+ abm->funcs->init_backlight(abm);
+ abm->funcs->abm_init(abm);
+ }
+
+ /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+ generic_reg_set_soc15(dc->ctx, 0, DIO_MEM_PWR_CTRL, 7,
+ FD(DIO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE), 0,
+ FD(DIO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE), 0);
+
+ /* This power gating should be one-time program for DAL.
+ * It can only change by registry key
+ * TODO: new task will for this.
+ * if power gating is disable, power_on_plane and power_off_plane
+ * should be skip. Otherwise, hand will be met in power_off_plane
+ */
+
+ enable_power_gating_plane(dc->ctx, true);
+}
+
+static enum dc_status dcn10_prog_pixclk_crtc_otg(
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context,
+ struct core_dc *dc)
+{
+ struct core_stream *stream = pipe_ctx->stream;
+ enum dc_color_space color_space;
+ struct tg_color black_color = {0};
+ bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
+ false:true;
+ bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
+
+
+ /* by upper caller loop, pipe0 is parent pipe and be called first.
+ * back end is set up by for pipe0. Other children pipe share back end
+ * with pipe 0. No program is needed.
+ */
+ if (pipe_ctx->top_pipe != NULL)
+ return DC_OK;
+
+ /* TODO check if timing_changed, disable stream if timing changed */
+
+ /* HW program guide assume display already disable
+ * by unplug sequence. OTG assume stop.
+ */
+ pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true);
+
+ if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
+ pipe_ctx->clock_source,
+ &pipe_ctx->pix_clk_params,
+ &pipe_ctx->pll_settings)) {
+ BREAK_TO_DEBUGGER();
+ return DC_ERROR_UNEXPECTED;
+ }
+ pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
+ pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
+ pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
+ pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
+
+ pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
+
+ pipe_ctx->tg->funcs->program_timing(
+ pipe_ctx->tg,
+ &stream->public.timing,
+ true);
+
+ pipe_ctx->opp->funcs->opp_set_stereo_polarity(
+ pipe_ctx->opp,
+ enableStereo,
+ rightEyePolarity);
+
+#if 0 /* move to after enable_crtc */
+ /* TODO: OPP FMT, ABM. etc. should be done here. */
+ /* or FPGA now. instance 0 only. TODO: move to opp.c */
+
+ inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
+
+ pipe_ctx->opp->funcs->opp_program_fmt(
+ pipe_ctx->opp,
+ &stream->bit_depth_params,
+ &stream->clamping);
+#endif
+ /* program otg blank color */
+ color_space = stream->public.output_color_space;
+ color_space_to_black_color(dc, color_space, &black_color);
+ pipe_ctx->tg->funcs->set_blank_color(
+ pipe_ctx->tg,
+ &black_color);
+
+ pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
+ hwss_wait_for_blank_complete(pipe_ctx->tg);
+
+ /* VTG is within DCHUB command block. DCFCLK is always on */
+ if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
+ BREAK_TO_DEBUGGER();
+ return DC_ERROR_UNEXPECTED;
+ }
+
+ /* TODO program crtc source select for non-virtual signal*/
+ /* TODO program FMT */
+ /* TODO setup link_enc */
+ /* TODO set stream attributes */
+ /* TODO program audio */
+ /* TODO enable stream if timing changed */
+ /* TODO unblank stream if DP */
+
+ return DC_OK;
+}
+
+static void reset_back_end_for_pipe(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context)
+{
+ int i;
+ struct dc_bios *bp;
+
+ bp = dc->ctx->dc_bios;
+
+ if (pipe_ctx->stream_enc == NULL) {
+ pipe_ctx->stream = NULL;
+ return;
+ }
+
+ /* TODOFPGA break core_link_disable_stream into 2 functions:
+ * disable_stream and disable_link. disable_link will disable PHYPLL
+ * which is used by otg. Move disable_link after disable_crtc
+ */
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ core_link_disable_stream(pipe_ctx);
+
+ /* by upper caller loop, parent pipe: pipe0, will be reset last.
+ * back end share by all pipes and will be disable only when disable
+ * parent pipe.
+ */
+ if (pipe_ctx->top_pipe == NULL) {
+ pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
+
+ pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false);
+ }
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ resource_unreference_clock_source(
+ &context->res_ctx, dc->res_pool,
+ &pipe_ctx->clock_source);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++)
+ if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx)
+ break;
+
+ if (i == dc->res_pool->pipe_count)
+ return;
+
+ pipe_ctx->stream = NULL;
+}
+
+static void reset_front_end_for_pipe(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context)
+{
+ struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc);
+ struct mpc_tree_cfg *tree_cfg = NULL;
+
+ if (!pipe_ctx->surface)
+ return;
+
+ lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
+
+ /* TODO: build stream pipes group id. For now, use stream otg
+ * id as pipe group id
+ */
+ tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
+
+ if (pipe_ctx->top_pipe == NULL)
+ dcn10_delete_mpc_tree(mpc, tree_cfg);
+ else {
+ if (dcn10_remove_dpp(mpc, tree_cfg, pipe_ctx->pipe_idx))
+ pipe_ctx->top_pipe->bottom_pipe = NULL;
+ else {
+ dm_logger_write(dc->ctx->logger, LOG_RESOURCE,
+ "%s: failed to find dpp to be removed!\n",
+ __func__);
+ }
+ }
+
+ pipe_ctx->top_pipe = NULL;
+ pipe_ctx->bottom_pipe = NULL;
+ pipe_ctx->mpc_idx = -1;
+
+ unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst);
+
+ pipe_ctx->mi->funcs->disable_request(pipe_ctx->mi);
+
+ wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx);
+
+ wait_mpcc_idle(mpc, pipe_ctx->pipe_idx);
+
+ disable_clocks(dc->ctx, pipe_ctx->pipe_idx);
+
+ pipe_ctx->xfm->funcs->transform_reset(pipe_ctx->xfm);
+
+ dm_logger_write(dc->ctx->logger, LOG_DC,
+ "Reset front end for pipe %d\n",
+ pipe_ctx->pipe_idx);
+
+ pipe_ctx->surface = NULL;
+}
+
+static void reset_hw_ctx(struct core_dc *dc,
+ struct validate_context *context,
+ void (*reset)(struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context))
+{
+ int i;
+
+ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+ struct pipe_ctx *pipe_ctx_old =
+ &dc->current_context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe_ctx_old->stream)
+ continue;
+
+ if (!pipe_ctx->stream ||
+ pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+ reset(dc, pipe_ctx_old, dc->current_context);
+ }
+}
+
+static void reset_hw_ctx_wrap(
+ struct core_dc *dc,
+ struct validate_context *context)
+{
+ /* Reset Front End*/
+ reset_hw_ctx(dc, context, reset_front_end_for_pipe);
+ /* Reset Back End*/
+ reset_hw_ctx(dc, context, reset_back_end_for_pipe);
+
+ memcpy(context->res_ctx.mpc_tree,
+ dc->current_context->res_ctx.mpc_tree,
+ sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count);
+}
+
+static bool patch_address_for_sbs_tb_stereo(struct pipe_ctx *pipe_ctx,
+ PHYSICAL_ADDRESS_LOC *addr)
+{
+ struct core_surface *surface = pipe_ctx->surface;
+ bool sec_split = pipe_ctx->top_pipe &&
+ pipe_ctx->top_pipe->surface == pipe_ctx->surface;
+ if (sec_split && surface->public.address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
+ (pipe_ctx->stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_SIDE_BY_SIDE ||
+ pipe_ctx->stream->public.timing.timing_3d_format ==
+ TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
+ *addr = surface->public.address.grph_stereo.left_addr;
+ surface->public.address.grph_stereo.left_addr =\
+ surface->public.address.grph_stereo.right_addr;
+ return true;
+ }
+ return false;
+}
+
+static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ bool addr_patched = false;
+ PHYSICAL_ADDRESS_LOC addr;
+ struct core_surface *surface = pipe_ctx->surface;
+
+ if (surface == NULL)
+ return;
+ addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
+ pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr(
+ pipe_ctx->mi,
+ &surface->public.address,
+ surface->public.flip_immediate);
+ surface->status.requested_address = surface->public.address;
+ if (addr_patched)
+ pipe_ctx->surface->public.address.grph_stereo.left_addr = addr;
+}
+
+static bool dcn10_set_input_transfer_func(
+ struct pipe_ctx *pipe_ctx,
+ const struct core_surface *surface)
+{
+ struct input_pixel_processor *ipp = pipe_ctx->ipp;
+ const struct core_transfer_func *tf = NULL;
+ bool result = true;
+
+ if (ipp == NULL)
+ return false;
+
+ if (surface->public.in_transfer_func)
+ tf = DC_TRANSFER_FUNC_TO_CORE(surface->public.in_transfer_func);
+
+ if (tf == NULL)
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
+ else if (tf->public.type == TF_TYPE_PREDEFINED) {
+ switch (tf->public.tf) {
+ case TRANSFER_FUNCTION_SRGB:
+ ipp->funcs->ipp_set_degamma(ipp,
+ IPP_DEGAMMA_MODE_HW_sRGB);
+ break;
+ case TRANSFER_FUNCTION_BT709:
+ ipp->funcs->ipp_set_degamma(ipp,
+ IPP_DEGAMMA_MODE_HW_xvYCC);
+ break;
+ case TRANSFER_FUNCTION_LINEAR:
+ ipp->funcs->ipp_set_degamma(ipp,
+ IPP_DEGAMMA_MODE_BYPASS);
+ break;
+ case TRANSFER_FUNCTION_PQ:
+ result = false;
+ break;
+ default:
+ result = false;
+ break;
+ }
+ } else if (tf->public.type == TF_TYPE_BYPASS) {
+ ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
+ } else {
+ /*TF_TYPE_DISTRIBUTED_POINTS*/
+ result = false;
+ }
+
+ return result;
+}
+/*modify the method to handle rgb for arr_points*/
+static bool convert_to_custom_float(
+ struct pwl_result_data *rgb_resulted,
+ struct curve_points *arr_points,
+ uint32_t hw_points_num)
+{
+ struct custom_float_format fmt;
+
+ struct pwl_result_data *rgb = rgb_resulted;
+
+ uint32_t i = 0;
+
+ fmt.exponenta_bits = 6;
+ fmt.mantissa_bits = 12;
+ fmt.sign = false;
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].x,
+ &fmt,
+ &arr_points[0].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].offset,
+ &fmt,
+ &arr_points[0].custom_float_offset)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[0].slope,
+ &fmt,
+ &arr_points[0].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ fmt.mantissa_bits = 10;
+ fmt.sign = false;
+
+ if (!convert_to_custom_float_format(
+ arr_points[1].x,
+ &fmt,
+ &arr_points[1].custom_float_x)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[1].y,
+ &fmt,
+ &arr_points[1].custom_float_y)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ arr_points[1].slope,
+ &fmt,
+ &arr_points[1].custom_float_slope)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ fmt.mantissa_bits = 12;
+ fmt.sign = true;
+
+ while (i != hw_points_num) {
+ if (!convert_to_custom_float_format(
+ rgb->red,
+ &fmt,
+ &rgb->red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->green,
+ &fmt,
+ &rgb->green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->blue,
+ &fmt,
+ &rgb->blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_red,
+ &fmt,
+ &rgb->delta_red_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_green,
+ &fmt,
+ &rgb->delta_green_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ if (!convert_to_custom_float_format(
+ rgb->delta_blue,
+ &fmt,
+ &rgb->delta_blue_reg)) {
+ BREAK_TO_DEBUGGER();
+ return false;
+ }
+
+ ++rgb;
+ ++i;
+ }
+
+ return true;
+}
+#define MAX_REGIONS_NUMBER 34
+#define MAX_LOW_POINT 25
+#define NUMBER_SEGMENTS 32
+
+static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
+ *output_tf, struct pwl_params *regamma_params)
+{
+ struct curve_points *arr_points;
+ struct pwl_result_data *rgb_resulted;
+ struct pwl_result_data *rgb;
+ struct pwl_result_data *rgb_plus_1;
+ struct fixed31_32 y_r;
+ struct fixed31_32 y_g;
+ struct fixed31_32 y_b;
+ struct fixed31_32 y1_min;
+ struct fixed31_32 y3_max;
+
+ int32_t segment_start, segment_end;
+ int32_t i;
+ uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
+
+ if (output_tf == NULL || regamma_params == NULL ||
+ output_tf->type == TF_TYPE_BYPASS)
+ return false;
+
+ arr_points = regamma_params->arr_points;
+ rgb_resulted = regamma_params->rgb_resulted;
+ hw_points = 0;
+
+ memset(regamma_params, 0, sizeof(struct pwl_params));
+ memset(seg_distr, 0, sizeof(seg_distr));
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* 32 segments
+ * segments are from 2^-25 to 2^7
+ */
+ for (i = 0; i < 32 ; i++)
+ seg_distr[i] = 3;
+
+ segment_start = -25;
+ segment_end = 7;
+ } else {
+ /* 10 segments
+ * segment is from 2^-10 to 2^0
+ * There are less than 256 points, for optimization
+ */
+ seg_distr[0] = 3;
+ seg_distr[1] = 4;
+ seg_distr[2] = 4;
+ seg_distr[3] = 4;
+ seg_distr[4] = 4;
+ seg_distr[5] = 4;
+ seg_distr[6] = 4;
+ seg_distr[7] = 4;
+ seg_distr[8] = 5;
+ seg_distr[9] = 5;
+
+ segment_start = -10;
+ segment_end = 0;
+ }
+
+ for (i = segment_end - segment_start; i < MAX_REGIONS_NUMBER ; i++)
+ seg_distr[i] = -1;
+
+ for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
+ if (seg_distr[k] != -1)
+ hw_points += (1 << seg_distr[k]);
+ }
+
+ j = 0;
+ for (k = 0; k < (segment_end - segment_start); k++) {
+ increment = NUMBER_SEGMENTS / (1 << seg_distr[k]);
+ start_index = (segment_start + k + MAX_LOW_POINT) * NUMBER_SEGMENTS;
+ for (i = start_index; i < start_index + NUMBER_SEGMENTS; i += increment) {
+ if (j == hw_points - 1)
+ break;
+ rgb_resulted[j].red = output_tf->tf_pts.red[i];
+ rgb_resulted[j].green = output_tf->tf_pts.green[i];
+ rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
+ j++;
+ }
+ }
+
+ /* last point */
+ start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS;
+ rgb_resulted[hw_points - 1].red =
+ output_tf->tf_pts.red[start_index];
+ rgb_resulted[hw_points - 1].green =
+ output_tf->tf_pts.green[start_index];
+ rgb_resulted[hw_points - 1].blue =
+ output_tf->tf_pts.blue[start_index];
+
+ arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_start));
+ arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_end));
+ arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
+ dal_fixed31_32_from_int(segment_end));
+
+ y_r = rgb_resulted[0].red;
+ y_g = rgb_resulted[0].green;
+ y_b = rgb_resulted[0].blue;
+
+ y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+
+ arr_points[0].y = y1_min;
+ arr_points[0].slope = dal_fixed31_32_div(
+ arr_points[0].y,
+ arr_points[0].x);
+ y_r = rgb_resulted[hw_points - 1].red;
+ y_g = rgb_resulted[hw_points - 1].green;
+ y_b = rgb_resulted[hw_points - 1].blue;
+
+ /* see comment above, m_arrPoints[1].y should be the Y value for the
+ * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
+ */
+ y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+
+ arr_points[1].y = y3_max;
+ arr_points[2].y = y3_max;
+
+ arr_points[1].slope = dal_fixed31_32_zero;
+ arr_points[2].slope = dal_fixed31_32_zero;
+
+ if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
+ /* for PQ, we want to have a straight line from last HW X point,
+ * and the slope to be such that we hit 1.0 at 10000 nits.
+ */
+ const struct fixed31_32 end_value =
+ dal_fixed31_32_from_int(125);
+
+ arr_points[1].slope = dal_fixed31_32_div(
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
+ arr_points[2].slope = dal_fixed31_32_div(
+ dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
+ dal_fixed31_32_sub(end_value, arr_points[1].x));
+ }
+
+ regamma_params->hw_points_num = hw_points;
+
+ i = 1;
+ for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
+ if (seg_distr[k] != -1) {
+ regamma_params->arr_curve_points[k].segments_num =
+ seg_distr[k];
+ regamma_params->arr_curve_points[i].offset =
+ regamma_params->arr_curve_points[k].
+ offset + (1 << seg_distr[k]);
+ }
+ i++;
+ }
+
+ if (seg_distr[k] != -1)
+ regamma_params->arr_curve_points[k].segments_num =
+ seg_distr[k];
+
+ rgb = rgb_resulted;
+ rgb_plus_1 = rgb_resulted + 1;
+
+ i = 1;
+
+ while (i != hw_points + 1) {
+ if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+ rgb_plus_1->red = rgb->red;
+ if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+ rgb_plus_1->green = rgb->green;
+ if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+ rgb_plus_1->blue = rgb->blue;
+
+ rgb->delta_red = dal_fixed31_32_sub(
+ rgb_plus_1->red,
+ rgb->red);
+ rgb->delta_green = dal_fixed31_32_sub(
+ rgb_plus_1->green,
+ rgb->green);
+ rgb->delta_blue = dal_fixed31_32_sub(
+ rgb_plus_1->blue,
+ rgb->blue);
+
+ ++rgb_plus_1;
+ ++rgb;
+ ++i;
+ }
+
+ convert_to_custom_float(rgb_resulted, arr_points, hw_points);
+
+ return true;
+}
+
+static bool dcn10_set_output_transfer_func(
+ struct pipe_ctx *pipe_ctx,
+ const struct core_surface *surface,
+ const struct core_stream *stream)
+{
+ struct output_pixel_processor *opp = pipe_ctx->opp;
+
+ opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
+
+ if (stream->public.out_transfer_func &&
+ stream->public.out_transfer_func->type ==
+ TF_TYPE_PREDEFINED &&
+ stream->public.out_transfer_func->tf ==
+ TRANSFER_FUNCTION_SRGB) {
+ opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
+ } else if (dcn10_translate_regamma_to_hw_format(
+ stream->public.out_transfer_func, &opp->regamma_params)) {
+ opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params);
+ opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
+ } else {
+ opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
+ }
+
+ return true;
+}
+
+static void dcn10_pipe_control_lock(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe,
+ bool lock)
+{
+ struct dce_hwseq *hws = hws = dc->hwseq;
+
+ /* use TG master update lock to lock everything on the TG
+ * therefore only top pipe need to lock
+ */
+ if (pipe->top_pipe)
+ return;
+
+ if (lock)
+ dcn10_lock(pipe->tg);
+ else
+ dcn10_unlock(pipe->tg);
+}
+
+static bool wait_for_reset_trigger_to_occur(
+ struct dc_context *dc_ctx,
+ struct timing_generator *tg)
+{
+ bool rc = false;
+
+ /* To avoid endless loop we wait at most
+ * frames_to_wait_on_triggered_reset frames for the reset to occur. */
+ const uint32_t frames_to_wait_on_triggered_reset = 10;
+ int i;
+
+ for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
+
+ if (!tg->funcs->is_counter_moving(tg)) {
+ DC_ERROR("TG counter is not moving!\n");
+ break;
+ }
+
+ if (tg->funcs->did_triggered_reset_occur(tg)) {
+ rc = true;
+ /* usually occurs at i=1 */
+ DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
+ i);
+ break;
+ }
+
+ /* Wait for one frame. */
+ tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
+ tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
+ }
+
+ if (false == rc)
+ DC_ERROR("GSL: Timeout on reset trigger!\n");
+
+ return rc;
+}
+
+static void dcn10_enable_timing_synchronization(
+ struct core_dc *dc,
+ int group_index,
+ int group_size,
+ struct pipe_ctx *grouped_pipes[])
+{
+ struct dc_context *dc_ctx = dc->ctx;
+ int i;
+
+ DC_SYNC_INFO("Setting up OTG reset trigger\n");
+
+ for (i = 1; i < group_size; i++)
+ grouped_pipes[i]->tg->funcs->enable_reset_trigger(
+ grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst);
+
+
+ DC_SYNC_INFO("Waiting for trigger\n");
+
+ /* Need to get only check 1 pipe for having reset as all the others are
+ * synchronized. Look at last pipe programmed to reset.
+ */
+ wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg);
+ for (i = 1; i < group_size; i++)
+ grouped_pipes[i]->tg->funcs->disable_reset_trigger(
+ grouped_pipes[i]->tg);
+
+ DC_SYNC_INFO("Sync complete\n");
+}
+
+static void dcn10_power_on_fe(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context)
+{
+ struct dc_surface *dc_surface = &pipe_ctx->surface->public;
+
+ /* power up DCHUP and DPP from pseudo code pipe_move.c */
+ /*TODO: function: power_on_plane. If already power up, skip
+ */
+ {
+ power_on_plane(dc->ctx,
+ pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
+
+ /* enable DCFCLK current DCHUB */
+ enable_dcfclk(dc->ctx,
+ pipe_ctx->pipe_idx,
+ pipe_ctx->pix_clk_params.requested_pix_clk,
+ context->dppclk_div);
+
+ if (dc_surface) {
+ dm_logger_write(dc->ctx->logger, LOG_DC,
+ "Pipe:%d 0x%x: addr hi:0x%x, "
+ "addr low:0x%x, "
+ "src: %d, %d, %d,"
+ " %d; dst: %d, %d, %d, %d;\n",
+ pipe_ctx->pipe_idx,
+ dc_surface,
+ dc_surface->address.grph.addr.high_part,
+ dc_surface->address.grph.addr.low_part,
+ dc_surface->src_rect.x,
+ dc_surface->src_rect.y,
+ dc_surface->src_rect.width,
+ dc_surface->src_rect.height,
+ dc_surface->dst_rect.x,
+ dc_surface->dst_rect.y,
+ dc_surface->dst_rect.width,
+ dc_surface->dst_rect.height);
+
+ dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE,
+ "Pipe %d: width, height, x, y\n"
+ "viewport:%d, %d, %d, %d\n"
+ "recout: %d, %d, %d, %d\n",
+ pipe_ctx->pipe_idx,
+ pipe_ctx->scl_data.viewport.width,
+ pipe_ctx->scl_data.viewport.height,
+ pipe_ctx->scl_data.viewport.x,
+ pipe_ctx->scl_data.viewport.y,
+ pipe_ctx->scl_data.recout.width,
+ pipe_ctx->scl_data.recout.height,
+ pipe_ctx->scl_data.recout.x,
+ pipe_ctx->scl_data.recout.y);
+ }
+ }
+
+}
+
+static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
+{
+ struct xfm_grph_csc_adjustment adjust;
+ memset(&adjust, 0, sizeof(adjust));
+ adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
+
+
+ if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
+ adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
+ adjust.temperature_matrix[0] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[0];
+ adjust.temperature_matrix[1] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[1];
+ adjust.temperature_matrix[2] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[2];
+ adjust.temperature_matrix[3] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[4];
+ adjust.temperature_matrix[4] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[5];
+ adjust.temperature_matrix[5] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[6];
+ adjust.temperature_matrix[6] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[8];
+ adjust.temperature_matrix[7] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[9];
+ adjust.temperature_matrix[8] =
+ pipe_ctx->stream->
+ public.gamut_remap_matrix.matrix[10];
+ }
+
+ pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
+}
+
+static void update_dchubp_dpp(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context)
+{
+ struct mem_input *mi = pipe_ctx->mi;
+ struct input_pixel_processor *ipp = pipe_ctx->ipp;
+ struct core_surface *surface = pipe_ctx->surface;
+ union plane_size size = surface->public.plane_size;
+ struct mpc_tree_cfg *tree_cfg = NULL;
+ struct default_adjustment ocsc = {0};
+ enum dc_color_space color_space;
+ struct tg_color black_color = {0};
+ struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc);
+
+ /* depends on DML calculation, DPP clock value may change dynamically */
+ enable_dppclk(
+ dc->ctx,
+ pipe_ctx->pipe_idx,
+ pipe_ctx->pix_clk_params.requested_pix_clk,
+ context->dppclk_div);
+
+ select_vtg(dc->ctx, pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
+
+ update_plane_addr(dc, pipe_ctx);
+
+ mi->funcs->mem_input_setup(
+ mi,
+ &pipe_ctx->dlg_regs,
+ &pipe_ctx->ttu_regs,
+ &pipe_ctx->rq_regs,
+ &pipe_ctx->pipe_dlg_param);
+
+ size.grph.surface_size = pipe_ctx->scl_data.viewport;
+
+ if (dc->public.config.gpu_vm_support)
+ mi->funcs->mem_input_program_pte_vm(
+ pipe_ctx->mi,
+ surface->public.format,
+ &surface->public.tiling_info,
+ surface->public.rotation);
+
+ ipp->funcs->ipp_setup(ipp,
+ surface->public.format,
+ 1,
+ IPP_OUTPUT_FORMAT_12_BIT_FIX);
+
+ /* mpc TODO un-hardcode object ids
+ * for pseudo code pipe_move.c :
+ * add_plane_mpcc(added_plane_inst, mpcc_inst, ...);
+ * Do we want to cache the tree_cfg?
+ */
+
+ /* TODO: build stream pipes group id. For now, use stream otg
+ * id as pipe group id
+ */
+ pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
+ tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
+ /* enable when bottom pipe is present and
+ * it does not share a surface with current pipe
+ */
+ if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface) {
+ pipe_ctx->scl_data.lb_params.alpha_en = 1;
+ tree_cfg->mode = TOP_BLND;
+ } else {
+ pipe_ctx->scl_data.lb_params.alpha_en = 0;
+ tree_cfg->mode = TOP_PASSTHRU;
+ }
+ if (!pipe_ctx->top_pipe) {
+ /* primary pipe, set mpc tree index 0 only */
+ tree_cfg->num_pipes = 1;
+ tree_cfg->opp_id = pipe_ctx->tg->inst;
+ tree_cfg->dpp[0] = pipe_ctx->pipe_idx;
+ tree_cfg->mpcc[0] = pipe_ctx->pipe_idx;
+ dcn10_set_mpc_tree(mpc, tree_cfg);
+ } else {
+ /* TODO: add position is hard code to 1 for now
+ * If more than 2 pipes are supported, calculate position
+ */
+ dcn10_add_dpp(mpc, tree_cfg,
+ pipe_ctx->pipe_idx, pipe_ctx->pipe_idx, 1);
+ }
+
+ color_space = pipe_ctx->stream->public.output_color_space;
+ color_space_to_black_color(dc, color_space, &black_color);
+ dcn10_set_mpc_background_color(mpc, pipe_ctx->pipe_idx, &black_color);
+
+ pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+ /* scaler configuration */
+ pipe_ctx->xfm->funcs->transform_set_scaler(
+ pipe_ctx->xfm, &pipe_ctx->scl_data);
+
+ /*gamut remap*/
+ program_gamut_remap(pipe_ctx);
+
+ /*TODO add adjustments parameters*/
+ ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
+ pipe_ctx->opp->funcs->opp_set_csc_default(pipe_ctx->opp, &ocsc);
+
+ mi->funcs->mem_input_program_surface_config(
+ mi,
+ surface->public.format,
+ &surface->public.tiling_info,
+ &size,
+ surface->public.rotation,
+ &surface->public.dcc,
+ surface->public.horizontal_mirror,
+ surface->public.visible);
+
+ /* Only support one plane for now. */
+ pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !surface->public.visible);
+
+}
+
+static void program_all_pipe_in_tree(
+ struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context)
+{
+ unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+
+ if (pipe_ctx->surface->public.visible || pipe_ctx->top_pipe == NULL) {
+ dcn10_power_on_fe(dc, pipe_ctx, context);
+
+ /* lock otg_master_update to process all pipes associated with
+ * this OTG. this is done only one time.
+ */
+ if (pipe_ctx->top_pipe == NULL) {
+ /* watermark is for all pipes */
+ pipe_ctx->mi->funcs->program_watermarks(
+ pipe_ctx->mi, &context->watermarks, ref_clk_mhz);
+ lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
+ }
+ pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
+ pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
+ pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
+ pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
+ pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
+ pipe_ctx->tg->funcs->program_global_sync(
+ pipe_ctx->tg);
+ update_dchubp_dpp(dc, pipe_ctx, context);
+ }
+
+ if (pipe_ctx->bottom_pipe != NULL)
+ program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
+}
+
+static void dcn10_pplib_apply_display_requirements(
+ struct core_dc *dc,
+ struct validate_context *context)
+{
+ struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
+
+ pp_display_cfg->all_displays_in_sync = false;/*todo*/
+ pp_display_cfg->nb_pstate_switch_disable = false;
+ pp_display_cfg->min_engine_clock_khz = context->dcfclk_khz;
+ pp_display_cfg->min_memory_clock_khz = context->fclk_khz;
+ pp_display_cfg->min_engine_clock_deep_sleep_khz = context->dcfclk_deep_sleep_khz;
+ pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->dcfclk_deep_sleep_khz;
+ pp_display_cfg->avail_mclk_switch_time_us =
+ context->dram_ccm_us > 0 ? context->dram_ccm_us : 0;
+ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us =
+ context->min_active_dram_ccm_us > 0 ? context->min_active_dram_ccm_us : 0;
+ pp_display_cfg->min_dcfclock_khz = context->dcfclk_khz;
+ pp_display_cfg->disp_clk_khz = context->dispclk_khz;
+ dce110_fill_display_configs(context, pp_display_cfg);
+
+ if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
+ struct dm_pp_display_configuration)) != 0)
+ dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+
+ dc->prev_display_config = *pp_display_cfg;
+}
+
+static void dcn10_apply_ctx_for_surface(
+ struct core_dc *dc,
+ struct core_surface *surface,
+ struct validate_context *context)
+{
+ int i;
+
+ memcpy(context->res_ctx.mpc_tree,
+ dc->current_context->res_ctx.mpc_tree,
+ sizeof(struct mpc_tree_cfg) * dc->res_pool->pipe_count);
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe_ctx->surface)
+ continue;
+
+ /* looking for top pipe to program */
+ if (!pipe_ctx->top_pipe)
+ program_all_pipe_in_tree(dc, pipe_ctx, context);
+ }
+
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (!pipe_ctx->surface || pipe_ctx->top_pipe)
+ continue;
+
+ /* unlock master update lock */
+ unlock_otg_master(dc->ctx, pipe_ctx->tg->inst);
+ }
+
+ /* reset unused pipe */
+ for (i = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *old_pipe_ctx =
+ &dc->current_context->res_ctx.pipe_ctx[i];
+
+ if ((!pipe_ctx->surface && old_pipe_ctx->surface)
+ || (!pipe_ctx->stream && old_pipe_ctx->stream))
+ reset_front_end_for_pipe(dc,
+ old_pipe_ctx, dc->current_context);
+ }
+}
+
+static void dcn10_set_bandwidth(
+ struct core_dc *dc,
+ struct validate_context *context,
+ bool decrease_allowed)
+{
+ struct dm_pp_clock_for_voltage_req clock;
+
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ return;
+
+ if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
+ dc->res_pool->display_clock->funcs->set_clock(
+ dc->res_pool->display_clock,
+ context->dispclk_khz);
+ dc->current_context->dispclk_khz = context->dispclk_khz;
+ }
+ if (decrease_allowed || context->dcfclk_khz > dc->current_context->dcfclk_khz) {
+ clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
+ clock.clocks_in_khz = context->dcfclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+ }
+ if (decrease_allowed || context->fclk_khz > dc->current_context->fclk_khz) {
+ clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
+ clock.clocks_in_khz = context->fclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+ dc->current_context->fclk_khz = clock.clocks_in_khz ;
+ }
+ dcn10_pplib_apply_display_requirements(dc, context);
+}
+
+static void dcn10_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
+{
+ struct dc_context *ctx = dc->ctx;
+ uint32_t inst_offset = 0;
+
+ HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
+ IP_REQUEST_EN, 1);
+ dpp_pg_control(ctx, pipe->pipe_idx, false);
+ hubp_pg_control(ctx, pipe->pipe_idx, false);
+ HWSEQ_REG_SET(DC_IP_REQUEST_CNTL,
+ IP_REQUEST_EN, 0);
+
+ if (pipe->xfm)
+ pipe->xfm->funcs->transform_reset(pipe->xfm);
+ memset(&pipe->scl_data, 0, sizeof(pipe->scl_data));
+}
+
+static void set_drr(struct pipe_ctx **pipe_ctx,
+ int num_pipes, int vmin, int vmax)
+{
+ int i = 0;
+ struct drr_params params = {0};
+
+ params.vertical_total_max = vmax;
+ params.vertical_total_min = vmin;
+
+ /* TODO: If multiple pipes are to be supported, you need
+ * some GSL stuff
+ */
+ for (i = 0; i < num_pipes; i++) {
+ pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, ¶ms);
+ }
+}
+
+static void get_position(struct pipe_ctx **pipe_ctx,
+ int num_pipes,
+ struct crtc_position *position)
+{
+ int i = 0;
+
+ /* TODO: handle pipes > 1
+ */
+ for (i = 0; i < num_pipes; i++)
+ pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
+}
+
+static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
+ int num_pipes, const struct dc_static_screen_events *events)
+{
+ unsigned int i;
+ unsigned int value = 0;
+
+ if (events->surface_update)
+ value |= 0x80;
+ if (events->cursor_update)
+ value |= 0x2;
+
+ for (i = 0; i < num_pipes; i++)
+ pipe_ctx[i]->tg->funcs->
+ set_static_screen_control(pipe_ctx[i]->tg, value);
+}
+
+static void set_plane_config(
+ const struct core_dc *dc,
+ struct pipe_ctx *pipe_ctx,
+ struct resource_context *res_ctx)
+{
+ /* TODO */
+ program_gamut_remap(pipe_ctx);
+}
+
+static const struct hw_sequencer_funcs dcn10_funcs = {
+ .init_hw = init_hw,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+ .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
+ .set_plane_config = set_plane_config,
+ .update_plane_addr = update_plane_addr,
+ .update_pending_status = dce110_update_pending_status,
+ .set_input_transfer_func = dcn10_set_input_transfer_func,
+ .set_output_transfer_func = dcn10_set_output_transfer_func,
+ .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
+ .enable_timing_synchronization = dcn10_enable_timing_synchronization,
+ .update_info_frame = dce110_update_info_frame,
+ .enable_stream = dce110_enable_stream,
+ .disable_stream = dce110_disable_stream,
+ .unblank_stream = dce110_unblank_stream,
+ .enable_display_pipe_clock_gating = NULL, /* TODOFPGA */
+ .enable_display_power_gating = dcn10_enable_display_power_gating,
+ .power_down_front_end = dcn10_power_down_fe,
+ .power_on_front_end = dcn10_power_on_fe,
+ .pipe_control_lock = dcn10_pipe_control_lock,
+ .set_bandwidth = dcn10_set_bandwidth,
+ .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
+ .prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
+ .set_drr = set_drr,
+ .get_position = get_position,
+ .set_static_screen_control = set_static_screen_control
+};
+
+
+bool dcn10_hw_sequencer_construct(struct core_dc *dc)
+{
+ dc->hwss = dcn10_funcs;
+ return true;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
new file mode 100644
index 0000000..c3aff2e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -0,0 +1,38 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN10_H__
+#define __DC_HWSS_DCN10_H__
+
+#include "core_types.h"
+
+struct core_dc;
+
+bool dcn10_hw_sequencer_construct(struct core_dc *dc);
+extern void fill_display_configs(
+ const struct validate_context *context,
+ struct dm_pp_display_configuration *pp_display_cfg);
+
+#endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
new file mode 100644
index 0000000..3062b7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn10_ipp.h"
+#include "reg_helper.h"
+
+#define REG(reg) \
+ (ippn10->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
+
+#define CTX \
+ ippn10->base.ctx
+
+
+struct dcn10_input_csc_matrix {
+ enum dc_color_space color_space;
+ uint32_t regval[12];
+};
+
+static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
+ {COLOR_SPACE_SRGB,
+ {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+ {COLOR_SPACE_SRGB_LIMITED,
+ {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+ {COLOR_SPACE_YCBCR601,
+ {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
+ 0, 0x2000, 0x38b4, 0xe3a6} },
+ {COLOR_SPACE_YCBCR601_LIMITED,
+ {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
+ 0, 0x2568, 0x40de, 0xdd3a} },
+ {COLOR_SPACE_YCBCR709,
+ {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
+ 0x2000, 0x3b61, 0xe24f} },
+
+ {COLOR_SPACE_YCBCR709_LIMITED,
+ {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
+ 0x2568, 0x43ee, 0xdbb2} }
+};
+
+enum dcn10_input_csc_select {
+ INPUT_CSC_SELECT_BYPASS = 0,
+ INPUT_CSC_SELECT_ICSC,
+ INPUT_CSC_SELECT_COMA
+};
+
+static void dcn10_program_input_csc(
+ struct input_pixel_processor *ipp,
+ enum dc_color_space color_space,
+ enum dcn10_input_csc_select select)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ int i;
+ int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
+ const uint32_t *regval = NULL;
+ uint32_t selection = 1;
+
+ if (select == INPUT_CSC_SELECT_BYPASS) {
+ REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
+ return;
+ }
+
+ for (i = 0; i < arr_size; i++)
+ if (dcn10_input_csc_matrix[i].color_space == color_space) {
+ regval = dcn10_input_csc_matrix[i].regval;
+ break;
+ }
+
+ if (regval == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ if (select == INPUT_CSC_SELECT_COMA)
+ selection = 2;
+ REG_SET(CM_ICSC_CONTROL, 0,
+ CM_ICSC_MODE, selection);
+
+ if (select == INPUT_CSC_SELECT_ICSC) {
+ /*R*/
+ REG_SET_2(CM_ICSC_C11_C12, 0,
+ CM_ICSC_C11, regval[0],
+ CM_ICSC_C12, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_ICSC_C13_C14, 0,
+ CM_ICSC_C13, regval[0],
+ CM_ICSC_C14, regval[1]);
+ /*G*/
+ regval += 2;
+ REG_SET_2(CM_ICSC_C21_C22, 0,
+ CM_ICSC_C21, regval[0],
+ CM_ICSC_C22, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_ICSC_C23_C24, 0,
+ CM_ICSC_C23, regval[0],
+ CM_ICSC_C24, regval[1]);
+ /*B*/
+ regval += 2;
+ REG_SET_2(CM_ICSC_C31_C32, 0,
+ CM_ICSC_C31, regval[0],
+ CM_ICSC_C32, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_ICSC_C33_C34, 0,
+ CM_ICSC_C33, regval[0],
+ CM_ICSC_C34, regval[1]);
+ } else {
+ /*R*/
+ REG_SET_2(CM_COMA_C11_C12, 0,
+ CM_COMA_C11, regval[0],
+ CM_COMA_C12, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C13_C14, 0,
+ CM_COMA_C13, regval[0],
+ CM_COMA_C14, regval[1]);
+ /*G*/
+ regval += 2;
+ REG_SET_2(CM_COMA_C21_C22, 0,
+ CM_COMA_C21, regval[0],
+ CM_COMA_C22, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C23_C24, 0,
+ CM_COMA_C23, regval[0],
+ CM_COMA_C24, regval[1]);
+ /*B*/
+ regval += 2;
+ REG_SET_2(CM_COMA_C31_C32, 0,
+ CM_COMA_C31, regval[0],
+ CM_COMA_C32, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C33_C34, 0,
+ CM_COMA_C33, regval[0],
+ CM_COMA_C34, regval[1]);
+ }
+}
+
+/*program de gamma RAM B*/
+static void dcn10_ipp_program_degamma_lutb_settings(
+ struct input_pixel_processor *ipp,
+ const struct pwl_params *params)
+{
+ const struct gamma_curve *curve;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ REG_SET_2(CM_DGAM_RAMB_START_CNTL_B, 0,
+ CM_DGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0);
+
+ REG_SET_2(CM_DGAM_RAMB_START_CNTL_G, 0,
+ CM_DGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0);
+
+ REG_SET_2(CM_DGAM_RAMB_START_CNTL_R, 0,
+ CM_DGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0);
+
+ REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_B, 0,
+ CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_G, 0,
+ CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMB_SLOPE_CNTL_R, 0,
+ CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMB_END_CNTL1_B, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMB_END_CNTL2_B, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMB_END_CNTL1_G, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMB_END_CNTL2_G, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMB_END_CNTL1_R, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMB_END_CNTL2_R, 0,
+ CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope);
+
+ curve = params->arr_curve_points;
+ REG_SET_4(CM_DGAM_RAMB_REGION_0_1, 0,
+ CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_2_3, 0,
+ CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_4_5, 0,
+ CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_6_7, 0,
+ CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_8_9, 0,
+ CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_10_11, 0,
+ CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_12_13, 0,
+ CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMB_REGION_14_15, 0,
+ CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+/*program de gamma RAM A*/
+static void dcn10_ipp_program_degamma_luta_settings(
+ struct input_pixel_processor *ipp,
+ const struct pwl_params *params)
+{
+ const struct gamma_curve *curve;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ REG_SET_2(CM_DGAM_RAMA_START_CNTL_B, 0,
+ CM_DGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+
+ REG_SET_2(CM_DGAM_RAMA_START_CNTL_G, 0,
+ CM_DGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
+
+ REG_SET_2(CM_DGAM_RAMA_START_CNTL_R, 0,
+ CM_DGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
+ CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
+
+ REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_B, 0,
+ CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_G, 0,
+ CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMA_SLOPE_CNTL_R, 0,
+ CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMA_END_CNTL1_B, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMA_END_CNTL2_B, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[2].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMA_END_CNTL1_G, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMA_END_CNTL2_G, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[2].custom_float_slope);
+
+ REG_SET(CM_DGAM_RAMA_END_CNTL1_R, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
+
+ REG_SET_2(CM_DGAM_RAMA_END_CNTL2_R, 0,
+ CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_y,
+ CM_DGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[2].custom_float_slope);
+
+ curve = params->arr_curve_points;
+ REG_SET_4(CM_DGAM_RAMA_REGION_0_1, 0,
+ CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_2_3, 0,
+ CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_4_5, 0,
+ CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_6_7, 0,
+ CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_8_9, 0,
+ CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_10_11, 0,
+ CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_12_13, 0,
+ CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_DGAM_RAMA_REGION_14_15, 0,
+ CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
+ CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
+ CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
+ CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+static void ipp_power_on_degamma_lut(
+ struct input_pixel_processor *ipp,
+ bool power_on)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ REG_SET(CM_MEM_PWR_CTRL, 0,
+ SHARED_MEM_PWR_DIS, power_on == true ? 0:1);
+
+}
+
+static void ipp_program_degamma_lut(
+ struct input_pixel_processor *ipp,
+ const struct pwl_result_data *rgb,
+ uint32_t num,
+ bool is_ram_a)
+{
+ uint32_t i;
+
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);
+ REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,
+ CM_DGAM_LUT_WRITE_EN_MASK, 7);
+ REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,
+ is_ram_a == true ? 0:1);
+
+ REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
+ for (i = 0 ; i < num; i++) {
+ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
+ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
+ REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
+
+ REG_SET(CM_DGAM_LUT_DATA, 0,
+ CM_DGAM_LUT_DATA, rgb[i].delta_red_reg);
+ REG_SET(CM_DGAM_LUT_DATA, 0,
+ CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
+ REG_SET(CM_DGAM_LUT_DATA, 0,
+ CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
+
+ }
+
+}
+
+static void dcn10_ipp_enable_cm_block(
+ struct input_pixel_processor *ipp)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
+ REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
+}
+
+
+static void dcn10_ipp_full_bypass(struct input_pixel_processor *ipp)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ /* Input pixel format: ARGB8888 */
+ REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
+ CNVC_SURFACE_PIXEL_FORMAT, 0x8);
+
+ /* Zero expansion */
+ REG_SET_3(FORMAT_CONTROL, 0,
+ CNVC_BYPASS, 0,
+ ALPHA_EN, 0,
+ FORMAT_EXPANSION_MODE, 0);
+
+ /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
+ REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+
+ /* Setting degamma bypass for now */
+ REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
+ REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
+}
+
+static void dcn10_ipp_set_degamma(
+ struct input_pixel_processor *ipp,
+ enum ipp_degamma_mode mode)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ dcn10_ipp_enable_cm_block(ipp);
+
+ switch (mode) {
+ case IPP_DEGAMMA_MODE_BYPASS:
+ /* Setting de gamma bypass for now */
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);
+ break;
+ case IPP_DEGAMMA_MODE_HW_sRGB:
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);
+ break;
+ case IPP_DEGAMMA_MODE_HW_xvYCC:
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+}
+
+static bool dcn10_cursor_program_control(
+ struct dcn10_ipp *ippn10,
+ bool pixel_data_invert,
+ enum dc_cursor_color_format color_format)
+{
+ REG_SET_2(CURSOR_SETTINS, 0,
+ /* no shift of the cursor HDL schedule */
+ CURSOR0_DST_Y_OFFSET, 0,
+ /* used to shift the cursor chunk request deadline */
+ CURSOR0_CHUNK_HDL_ADJUST, 3);
+
+ REG_UPDATE_2(CURSOR0_CONTROL,
+ CUR0_MODE, color_format,
+ CUR0_INVERT_MODE, 0);
+
+ if (color_format == CURSOR_MODE_MONO) {
+ /* todo: clarify what to program these to */
+ REG_UPDATE(CURSOR0_COLOR0,
+ CUR0_COLOR0, 0x00000000);
+ REG_UPDATE(CURSOR0_COLOR1,
+ CUR0_COLOR1, 0xFFFFFFFF);
+ }
+
+ /* TODO: Fixed vs float */
+
+ REG_UPDATE_3(FORMAT_CONTROL,
+ CNVC_BYPASS, 0,
+ ALPHA_EN, 1,
+ FORMAT_EXPANSION_MODE, 0);
+
+ REG_UPDATE(CURSOR0_CONTROL,
+ CUR0_EXPANSION_MODE, 0);
+
+ if (0 /*attributes->attribute_flags.bits.MIN_MAX_INVERT*/) {
+ REG_UPDATE(CURSOR0_CONTROL,
+ CUR0_MAX,
+ 0 /* TODO */);
+ REG_UPDATE(CURSOR0_CONTROL,
+ CUR0_MIN,
+ 0 /* TODO */);
+ }
+
+ return true;
+}
+
+enum cursor_pitch {
+ CURSOR_PITCH_64_PIXELS = 0,
+ CURSOR_PITCH_128_PIXELS,
+ CURSOR_PITCH_256_PIXELS
+};
+
+enum cursor_lines_per_chunk {
+ CURSOR_LINE_PER_CHUNK_2 = 1,
+ CURSOR_LINE_PER_CHUNK_4,
+ CURSOR_LINE_PER_CHUNK_8,
+ CURSOR_LINE_PER_CHUNK_16
+};
+
+static enum cursor_pitch dcn10_get_cursor_pitch(
+ unsigned int pitch)
+{
+ enum cursor_pitch hw_pitch;
+
+ switch (pitch) {
+ case 64:
+ hw_pitch = CURSOR_PITCH_64_PIXELS;
+ break;
+ case 128:
+ hw_pitch = CURSOR_PITCH_128_PIXELS;
+ break;
+ case 256:
+ hw_pitch = CURSOR_PITCH_256_PIXELS;
+ break;
+ default:
+ DC_ERR("Invalid cursor pitch of %d. "
+ "Only 64/128/256 is supported on DCN.\n", pitch);
+ hw_pitch = CURSOR_PITCH_64_PIXELS;
+ break;
+ }
+ return hw_pitch;
+}
+
+static enum cursor_lines_per_chunk dcn10_get_lines_per_chunk(
+ unsigned int cur_width,
+ enum dc_cursor_color_format format)
+{
+ enum cursor_lines_per_chunk line_per_chunk;
+
+ if (format == CURSOR_MODE_MONO)
+ /* impl B. expansion in CUR Buffer reader */
+ line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
+ else if (cur_width <= 32)
+ line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
+ else if (cur_width <= 64)
+ line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
+ else if (cur_width <= 128)
+ line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
+ else
+ line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
+
+ return line_per_chunk;
+}
+
+static void dcn10_cursor_set_attributes(
+ struct input_pixel_processor *ipp,
+ const struct dc_cursor_attributes *attr)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ enum cursor_pitch hw_pitch = dcn10_get_cursor_pitch(attr->pitch);
+ enum cursor_lines_per_chunk lpc = dcn10_get_lines_per_chunk(
+ attr->width, attr->color_format);
+
+ ippn10->curs_attr = *attr;
+
+ REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
+ CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
+ REG_UPDATE(CURSOR_SURFACE_ADDRESS,
+ CURSOR_SURFACE_ADDRESS, attr->address.low_part);
+
+ REG_UPDATE_2(CURSOR_SIZE,
+ CURSOR_WIDTH, attr->width,
+ CURSOR_HEIGHT, attr->height);
+
+ REG_UPDATE_3(CURSOR_CONTROL,
+ CURSOR_MODE, attr->color_format,
+ CURSOR_PITCH, hw_pitch,
+ CURSOR_LINES_PER_CHUNK, lpc);
+
+ dcn10_cursor_program_control(ippn10,
+ attr->attribute_flags.bits.INVERT_PIXEL_DATA,
+ attr->color_format);
+}
+
+static void dcn10_cursor_set_position(
+ struct input_pixel_processor *ipp,
+ const struct dc_cursor_position *pos,
+ const struct dc_cursor_mi_param *param)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ int src_x_offset = pos->x - pos->x_hotspot - param->viewport_x_start;
+ uint32_t cur_en = pos->enable ? 1 : 0;
+ uint32_t dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
+
+ dst_x_offset *= param->ref_clk_khz;
+ dst_x_offset /= param->pixel_clk_khz;
+
+ ASSERT(param->h_scale_ratio.value);
+
+ if (param->h_scale_ratio.value)
+ dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(
+ dal_fixed31_32_from_int(dst_x_offset),
+ param->h_scale_ratio));
+
+ if (src_x_offset >= (int)param->viewport_width)
+ cur_en = 0; /* not visible beyond right edge*/
+
+ if (src_x_offset + (int)ippn10->curs_attr.width < 0)
+ cur_en = 0; /* not visible beyond left edge*/
+
+ if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
+ dcn10_cursor_set_attributes(ipp, &ippn10->curs_attr);
+ REG_UPDATE(CURSOR_CONTROL,
+ CURSOR_ENABLE, cur_en);
+ REG_UPDATE(CURSOR0_CONTROL,
+ CUR0_ENABLE, cur_en);
+
+ REG_SET_2(CURSOR_POSITION, 0,
+ CURSOR_X_POSITION, pos->x,
+ CURSOR_Y_POSITION, pos->y);
+
+ REG_SET_2(CURSOR_HOT_SPOT, 0,
+ CURSOR_HOT_SPOT_X, pos->x_hotspot,
+ CURSOR_HOT_SPOT_Y, pos->y_hotspot);
+
+ REG_SET(CURSOR_DST_OFFSET, 0,
+ CURSOR_DST_X_OFFSET, dst_x_offset);
+ /* TODO Handle surface pixel formats other than 4:4:4 */
+}
+
+enum pixel_format_description {
+ PIXEL_FORMAT_FIXED = 0,
+ PIXEL_FORMAT_FIXED16,
+ PIXEL_FORMAT_FLOAT
+
+};
+
+static void dcn10_setup_format_flags(enum surface_pixel_format input_format,\
+ enum pixel_format_description *fmt)
+{
+
+ if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
+ input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
+ *fmt = PIXEL_FORMAT_FLOAT;
+ else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
+ *fmt = PIXEL_FORMAT_FIXED16;
+ else
+ *fmt = PIXEL_FORMAT_FIXED;
+}
+
+static void dcn10_ipp_set_degamma_format_float(struct input_pixel_processor *ipp,
+ bool is_float)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ if (is_float) {
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
+ } else {
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
+ REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
+ }
+}
+
+
+static void dcn10_ipp_cnv_setup (
+ struct input_pixel_processor *ipp,
+ enum surface_pixel_format input_format,
+ enum expansion_mode mode,
+ enum ipp_output_format cnv_out_format)
+{
+ uint32_t pixel_format;
+ uint32_t alpha_en;
+ enum pixel_format_description fmt ;
+ enum dc_color_space color_space;
+ enum dcn10_input_csc_select select;
+ bool is_float;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+ bool force_disable_cursor = false;
+
+ dcn10_setup_format_flags(input_format, &fmt);
+ alpha_en = 1;
+ pixel_format = 0;
+ color_space = COLOR_SPACE_SRGB;
+ select = INPUT_CSC_SELECT_BYPASS;
+ is_float = false;
+
+ switch (fmt) {
+ case PIXEL_FORMAT_FIXED:
+ case PIXEL_FORMAT_FIXED16:
+ /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
+ REG_SET_3(FORMAT_CONTROL, 0,
+ CNVC_BYPASS, 0,
+ FORMAT_EXPANSION_MODE, mode,
+ OUTPUT_FP, 0);
+ break;
+ case PIXEL_FORMAT_FLOAT:
+ REG_SET_3(FORMAT_CONTROL, 0,
+ CNVC_BYPASS, 0,
+ FORMAT_EXPANSION_MODE, mode,
+ OUTPUT_FP, 1);
+ is_float = true;
+ break;
+ default:
+
+ break;
+ }
+
+ dcn10_ipp_set_degamma_format_float(ipp, is_float);
+
+ switch (input_format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+ pixel_format = 1;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+ pixel_format = 3;
+ alpha_en = 0;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+ pixel_format = 8;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+ pixel_format = 10;
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
+ force_disable_cursor = false;
+ pixel_format = 65;
+ color_space = COLOR_SPACE_YCBCR709;
+ select = INPUT_CSC_SELECT_ICSC;
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
+ force_disable_cursor = true;
+ pixel_format = 64;
+ color_space = COLOR_SPACE_YCBCR709;
+ select = INPUT_CSC_SELECT_ICSC;
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
+ force_disable_cursor = true;
+ pixel_format = 67;
+ color_space = COLOR_SPACE_YCBCR709;
+ select = INPUT_CSC_SELECT_ICSC;
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
+ force_disable_cursor = true;
+ pixel_format = 66;
+ color_space = COLOR_SPACE_YCBCR709;
+ select = INPUT_CSC_SELECT_ICSC;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ pixel_format = 22;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+ pixel_format = 24;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+ pixel_format = 25;
+ break;
+ default:
+ break;
+ }
+ REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
+ CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
+ REG_UPDATE(FORMAT_CONTROL, ALPHA_EN, alpha_en);
+
+ dcn10_program_input_csc(ipp, color_space, select);
+
+ if (force_disable_cursor) {
+ REG_UPDATE(CURSOR_CONTROL,
+ CURSOR_ENABLE, 0);
+ REG_UPDATE(CURSOR0_CONTROL,
+ CUR0_ENABLE, 0);
+ }
+}
+
+
+static bool dcn10_degamma_ram_inuse(struct input_pixel_processor *ipp,
+ bool *ram_a_inuse)
+{
+ bool ret = false;
+ uint32_t status_reg = 0;
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ status_reg = (REG_READ(CM_IGAM_LUT_RW_CONTROL) & 0x0F00) >>16;
+ if (status_reg == 9) {
+ *ram_a_inuse = true;
+ ret = true;
+ } else if (status_reg == 10) {
+ *ram_a_inuse = false;
+ ret = true;
+ }
+ return ret;
+}
+
+static void dcn10_degamma_ram_select(struct input_pixel_processor *ipp,
+ bool use_ram_a)
+{
+ struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
+
+ if (use_ram_a)
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);
+ else
+ REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);
+
+}
+
+static void dcn10_ipp_set_degamma_pwl(struct input_pixel_processor *ipp,
+ const struct pwl_params *params)
+{
+ bool is_ram_a = true;
+
+ ipp_power_on_degamma_lut(ipp, true);
+ dcn10_ipp_enable_cm_block(ipp);
+ dcn10_degamma_ram_inuse(ipp, &is_ram_a);
+ if (is_ram_a == true)
+ dcn10_ipp_program_degamma_lutb_settings(ipp, params);
+ else
+ dcn10_ipp_program_degamma_luta_settings(ipp, params);
+
+ ipp_program_degamma_lut(ipp, params->rgb_resulted,
+ params->hw_points_num, !is_ram_a);
+ dcn10_degamma_ram_select(ipp, !is_ram_a);
+}
+
+/*****************************************/
+/* Constructor, Destructor */
+/*****************************************/
+
+static void dcn10_ipp_destroy(struct input_pixel_processor **ipp)
+{
+ dm_free(TO_DCN10_IPP(*ipp));
+ *ipp = NULL;
+}
+
+static const struct ipp_funcs dcn10_ipp_funcs = {
+ .ipp_cursor_set_attributes = dcn10_cursor_set_attributes,
+ .ipp_cursor_set_position = dcn10_cursor_set_position,
+ .ipp_set_degamma = dcn10_ipp_set_degamma,
+ .ipp_full_bypass = dcn10_ipp_full_bypass,
+ .ipp_setup = dcn10_ipp_cnv_setup,
+ .ipp_program_degamma_pwl = dcn10_ipp_set_degamma_pwl,
+ .ipp_destroy = dcn10_ipp_destroy
+};
+
+void dcn10_ipp_construct(
+ struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+ int inst,
+ const struct dcn10_ipp_registers *regs,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask)
+{
+ ippn10->base.ctx = ctx;
+ ippn10->base.inst = inst;
+ ippn10->base.funcs = &dcn10_ipp_funcs;
+
+ ippn10->regs = regs;
+ ippn10->ipp_shift = ipp_shift;
+ ippn10->ipp_mask = ipp_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
new file mode 100644
index 0000000..a4ea4e7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -0,0 +1,549 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN10_IPP_H_
+#define _DCN10_IPP_H_
+
+#include "ipp.h"
+
+#define TO_DCN10_IPP(ipp)\
+ container_of(ipp, struct dcn10_ipp, base)
+
+#define IPP_DCN10_REG_LIST(id) \
+ SRI(CM_ICSC_CONTROL, CM, id), \
+ SRI(CM_ICSC_C11_C12, CM, id), \
+ SRI(CM_ICSC_C13_C14, CM, id), \
+ SRI(CM_ICSC_C21_C22, CM, id), \
+ SRI(CM_ICSC_C23_C24, CM, id), \
+ SRI(CM_ICSC_C31_C32, CM, id), \
+ SRI(CM_ICSC_C33_C34, CM, id), \
+ SRI(CM_COMA_C11_C12, CM, id), \
+ SRI(CM_COMA_C13_C14, CM, id), \
+ SRI(CM_COMA_C21_C22, CM, id), \
+ SRI(CM_COMA_C23_C24, CM, id), \
+ SRI(CM_COMA_C31_C32, CM, id), \
+ SRI(CM_COMA_C33_C34, CM, id), \
+ SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
+ SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
+ SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
+ SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
+ SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
+ SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
+ SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_2_3, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_4_5, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_6_7, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_8_9, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_10_11, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_12_13, CM, id), \
+ SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
+ SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
+ SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
+ SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
+ SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
+ SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
+ SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
+ SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_2_3, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_4_5, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_6_7, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_8_9, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_10_11, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \
+ SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
+ SRI(CM_MEM_PWR_CTRL, CM, id), \
+ SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
+ SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
+ SRI(CM_DGAM_LUT_INDEX, CM, id), \
+ SRI(CM_DGAM_LUT_DATA, CM, id), \
+ SRI(CM_CONTROL, CM, id), \
+ SRI(CM_DGAM_CONTROL, CM, id), \
+ SRI(CM_IGAM_CONTROL, CM, id), \
+ SRI(DPP_CONTROL, DPP_TOP, id), \
+ SRI(CURSOR_SETTINS, HUBPREQ, id), \
+ SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
+ SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
+ SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
+ SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
+ SRI(FORMAT_CONTROL, CNVC_CFG, id), \
+ SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
+ SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
+ SRI(CURSOR_SIZE, CURSOR, id), \
+ SRI(CURSOR_CONTROL, CURSOR, id), \
+ SRI(CURSOR_POSITION, CURSOR, id), \
+ SRI(CURSOR_HOT_SPOT, CURSOR, id), \
+ SRI(CURSOR_DST_OFFSET, CURSOR, id)
+
+#define IPP_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define IPP_DCN10_MASK_SH_LIST(mask_sh) \
+ IPP_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
+ IPP_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh), \
+ IPP_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_2_3, CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_4_5, CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_6_7, CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_8_9, CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_10_11, CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_12_13, CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_2_3, CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_4_5, CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_6_7, CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_8_9, CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_10_11, CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_12_13, CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
+ IPP_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
+ IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
+ IPP_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
+ IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
+ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
+ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
+ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
+ IPP_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
+ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+ IPP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_INVERT_MODE, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MAX, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MIN, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+ IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
+ IPP_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
+ IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
+
+#define IPP_DCN10_REG_FIELD_LIST(type) \
+ type CM_ICSC_MODE; \
+ type CM_ICSC_C11; \
+ type CM_ICSC_C12; \
+ type CM_ICSC_C13; \
+ type CM_ICSC_C14; \
+ type CM_ICSC_C21; \
+ type CM_ICSC_C22; \
+ type CM_ICSC_C23; \
+ type CM_ICSC_C24; \
+ type CM_ICSC_C31; \
+ type CM_ICSC_C32; \
+ type CM_ICSC_C33; \
+ type CM_ICSC_C34; \
+ type CM_COMA_C11; \
+ type CM_COMA_C12; \
+ type CM_COMA_C13; \
+ type CM_COMA_C14; \
+ type CM_COMA_C21; \
+ type CM_COMA_C22; \
+ type CM_COMA_C23; \
+ type CM_COMA_C24; \
+ type CM_COMA_C31; \
+ type CM_COMA_C32; \
+ type CM_COMA_C33; \
+ type CM_COMA_C34; \
+ type CM_DGAM_RAMB_EXP_REGION_START_B; \
+ type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
+ type CM_DGAM_RAMB_EXP_REGION_START_G; \
+ type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
+ type CM_DGAM_RAMB_EXP_REGION_START_R; \
+ type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
+ type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
+ type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
+ type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
+ type CM_DGAM_RAMB_EXP_REGION_END_B; \
+ type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
+ type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
+ type CM_DGAM_RAMB_EXP_REGION_END_G; \
+ type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
+ type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
+ type CM_DGAM_RAMB_EXP_REGION_END_R; \
+ type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
+ type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
+ type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
+ type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
+ type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION_START_B; \
+ type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
+ type CM_DGAM_RAMA_EXP_REGION_START_G; \
+ type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
+ type CM_DGAM_RAMA_EXP_REGION_START_R; \
+ type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
+ type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
+ type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
+ type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
+ type CM_DGAM_RAMA_EXP_REGION_END_B; \
+ type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
+ type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
+ type CM_DGAM_RAMA_EXP_REGION_END_G; \
+ type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
+ type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
+ type CM_DGAM_RAMA_EXP_REGION_END_R; \
+ type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
+ type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
+ type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
+ type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
+ type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
+ type SHARED_MEM_PWR_DIS; \
+ type CM_IGAM_LUT_HOST_EN; \
+ type CM_DGAM_LUT_WRITE_EN_MASK; \
+ type CM_DGAM_LUT_WRITE_SEL; \
+ type CM_DGAM_LUT_INDEX; \
+ type CM_DGAM_LUT_DATA; \
+ type DPP_CLOCK_ENABLE; \
+ type CM_BYPASS_EN; \
+ type CNVC_SURFACE_PIXEL_FORMAT; \
+ type CNVC_BYPASS; \
+ type ALPHA_EN; \
+ type FORMAT_EXPANSION_MODE; \
+ type CM_DGAM_LUT_MODE; \
+ type CM_IGAM_LUT_MODE; \
+ type CURSOR0_DST_Y_OFFSET; \
+ type CURSOR0_CHUNK_HDL_ADJUST; \
+ type CUR0_MODE; \
+ type CUR0_INVERT_MODE; \
+ type CUR0_COLOR0; \
+ type CUR0_COLOR1; \
+ type CUR0_EXPANSION_MODE; \
+ type CUR0_MAX; \
+ type CUR0_MIN; \
+ type CURSOR_SURFACE_ADDRESS_HIGH; \
+ type CURSOR_SURFACE_ADDRESS; \
+ type CURSOR_WIDTH; \
+ type CURSOR_HEIGHT; \
+ type CURSOR_MODE; \
+ type CURSOR_PITCH; \
+ type CURSOR_LINES_PER_CHUNK; \
+ type CURSOR_ENABLE; \
+ type CUR0_ENABLE; \
+ type CURSOR_X_POSITION; \
+ type CURSOR_Y_POSITION; \
+ type CURSOR_HOT_SPOT_X; \
+ type CURSOR_HOT_SPOT_Y; \
+ type CURSOR_DST_X_OFFSET; \
+ type CM_IGAM_INPUT_FORMAT; \
+ type OUTPUT_FP
+
+struct dcn10_ipp_shift {
+ IPP_DCN10_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn10_ipp_mask {
+ IPP_DCN10_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn10_ipp_registers {
+ uint32_t CM_ICSC_CONTROL;
+ uint32_t CM_ICSC_C11_C12;
+ uint32_t CM_ICSC_C13_C14;
+ uint32_t CM_ICSC_C21_C22;
+ uint32_t CM_ICSC_C23_C24;
+ uint32_t CM_ICSC_C31_C32;
+ uint32_t CM_ICSC_C33_C34;
+ uint32_t CM_COMA_C11_C12;
+ uint32_t CM_COMA_C13_C14;
+ uint32_t CM_COMA_C21_C22;
+ uint32_t CM_COMA_C23_C24;
+ uint32_t CM_COMA_C31_C32;
+ uint32_t CM_COMA_C33_C34;
+ uint32_t CM_DGAM_RAMB_START_CNTL_B;
+ uint32_t CM_DGAM_RAMB_START_CNTL_G;
+ uint32_t CM_DGAM_RAMB_START_CNTL_R;
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
+ uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
+ uint32_t CM_DGAM_RAMB_END_CNTL1_B;
+ uint32_t CM_DGAM_RAMB_END_CNTL2_B;
+ uint32_t CM_DGAM_RAMB_END_CNTL1_G;
+ uint32_t CM_DGAM_RAMB_END_CNTL2_G;
+ uint32_t CM_DGAM_RAMB_END_CNTL1_R;
+ uint32_t CM_DGAM_RAMB_END_CNTL2_R;
+ uint32_t CM_DGAM_RAMB_REGION_0_1;
+ uint32_t CM_DGAM_RAMB_REGION_2_3;
+ uint32_t CM_DGAM_RAMB_REGION_4_5;
+ uint32_t CM_DGAM_RAMB_REGION_6_7;
+ uint32_t CM_DGAM_RAMB_REGION_8_9;
+ uint32_t CM_DGAM_RAMB_REGION_10_11;
+ uint32_t CM_DGAM_RAMB_REGION_12_13;
+ uint32_t CM_DGAM_RAMB_REGION_14_15;
+ uint32_t CM_DGAM_RAMA_START_CNTL_B;
+ uint32_t CM_DGAM_RAMA_START_CNTL_G;
+ uint32_t CM_DGAM_RAMA_START_CNTL_R;
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
+ uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
+ uint32_t CM_DGAM_RAMA_END_CNTL1_B;
+ uint32_t CM_DGAM_RAMA_END_CNTL2_B;
+ uint32_t CM_DGAM_RAMA_END_CNTL1_G;
+ uint32_t CM_DGAM_RAMA_END_CNTL2_G;
+ uint32_t CM_DGAM_RAMA_END_CNTL1_R;
+ uint32_t CM_DGAM_RAMA_END_CNTL2_R;
+ uint32_t CM_DGAM_RAMA_REGION_0_1;
+ uint32_t CM_DGAM_RAMA_REGION_2_3;
+ uint32_t CM_DGAM_RAMA_REGION_4_5;
+ uint32_t CM_DGAM_RAMA_REGION_6_7;
+ uint32_t CM_DGAM_RAMA_REGION_8_9;
+ uint32_t CM_DGAM_RAMA_REGION_10_11;
+ uint32_t CM_DGAM_RAMA_REGION_12_13;
+ uint32_t CM_DGAM_RAMA_REGION_14_15;
+ uint32_t CM_MEM_PWR_CTRL;
+ uint32_t CM_IGAM_LUT_RW_CONTROL;
+ uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
+ uint32_t CM_DGAM_LUT_INDEX;
+ uint32_t CM_DGAM_LUT_DATA;
+ uint32_t CM_CONTROL;
+ uint32_t CM_DGAM_CONTROL;
+ uint32_t CM_IGAM_CONTROL;
+ uint32_t DPP_CONTROL;
+ uint32_t CURSOR_SETTINS;
+ uint32_t CNVC_SURFACE_PIXEL_FORMAT;
+ uint32_t CURSOR0_CONTROL;
+ uint32_t CURSOR0_COLOR0;
+ uint32_t CURSOR0_COLOR1;
+ uint32_t FORMAT_CONTROL;
+ uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
+ uint32_t CURSOR_SURFACE_ADDRESS;
+ uint32_t CURSOR_SIZE;
+ uint32_t CURSOR_CONTROL;
+ uint32_t CURSOR_POSITION;
+ uint32_t CURSOR_HOT_SPOT;
+ uint32_t CURSOR_DST_OFFSET;
+};
+
+struct dcn10_ipp {
+ struct input_pixel_processor base;
+
+ const struct dcn10_ipp_registers *regs;
+ const struct dcn10_ipp_shift *ipp_shift;
+ const struct dcn10_ipp_mask *ipp_mask;
+
+ struct dc_cursor_attributes curs_attr;
+};
+
+void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+ int inst,
+ const struct dcn10_ipp_registers *regs,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask);
+
+#endif /* _DCN10_IPP_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
new file mode 100644
index 0000000..bf89608
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -0,0 +1,1102 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "dcn10_mem_input.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
+
+#define REG(reg)\
+ mi->mi_regs->reg
+
+#define CTX \
+ mi->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ mi->mi_shift->field_name, mi->mi_mask->field_name
+
+static void set_blank(struct dcn10_mem_input *mi, bool blank)
+{
+ uint32_t blank_en = blank ? 1 : 0;
+
+ REG_UPDATE_2(DCHUBP_CNTL,
+ HUBP_BLANK_EN, blank_en,
+ HUBP_TTU_DISABLE, blank_en);
+}
+
+
+static void disable_request(struct mem_input *mem_input)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ /* To disable the requestors, set blank_en to 1 */
+ set_blank(mi, true);
+}
+
+static void vready_workaround(struct mem_input *mem_input,
+ struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
+{
+ uint32_t value = 0;
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ /* set HBUBREQ_DEBUG_DB[12] = 1 */
+ value = REG_READ(HUBPREQ_DEBUG_DB);
+
+ /* hack mode disable */
+ value |= 0x100;
+ value &= ~0x1000;
+
+ if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
+ + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
+ /* if (eco_fix_needed(otg_global_sync_timing)
+ * set HBUBREQ_DEBUG_DB[12] = 1 */
+ value |= 0x1000;
+ }
+
+ REG_WRITE(HUBPREQ_DEBUG_DB, value);
+}
+
+static void program_tiling(
+ struct dcn10_mem_input *mi,
+ const union dc_tiling_info *info,
+ const enum surface_pixel_format pixel_format)
+{
+ REG_UPDATE_6(DCSURF_ADDR_CONFIG,
+ NUM_PIPES, log_2(info->gfx9.num_pipes),
+ NUM_BANKS, log_2(info->gfx9.num_banks),
+ PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
+ NUM_SE, log_2(info->gfx9.num_shader_engines),
+ NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
+ MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
+
+ REG_UPDATE_4(DCSURF_TILING_CONFIG,
+ SW_MODE, info->gfx9.swizzle,
+ META_LINEAR, info->gfx9.meta_linear,
+ RB_ALIGNED, info->gfx9.rb_aligned,
+ PIPE_ALIGNED, info->gfx9.pipe_aligned);
+}
+
+static void program_size_and_rotation(
+ struct dcn10_mem_input *mi,
+ enum dc_rotation_angle rotation,
+ enum surface_pixel_format format,
+ const union plane_size *plane_size,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror)
+{
+ uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c, mirror;
+
+ /* Program data and meta surface pitch (calculation from addrlib)
+ * 444 or 420 luma
+ */
+ if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+ pitch = plane_size->video.luma_pitch - 1;
+ meta_pitch = dcc->video.meta_pitch_l - 1;
+ pitch_c = plane_size->video.chroma_pitch - 1;
+ meta_pitch_c = dcc->video.meta_pitch_c - 1;
+ } else {
+ pitch = plane_size->grph.surface_pitch - 1;
+ meta_pitch = dcc->grph.meta_pitch - 1;
+ pitch_c = 0;
+ meta_pitch_c = 0;
+ }
+
+ if (!dcc->enable) {
+ meta_pitch = 0;
+ meta_pitch_c = 0;
+ }
+
+ REG_UPDATE_2(DCSURF_SURFACE_PITCH,
+ PITCH, pitch, META_PITCH, meta_pitch);
+
+ if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
+ PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
+
+ if (horizontal_mirror)
+ mirror = 1;
+ else
+ mirror = 0;
+
+
+ /* Program rotation angle and horz mirror - no mirror */
+ if (rotation == ROTATION_ANGLE_0)
+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
+ ROTATION_ANGLE, 0,
+ H_MIRROR_EN, mirror);
+ else if (rotation == ROTATION_ANGLE_90)
+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
+ ROTATION_ANGLE, 1,
+ H_MIRROR_EN, mirror);
+ else if (rotation == ROTATION_ANGLE_180)
+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
+ ROTATION_ANGLE, 2,
+ H_MIRROR_EN, mirror);
+ else if (rotation == ROTATION_ANGLE_270)
+ REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
+ ROTATION_ANGLE, 3,
+ H_MIRROR_EN, mirror);
+}
+
+static void program_pixel_format(
+ struct dcn10_mem_input *mi,
+ enum surface_pixel_format format)
+{
+ uint32_t red_bar = 3;
+ uint32_t blue_bar = 2;
+
+ /* swap for ABGR format */
+ if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
+ || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
+ red_bar = 2;
+ blue_bar = 3;
+ }
+
+ REG_UPDATE_2(HUBPRET_CONTROL,
+ CROSSBAR_SRC_CB_B, blue_bar,
+ CROSSBAR_SRC_CR_R, red_bar);
+
+ /* Mapping is same as ipp programming (cnvc) */
+
+ switch (format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 1);
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 3);
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 8);
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 10);
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 22);
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 24);
+ break;
+
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 65);
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 64);
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 67);
+ break;
+ case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
+ REG_UPDATE(DCSURF_SURFACE_CONFIG,
+ SURFACE_PIXEL_FORMAT, 66);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+
+ /* don't see the need of program the xbar in DCN 1.0 */
+}
+
+static bool mem_input_program_surface_flip_and_addr(
+ struct mem_input *mem_input,
+ const struct dc_plane_address *address,
+ bool flip_immediate)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ /* program flip type */
+
+ REG_UPDATE(DCSURF_FLIP_CONTROL,
+ SURFACE_FLIP_TYPE, flip_immediate);
+
+ /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); */
+
+
+ /* program high first and then the low addr, order matters! */
+ switch (address->type) {
+ case PLN_ADDR_TYPE_GRAPHICS:
+ if (address->grph.addr.quad_part == 0)
+ break;
+
+ if (address->grph.meta_addr.quad_part != 0) {
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ address->grph.meta_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ PRIMARY_META_SURFACE_ADDRESS,
+ address->grph.meta_addr.low_part);
+ }
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ PRIMARY_SURFACE_ADDRESS_HIGH,
+ address->grph.addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ PRIMARY_SURFACE_ADDRESS,
+ address->grph.addr.low_part);
+
+
+ /* DCN1.0 does not support const color
+ * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
+ * base on address->grph.dcc_const_color
+ * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
+ * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
+ */
+ break;
+ case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
+ if (address->video_progressive.luma_addr.quad_part == 0
+ || address->video_progressive.chroma_addr.quad_part == 0)
+ break;
+
+ if (address->video_progressive.luma_meta_addr.quad_part != 0) {
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ address->video_progressive.luma_meta_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ PRIMARY_META_SURFACE_ADDRESS,
+ address->video_progressive.luma_meta_addr.low_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
+ PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
+ address->video_progressive.chroma_meta_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C,
+ PRIMARY_META_SURFACE_ADDRESS_C,
+ address->video_progressive.chroma_meta_addr.low_part);
+ }
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ PRIMARY_SURFACE_ADDRESS_HIGH,
+ address->video_progressive.luma_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ PRIMARY_SURFACE_ADDRESS,
+ address->video_progressive.luma_addr.low_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
+ PRIMARY_SURFACE_ADDRESS_HIGH_C,
+ address->video_progressive.chroma_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_C,
+ PRIMARY_SURFACE_ADDRESS_C,
+ address->video_progressive.chroma_addr.low_part);
+
+ break;
+ case PLN_ADDR_TYPE_GRPH_STEREO:
+ if (address->grph_stereo.left_addr.quad_part == 0)
+ break;
+ if (address->grph_stereo.right_addr.quad_part == 0)
+ break;
+ if (address->grph_stereo.right_meta_addr.quad_part != 0) {
+
+ REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH,
+ SECONDARY_META_SURFACE_ADDRESS_HIGH,
+ address->grph_stereo.right_meta_addr.high_part);
+
+ REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS,
+ SECONDARY_META_SURFACE_ADDRESS,
+ address->grph_stereo.right_meta_addr.low_part);
+ }
+ if (address->grph_stereo.left_meta_addr.quad_part != 0) {
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ PRIMARY_META_SURFACE_ADDRESS_HIGH,
+ address->grph_stereo.left_meta_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
+ PRIMARY_META_SURFACE_ADDRESS,
+ address->grph_stereo.left_meta_addr.low_part);
+ }
+
+ REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH,
+ SECONDARY_SURFACE_ADDRESS_HIGH,
+ address->grph_stereo.right_addr.high_part);
+
+ REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS,
+ SECONDARY_SURFACE_ADDRESS,
+ address->grph_stereo.right_addr.low_part);
+
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
+ PRIMARY_SURFACE_ADDRESS_HIGH,
+ address->grph_stereo.left_addr.high_part);
+
+ REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
+ PRIMARY_SURFACE_ADDRESS,
+ address->grph_stereo.left_addr.low_part);
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ break;
+ }
+ /* REG_UPDATE(FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); */
+
+ mem_input->request_address = *address;
+
+ if (flip_immediate)
+ mem_input->current_address = *address;
+
+ return true;
+}
+
+static void program_control(struct dcn10_mem_input *mi,
+ struct dc_plane_dcc_param *dcc)
+{
+ uint32_t dcc_en = dcc->enable ? 1 : 0;
+ uint32_t dcc_ind_64b_blk = dcc->grph.independent_64b_blks ? 1 : 0;
+
+ REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
+ PRIMARY_SURFACE_DCC_EN, dcc_en,
+ PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
+
+}
+
+static void mem_input_program_surface_config(
+ struct mem_input *mem_input,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ union plane_size *plane_size,
+ enum dc_rotation_angle rotation,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror,
+ bool visible)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ program_control(mi, dcc);
+ program_tiling(mi, tiling_info, format);
+ program_size_and_rotation(
+ mi, rotation, format, plane_size, dcc, horizontal_mirror);
+ program_pixel_format(mi, format);
+
+ set_blank(mi, !visible);
+}
+
+static void program_requestor(
+ struct mem_input *mem_input,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs)
+{
+
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ REG_UPDATE(HUBPRET_CONTROL,
+ DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
+ REG_SET_4(DCN_EXPANSION_MODE, 0,
+ DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
+ PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
+ MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
+ CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
+ REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
+ CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
+ MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
+ META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
+ MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
+ DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
+ MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
+ SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
+ PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
+ REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
+ CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
+ MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
+ META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
+ MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
+ DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
+ MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
+ SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
+ PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
+}
+
+
+static void program_deadline(
+ struct mem_input *mem_input,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ /* DLG - Per hubp */
+ REG_SET_2(BLANK_OFFSET_0, 0,
+ REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
+ DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
+
+ REG_SET(BLANK_OFFSET_1, 0,
+ MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
+
+ REG_SET(DST_DIMENSIONS, 0,
+ REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
+
+ REG_SET_2(DST_AFTER_SCALER, 0,
+ REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
+ DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
+
+ REG_SET_2(PREFETCH_SETTINS, 0,
+ DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
+ VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
+
+ REG_SET_2(VBLANK_PARAMETERS_0, 0,
+ DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
+ DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
+
+ REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
+ REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
+
+ /* DLG - Per luma/chroma */
+ REG_SET(VBLANK_PARAMETERS_1, 0,
+ REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
+
+ REG_SET(VBLANK_PARAMETERS_3, 0,
+ REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
+
+ REG_SET(NOM_PARAMETERS_0, 0,
+ DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
+
+ REG_SET(NOM_PARAMETERS_1, 0,
+ REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
+
+ REG_SET(NOM_PARAMETERS_4, 0,
+ DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
+
+ REG_SET(NOM_PARAMETERS_5, 0,
+ REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
+
+ REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
+ REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
+ REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
+
+ REG_SET_2(PER_LINE_DELIVERY, 0,
+ REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
+ REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
+
+ REG_SET(PREFETCH_SETTINS_C, 0,
+ VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
+
+ REG_SET(VBLANK_PARAMETERS_2, 0,
+ REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
+
+ REG_SET(VBLANK_PARAMETERS_4, 0,
+ REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
+
+ REG_SET(NOM_PARAMETERS_2, 0,
+ DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
+
+ REG_SET(NOM_PARAMETERS_3, 0,
+ REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
+
+ REG_SET(NOM_PARAMETERS_6, 0,
+ DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
+
+ REG_SET(NOM_PARAMETERS_7, 0,
+ REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
+
+ /* TTU - per hubp */
+ REG_SET_2(DCN_TTU_QOS_WM, 0,
+ QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
+ QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
+
+ REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
+ MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
+ QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
+
+ /* TTU - per luma/chroma */
+ /* Assumed surf0 is luma and 1 is chroma */
+
+ REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
+
+ REG_SET(DCN_SURF0_TTU_CNTL1, 0,
+ REFCYC_PER_REQ_DELIVERY_PRE,
+ ttu_attr->refcyc_per_req_delivery_pre_l);
+
+ REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
+ REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
+ QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
+ QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
+
+ REG_SET(DCN_SURF1_TTU_CNTL1, 0,
+ REFCYC_PER_REQ_DELIVERY_PRE,
+ ttu_attr->refcyc_per_req_delivery_pre_c);
+}
+
+static void mem_input_setup(
+ struct mem_input *mem_input,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
+{
+ /* otg is locked when this func is called. Register are double buffered.
+ * disable the requestors is not needed
+ */
+ /* disable_request(mem_input); */
+ program_requestor(mem_input, rq_regs);
+ program_deadline(mem_input, dlg_attr, ttu_attr);
+ vready_workaround(mem_input, pipe_dest);
+}
+
+static uint32_t convert_and_clamp(
+ uint32_t wm_ns,
+ uint32_t refclk_mhz,
+ uint32_t clamp_value)
+{
+ uint32_t ret_val = 0;
+ ret_val = wm_ns * refclk_mhz;
+ ret_val /= 1000;
+
+ if (ret_val > clamp_value)
+ ret_val = clamp_value;
+
+ return ret_val;
+}
+
+static void program_watermarks(
+ struct mem_input *mem_input,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_mhz)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+ /*
+ * Need to clamp to max of the register values (i.e. no wrap)
+ * for dcn1, all wm registers are 21-bit wide
+ */
+ uint32_t prog_wm_value;
+
+ /* Repeat for water mark set A, B, C and D. */
+ /* clock state A */
+ prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "URGENCY_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.urgent_ns, prog_wm_value);
+
+ prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.pte_meta_urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_EXIT_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->a.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+ "HW register value = 0x%x\n\n",
+ watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+
+ /* clock state B */
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "URGENCY_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.pte_meta_urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_ENTER_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_EXIT_WATERMARK_B calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->b.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
+ "HW register value = 0x%x\n",
+ watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ /* clock state C */
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "URGENCY_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.pte_meta_urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_ENTER_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_EXIT_WATERMARK_C calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->c.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
+ "HW register value = 0x%x\n",
+ watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ /* clock state D */
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "URGENCY_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.urgent_ns, prog_wm_value);
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.pte_meta_urgent_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.pte_meta_urgent_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_ENTER_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.cstate_exit_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "SR_EXIT_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n",
+ watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+
+
+ prog_wm_value = convert_and_clamp(
+ watermarks->d.cstate_pstate.pstate_change_ns,
+ refclk_mhz, 0x1fffff);
+ REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
+ dm_logger_write(mem_input->ctx->logger, LOG_HW_MARKS,
+ "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+ "HW register value = 0x%x\n\n",
+ watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+
+ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+ REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
+ REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
+ DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+ REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+ DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
+
+#if 0
+ REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
+ DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
+#endif
+}
+
+static void mem_input_program_display_marks(
+ struct mem_input *mem_input,
+ struct bw_watermarks nbp,
+ struct bw_watermarks stutter,
+ struct bw_watermarks urgent,
+ uint32_t total_dest_line_time_ns)
+{
+ /* only for dce
+ * dcn use only program_watermarks
+ */
+}
+
+bool mem_input_is_flip_pending(struct mem_input *mem_input)
+{
+ uint32_t update_pending = 0;
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+
+ REG_GET(DCSURF_FLIP_CONTROL,
+ SURFACE_UPDATE_PENDING, &update_pending);
+
+ if (update_pending)
+ return true;
+
+ mem_input->current_address = mem_input->request_address;
+ return false;
+}
+
+static void mem_input_update_dchub(
+ struct mem_input *mem_input,
+ struct dchub_init_data *dh_data)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+ /* TODO: port code from dal2 */
+ switch (dh_data->fb_mode) {
+ case FRAME_BUFFER_MODE_ZFB_ONLY:
+ /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
+ REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
+ SDPIF_FB_TOP, 0);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
+ SDPIF_FB_BASE, 0x0FFFF);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
+ dh_data->zfb_size_in_byte - 1) >> 22);
+ break;
+ case FRAME_BUFFER_MODE_LOCAL_ONLY:
+ /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
+ SDPIF_AGP_BASE, 0);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
+ SDPIF_AGP_BOT, 0X03FFFF);
+
+ REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
+ SDPIF_AGP_TOP, 0);
+ break;
+ default:
+ break;
+ }
+
+ dh_data->dchub_initialzied = true;
+ dh_data->dchub_info_valid = false;
+}
+
+struct vm_system_aperture_param {
+ PHYSICAL_ADDRESS_LOC sys_default;
+ PHYSICAL_ADDRESS_LOC sys_low;
+ PHYSICAL_ADDRESS_LOC sys_high;
+};
+
+static void read_vm_system_aperture_settings(struct dcn10_mem_input *mi,
+ struct vm_system_aperture_param *apt)
+{
+ PHYSICAL_ADDRESS_LOC physical_page_number;
+ uint32_t logical_addr_low;
+ uint32_t logical_addr_high;
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+ PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
+ REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+ PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ LOGICAL_ADDR, &logical_addr_low);
+
+ REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ LOGICAL_ADDR, &logical_addr_high);
+
+ apt->sys_default.quad_part = physical_page_number.quad_part << 12;
+ apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
+ apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
+}
+
+static void set_vm_system_aperture_settings(struct dcn10_mem_input *mi,
+ struct vm_system_aperture_param *apt)
+{
+ PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
+ PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
+ PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
+
+ mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
+ mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
+ mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
+
+ REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
+ MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
+ MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
+ REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
+ MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
+
+ REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
+ MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
+ REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
+ MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
+
+ REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
+ REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
+ MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
+}
+
+struct vm_context0_param {
+ PHYSICAL_ADDRESS_LOC pte_base;
+ PHYSICAL_ADDRESS_LOC pte_start;
+ PHYSICAL_ADDRESS_LOC pte_end;
+ PHYSICAL_ADDRESS_LOC fault_default;
+};
+
+/* Temporary read settings, future will get values from kmd directly */
+static void read_vm_context0_settings(struct dcn10_mem_input *mi,
+ struct vm_context0_param *vm0)
+{
+ PHYSICAL_ADDRESS_LOC fb_base;
+ PHYSICAL_ADDRESS_LOC fb_offset;
+ uint32_t fb_base_value;
+ uint32_t fb_offset_value;
+
+ REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
+ REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
+
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
+ REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
+
+ REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+ PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
+ REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+ PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
+
+ /*
+ * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
+ * Therefore we need to do
+ * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
+ */
+ fb_base.quad_part = (uint64_t)fb_base_value << 24;
+ fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
+ vm0->pte_base.quad_part += fb_base.quad_part;
+ vm0->pte_base.quad_part -= fb_offset.quad_part;
+}
+
+static void set_vm_context0_settings(struct dcn10_mem_input *mi,
+ const struct vm_context0_param *vm0)
+{
+ /* pte base */
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
+
+ /* pte start */
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
+
+ /* pte end */
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
+ REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
+
+ /* fault handling */
+ REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
+ VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->fault_default.high_part);
+ /* VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, 0 */
+ REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
+ VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
+}
+
+void dcn_mem_input_program_pte_vm(struct mem_input *mem_input,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ enum dc_rotation_angle rotation)
+{
+ struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+ struct vm_system_aperture_param apt = { {{ 0 } } };
+ struct vm_context0_param vm0 = { { { 0 } } };
+
+
+ read_vm_system_aperture_settings(mi, &apt);
+ read_vm_context0_settings(mi, &vm0);
+
+ set_vm_system_aperture_settings(mi, &apt);
+ set_vm_context0_settings(mi, &vm0);
+
+ /* control: enable VM PTE*/
+ REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
+ ENABLE_L1_TLB, 1,
+ SYSTEM_ACCESS_MODE, 3);
+}
+
+static struct mem_input_funcs dcn10_mem_input_funcs = {
+ .mem_input_program_display_marks = mem_input_program_display_marks,
+ .allocate_mem_input = NULL,
+ .free_mem_input = NULL,
+ .disable_request = disable_request,
+ .mem_input_program_surface_flip_and_addr =
+ mem_input_program_surface_flip_and_addr,
+ .mem_input_program_surface_config =
+ mem_input_program_surface_config,
+ .mem_input_is_flip_pending = mem_input_is_flip_pending,
+ .mem_input_setup = mem_input_setup,
+ .program_watermarks = program_watermarks,
+ .mem_input_update_dchub = mem_input_update_dchub,
+ .mem_input_program_pte_vm = dcn_mem_input_program_pte_vm,
+};
+
+
+/*****************************************/
+/* Constructor, Destructor */
+/*****************************************/
+
+bool dcn10_mem_input_construct(
+ struct dcn10_mem_input *mi,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn_mi_registers *mi_regs,
+ const struct dcn_mi_shift *mi_shift,
+ const struct dcn_mi_mask *mi_mask)
+{
+ mi->base.funcs = &dcn10_mem_input_funcs;
+ mi->base.ctx = ctx;
+ mi->mi_regs = mi_regs;
+ mi->mi_shift = mi_shift;
+ mi->mi_mask = mi_mask;
+ mi->base.inst = inst;
+
+ return true;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
new file mode 100644
index 0000000..4a5eb6a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -0,0 +1,553 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MEM_INPUT_DCN10_H__
+#define __DC_MEM_INPUT_DCN10_H__
+
+#include "mem_input.h"
+
+#define TO_DCN10_MEM_INPUT(mi)\
+ container_of(mi, struct dcn10_mem_input, base)
+
+
+#define MI_DCN10_REG_LIST(id)\
+ SRI(DCHUBP_CNTL, HUBP, id),\
+ SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
+ SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
+ SRI(DCSURF_TILING_CONFIG, HUBP, id),\
+ SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
+ SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
+ SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
+ SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
+ SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+ SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
+ SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
+ SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
+ SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
+ SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
+ SRI(HUBPRET_CONTROL, HUBPRET, id),\
+ SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
+ SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
+ SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
+ SRI(BLANK_OFFSET_0, HUBPREQ, id),\
+ SRI(BLANK_OFFSET_1, HUBPREQ, id),\
+ SRI(DST_DIMENSIONS, HUBPREQ, id),\
+ SRI(DST_AFTER_SCALER, HUBPREQ, id),\
+ SRI(PREFETCH_SETTINS, HUBPREQ, id),\
+ SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
+ SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
+ SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
+ SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
+ SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
+ SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
+ SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
+ SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
+ SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
+ SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
+ SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
+ SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
+ SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
+ SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
+ SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
+ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
+ SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
+ SR(DCHUBBUB_SDPIF_FB_TOP),\
+ SR(DCHUBBUB_SDPIF_FB_BASE),\
+ SR(DCHUBBUB_SDPIF_FB_OFFSET),\
+ SR(DCHUBBUB_SDPIF_AGP_BASE),\
+ SR(DCHUBBUB_SDPIF_AGP_BOT),\
+ SR(DCHUBBUB_SDPIF_AGP_TOP),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
+ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\
+ SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\
+ SR(DCHUBBUB_ARB_SAT_LEVEL),\
+ SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
+ /* todo: get these from GVM instead of reading registers ourselves */\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
+ GC_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
+ GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
+ GC_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
+ GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
+ GC_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
+ GC_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
+ GC_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
+
+struct dcn_mi_registers {
+ uint32_t DCHUBP_CNTL;
+ uint32_t HUBPREQ_DEBUG_DB;
+ uint32_t DCSURF_ADDR_CONFIG;
+ uint32_t DCSURF_TILING_CONFIG;
+ uint32_t DCSURF_SURFACE_PITCH;
+ uint32_t DCSURF_SURFACE_PITCH_C;
+ uint32_t DCSURF_SURFACE_CONFIG;
+ uint32_t DCSURF_FLIP_CONTROL;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
+ uint32_t DCSURF_SURFACE_CONTROL;
+ uint32_t HUBPRET_CONTROL;
+ uint32_t DCN_EXPANSION_MODE;
+ uint32_t DCHUBP_REQ_SIZE_CONFIG;
+ uint32_t DCHUBP_REQ_SIZE_CONFIG_C;
+ uint32_t BLANK_OFFSET_0;
+ uint32_t BLANK_OFFSET_1;
+ uint32_t DST_DIMENSIONS;
+ uint32_t DST_AFTER_SCALER;
+ uint32_t PREFETCH_SETTINS;
+ uint32_t VBLANK_PARAMETERS_0;
+ uint32_t REF_FREQ_TO_PIX_FREQ;
+ uint32_t VBLANK_PARAMETERS_1;
+ uint32_t VBLANK_PARAMETERS_3;
+ uint32_t NOM_PARAMETERS_0;
+ uint32_t NOM_PARAMETERS_1;
+ uint32_t NOM_PARAMETERS_4;
+ uint32_t NOM_PARAMETERS_5;
+ uint32_t PER_LINE_DELIVERY_PRE;
+ uint32_t PER_LINE_DELIVERY;
+ uint32_t PREFETCH_SETTINS_C;
+ uint32_t VBLANK_PARAMETERS_2;
+ uint32_t VBLANK_PARAMETERS_4;
+ uint32_t NOM_PARAMETERS_2;
+ uint32_t NOM_PARAMETERS_3;
+ uint32_t NOM_PARAMETERS_6;
+ uint32_t NOM_PARAMETERS_7;
+ uint32_t DCN_TTU_QOS_WM;
+ uint32_t DCN_GLOBAL_TTU_CNTL;
+ uint32_t DCN_SURF0_TTU_CNTL0;
+ uint32_t DCN_SURF0_TTU_CNTL1;
+ uint32_t DCN_SURF1_TTU_CNTL0;
+ uint32_t DCN_SURF1_TTU_CNTL1;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;
+ uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;
+ uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
+ uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
+ uint32_t DCN_VM_MX_L1_TLB_CNTL;
+ uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;
+ uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;
+ uint32_t DCHUBBUB_SDPIF_FB_TOP;
+ uint32_t DCHUBBUB_SDPIF_FB_BASE;
+ uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
+ uint32_t DCHUBBUB_SDPIF_AGP_BASE;
+ uint32_t DCHUBBUB_SDPIF_AGP_BOT;
+ uint32_t DCHUBBUB_SDPIF_AGP_TOP;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;
+ uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;
+ uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;
+ uint32_t DCHUBBUB_ARB_SAT_LEVEL;
+ uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;
+
+ /* GC registers. read only. temporary hack */
+ uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
+ uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+ uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
+ uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
+ uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
+ uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
+ uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
+ uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
+ uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
+ uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
+ uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
+ uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
+};
+
+#define MI_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define MI_DCN10_MASK_SH_LIST(mask_sh)\
+ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
+ MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
+ MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
+ MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
+ MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
+ MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
+ MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
+ MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
+ MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
+ MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
+ MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
+ MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
+ MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
+ MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
+ MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
+ MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
+ MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
+ MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
+ MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
+ MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
+ MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
+ MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
+ MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
+ MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
+ MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
+ MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
+ MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
+ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\
+ MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\
+ MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\
+ MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\
+ MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\
+ MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\
+ /* todo: get these from GVM instead of reading registers ourselves */\
+ MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
+ MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
+ MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
+ MI_SF(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
+ MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
+ MI_SF(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
+ MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
+ MI_SF(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
+ MI_SF(MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh)
+
+#define DCN_MI_REG_FIELD_LIST(type) \
+ type HUBP_BLANK_EN;\
+ type HUBP_TTU_DISABLE;\
+ type NUM_PIPES;\
+ type NUM_BANKS;\
+ type PIPE_INTERLEAVE;\
+ type NUM_SE;\
+ type NUM_RB_PER_SE;\
+ type MAX_COMPRESSED_FRAGS;\
+ type SW_MODE;\
+ type META_LINEAR;\
+ type RB_ALIGNED;\
+ type PIPE_ALIGNED;\
+ type PITCH;\
+ type META_PITCH;\
+ type PITCH_C;\
+ type META_PITCH_C;\
+ type ROTATION_ANGLE;\
+ type H_MIRROR_EN;\
+ type SURFACE_PIXEL_FORMAT;\
+ type SURFACE_FLIP_TYPE;\
+ type SURFACE_UPDATE_PENDING;\
+ type PRIMARY_SURFACE_ADDRESS_HIGH;\
+ type PRIMARY_SURFACE_ADDRESS;\
+ type SECONDARY_SURFACE_ADDRESS_HIGH;\
+ type SECONDARY_SURFACE_ADDRESS;\
+ type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
+ type PRIMARY_META_SURFACE_ADDRESS;\
+ type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
+ type SECONDARY_META_SURFACE_ADDRESS;\
+ type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
+ type PRIMARY_SURFACE_ADDRESS_C;\
+ type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
+ type PRIMARY_META_SURFACE_ADDRESS_C;\
+ type PRIMARY_SURFACE_DCC_EN;\
+ type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
+ type DET_BUF_PLANE1_BASE_ADDRESS;\
+ type CROSSBAR_SRC_CB_B;\
+ type CROSSBAR_SRC_CR_R;\
+ type DRQ_EXPANSION_MODE;\
+ type PRQ_EXPANSION_MODE;\
+ type MRQ_EXPANSION_MODE;\
+ type CRQ_EXPANSION_MODE;\
+ type CHUNK_SIZE;\
+ type MIN_CHUNK_SIZE;\
+ type META_CHUNK_SIZE;\
+ type MIN_META_CHUNK_SIZE;\
+ type DPTE_GROUP_SIZE;\
+ type MPTE_GROUP_SIZE;\
+ type SWATH_HEIGHT;\
+ type PTE_ROW_HEIGHT_LINEAR;\
+ type CHUNK_SIZE_C;\
+ type MIN_CHUNK_SIZE_C;\
+ type META_CHUNK_SIZE_C;\
+ type MIN_META_CHUNK_SIZE_C;\
+ type DPTE_GROUP_SIZE_C;\
+ type MPTE_GROUP_SIZE_C;\
+ type SWATH_HEIGHT_C;\
+ type PTE_ROW_HEIGHT_LINEAR_C;\
+ type REFCYC_H_BLANK_END;\
+ type DLG_V_BLANK_END;\
+ type MIN_DST_Y_NEXT_START;\
+ type REFCYC_PER_HTOTAL;\
+ type REFCYC_X_AFTER_SCALER;\
+ type DST_Y_AFTER_SCALER;\
+ type DST_Y_PREFETCH;\
+ type VRATIO_PREFETCH;\
+ type DST_Y_PER_VM_VBLANK;\
+ type DST_Y_PER_ROW_VBLANK;\
+ type REF_FREQ_TO_PIX_FREQ;\
+ type REFCYC_PER_PTE_GROUP_VBLANK_L;\
+ type REFCYC_PER_META_CHUNK_VBLANK_L;\
+ type DST_Y_PER_PTE_ROW_NOM_L;\
+ type REFCYC_PER_PTE_GROUP_NOM_L;\
+ type DST_Y_PER_META_ROW_NOM_L;\
+ type REFCYC_PER_META_CHUNK_NOM_L;\
+ type REFCYC_PER_LINE_DELIVERY_PRE_L;\
+ type REFCYC_PER_LINE_DELIVERY_PRE_C;\
+ type REFCYC_PER_LINE_DELIVERY_L;\
+ type REFCYC_PER_LINE_DELIVERY_C;\
+ type VRATIO_PREFETCH_C;\
+ type REFCYC_PER_PTE_GROUP_VBLANK_C;\
+ type REFCYC_PER_META_CHUNK_VBLANK_C;\
+ type DST_Y_PER_PTE_ROW_NOM_C;\
+ type REFCYC_PER_PTE_GROUP_NOM_C;\
+ type DST_Y_PER_META_ROW_NOM_C;\
+ type REFCYC_PER_META_CHUNK_NOM_C;\
+ type QoS_LEVEL_LOW_WM;\
+ type QoS_LEVEL_HIGH_WM;\
+ type MIN_TTU_VBLANK;\
+ type QoS_LEVEL_FLIP;\
+ type REFCYC_PER_REQ_DELIVERY;\
+ type QoS_LEVEL_FIXED;\
+ type QoS_RAMP_DISABLE;\
+ type REFCYC_PER_REQ_DELIVERY_PRE;\
+ type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
+ type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
+ type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
+ type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
+ type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
+ type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
+ type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
+ type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
+ type ENABLE_L1_TLB;\
+ type SYSTEM_ACCESS_MODE;\
+ type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
+ type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
+ type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
+ type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
+ type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
+ type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
+ type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
+ type SDPIF_FB_TOP;\
+ type SDPIF_FB_BASE;\
+ type SDPIF_FB_OFFSET;\
+ type SDPIF_AGP_BASE;\
+ type SDPIF_AGP_BOT;\
+ type SDPIF_AGP_TOP;\
+ type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
+ type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
+ type DCHUBBUB_ARB_SAT_LEVEL;\
+ type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
+ /* todo: get these from GVM instead of reading registers ourselves */\
+ type PAGE_DIRECTORY_ENTRY_HI32;\
+ type PAGE_DIRECTORY_ENTRY_LO32;\
+ type LOGICAL_PAGE_NUMBER_HI4;\
+ type LOGICAL_PAGE_NUMBER_LO32;\
+ type PHYSICAL_PAGE_ADDR_HI4;\
+ type PHYSICAL_PAGE_ADDR_LO32;\
+ type PHYSICAL_PAGE_NUMBER_MSB;\
+ type PHYSICAL_PAGE_NUMBER_LSB;\
+ type LOGICAL_ADDR
+
+struct dcn_mi_shift {
+ DCN_MI_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn_mi_mask {
+ DCN_MI_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn10_mem_input {
+ struct mem_input base;
+ const struct dcn_mi_registers *mi_regs;
+ const struct dcn_mi_shift *mi_shift;
+ const struct dcn_mi_mask *mi_mask;
+};
+
+bool dcn10_mem_input_construct(
+ struct dcn10_mem_input *mi,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn_mi_registers *mi_regs,
+ const struct dcn_mi_shift *mi_shift,
+ const struct dcn_mi_mask *mi_mask);
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
new file mode 100644
index 0000000..cb22cd1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -0,0 +1,376 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn10_mpc.h"
+
+#define REG(reg)\
+ mpc->mpc_regs->reg
+
+#define CTX \
+ mpc->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ mpc->mpc_shift->field_name, mpc->mpc_mask->field_name
+
+/* Internal function to set mpc output mux */
+static void set_output_mux(struct dcn10_mpc *mpc,
+ uint8_t opp_id,
+ uint8_t mpcc_id)
+{
+ if (mpcc_id != 0xf)
+ REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+ OPP_PIPE_CLOCK_EN, 1);
+
+ REG_SET(MUX[opp_id], 0,
+ MPC_OUT_MUX, mpcc_id);
+
+/* TODO: Move to post when ready.
+ if (mpcc_id == 0xf) {
+ MPCC_REG_UPDATE(OPP_PIPE0_OPP_PIPE_CONTROL,
+ OPP_PIPE_CLOCK_EN, 0);
+ }
+*/
+}
+
+static void set_blend_mode(struct dcn10_mpc *mpc,
+ enum blend_mode mode,
+ uint8_t mpcc_id)
+{
+ /* Enable per-pixel alpha on this pipe */
+ if (mode == TOP_BLND)
+ REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
+ MPCC_ALPHA_BLND_MODE, 0,
+ MPCC_ALPHA_MULTIPLIED_MODE, 0,
+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, 0);
+ else
+ REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
+ MPCC_ALPHA_BLND_MODE, 0,
+ MPCC_ALPHA_MULTIPLIED_MODE, 1,
+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, 1);
+}
+
+void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
+ unsigned int mpcc_inst,
+ struct tg_color *bg_color)
+{
+ /* mpc color is 12 bit. tg_color is 10 bit */
+ /* todo: might want to use 16 bit to represent color and have each
+ * hw block translate to correct color depth.
+ */
+ uint32_t bg_r_cr = bg_color->color_r_cr << 2;
+ uint32_t bg_g_y = bg_color->color_g_y << 2;
+ uint32_t bg_b_cb = bg_color->color_b_cb << 2;
+
+ REG_SET(MPCC_BG_R_CR[mpcc_inst], 0,
+ MPCC_BG_R_CR, bg_r_cr);
+ REG_SET(MPCC_BG_G_Y[mpcc_inst], 0,
+ MPCC_BG_G_Y, bg_g_y);
+ REG_SET(MPCC_BG_B_CB[mpcc_inst], 0,
+ MPCC_BG_B_CB, bg_b_cb);
+}
+
+/* This function programs MPC tree configuration
+ * Assume it is the initial time to setup MPC tree_configure, means
+ * the instance of dpp/mpcc/opp specified in structure tree_cfg are
+ * in idle status.
+ * Before invoke this function, ensure that master lock of OPTC specified
+ * by opp_id is set.
+ *
+ * tree_cfg[in] - new MPC_TREE_CFG
+ */
+
+void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg)
+{
+ int i;
+
+ for (i = 0; i < tree_cfg->num_pipes; i++) {
+ uint8_t mpcc_inst = tree_cfg->mpcc[i];
+
+ REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
+ MPCC_OPP_ID, tree_cfg->opp_id);
+
+ REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
+ MPCC_TOP_SEL, tree_cfg->dpp[i]);
+
+ if (i == tree_cfg->num_pipes-1) {
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, 0xF);
+
+ /* MPCC_CONTROL->MPCC_MODE */
+ REG_UPDATE(MPCC_CONTROL[mpcc_inst],
+ MPCC_MODE, tree_cfg->mode);
+ } else {
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, tree_cfg->dpp[i+1]);
+
+ /* MPCC_CONTROL->MPCC_MODE */
+ REG_UPDATE(MPCC_CONTROL[mpcc_inst],
+ MPCC_MODE, 3);
+ }
+
+ if (i == 0)
+ set_output_mux(
+ mpc, tree_cfg->opp_id, mpcc_inst);
+
+ set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
+ }
+}
+
+void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
+ uint8_t dpp_idx,
+ uint8_t mpcc_idx,
+ uint8_t opp_idx)
+{
+ struct mpc_tree_cfg tree_cfg = { 0 };
+
+ tree_cfg.num_pipes = 1;
+ tree_cfg.opp_id = opp_idx;
+ tree_cfg.mode = TOP_PASSTHRU;
+ /* TODO: FPGA bring up one MPC has only 1 DPP and 1 MPCC
+ * For blend case, need fill mode DPP and cascade MPCC
+ */
+ tree_cfg.dpp[0] = dpp_idx;
+ tree_cfg.mpcc[0] = mpcc_idx;
+ dcn10_set_mpc_tree(mpc, &tree_cfg);
+}
+
+/*
+ * This is the function to remove current MPC tree specified by tree_cfg
+ * Before invoke this function, ensure that master lock of OPTC specified
+ * by opp_id is set.
+ *
+ *tree_cfg[in/out] - current MPC_TREE_CFG
+ */
+void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg)
+{
+ int i;
+
+ for (i = 0; i < tree_cfg->num_pipes; i++) {
+ uint8_t mpcc_inst = tree_cfg->mpcc[i];
+
+ REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
+ MPCC_OPP_ID, 0xf);
+
+ REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
+ MPCC_TOP_SEL, 0xf);
+
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, 0xF);
+
+ /* add remove dpp/mpcc pair into pending list
+ * TODO FPGA AddToPendingList if empty from pseudo code
+ */
+ tree_cfg->dpp[i] = 0xf;
+ tree_cfg->mpcc[i] = 0xf;
+ }
+ set_output_mux(mpc, tree_cfg->opp_id, 0xf);
+ tree_cfg->opp_id = 0xf;
+ tree_cfg->num_pipes = 0;
+}
+
+/* TODO FPGA: how to handle DPP?
+ * Function to remove one of pipe from MPC configure tree by dpp idx
+ * Before invoke this function, ensure that master lock of OPTC specified
+ * by opp_id is set
+ * This function can be invoke multiple times to remove more than 1 dpps.
+ *
+ * tree_cfg[in/out] - current MPC_TREE_CFG
+ * idx[in] - index of dpp from tree_cfg to be removed.
+ */
+bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg,
+ uint8_t idx)
+{
+ int i;
+ bool found = false;
+
+ /* find dpp_idx from dpp array of tree_cfg */
+ for (i = 0; i < tree_cfg->num_pipes; i++) {
+ if (tree_cfg->dpp[i] == idx) {
+ found = true;
+ break;
+ }
+ }
+
+ if (found) {
+ /* add remove dpp/mpcc pair into pending list */
+
+ /* TODO FPGA AddToPendingList if empty from pseudo code
+ * AddToPendingList(tree_cfg->dpp[i],tree_cfg->mpcc[i]);
+ */
+ uint8_t mpcc_inst = tree_cfg->mpcc[i];
+
+ REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
+ MPCC_OPP_ID, 0xf);
+
+ REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
+ MPCC_TOP_SEL, 0xf);
+
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, 0xF);
+
+ if (i == 0) {
+ if (tree_cfg->num_pipes > 1)
+ set_output_mux(mpc,
+ tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
+ else
+ set_output_mux(mpc, tree_cfg->opp_id, 0xf);
+ } else if (i == tree_cfg->num_pipes-1) {
+ mpcc_inst = tree_cfg->mpcc[i - 1];
+
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, 0xF);
+
+ REG_UPDATE(MPCC_CONTROL[mpcc_inst],
+ MPCC_MODE, tree_cfg->mode);
+ } else {
+ mpcc_inst = tree_cfg->mpcc[i - 1];
+
+ REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
+ MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
+ }
+ set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
+
+ /* update tree_cfg structure */
+ while (i < tree_cfg->num_pipes - 1) {
+ tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
+ tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
+ i++;
+ }
+ tree_cfg->num_pipes--;
+ }
+ return found;
+}
+
+/* TODO FPGA: how to handle DPP?
+ * Function to add DPP/MPCC pair into MPC configure tree by position.
+ * Before invoke this function, ensure that master lock of OPTC specified
+ * by opp_id is set
+ * This function can be invoke multiple times to add more than 1 pipes.
+ *
+ * tree_cfg[in/out] - current MPC_TREE_CFG
+ * dpp_idx[in] - index of an idle dpp insatnce to be added.
+ * mpcc_idx[in] - index of an idle mpcc instance to be added.
+ * poistion[in] - position of dpp/mpcc pair to be added into current tree_cfg
+ * 0 means insert to the most top layer of MPC tree
+ */
+void dcn10_add_dpp(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg,
+ uint8_t dpp_idx,
+ uint8_t mpcc_idx,
+ uint8_t position)
+{
+ uint8_t temp;
+ uint8_t temp1;
+
+ REG_SET(MPCC_OPP_ID[mpcc_idx], 0,
+ MPCC_OPP_ID, tree_cfg->opp_id);
+
+ REG_SET(MPCC_TOP_SEL[mpcc_idx], 0,
+ MPCC_TOP_SEL, dpp_idx);
+
+ if (position == 0) {
+ /* idle dpp/mpcc is added to the top layer of tree */
+ REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
+ MPCC_BOT_SEL, tree_cfg->mpcc[0]);
+ REG_UPDATE(MPCC_CONTROL[mpcc_idx],
+ MPCC_MODE, 3);
+
+ /* opp will get new output. from new added mpcc */
+ set_output_mux(mpc, tree_cfg->opp_id, mpcc_idx);
+
+ set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
+
+ } else if (position == tree_cfg->num_pipes) {
+ /* idle dpp/mpcc is added to the bottom layer of tree */
+
+ /* get instance of previous bottom mpcc, set to middle layer */
+ temp = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
+
+ REG_SET(MPCC_BOT_SEL[temp], 0,
+ MPCC_BOT_SEL, mpcc_idx);
+
+ REG_UPDATE(MPCC_CONTROL[temp],
+ MPCC_MODE, 3);
+
+ /* mpcc_idx become new bottom mpcc*/
+ REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
+ MPCC_BOT_SEL, 0xf);
+
+ REG_UPDATE(MPCC_CONTROL[mpcc_idx],
+ MPCC_MODE, tree_cfg->mode);
+
+ set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
+ } else {
+ /* idle dpp/mpcc is added to middle of tree */
+ temp = tree_cfg->mpcc[position - 1];
+ temp1 = tree_cfg->mpcc[position];
+
+ /* new mpcc instance temp1 is added right after temp*/
+ REG_SET(MPCC_BOT_SEL[temp], 0,
+ MPCC_BOT_SEL, mpcc_idx);
+
+ /* mpcc_idx connect previous temp+1 to new mpcc */
+ REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
+ MPCC_BOT_SEL, temp1);
+
+ /* temp TODO: may not need*/
+ REG_UPDATE(MPCC_CONTROL[temp],
+ MPCC_MODE, 3);
+
+ set_blend_mode(mpc, tree_cfg->mode, temp);
+ }
+
+ /* update tree_cfg structure */
+ temp = tree_cfg->num_pipes - 1;
+
+ /*
+ * iterating from the last mpc/dpp pair to the one being added, shift
+ * them down one position
+ */
+ while (temp > position) {
+ tree_cfg->dpp[temp + 1] = tree_cfg->dpp[temp];
+ tree_cfg->mpcc[temp + 1] = tree_cfg->mpcc[temp];
+ temp--;
+ }
+
+ /* insert the new mpc/dpp pair into the tree_cfg*/
+ tree_cfg->dpp[position] = dpp_idx;
+ tree_cfg->mpcc[position] = mpcc_idx;
+ tree_cfg->num_pipes++;
+}
+
+void wait_mpcc_idle(struct dcn10_mpc *mpc,
+ uint8_t mpcc_id)
+{
+ REG_WAIT(MPCC_STATUS[mpcc_id],
+ MPCC_IDLE, 1,
+ 1000, 1000);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
new file mode 100644
index 0000000..6550b93
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -0,0 +1,135 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MPC_DCN10_H__
+#define __DC_MPC_DCN10_H__
+
+#include "mpc.h"
+
+#define TO_DCN10_MPC(mpc_base)\
+ container_of(mpc_base, struct dcn10_mpc, base)
+
+#define MAX_MPCC 4
+#define MAX_MPC_OUT 4
+#define MAX_OPP 4
+
+#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
+ SRII(MPCC_TOP_SEL, MPCC, inst),\
+ SRII(MPCC_BOT_SEL, MPCC, inst),\
+ SRII(MPCC_CONTROL, MPCC, inst),\
+ SRII(MPCC_STATUS, MPCC, inst),\
+ SRII(MPCC_OPP_ID, MPCC, inst),\
+ SRII(MPCC_BG_G_Y, MPCC, inst),\
+ SRII(MPCC_BG_R_CR, MPCC, inst),\
+ SRII(MPCC_BG_B_CB, MPCC, inst),\
+ SRII(MPCC_BG_B_CB, MPCC, inst),\
+ SRII(MUX, MPC_OUT, inst),\
+ SRII(OPP_PIPE_CONTROL, OPP_PIPE, inst)
+
+struct dcn_mpc_registers {
+ uint32_t MPCC_TOP_SEL[MAX_MPCC];
+ uint32_t MPCC_BOT_SEL[MAX_MPCC];
+ uint32_t MPCC_CONTROL[MAX_MPCC];
+ uint32_t MPCC_STATUS[MAX_MPCC];
+ uint32_t MPCC_OPP_ID[MAX_MPCC];
+ uint32_t MPCC_BG_G_Y[MAX_MPCC];
+ uint32_t MPCC_BG_R_CR[MAX_MPCC];
+ uint32_t MPCC_BG_B_CB[MAX_MPCC];
+ uint32_t MUX[MAX_MPC_OUT];
+ uint32_t OPP_PIPE_CONTROL[MAX_OPP];
+};
+
+#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
+ SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
+ SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
+ SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
+ SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
+ SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
+ SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
+ SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
+ SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
+ SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
+ SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh)
+
+#define MPC_REG_FIELD_LIST(type) \
+ type MPCC_TOP_SEL;\
+ type MPCC_BOT_SEL;\
+ type MPCC_MODE;\
+ type MPCC_ALPHA_BLND_MODE;\
+ type MPCC_ALPHA_MULTIPLIED_MODE;\
+ type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
+ type MPCC_IDLE;\
+ type MPCC_OPP_ID;\
+ type MPCC_BG_G_Y;\
+ type MPCC_BG_R_CR;\
+ type MPCC_BG_B_CB;\
+ type MPC_OUT_MUX;\
+ type OPP_PIPE_CLOCK_EN;\
+
+struct dcn_mpc_shift {
+ MPC_REG_FIELD_LIST(uint8_t)
+};
+
+struct dcn_mpc_mask {
+ MPC_REG_FIELD_LIST(uint32_t)
+};
+
+struct dcn10_mpc {
+ struct mpc base;
+ const struct dcn_mpc_registers *mpc_regs;
+ const struct dcn_mpc_shift *mpc_shift;
+ const struct dcn_mpc_mask *mpc_mask;
+};
+
+void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
+ uint8_t dpp_idx,
+ uint8_t mpcc_idx,
+ uint8_t opp_idx);
+
+void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg);
+
+bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg,
+ uint8_t idx);
+
+void dcn10_add_dpp(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg,
+ uint8_t dpp_idx,
+ uint8_t mpcc_idx,
+ uint8_t position);
+
+void wait_mpcc_idle(struct dcn10_mpc *mpc,
+ uint8_t mpcc_id);
+
+void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
+ struct mpc_tree_cfg *tree_cfg);
+
+void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
+ unsigned int mpcc_inst,
+ struct tg_color *bg_color);
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
new file mode 100644
index 0000000..fce08e5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -0,0 +1,801 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn10_opp.h"
+#include "reg_helper.h"
+
+#define REG(reg) \
+ (oppn10->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
+
+#define CTX \
+ oppn10->base.ctx
+
+static void opp_set_regamma_mode(
+ struct output_pixel_processor *opp,
+ enum opp_regamma mode)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+ uint32_t re_mode = 0;
+ uint32_t obuf_bypass = 0; /* need for pipe split */
+ uint32_t obuf_hupscale = 0;
+
+ switch (mode) {
+ case OPP_REGAMMA_BYPASS:
+ re_mode = 0;
+ break;
+ case OPP_REGAMMA_SRGB:
+ re_mode = 1;
+ break;
+ case OPP_REGAMMA_3_6:
+ re_mode = 2;
+ break;
+ case OPP_REGAMMA_USER:
+ re_mode = oppn10->is_write_to_ram_a_safe ? 3 : 4;
+ oppn10->is_write_to_ram_a_safe = !oppn10->is_write_to_ram_a_safe;
+ break;
+ default:
+ break;
+ }
+
+ REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
+ REG_UPDATE_2(OBUF_CONTROL,
+ OBUF_BYPASS, obuf_bypass,
+ OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
+}
+
+/************* FORMATTER ************/
+
+/**
+ * set_truncation
+ * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
+ * 2) enable truncation
+ * 3) HW remove 12bit FMT support for DCE11 power saving reason.
+ */
+static void set_truncation(
+ struct dcn10_opp *oppn10,
+ const struct bit_depth_reduction_params *params)
+{
+ REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
+ FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
+ FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
+ FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
+}
+
+static void set_spatial_dither(
+ struct dcn10_opp *oppn10,
+ const struct bit_depth_reduction_params *params)
+{
+ /*Disable spatial (random) dithering*/
+ REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
+ FMT_SPATIAL_DITHER_EN, 0,
+ FMT_SPATIAL_DITHER_MODE, 0,
+ FMT_SPATIAL_DITHER_DEPTH, 0,
+ FMT_TEMPORAL_DITHER_EN, 0,
+ FMT_HIGHPASS_RANDOM_ENABLE, 0,
+ FMT_FRAME_RANDOM_ENABLE, 0,
+ FMT_RGB_RANDOM_ENABLE, 0);
+
+
+ /* only use FRAME_COUNTER_MAX if frameRandom == 1*/
+ if (params->flags.FRAME_RANDOM == 1) {
+ if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
+ REG_UPDATE_2(FMT_CONTROL,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
+ } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
+ REG_UPDATE_2(FMT_CONTROL,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
+ } else {
+ return;
+ }
+ } else {
+ REG_UPDATE_2(FMT_CONTROL,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
+ FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
+ }
+
+ /*Set seed for random values for
+ * spatial dithering for R,G,B channels*/
+
+ REG_SET(FMT_DITHER_RAND_R_SEED, 0,
+ FMT_RAND_R_SEED, params->r_seed_value);
+
+ REG_SET(FMT_DITHER_RAND_G_SEED, 0,
+ FMT_RAND_G_SEED, params->g_seed_value);
+
+ REG_SET(FMT_DITHER_RAND_B_SEED, 0,
+ FMT_RAND_B_SEED, params->b_seed_value);
+
+ /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
+ * offset for the R/Cr channel, lower 4LSB
+ * is forced to zeros. Typically set to 0
+ * RGB and 0x80000 YCbCr.
+ */
+ /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
+ * offset for the G/Y channel, lower 4LSB is
+ * forced to zeros. Typically set to 0 RGB
+ * and 0x80000 YCbCr.
+ */
+ /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
+ * offset for the B/Cb channel, lower 4LSB is
+ * forced to zeros. Typically set to 0 RGB and
+ * 0x80000 YCbCr.
+ */
+
+ REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
+ /*Enable spatial dithering*/
+ FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
+ /* Set spatial dithering mode
+ * (default is Seed patterrn AAAA...)
+ */
+ FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
+ /*Set spatial dithering bit depth*/
+ FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
+ /*Disable High pass filter*/
+ FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
+ /*Reset only at startup*/
+ FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
+ /*Set RGB data dithered with x^28+x^3+1*/
+ FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
+}
+
+static void opp_program_bit_depth_reduction(
+ struct output_pixel_processor *opp,
+ const struct bit_depth_reduction_params *params)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ set_truncation(oppn10, params);
+ set_spatial_dither(oppn10, params);
+ /* TODO
+ * set_temporal_dither(oppn10, params);
+ */
+}
+
+/**
+ * set_pixel_encoding
+ *
+ * Set Pixel Encoding
+ * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
+ * 1: YCbCr 4:2:2
+ */
+static void set_pixel_encoding(
+ struct dcn10_opp *oppn10,
+ const struct clamping_and_pixel_encoding_params *params)
+{
+ switch (params->pixel_encoding) {
+
+ case PIXEL_ENCODING_RGB:
+ case PIXEL_ENCODING_YCBCR444:
+ REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
+ break;
+ case PIXEL_ENCODING_YCBCR422:
+ REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
+ break;
+ case PIXEL_ENCODING_YCBCR420:
+ REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * Set Clamping
+ * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
+ * 1 for 8 bpc
+ * 2 for 10 bpc
+ * 3 for 12 bpc
+ * 7 for programable
+ * 2) Enable clamp if Limited range requested
+ */
+static void opp_set_clamping(
+ struct dcn10_opp *oppn10,
+ const struct clamping_and_pixel_encoding_params *params)
+{
+ REG_UPDATE_2(FMT_CLAMP_CNTL,
+ FMT_CLAMP_DATA_EN, 0,
+ FMT_CLAMP_COLOR_FORMAT, 0);
+
+ switch (params->clamping_level) {
+ case CLAMPING_FULL_RANGE:
+ REG_UPDATE_2(FMT_CLAMP_CNTL,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 0);
+ break;
+ case CLAMPING_LIMITED_RANGE_8BPC:
+ REG_UPDATE_2(FMT_CLAMP_CNTL,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 1);
+ break;
+ case CLAMPING_LIMITED_RANGE_10BPC:
+ REG_UPDATE_2(FMT_CLAMP_CNTL,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 2);
+
+ break;
+ case CLAMPING_LIMITED_RANGE_12BPC:
+ REG_UPDATE_2(FMT_CLAMP_CNTL,
+ FMT_CLAMP_DATA_EN, 1,
+ FMT_CLAMP_COLOR_FORMAT, 3);
+ break;
+ case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
+ /* TODO */
+ default:
+ break;
+ }
+
+}
+
+static void opp_set_dyn_expansion(
+ struct output_pixel_processor *opp,
+ enum dc_color_space color_sp,
+ enum dc_color_depth color_dpth,
+ enum signal_type signal)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
+ FMT_DYNAMIC_EXP_EN, 0,
+ FMT_DYNAMIC_EXP_MODE, 0);
+
+ /*00 - 10-bit -> 12-bit dynamic expansion*/
+ /*01 - 8-bit -> 12-bit dynamic expansion*/
+ if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+ signal == SIGNAL_TYPE_DISPLAY_PORT ||
+ signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ switch (color_dpth) {
+ case COLOR_DEPTH_888:
+ REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
+ FMT_DYNAMIC_EXP_EN, 1,
+ FMT_DYNAMIC_EXP_MODE, 1);
+ break;
+ case COLOR_DEPTH_101010:
+ REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
+ FMT_DYNAMIC_EXP_EN, 1,
+ FMT_DYNAMIC_EXP_MODE, 0);
+ break;
+ case COLOR_DEPTH_121212:
+ REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
+ FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
+ FMT_DYNAMIC_EXP_MODE, 0);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void opp_program_clamping_and_pixel_encoding(
+ struct output_pixel_processor *opp,
+ const struct clamping_and_pixel_encoding_params *params)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ opp_set_clamping(oppn10, params);
+ set_pixel_encoding(oppn10, params);
+}
+
+static void opp_program_fmt(
+ struct output_pixel_processor *opp,
+ struct bit_depth_reduction_params *fmt_bit_depth,
+ struct clamping_and_pixel_encoding_params *clamping)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
+
+ /* dithering is affected by <CrtcSourceSelect>, hence should be
+ * programmed afterwards */
+ opp_program_bit_depth_reduction(
+ opp,
+ fmt_bit_depth);
+
+ opp_program_clamping_and_pixel_encoding(
+ opp,
+ clamping);
+
+ return;
+}
+
+static void opp_set_output_csc_default(
+ struct output_pixel_processor *opp,
+ const struct default_adjustment *default_adjust)
+{
+
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+ uint32_t ocsc_mode = 0;
+
+ if (default_adjust != NULL) {
+ switch (default_adjust->out_color_space) {
+ case COLOR_SPACE_SRGB:
+ ocsc_mode = 0;
+ break;
+ case COLOR_SPACE_SRGB_LIMITED:
+ ocsc_mode = 1;
+ break;
+ case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
+ ocsc_mode = 2;
+ break;
+ case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
+ ocsc_mode = 3;
+ break;
+ case COLOR_SPACE_UNKNOWN:
+ default:
+ break;
+ }
+ }
+
+ REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
+
+}
+/*program re gamma RAM B*/
+static void opp_program_regamma_lutb_settings(
+ struct output_pixel_processor *opp,
+ const struct pwl_params *params)
+{
+ const struct gamma_curve *curve;
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0,
+ CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0);
+ REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0,
+ CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0);
+ REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0,
+ CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0);
+
+ REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0,
+ CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
+ REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0,
+ CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
+ REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0,
+ CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
+
+ REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
+
+ REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0,
+ CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
+
+ curve = params->arr_curve_points;
+ REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0,
+ CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0,
+ CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0,
+ CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0,
+ CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0,
+ CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0,
+ CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0,
+ CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0,
+ CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0,
+ CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0,
+ CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0,
+ CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0,
+ CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0,
+ CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0,
+ CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0,
+ CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0,
+ CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0,
+ CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
+
+}
+
+/*program re gamma RAM A*/
+static void opp_program_regamma_luta_settings(
+ struct output_pixel_processor *opp,
+ const struct pwl_params *params)
+{
+ const struct gamma_curve *curve;
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0,
+ CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
+ REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0,
+ CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
+ REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0,
+ CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
+ CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
+
+ REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0,
+ CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
+ REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0,
+ CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
+ REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0,
+ CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
+
+ REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
+
+ REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
+
+ REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
+ REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0,
+ CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
+ CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
+
+ curve = params->arr_curve_points;
+ REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0,
+ CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0,
+ CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0,
+ CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0,
+ CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0,
+ CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0,
+ CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0,
+ CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0,
+ CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0,
+ CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0,
+ CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0,
+ CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0,
+ CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0,
+ CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0,
+ CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0,
+ CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0,
+ CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
+
+ curve += 2;
+ REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0,
+ CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
+ CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
+ CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
+ CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
+}
+
+static void opp_configure_regamma_lut(
+ struct output_pixel_processor *opp,
+ bool is_ram_a)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
+ CM_RGAM_LUT_WRITE_EN_MASK, 7);
+ REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
+ CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
+ REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
+}
+
+static void opp_power_on_regamma_lut(
+ struct output_pixel_processor *opp,
+ bool power_on)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+ REG_SET(CM_MEM_PWR_CTRL, 0,
+ RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+
+}
+
+static void opp_program_regamma_lut(
+ struct output_pixel_processor *opp,
+ const struct pwl_result_data *rgb,
+ uint32_t num)
+{
+ uint32_t i;
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+ for (i = 0 ; i < num; i++) {
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
+
+ REG_SET(CM_RGAM_LUT_DATA, 0,
+ CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0,
+ CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
+ REG_SET(CM_RGAM_LUT_DATA, 0,
+ CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
+
+ }
+
+}
+
+static bool opp_set_regamma_pwl(
+ struct output_pixel_processor *opp, const struct pwl_params *params)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ opp_power_on_regamma_lut(opp, true);
+ opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe);
+
+ if (oppn10->is_write_to_ram_a_safe)
+ opp_program_regamma_luta_settings(opp, params);
+ else
+ opp_program_regamma_lutb_settings(opp, params);
+
+ opp_program_regamma_lut(
+ opp, params->rgb_resulted, params->hw_points_num);
+
+ return true;
+}
+
+static void opp_set_stereo_polarity(
+ struct output_pixel_processor *opp,
+ bool enable, bool rightEyePolarity)
+{
+ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+
+ REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
+}
+
+/*****************************************/
+/* Constructor, Destructor */
+/*****************************************/
+
+static void dcn10_opp_destroy(struct output_pixel_processor **opp)
+{
+ dm_free(TO_DCN10_OPP(*opp));
+ *opp = NULL;
+}
+
+static struct opp_funcs dcn10_opp_funcs = {
+ .opp_power_on_regamma_lut = opp_power_on_regamma_lut,
+ .opp_set_csc_adjustment = NULL,
+ .opp_set_csc_default = opp_set_output_csc_default,
+ .opp_set_dyn_expansion = opp_set_dyn_expansion,
+ .opp_program_regamma_pwl = opp_set_regamma_pwl,
+ .opp_set_regamma_mode = opp_set_regamma_mode,
+ .opp_program_fmt = opp_program_fmt,
+ .opp_program_bit_depth_reduction = opp_program_bit_depth_reduction,
+ .opp_set_stereo_polarity = opp_set_stereo_polarity,
+ .opp_destroy = dcn10_opp_destroy
+};
+
+void dcn10_opp_construct(struct dcn10_opp *oppn10,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn10_opp_registers *regs,
+ const struct dcn10_opp_shift *opp_shift,
+ const struct dcn10_opp_mask *opp_mask)
+{
+ oppn10->base.ctx = ctx;
+ oppn10->base.inst = inst;
+ oppn10->base.funcs = &dcn10_opp_funcs;
+
+ oppn10->regs = regs;
+ oppn10->opp_shift = opp_shift;
+ oppn10->opp_mask = opp_mask;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
new file mode 100644
index 0000000..113e0bc
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -0,0 +1,622 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPP_DCN10_H__
+#define __DC_OPP_DCN10_H__
+
+#include "opp.h"
+
+#define TO_DCN10_OPP(opp)\
+ container_of(opp, struct dcn10_opp, base)
+
+#define OPP_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define OPP_DCN10_REG_LIST(id) \
+ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id), \
+ SRI(CM_RGAM_CONTROL, CM, id), \
+ SRI(OBUF_CONTROL, DSCL, id), \
+ SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
+ SRI(FMT_CONTROL, FMT, id), \
+ SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
+ SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
+ SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
+ SRI(FMT_CLAMP_CNTL, FMT, id), \
+ SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
+ SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
+ SRI(CM_OCSC_CONTROL, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
+ SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
+ SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
+ SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
+ SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_2_3, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_4_5, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_6_7, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_8_9, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_10_11, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_12_13, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_14_15, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_16_17, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_18_19, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_20_21, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_22_23, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_24_25, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_26_27, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_28_29, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_30_31, CM, id), \
+ SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
+ SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
+ SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
+ SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
+ SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
+ SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
+ SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_2_3, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_4_5, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_6_7, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_8_9, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_10_11, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_12_13, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_14_15, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_16_17, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_18_19, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_20_21, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_22_23, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_24_25, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_26_27, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_28_29, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_30_31, CM, id), \
+ SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
+ SRI(CM_RGAM_LUT_INDEX, CM, id), \
+ SRI(CM_MEM_PWR_CTRL, CM, id), \
+ SRI(CM_RGAM_LUT_DATA, CM, id)
+
+#define OPP_DCN10_MASK_SH_LIST(mask_sh) \
+ OPP_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
+ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \
+ OPP_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
+ OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
+ OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
+ OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
+ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
+ OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \
+ OPP_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_2_3, CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_4_5, CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_6_7, CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_8_9, CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_10_11, CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_12_13, CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_14_15, CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_16_17, CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_18_19, CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_20_21, CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_22_23, CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_24_25, CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_26_27, CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_28_29, CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_30_31, CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_2_3, CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_4_5, CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_6_7, CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_8_9, CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_10_11, CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_12_13, CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_14_15, CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_16_17, CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_18_19, CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_20_21, CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_22_23, CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_24_25, CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_26_27, CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_28_29, CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_30_31, CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
+ OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
+ OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
+ OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+
+#define OPP_DCN10_REG_FIELD_LIST(type) \
+ type CM_RGAM_LUT_MODE; \
+ type OBUF_BYPASS; \
+ type OBUF_H_2X_UPSCALE_EN; \
+ type FMT_TRUNCATE_EN; \
+ type FMT_TRUNCATE_DEPTH; \
+ type FMT_TRUNCATE_MODE; \
+ type FMT_SPATIAL_DITHER_EN; \
+ type FMT_SPATIAL_DITHER_MODE; \
+ type FMT_SPATIAL_DITHER_DEPTH; \
+ type FMT_TEMPORAL_DITHER_EN; \
+ type FMT_HIGHPASS_RANDOM_ENABLE; \
+ type FMT_FRAME_RANDOM_ENABLE; \
+ type FMT_RGB_RANDOM_ENABLE; \
+ type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
+ type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
+ type FMT_RAND_R_SEED; \
+ type FMT_RAND_G_SEED; \
+ type FMT_RAND_B_SEED; \
+ type FMT_PIXEL_ENCODING; \
+ type FMT_CLAMP_DATA_EN; \
+ type FMT_CLAMP_COLOR_FORMAT; \
+ type FMT_DYNAMIC_EXP_EN; \
+ type FMT_DYNAMIC_EXP_MODE; \
+ type FMT_MAP420MEM_PWR_FORCE; \
+ type CM_OCSC_MODE; \
+ type CM_RGAM_RAMB_EXP_REGION_START_B; \
+ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
+ type CM_RGAM_RAMB_EXP_REGION_START_G; \
+ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
+ type CM_RGAM_RAMB_EXP_REGION_START_R; \
+ type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
+ type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
+ type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
+ type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
+ type CM_RGAM_RAMB_EXP_REGION_END_B; \
+ type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
+ type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
+ type CM_RGAM_RAMB_EXP_REGION_END_G; \
+ type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
+ type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
+ type CM_RGAM_RAMB_EXP_REGION_END_R; \
+ type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
+ type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
+ type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
+ type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
+ type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION_START_B; \
+ type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
+ type CM_RGAM_RAMA_EXP_REGION_START_G; \
+ type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
+ type CM_RGAM_RAMA_EXP_REGION_START_R; \
+ type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
+ type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
+ type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
+ type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
+ type CM_RGAM_RAMA_EXP_REGION_END_B; \
+ type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
+ type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
+ type CM_RGAM_RAMA_EXP_REGION_END_G; \
+ type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
+ type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
+ type CM_RGAM_RAMA_EXP_REGION_END_R; \
+ type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
+ type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
+ type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
+ type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
+ type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
+ type CM_RGAM_LUT_WRITE_EN_MASK; \
+ type CM_RGAM_LUT_WRITE_SEL; \
+ type CM_RGAM_LUT_INDEX; \
+ type RGAM_MEM_PWR_FORCE; \
+ type CM_RGAM_LUT_DATA; \
+ type FMT_STEREOSYNC_OVERRIDE
+
+struct dcn10_opp_shift {
+ OPP_DCN10_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn10_opp_mask {
+ OPP_DCN10_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn10_opp_registers {
+ uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
+ uint32_t CM_RGAM_CONTROL;
+ uint32_t OBUF_CONTROL;
+ uint32_t FMT_BIT_DEPTH_CONTROL;
+ uint32_t FMT_CONTROL;
+ uint32_t FMT_DITHER_RAND_R_SEED;
+ uint32_t FMT_DITHER_RAND_G_SEED;
+ uint32_t FMT_DITHER_RAND_B_SEED;
+ uint32_t FMT_CLAMP_CNTL;
+ uint32_t FMT_DYNAMIC_EXP_CNTL;
+ uint32_t FMT_MAP420_MEMORY_CONTROL;
+ uint32_t CM_OCSC_CONTROL;
+ uint32_t CM_RGAM_RAMB_START_CNTL_B;
+ uint32_t CM_RGAM_RAMB_START_CNTL_G;
+ uint32_t CM_RGAM_RAMB_START_CNTL_R;
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
+ uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
+ uint32_t CM_RGAM_RAMB_END_CNTL1_B;
+ uint32_t CM_RGAM_RAMB_END_CNTL2_B;
+ uint32_t CM_RGAM_RAMB_END_CNTL1_G;
+ uint32_t CM_RGAM_RAMB_END_CNTL2_G;
+ uint32_t CM_RGAM_RAMB_END_CNTL1_R;
+ uint32_t CM_RGAM_RAMB_END_CNTL2_R;
+ uint32_t CM_RGAM_RAMB_REGION_0_1;
+ uint32_t CM_RGAM_RAMB_REGION_2_3;
+ uint32_t CM_RGAM_RAMB_REGION_4_5;
+ uint32_t CM_RGAM_RAMB_REGION_6_7;
+ uint32_t CM_RGAM_RAMB_REGION_8_9;
+ uint32_t CM_RGAM_RAMB_REGION_10_11;
+ uint32_t CM_RGAM_RAMB_REGION_12_13;
+ uint32_t CM_RGAM_RAMB_REGION_14_15;
+ uint32_t CM_RGAM_RAMB_REGION_16_17;
+ uint32_t CM_RGAM_RAMB_REGION_18_19;
+ uint32_t CM_RGAM_RAMB_REGION_20_21;
+ uint32_t CM_RGAM_RAMB_REGION_22_23;
+ uint32_t CM_RGAM_RAMB_REGION_24_25;
+ uint32_t CM_RGAM_RAMB_REGION_26_27;
+ uint32_t CM_RGAM_RAMB_REGION_28_29;
+ uint32_t CM_RGAM_RAMB_REGION_30_31;
+ uint32_t CM_RGAM_RAMB_REGION_32_33;
+ uint32_t CM_RGAM_RAMA_START_CNTL_B;
+ uint32_t CM_RGAM_RAMA_START_CNTL_G;
+ uint32_t CM_RGAM_RAMA_START_CNTL_R;
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
+ uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
+ uint32_t CM_RGAM_RAMA_END_CNTL1_B;
+ uint32_t CM_RGAM_RAMA_END_CNTL2_B;
+ uint32_t CM_RGAM_RAMA_END_CNTL1_G;
+ uint32_t CM_RGAM_RAMA_END_CNTL2_G;
+ uint32_t CM_RGAM_RAMA_END_CNTL1_R;
+ uint32_t CM_RGAM_RAMA_END_CNTL2_R;
+ uint32_t CM_RGAM_RAMA_REGION_0_1;
+ uint32_t CM_RGAM_RAMA_REGION_2_3;
+ uint32_t CM_RGAM_RAMA_REGION_4_5;
+ uint32_t CM_RGAM_RAMA_REGION_6_7;
+ uint32_t CM_RGAM_RAMA_REGION_8_9;
+ uint32_t CM_RGAM_RAMA_REGION_10_11;
+ uint32_t CM_RGAM_RAMA_REGION_12_13;
+ uint32_t CM_RGAM_RAMA_REGION_14_15;
+ uint32_t CM_RGAM_RAMA_REGION_16_17;
+ uint32_t CM_RGAM_RAMA_REGION_18_19;
+ uint32_t CM_RGAM_RAMA_REGION_20_21;
+ uint32_t CM_RGAM_RAMA_REGION_22_23;
+ uint32_t CM_RGAM_RAMA_REGION_24_25;
+ uint32_t CM_RGAM_RAMA_REGION_26_27;
+ uint32_t CM_RGAM_RAMA_REGION_28_29;
+ uint32_t CM_RGAM_RAMA_REGION_30_31;
+ uint32_t CM_RGAM_RAMA_REGION_32_33;
+ uint32_t CM_RGAM_LUT_INDEX;
+ uint32_t CM_MEM_PWR_CTRL;
+ uint32_t CM_RGAM_LUT_DATA;
+};
+
+struct dcn10_opp {
+ struct output_pixel_processor base;
+
+ const struct dcn10_opp_registers *regs;
+ const struct dcn10_opp_shift *opp_shift;
+ const struct dcn10_opp_mask *opp_mask;
+
+ bool is_write_to_ram_a_safe;
+};
+
+void dcn10_opp_construct(struct dcn10_opp *oppn10,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn10_opp_registers *regs,
+ const struct dcn10_opp_shift *opp_shift,
+ const struct dcn10_opp_mask *opp_mask);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
new file mode 100644
index 0000000..7aa438c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -0,0 +1,1475 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn10/dcn10_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn10/dcn10_mpc.h"
+#include "irq/dcn10/irq_service_dcn10.h"
+#include "dcn10/dcn10_transform.h"
+#include "dcn10/dcn10_timing_generator.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_opp.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
+#include "dce/dce_clocks.h"
+#include "dce/dce_clock_source.h"
+#include "dcn10/dcn10_mem_input.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "../virtual/virtual_stream_encoder.h"
+#include "dce110/dce110_resource.h"
+
+#include "vega10/soc15ip.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+
+#include "raven1/NBIO/nbio_7_0_offset.h"
+
+#include "raven1/MMHUB/mmhub_9_1_offset.h"
+#include "raven1/MMHUB/mmhub_9_1_sh_mask.h"
+
+#include "reg_helper.h"
+#include "dce/dce_abm.h"
+#include "dce/dce_dmcu.h"
+
+#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
+ #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
+ #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
+ #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
+ #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
+ #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
+ #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
+ #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+ #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
+ #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
+#endif
+
+
+enum dcn10_clk_src_array_id {
+ DCN10_CLK_SRC_PLL0,
+ DCN10_CLK_SRC_PLL1,
+ DCN10_CLK_SRC_PLL2,
+ DCN10_CLK_SRC_PLL3,
+ DCN10_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SR(reg_name)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+ NBIF_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+ NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+ .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+/* GC */
+#define GC_BASE_INNER(seg) \
+ GC_BASE__INST0_SEG ## seg
+
+#define GC_BASE(seg) \
+ GC_BASE_INNER(seg)
+
+#define GC_SR(reg_name)\
+ .reg_name = GC_BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_DCN10_REG_LIST()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
+static const struct dce_dmcu_registers dmcu_regs = {
+ DMCU_DCN10_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+ DMCU_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+ DMCU_MASK_SH_LIST_DCN10(_MASK)
+};
+
+static const struct dce_abm_registers abm_regs = {
+ ABM_DCN10_REG_LIST(0)
+};
+
+static const struct dce_abm_shift abm_shift = {
+ ABM_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+ ABM_MASK_SH_LIST_DCN10(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+ SE_DCN_REG_LIST(id),\
+ .TMDS_CNTL = 0,\
+ .AFMT_AVI_INFO0 = 0,\
+ .AFMT_AVI_INFO1 = 0,\
+ .AFMT_AVI_INFO2 = 0,\
+ .AFMT_AVI_INFO3 = 0,\
+}
+
+static const struct dce110_stream_enc_registers stream_enc_regs[] = {
+ stream_enc_regs(0),
+ stream_enc_regs(1),
+ stream_enc_regs(2),
+ stream_enc_regs(3),
+};
+
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
+ .AFMT_GENERIC0_UPDATE = 0,
+ .AFMT_GENERIC2_UPDATE = 0,
+ .DP_DYN_RANGE = 0,
+ .DP_YCBCR_RANGE = 0,
+ .HDMI_AVI_INFO_SEND = 0,
+ .HDMI_AVI_INFO_CONT = 0,
+ .HDMI_AVI_INFO_LINE = 0,
+ .DP_SEC_AVI_ENABLE = 0,
+ .AFMT_AVI_INFO_VERSION = 0
+};
+
+#define audio_regs(id)\
+[id] = {\
+ AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+ audio_regs(0),
+ audio_regs(1),
+ audio_regs(2),
+ audio_regs(3),
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+ SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+ AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+ DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_aduio_mask audio_mask = {
+ DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define aux_regs(id)\
+[id] = {\
+ AUX_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
+ aux_regs(0),
+ aux_regs(1),
+ aux_regs(2),
+ aux_regs(3),
+ aux_regs(4),
+ aux_regs(5)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+ HPD_REG_LIST(id)\
+}
+
+static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+ hpd_regs(0),
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5)
+};
+
+#define link_regs(id)\
+[id] = {\
+ LE_DCN10_REG_LIST(id), \
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
+}
+
+static const struct dce110_link_enc_registers link_enc_regs[] = {
+ link_regs(0),
+ link_regs(1),
+ link_regs(2),
+ link_regs(3),
+ link_regs(4),
+ link_regs(5),
+ link_regs(6),
+};
+
+#define ipp_regs(id)\
+[id] = {\
+ IPP_DCN10_REG_LIST(id),\
+}
+
+static const struct dcn10_ipp_registers ipp_regs[] = {
+ ipp_regs(0),
+ ipp_regs(1),
+ ipp_regs(2),
+ ipp_regs(3),
+};
+
+static const struct dcn10_ipp_shift ipp_shift = {
+ IPP_DCN10_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_ipp_mask ipp_mask = {
+ IPP_DCN10_MASK_SH_LIST(_MASK),
+};
+
+#define opp_regs(id)\
+[id] = {\
+ OPP_DCN10_REG_LIST(id),\
+}
+
+static const struct dcn10_opp_registers opp_regs[] = {
+ opp_regs(0),
+ opp_regs(1),
+ opp_regs(2),
+ opp_regs(3),
+};
+
+static const struct dcn10_opp_shift opp_shift = {
+ OPP_DCN10_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_opp_mask opp_mask = {
+ OPP_DCN10_MASK_SH_LIST(_MASK),
+};
+
+#define tf_regs(id)\
+[id] = {\
+ TF_REG_LIST_DCN(id),\
+}
+
+static const struct dcn_transform_registers tf_regs[] = {
+ tf_regs(0),
+ tf_regs(1),
+ tf_regs(2),
+ tf_regs(3),
+};
+
+static const struct dcn_transform_shift tf_shift = {
+ TF_REG_LIST_SH_MASK_DCN(__SHIFT)
+};
+
+static const struct dcn_transform_mask tf_mask = {
+ TF_REG_LIST_SH_MASK_DCN(_MASK),
+};
+
+
+static const struct dcn_mpc_registers mpc_regs = {
+ MPC_COMMON_REG_LIST_DCN1_0(0),
+ MPC_COMMON_REG_LIST_DCN1_0(1),
+ MPC_COMMON_REG_LIST_DCN1_0(2),
+ MPC_COMMON_REG_LIST_DCN1_0(3),
+};
+
+static const struct dcn_mpc_shift mpc_shift = {
+ MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
+};
+
+static const struct dcn_mpc_mask mpc_mask = {
+ MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
+};
+
+#define tg_regs(id)\
+[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
+
+static const struct dcn_tg_registers tg_regs[] = {
+ tg_regs(0),
+ tg_regs(1),
+ tg_regs(2),
+ tg_regs(3),
+};
+
+static const struct dcn_tg_shift tg_shift = {
+ TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
+};
+
+static const struct dcn_tg_mask tg_mask = {
+ TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
+};
+
+
+static const struct bios_registers bios_regs = {
+ NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define mi_regs(id)\
+[id] = {\
+ MI_DCN10_REG_LIST(id)\
+}
+
+
+static const struct dcn_mi_registers mi_regs[] = {
+ mi_regs(0),
+ mi_regs(1),
+ mi_regs(2),
+ mi_regs(3),
+};
+
+static const struct dcn_mi_shift mi_shift = {
+ MI_DCN10_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn_mi_mask mi_mask = {
+ MI_DCN10_MASK_SH_LIST(_MASK)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+ CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+ clk_src_regs(0, A),
+ clk_src_regs(1, B),
+ clk_src_regs(2, C),
+ clk_src_regs(3, D)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+ CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+ CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
+};
+
+
+static const struct resource_caps res_cap = {
+ .num_timing_generator = 4,
+ .num_video_plane = 4,
+ .num_audio = 4,
+ .num_stream_encoder = 4,
+ .num_pll = 4,
+};
+
+static const struct dc_debug debug_defaults_drv = {
+ .disable_dcc = false,
+ .disable_dpp_power_gate = false,
+ .disable_hubp_power_gate = false,
+ .disable_dmcu = true,
+ .force_abm_enable = false,
+ .timing_trace = false,
+ .disable_pplib_clock_request = true,
+ .disable_pplib_wm_range = true,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ .use_dml_wm = false,
+ .use_max_voltage = true
+#endif
+};
+
+static const struct dc_debug debug_defaults_diags = {
+ .disable_dpp_power_gate = false,
+ .disable_hubp_power_gate = false,
+ .disable_clock_gate = true,
+ .disable_dmcu = true,
+ .force_abm_enable = false,
+ .timing_trace = true,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ .disable_pplib_clock_request = true,
+ .disable_pplib_wm_range = true,
+ .use_dml_wm = false,
+ .use_max_voltage = false
+#endif
+};
+
+static void dcn10_transform_destroy(struct transform **xfm)
+{
+ dm_free(TO_DCN10_TRANSFORM(*xfm));
+ *xfm = NULL;
+}
+
+static struct transform *dcn10_transform_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn10_transform *transform =
+ dm_alloc(sizeof(struct dcn10_transform));
+
+ if (!transform)
+ return NULL;
+
+ if (dcn10_transform_construct(transform, ctx,
+ &tf_regs[inst], &tf_shift, &tf_mask))
+ return &transform->base;
+
+ BREAK_TO_DEBUGGER();
+ dm_free(transform);
+ return NULL;
+}
+
+static struct input_pixel_processor *dcn10_ipp_create(
+ struct dc_context *ctx, uint32_t inst)
+{
+ struct dcn10_ipp *ipp =
+ dm_alloc(sizeof(struct dcn10_ipp));
+
+ if (!ipp) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dcn10_ipp_construct(ipp, ctx, inst,
+ &ipp_regs[inst], &ipp_shift, &ipp_mask);
+ return &ipp->base;
+}
+
+
+static struct output_pixel_processor *dcn10_opp_create(
+ struct dc_context *ctx, uint32_t inst)
+{
+ struct dcn10_opp *opp =
+ dm_alloc(sizeof(struct dcn10_opp));
+
+ if (!opp) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dcn10_opp_construct(opp, ctx, inst,
+ &opp_regs[inst], &opp_shift, &opp_mask);
+ return &opp->base;
+}
+
+static struct mpc *dcn10_mpc_create(
+ struct dc_context *ctx)
+{
+ struct dcn10_mpc *mpc = dm_alloc(sizeof(struct dcn10_mpc));
+
+ if (!mpc)
+ return NULL;
+
+ mpc->base.ctx = ctx;
+ mpc->mpc_regs = &mpc_regs;
+ mpc->mpc_shift = &mpc_shift;
+ mpc->mpc_mask = &mpc_mask;
+
+ return &mpc->base;
+}
+
+static void dcn10_mpc_destroy(struct mpc **mpc_base)
+{
+ if (*mpc_base)
+ dm_free(TO_DCN10_MPC(*mpc_base));
+
+ *mpc_base = NULL;
+}
+
+static struct timing_generator *dcn10_timing_generator_create(
+ struct dc_context *ctx,
+ uint32_t instance)
+{
+ struct dcn10_timing_generator *tgn10 =
+ dm_alloc(sizeof(struct dcn10_timing_generator));
+
+ if (!tgn10)
+ return NULL;
+
+ tgn10->base.inst = instance;
+ tgn10->base.ctx = ctx;
+
+ tgn10->tg_regs = &tg_regs[instance];
+ tgn10->tg_shift = &tg_shift;
+ tgn10->tg_mask = &tg_mask;
+
+ dcn10_timing_generator_init(tgn10);
+
+ return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+ .max_hdmi_deep_color = COLOR_DEPTH_121212,
+ .max_hdmi_pixel_clock = 600000,
+ .ycbcr420_supported = true,
+ .flags.bits.IS_HBR2_CAPABLE = true,
+ .flags.bits.IS_HBR3_CAPABLE = true,
+ .flags.bits.IS_TPS3_CAPABLE = true,
+ .flags.bits.IS_TPS4_CAPABLE = true,
+ .flags.bits.IS_YCBCR_CAPABLE = true
+};
+
+struct link_encoder *dcn10_link_encoder_create(
+ const struct encoder_init_data *enc_init_data)
+{
+ struct dce110_link_encoder *enc110 =
+ dm_alloc(sizeof(struct dce110_link_encoder));
+
+ if (!enc110)
+ return NULL;
+
+ if (dce110_link_encoder_construct(
+ enc110,
+ enc_init_data,
+ &link_enc_feature,
+ &link_enc_regs[enc_init_data->transmitter],
+ &link_enc_aux_regs[enc_init_data->channel - 1],
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ return &enc110->base;
+ }
+
+ BREAK_TO_DEBUGGER();
+ dm_free(enc110);
+ return NULL;
+}
+
+struct clock_source *dcn10_clock_source_create(
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ bool dp_clk_src)
+{
+ struct dce110_clk_src *clk_src =
+ dm_alloc(sizeof(struct dce110_clk_src));
+
+ if (!clk_src)
+ return NULL;
+
+ if (dce110_clk_src_construct(clk_src, ctx, bios, id,
+ regs, &cs_shift, &cs_mask)) {
+ clk_src->base.dp_clk_src = dp_clk_src;
+ return &clk_src->base;
+ }
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
+
+static void read_dce_straps(
+ struct dc_context *ctx,
+ struct resource_straps *straps)
+{
+ /* TODO: Registers are missing */
+ /*REG_GET_2(CC_DC_HDMI_STRAPS,
+ HDMI_DISABLE, &straps->hdmi_disable,
+ AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
+
+ REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);*/
+}
+
+static struct audio *create_audio(
+ struct dc_context *ctx, unsigned int inst)
+{
+ return dce_audio_create(ctx, inst,
+ &audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct stream_encoder *dcn10_stream_encoder_create(
+ enum engine_id eng_id,
+ struct dc_context *ctx)
+{
+ struct dce110_stream_encoder *enc110 =
+ dm_alloc(sizeof(struct dce110_stream_encoder));
+
+ if (!enc110)
+ return NULL;
+
+ if (dce110_stream_encoder_construct(
+ enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id], &se_shift, &se_mask))
+ return &enc110->base;
+
+ BREAK_TO_DEBUGGER();
+ dm_free(enc110);
+ return NULL;
+}
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_DCN1_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_DCN1_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_hwseq *dcn10_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
+static const struct resource_create_funcs res_create_funcs = {
+ .read_dce_straps = read_dce_straps,
+ .create_audio = create_audio,
+ .create_stream_encoder = dcn10_stream_encoder_create,
+ .create_hwseq = dcn10_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+ .read_dce_straps = NULL,
+ .create_audio = NULL,
+ .create_stream_encoder = NULL,
+ .create_hwseq = dcn10_hwseq_create,
+};
+
+void dcn10_clock_source_destroy(struct clock_source **clk_src)
+{
+ dm_free(TO_DCE110_CLK_SRC(*clk_src));
+ *clk_src = NULL;
+}
+
+static void destruct(struct dcn10_resource_pool *pool)
+{
+ unsigned int i;
+
+ for (i = 0; i < pool->base.stream_enc_count; i++) {
+ if (pool->base.stream_enc[i] != NULL) {
+ /* TODO: free dcn version of stream encoder once implemented
+ * rather than using virtual stream encoder
+ */
+ dm_free(pool->base.stream_enc[i]);
+ pool->base.stream_enc[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ if (pool->base.opps[i] != NULL)
+ pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+
+ if (pool->base.transforms[i] != NULL)
+ dcn10_transform_destroy(&pool->base.transforms[i]);
+
+ if (pool->base.ipps[i] != NULL)
+ pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+ if (pool->base.mis[i] != NULL) {
+ dm_free(TO_DCN10_MEM_INPUT(pool->base.mis[i]));
+ pool->base.mis[i] = NULL;
+ }
+
+ if (pool->base.irqs != NULL) {
+ dal_irq_service_destroy(&pool->base.irqs);
+ }
+
+ if (pool->base.timing_generators[i] != NULL) {
+ dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+ pool->base.timing_generators[i] = NULL;
+ }
+ }
+
+ for (i = 0; i < pool->base.stream_enc_count; i++) {
+ if (pool->base.stream_enc[i] != NULL)
+ dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+ }
+
+ for (i = 0; i < pool->base.audio_count; i++) {
+ if (pool->base.audios[i])
+ dce_aud_destroy(&pool->base.audios[i]);
+ }
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] != NULL) {
+ dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
+ pool->base.clock_sources[i] = NULL;
+ }
+ }
+
+ if (pool->base.dp_clock_source != NULL) {
+ dcn10_clock_source_destroy(&pool->base.dp_clock_source);
+ pool->base.dp_clock_source = NULL;
+ }
+
+ if (pool->base.mpc != NULL)
+ dcn10_mpc_destroy(&pool->base.mpc);
+
+ if (pool->base.abm != NULL)
+ dce_abm_destroy(&pool->base.abm);
+
+ if (pool->base.dmcu != NULL)
+ dce_dmcu_destroy(&pool->base.dmcu);
+
+ if (pool->base.display_clock != NULL)
+ dce_disp_clk_destroy(&pool->base.display_clock);
+}
+
+static struct mem_input *dcn10_mem_input_create(
+ struct dc_context *ctx,
+ uint32_t inst)
+{
+ struct dcn10_mem_input *mem_inputn10 =
+ dm_alloc(sizeof(struct dcn10_mem_input));
+
+ if (!mem_inputn10)
+ return NULL;
+
+ if (dcn10_mem_input_construct(mem_inputn10, ctx, inst,
+ &mi_regs[inst], &mi_shift, &mi_mask))
+ return &mem_inputn10->base;
+
+ BREAK_TO_DEBUGGER();
+ dm_free(mem_inputn10);
+ return NULL;
+}
+
+static void get_pixel_clock_parameters(
+ const struct pipe_ctx *pipe_ctx,
+ struct pixel_clk_params *pixel_clk_params)
+{
+ const struct core_stream *stream = pipe_ctx->stream;
+ pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
+ pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
+ pixel_clk_params->signal_type = pipe_ctx->stream->signal;
+ pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
+ /* TODO: un-hardcode*/
+ pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
+ LINK_RATE_REF_FREQ_IN_KHZ;
+ pixel_clk_params->flags.ENABLE_SS = 0;
+ pixel_clk_params->color_depth =
+ stream->public.timing.display_color_depth;
+ pixel_clk_params->flags.DISPLAY_BLANKED = 1;
+ pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding;
+
+ if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ pixel_clk_params->color_depth = COLOR_DEPTH_888;
+
+ if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ pixel_clk_params->requested_pix_clk /= 2;
+
+ if (stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING ||
+ stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_SW_FRAME_PACKING ||
+ stream->public.timing. timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA)
+ pixel_clk_params->requested_pix_clk *= 2;
+}
+
+static void build_clamping_params(struct core_stream *stream)
+{
+ stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
+ stream->clamping.c_depth = stream->public.timing.display_color_depth;
+ stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding;
+}
+
+static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
+{
+
+ get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params);
+
+ pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
+ pipe_ctx->clock_source,
+ &pipe_ctx->pix_clk_params,
+ &pipe_ctx->pll_settings);
+
+ pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding;
+
+ resource_build_bit_depth_reduction_params(pipe_ctx->stream,
+ &pipe_ctx->stream->bit_depth_params);
+ build_clamping_params(pipe_ctx->stream);
+
+ return DC_OK;
+}
+
+static enum dc_status validate_mapped_resource(
+ const struct core_dc *dc,
+ struct validate_context *context)
+{
+ enum dc_status status = DC_OK;
+ uint8_t i, j;
+
+ for (i = 0; i < context->stream_count; i++) {
+ struct core_stream *stream = context->streams[i];
+ struct core_link *link = stream->sink->link;
+
+ if (resource_is_stream_unchanged(dc->current_context, stream)) {
+ if (stream != NULL && dc->current_context->streams[i] != NULL) {
+ /* todo: shouldn't have to copy missing parameter here */
+ resource_build_bit_depth_reduction_params(stream,
+ &stream->bit_depth_params);
+ stream->clamping.pixel_encoding =
+ stream->public.timing.pixel_encoding;
+
+ resource_build_bit_depth_reduction_params(stream,
+ &stream->bit_depth_params);
+ build_clamping_params(stream);
+
+ continue;
+ }
+ }
+
+ for (j = 0; j < dc->res_pool->pipe_count ; j++) {
+ struct pipe_ctx *pipe_ctx =
+ &context->res_ctx.pipe_ctx[j];
+
+ if (context->res_ctx.pipe_ctx[j].stream != stream)
+ continue;
+
+
+ if (!pipe_ctx->tg->funcs->validate_timing(
+ pipe_ctx->tg, &stream->public.timing))
+ return DC_FAIL_CONTROLLER_VALIDATE;
+
+ status = build_pipe_hw_param(pipe_ctx);
+
+ if (status != DC_OK)
+ return status;
+
+ if (!link->link_enc->funcs->validate_output_with_stream(
+ link->link_enc, pipe_ctx))
+ return DC_FAIL_ENC_VALIDATE;
+
+ /* TODO: validate audio ASIC caps, encoder */
+
+ status = dc_link_validate_mode_timing(
+ stream, link, &stream->public.timing);
+
+ if (status != DC_OK)
+ return status;
+
+
+ /* do not need to validate non root pipes */
+ break;
+ }
+ }
+
+ return DC_OK;
+}
+
+enum dc_status dcn10_validate_with_context(
+ const struct core_dc *dc,
+ const struct dc_validation_set set[],
+ int set_count,
+ struct validate_context *context)
+{
+ enum dc_status result = DC_OK;
+ int i;
+
+ if (set_count == 0)
+ return result;
+
+ for (i = 0; i < set_count; i++) {
+ context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
+ dc_stream_retain(&context->streams[i]->public);
+ context->stream_count++;
+ }
+
+ result = resource_map_pool_resources(dc, context);
+ if (result != DC_OK)
+ return result;
+
+ result = resource_map_phy_clock_resources(dc, context);
+ if (result != DC_OK)
+ return result;
+
+ result = validate_mapped_resource(dc, context);
+ if (result != DC_OK)
+ return result;
+
+ if (!resource_validate_attach_surfaces(set, set_count,
+ dc->current_context, context, dc->res_pool))
+ return DC_FAIL_ATTACH_SURFACES;
+
+ result = resource_build_scaling_params_for_context(dc, context);
+ if (result != DC_OK)
+ return result;
+
+ if (!dcn_validate_bandwidth(dc, context))
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+
+ return result;
+}
+
+enum dc_status dcn10_validate_guaranteed(
+ const struct core_dc *dc,
+ const struct dc_stream *dc_stream,
+ struct validate_context *context)
+{
+ enum dc_status result = DC_ERROR_UNEXPECTED;
+
+ context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
+ dc_stream_retain(&context->streams[0]->public);
+ context->stream_count++;
+
+ result = resource_map_pool_resources(dc, context);
+
+ if (result == DC_OK)
+ result = resource_map_phy_clock_resources(dc, context);
+
+ if (result == DC_OK)
+ result = validate_mapped_resource(dc, context);
+
+ if (result == DC_OK) {
+ validate_guaranteed_copy_streams(
+ context, dc->public.caps.max_streams);
+ result = resource_build_scaling_params_for_context(dc, context);
+ }
+ if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+
+ return result;
+}
+
+static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
+ struct validate_context *context,
+ const struct resource_pool *pool,
+ struct core_stream *stream)
+{
+ struct resource_context *res_ctx = &context->res_ctx;
+ struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
+ struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
+
+ if (!head_pipe)
+ ASSERT(0);
+
+ if (!idle_pipe)
+ return false;
+
+ idle_pipe->stream = head_pipe->stream;
+ idle_pipe->tg = head_pipe->tg;
+
+ idle_pipe->mi = pool->mis[idle_pipe->pipe_idx];
+ idle_pipe->ipp = pool->ipps[idle_pipe->pipe_idx];
+ idle_pipe->xfm = pool->transforms[idle_pipe->pipe_idx];
+ idle_pipe->opp = pool->opps[idle_pipe->pipe_idx];
+
+ return idle_pipe;
+}
+
+enum dcc_control {
+ dcc_control__256_256_xxx,
+ dcc_control__128_128_xxx,
+ dcc_control__256_64_64,
+};
+
+enum segment_order {
+ segment_order__na,
+ segment_order__contiguous,
+ segment_order__non_contiguous,
+};
+
+static bool dcc_support_pixel_format(
+ enum surface_pixel_format format,
+ unsigned int *bytes_per_element)
+{
+ /* DML: get_bytes_per_element */
+ switch (format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+ *bytes_per_element = 2;
+ return true;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+ *bytes_per_element = 4;
+ return true;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+ *bytes_per_element = 8;
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool dcc_support_swizzle(
+ enum swizzle_mode_values swizzle,
+ unsigned int bytes_per_element,
+ enum segment_order *segment_order_horz,
+ enum segment_order *segment_order_vert)
+{
+ bool standard_swizzle = false;
+ bool display_swizzle = false;
+
+ switch (swizzle) {
+ case DC_SW_4KB_S:
+ case DC_SW_64KB_S:
+ case DC_SW_VAR_S:
+ case DC_SW_4KB_S_X:
+ case DC_SW_64KB_S_X:
+ case DC_SW_VAR_S_X:
+ standard_swizzle = true;
+ break;
+ case DC_SW_4KB_D:
+ case DC_SW_64KB_D:
+ case DC_SW_VAR_D:
+ case DC_SW_4KB_D_X:
+ case DC_SW_64KB_D_X:
+ case DC_SW_VAR_D_X:
+ display_swizzle = true;
+ break;
+ default:
+ break;
+ };
+
+ if (bytes_per_element == 1 && standard_swizzle) {
+ *segment_order_horz = segment_order__contiguous;
+ *segment_order_vert = segment_order__na;
+ return true;
+ }
+ if (bytes_per_element == 2 && standard_swizzle) {
+ *segment_order_horz = segment_order__non_contiguous;
+ *segment_order_vert = segment_order__contiguous;
+ return true;
+ }
+ if (bytes_per_element == 4 && standard_swizzle) {
+ *segment_order_horz = segment_order__non_contiguous;
+ *segment_order_vert = segment_order__contiguous;
+ return true;
+ }
+ if (bytes_per_element == 8 && standard_swizzle) {
+ *segment_order_horz = segment_order__na;
+ *segment_order_vert = segment_order__contiguous;
+ return true;
+ }
+ if (bytes_per_element == 8 && display_swizzle) {
+ *segment_order_horz = segment_order__contiguous;
+ *segment_order_vert = segment_order__non_contiguous;
+ return true;
+ }
+
+ return false;
+}
+
+static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
+ unsigned int bytes_per_element)
+{
+ /* copied from DML. might want to refactor DML to leverage from DML */
+ /* DML : get_blk256_size */
+ if (bytes_per_element == 1) {
+ *blk256_width = 16;
+ *blk256_height = 16;
+ } else if (bytes_per_element == 2) {
+ *blk256_width = 16;
+ *blk256_height = 8;
+ } else if (bytes_per_element == 4) {
+ *blk256_width = 8;
+ *blk256_height = 8;
+ } else if (bytes_per_element == 8) {
+ *blk256_width = 8;
+ *blk256_height = 4;
+ }
+}
+
+static void det_request_size(
+ unsigned int height,
+ unsigned int width,
+ unsigned int bpe,
+ bool *req128_horz_wc,
+ bool *req128_vert_wc)
+{
+ unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
+
+ unsigned int blk256_height = 0;
+ unsigned int blk256_width = 0;
+ unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
+
+ get_blk256_size(&blk256_width, &blk256_height, bpe);
+
+ swath_bytes_horz_wc = height * blk256_height * bpe;
+ swath_bytes_vert_wc = width * blk256_width * bpe;
+
+ *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
+ false : /* full 256B request */
+ true; /* half 128b request */
+
+ *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
+ false : /* full 256B request */
+ true; /* half 128b request */
+}
+
+static bool get_dcc_compression_cap(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output)
+{
+ /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
+ enum dcc_control dcc_control;
+ unsigned int bpe;
+ enum segment_order segment_order_horz, segment_order_vert;
+ bool req128_horz_wc, req128_vert_wc;
+
+ memset(output, 0, sizeof(*output));
+
+ if (dc->debug.disable_dcc)
+ return false;
+
+ if (!dcc_support_pixel_format(input->format,
+ &bpe))
+ return false;
+
+ if (!dcc_support_swizzle(input->swizzle_mode, bpe,
+ &segment_order_horz, &segment_order_vert))
+ return false;
+
+ det_request_size(input->surface_size.height, input->surface_size.width,
+ bpe, &req128_horz_wc, &req128_vert_wc);
+
+ if (!req128_horz_wc && !req128_vert_wc) {
+ dcc_control = dcc_control__256_256_xxx;
+ } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
+ if (!req128_horz_wc)
+ dcc_control = dcc_control__256_256_xxx;
+ else if (segment_order_horz == segment_order__contiguous)
+ dcc_control = dcc_control__128_128_xxx;
+ else
+ dcc_control = dcc_control__256_64_64;
+ } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
+ if (!req128_vert_wc)
+ dcc_control = dcc_control__256_256_xxx;
+ else if (segment_order_vert == segment_order__contiguous)
+ dcc_control = dcc_control__128_128_xxx;
+ else
+ dcc_control = dcc_control__256_64_64;
+ } else {
+ if ((req128_horz_wc &&
+ segment_order_horz == segment_order__non_contiguous) ||
+ (req128_vert_wc &&
+ segment_order_vert == segment_order__non_contiguous))
+ /* access_dir not known, must use most constraining */
+ dcc_control = dcc_control__256_64_64;
+ else
+ /* reg128 is true for either horz and vert
+ * but segment_order is contiguous
+ */
+ dcc_control = dcc_control__128_128_xxx;
+ }
+
+ switch (dcc_control) {
+ case dcc_control__256_256_xxx:
+ output->grph.rgb.max_uncompressed_blk_size = 256;
+ output->grph.rgb.max_compressed_blk_size = 256;
+ output->grph.rgb.independent_64b_blks = false;
+ break;
+ case dcc_control__128_128_xxx:
+ output->grph.rgb.max_uncompressed_blk_size = 128;
+ output->grph.rgb.max_compressed_blk_size = 128;
+ output->grph.rgb.independent_64b_blks = false;
+ break;
+ case dcc_control__256_64_64:
+ output->grph.rgb.max_uncompressed_blk_size = 256;
+ output->grph.rgb.max_compressed_blk_size = 64;
+ output->grph.rgb.independent_64b_blks = true;
+ break;
+ }
+ output->capable = true;
+ output->const_color_support = false;
+
+ return true;
+}
+
+
+static void dcn10_destroy_resource_pool(struct resource_pool **pool)
+{
+ struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
+
+ destruct(dcn10_pool);
+ dm_free(dcn10_pool);
+ *pool = NULL;
+}
+
+
+static struct dc_cap_funcs cap_funcs = {
+ .get_dcc_compression_cap = get_dcc_compression_cap
+};
+
+static struct resource_funcs dcn10_res_pool_funcs = {
+ .destroy = dcn10_destroy_resource_pool,
+ .link_enc_create = dcn10_link_encoder_create,
+ .validate_with_context = dcn10_validate_with_context,
+ .validate_guaranteed = dcn10_validate_guaranteed,
+ .validate_bandwidth = dcn_validate_bandwidth,
+ .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
+};
+
+static bool construct(
+ uint8_t num_virtual_links,
+ struct core_dc *dc,
+ struct dcn10_resource_pool *pool)
+{
+ int i;
+ struct dc_context *ctx = dc->ctx;
+
+ ctx->dc_bios->regs = &bios_regs;
+
+ pool->base.res_cap = &res_cap;
+ pool->base.funcs = &dcn10_res_pool_funcs;
+
+ /*
+ * TODO fill in from actual raven resource when we create
+ * more than virtual encoder
+ */
+
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+
+ /* TODO: Hardcode to correct number of functional controllers */
+ pool->base.pipe_count = 4;
+ dc->public.caps.max_downscale_ratio = 200;
+ dc->public.caps.i2c_speed_in_khz = 100;
+ dc->public.caps.max_cursor_size = 256;
+
+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+ dc->public.debug = debug_defaults_drv;
+ else
+ dc->public.debug = debug_defaults_diags;
+
+ /*************************************************
+ * Create resources *
+ *************************************************/
+
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL0,
+ &clk_src_regs[0], false);
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL1,
+ &clk_src_regs[1], false);
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL2,
+ &clk_src_regs[2], false);
+ pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_COMBO_PHY_PLL3,
+ &clk_src_regs[3], false);
+
+ pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
+
+ pool->base.dp_clock_source =
+ dcn10_clock_source_create(ctx, ctx->dc_bios,
+ CLOCK_SOURCE_ID_DP_DTO,
+ /* todo: not reuse phy_pll registers */
+ &clk_src_regs[0], true);
+
+ for (i = 0; i < pool->base.clk_src_count; i++) {
+ if (pool->base.clock_sources[i] == NULL) {
+ dm_error("DC: failed to create clock sources!\n");
+ BREAK_TO_DEBUGGER();
+ goto clock_source_create_fail;
+ }
+ }
+
+ if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ pool->base.display_clock = dce120_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
+ if (pool->base.display_clock == NULL) {
+ dm_error("DC: failed to create display clock!\n");
+ BREAK_TO_DEBUGGER();
+ goto disp_clk_create_fail;
+ }
+ }
+
+ pool->base.dmcu = dcn10_dmcu_create(ctx,
+ &dmcu_regs,
+ &dmcu_shift,
+ &dmcu_mask);
+ if (pool->base.dmcu == NULL) {
+ dm_error("DC: failed to create dmcu!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ pool->base.abm = dce_abm_create(ctx,
+ &abm_regs,
+ &abm_shift,
+ &abm_mask);
+ if (pool->base.abm == NULL) {
+ dm_error("DC: failed to create abm!\n");
+ BREAK_TO_DEBUGGER();
+ goto res_create_fail;
+ }
+
+ dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
+ dc->dcn_ip = dcn10_ip_defaults;
+ dc->dcn_soc = dcn10_soc_defaults;
+ if (!dc->public.debug.disable_pplib_clock_request)
+ dcn_bw_update_from_pplib(dc);
+ dcn_bw_sync_calcs_and_dml(dc);
+ if (!dc->public.debug.disable_pplib_wm_range)
+ dcn_bw_notify_pplib_of_wm_ranges(dc);
+
+ {
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ struct irq_service_init_data init_data;
+ init_data.ctx = dc->ctx;
+ pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
+ if (!pool->base.irqs)
+ goto irqs_create_fail;
+ #endif
+ }
+
+ /* mem input -> ipp -> transform -> opp -> TG */
+ for (i = 0; i < pool->base.pipe_count; i++) {
+ pool->base.mis[i] = dcn10_mem_input_create(ctx, i);
+ if (pool->base.mis[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create memory input!\n");
+ goto mi_create_fail;
+ }
+
+ pool->base.ipps[i] = dcn10_ipp_create(ctx, i);
+ if (pool->base.ipps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create input pixel processor!\n");
+ goto ipp_create_fail;
+ }
+
+ pool->base.transforms[i] = dcn10_transform_create(ctx, i);
+ if (pool->base.transforms[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create transform!\n");
+ goto transform_create_fail;
+ }
+
+ pool->base.opps[i] = dcn10_opp_create(ctx, i);
+ if (pool->base.opps[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error(
+ "DC: failed to create output pixel processor!\n");
+ goto opp_create_fail;
+ }
+
+ pool->base.timing_generators[i] = dcn10_timing_generator_create(
+ ctx, i);
+ if (pool->base.timing_generators[i] == NULL) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create tg!\n");
+ goto otg_create_fail;
+ }
+ }
+
+ pool->base.mpc = dcn10_mpc_create(ctx);
+
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+ &res_create_funcs : &res_create_maximus_funcs)))
+ goto res_create_fail;
+
+ dcn10_hw_sequencer_construct(dc);
+ dc->public.caps.max_surfaces = pool->base.pipe_count;
+
+ dc->public.cap_funcs = cap_funcs;
+
+ return true;
+
+disp_clk_create_fail:
+otg_create_fail:
+opp_create_fail:
+transform_create_fail:
+ipp_create_fail:
+mi_create_fail:
+irqs_create_fail:
+res_create_fail:
+clock_source_create_fail:
+
+ destruct(pool);
+
+ return false;
+}
+
+struct resource_pool *dcn10_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct core_dc *dc)
+{
+ struct dcn10_resource_pool *pool =
+ dm_alloc(sizeof(struct dcn10_resource_pool));
+
+ if (!pool)
+ return NULL;
+
+ if (construct(num_virtual_links, dc, pool))
+ return &pool->base;
+
+ BREAK_TO_DEBUGGER();
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
new file mode 100644
index 0000000..5f84dbd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
@@ -0,0 +1,47 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_RESOURCE_DCN10_H__
+#define __DC_RESOURCE_DCN10_H__
+
+#include "core_types.h"
+
+#define TO_DCN10_RES_POOL(pool)\
+ container_of(pool, struct dcn10_resource_pool, base)
+
+struct core_dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+struct dcn10_resource_pool {
+ struct resource_pool base;
+};
+struct resource_pool *dcn10_create_resource_pool(
+ uint8_t num_virtual_links,
+ struct core_dc *dc);
+
+
+#endif /* __DC_RESOURCE_DCN10_H__ */
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
new file mode 100644
index 0000000..d7072132
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -0,0 +1,1202 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn10_timing_generator.h"
+
+#define REG(reg)\
+ tgn10->tg_regs->reg
+
+#define CTX \
+ tgn10->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ tgn10->tg_shift->field_name, tgn10->tg_mask->field_name
+
+#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
+
+/**
+* apply_front_porch_workaround TODO FPGA still need?
+*
+* This is a workaround for a bug that has existed since R5xx and has not been
+* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
+*/
+static void tg_apply_front_porch_workaround(
+ struct timing_generator *tg,
+ struct dc_crtc_timing *timing)
+{
+ if (timing->flags.INTERLACE == 1) {
+ if (timing->v_front_porch < 2)
+ timing->v_front_porch = 2;
+ } else {
+ if (timing->v_front_porch < 1)
+ timing->v_front_porch = 1;
+ }
+}
+
+static void dcn10_program_global_sync(
+ struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ if (tg->dlg_otg_param.vstartup_start == 0) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ REG_SET(OTG_VSTARTUP_PARAM, 0,
+ VSTARTUP_START, tg->dlg_otg_param.vstartup_start);
+
+ REG_SET_2(OTG_VUPDATE_PARAM, 0,
+ VUPDATE_OFFSET, tg->dlg_otg_param.vupdate_offset,
+ VUPDATE_WIDTH, tg->dlg_otg_param.vupdate_width);
+
+ REG_SET(OTG_VREADY_PARAM, 0,
+ VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
+}
+
+struct crtc_stereo_flags {
+ uint8_t PROGRAM_STEREO :1;
+ uint8_t PROGRAM_POLARITY :1;
+ uint8_t RIGHT_EYE_POLARITY :1;
+ uint8_t FRAME_PACKED :1;
+ uint8_t DISABLE_STEREO_DP_SYNC :1;
+};
+
+static void dcn10_enable_stereo(struct timing_generator *tg,
+ const struct crtc_stereo_flags *flags,
+ const struct dc_crtc_timing *timing)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ uint32_t active_width = timing->h_addressable;
+ uint32_t space1_size = timing->v_total - timing->v_addressable;
+
+ if (flags) {
+ uint32_t stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
+
+ if (flags->PROGRAM_STEREO)
+ REG_UPDATE_3(OTG_STEREO_CONTROL,
+ OTG_STEREO_EN, stereo_en,
+ OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
+ OTG_STEREO_SYNC_OUTPUT_POLARITY, 0);
+
+ if (flags->PROGRAM_POLARITY)
+ REG_UPDATE(OTG_STEREO_CONTROL,
+ OTG_STEREO_EYE_FLAG_POLARITY,
+ flags->RIGHT_EYE_POLARITY == 0 ? 0:1);
+
+ if (flags->DISABLE_STEREO_DP_SYNC)
+ REG_UPDATE(OTG_STEREO_CONTROL,
+ OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
+
+ if (flags->PROGRAM_STEREO && flags->FRAME_PACKED)
+ REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
+ OTG_3D_STRUCTURE_EN, 1,
+ OTG_3D_STRUCTURE_V_UPDATE_MODE, 1,
+ OTG_3D_STRUCTURE_STEREO_SEL_OVR, 1);
+
+ }
+
+ REG_UPDATE(OPPBUF_CONTROL,
+ OPPBUF_ACTIVE_WIDTH, active_width);
+
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
+ OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
+
+ return;
+}
+
+static void dcn10_disable_stereo(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_SET(OTG_STEREO_CONTROL, 0,
+ OTG_STEREO_EN, 0);
+
+ REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0,
+ OTG_3D_STRUCTURE_EN, 0,
+ OTG_3D_STRUCTURE_V_UPDATE_MODE, 0,
+ OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
+
+ REG_UPDATE(OPPBUF_CONTROL,
+ OPPBUF_ACTIVE_WIDTH, 0);
+ REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
+ OPPBUF_3D_VACT_SPACE1_SIZE, 0);
+ return;
+}
+
+static bool is_frame_alternate_stereo(enum dc_timing_3d_format fmt)
+{
+ bool ret = false;
+ if (fmt == TIMING_3D_FORMAT_FRAME_ALTERNATE ||
+ fmt == TIMING_3D_FORMAT_INBAND_FA ||
+ fmt == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
+ fmt == TIMING_3D_FORMAT_SIDEBAND_FA)
+ ret = true;
+ return ret;
+}
+
+static void dcn10_do_stereo(struct timing_generator *tg,
+ const struct dc_crtc_timing *dc_crtc_timing)
+{
+ struct crtc_stereo_flags stereo_flags = {0};
+ if (dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_NONE ||
+ dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
+ dc_crtc_timing->timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
+ dcn10_disable_stereo(tg);
+ else {
+ stereo_flags.PROGRAM_STEREO = 1;
+ stereo_flags.PROGRAM_POLARITY = 1;
+ stereo_flags.DISABLE_STEREO_DP_SYNC = 0;
+ stereo_flags.RIGHT_EYE_POLARITY =
+ dc_crtc_timing->flags.RIGHT_EYE_3D_POLARITY;
+ if (dc_crtc_timing->timing_3d_format ==
+ TIMING_3D_FORMAT_HW_FRAME_PACKING)
+ stereo_flags.FRAME_PACKED = 1;
+
+ if (is_frame_alternate_stereo(
+ dc_crtc_timing->timing_3d_format) ||
+ dc_crtc_timing->timing_3d_format ==
+ TIMING_3D_FORMAT_HW_FRAME_PACKING)
+ dcn10_enable_stereo(tg, &stereo_flags, dc_crtc_timing);
+ }
+}
+
+/**
+ * program_timing_generator used by mode timing set
+ * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
+ * Including SYNC. Call BIOS command table to program Timings.
+ */
+static void tg_program_timing_generator(
+ struct timing_generator *tg,
+ const struct dc_crtc_timing *dc_crtc_timing)
+{
+ struct dc_crtc_timing patched_crtc_timing;
+ uint32_t vesa_sync_start;
+ uint32_t asic_blank_end;
+ uint32_t asic_blank_start;
+ uint32_t v_total;
+ uint32_t v_sync_end;
+ uint32_t v_init, v_fp2;
+ uint32_t h_sync_polarity, v_sync_polarity;
+ uint32_t interlace_factor;
+ uint32_t start_point = 0;
+ uint32_t field_num = 0;
+ uint32_t h_div_2;
+
+
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ patched_crtc_timing = *dc_crtc_timing;
+ tg_apply_front_porch_workaround(tg, &patched_crtc_timing);
+
+ /* Load horizontal timing */
+
+ /* CRTC_H_TOTAL = vesa.h_total - 1 */
+ REG_SET(OTG_H_TOTAL, 0,
+ OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
+
+ /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
+ REG_UPDATE_2(OTG_H_SYNC_A,
+ OTG_H_SYNC_A_START, 0,
+ OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
+
+ /* asic_h_blank_end = HsyncWidth + HbackPorch =
+ * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart -
+ * vesa.h_left_border
+ */
+ vesa_sync_start = patched_crtc_timing.h_addressable +
+ patched_crtc_timing.h_border_right +
+ patched_crtc_timing.h_front_porch;
+
+ asic_blank_end = patched_crtc_timing.h_total -
+ vesa_sync_start -
+ patched_crtc_timing.h_border_left;
+
+ /* h_blank_start = v_blank_end + v_active */
+ asic_blank_start = asic_blank_end +
+ patched_crtc_timing.h_border_left +
+ patched_crtc_timing.h_addressable +
+ patched_crtc_timing.h_border_right;
+
+ REG_UPDATE_2(OTG_H_BLANK_START_END,
+ OTG_H_BLANK_START, asic_blank_start,
+ OTG_H_BLANK_END, asic_blank_end);
+
+ /* h_sync polarity */
+ h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
+ 0 : 1;
+
+ REG_UPDATE(OTG_H_SYNC_A_CNTL,
+ OTG_H_SYNC_A_POL, h_sync_polarity);
+
+ /* Load vertical timing */
+
+ /* CRTC_V_TOTAL = v_total - 1 */
+ if (patched_crtc_timing.flags.INTERLACE) {
+ interlace_factor = 2;
+ v_total = 2 * patched_crtc_timing.v_total;
+ } else {
+ interlace_factor = 1;
+ v_total = patched_crtc_timing.v_total - 1;
+ }
+ REG_SET(OTG_V_TOTAL, 0,
+ OTG_V_TOTAL, v_total);
+
+ /* v_sync_start = 0, v_sync_end = v_sync_width */
+ v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
+
+ REG_UPDATE_2(OTG_V_SYNC_A,
+ OTG_V_SYNC_A_START, 0,
+ OTG_V_SYNC_A_END, v_sync_end);
+
+ vesa_sync_start = patched_crtc_timing.v_addressable +
+ patched_crtc_timing.v_border_bottom +
+ patched_crtc_timing.v_front_porch;
+
+ asic_blank_end = (patched_crtc_timing.v_total -
+ vesa_sync_start -
+ patched_crtc_timing.v_border_top)
+ * interlace_factor;
+
+ /* v_blank_start = v_blank_end + v_active */
+ asic_blank_start = asic_blank_end +
+ (patched_crtc_timing.v_border_top +
+ patched_crtc_timing.v_addressable +
+ patched_crtc_timing.v_border_bottom)
+ * interlace_factor;
+
+ REG_UPDATE_2(OTG_V_BLANK_START_END,
+ OTG_V_BLANK_START, asic_blank_start,
+ OTG_V_BLANK_END, asic_blank_end);
+
+
+ /* v_sync polarity */
+ v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
+ 0 : 1;
+
+ REG_UPDATE(OTG_V_SYNC_A_CNTL,
+ OTG_V_SYNC_A_POL, v_sync_polarity);
+
+ v_init = asic_blank_start;
+ if (tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||
+ tg->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
+ tg->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {
+ v_init = asic_blank_start;
+ start_point = 1;
+ if (patched_crtc_timing.flags.INTERLACE == 1)
+ field_num = 1;
+ }
+ if (v_init < 0)
+ v_init = 0;
+ v_fp2 = 0;
+ if (tg->dlg_otg_param.vstartup_start > asic_blank_end)
+ v_fp2 = tg->dlg_otg_param.vstartup_start > asic_blank_end;
+
+ /* Interlace */
+ if (patched_crtc_timing.flags.INTERLACE == 1) {
+ REG_UPDATE(OTG_INTERLACE_CONTROL,
+ OTG_INTERLACE_ENABLE, 1);
+ v_init = v_init / 2;
+ if ((tg->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
+ v_fp2 = v_fp2 / 2;
+ }
+ else
+ REG_UPDATE(OTG_INTERLACE_CONTROL,
+ OTG_INTERLACE_ENABLE, 0);
+
+
+ /* VTG enable set to 0 first VInit */
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 0);
+
+ REG_UPDATE_2(CONTROL,
+ VTG0_FP2, v_fp2,
+ VTG0_VCOUNT_INIT, v_init);
+
+ /* original code is using VTG offset to address OTG reg, seems wrong */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_START_POINT_CNTL, start_point,
+ OTG_FIELD_NUMBER_CNTL, field_num);
+
+ dcn10_program_global_sync(tg);
+
+ /* TODO
+ * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
+ * program_horz_count_by_2
+ * for DVI 30bpp mode, 0 otherwise
+ * program_horz_count_by_2(tg, &patched_crtc_timing);
+ */
+
+ /* Enable stereo - only when we need to pack 3D frame. Other types
+ * of stereo handled in explicit call
+ */
+ h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ?
+ 1 : 0;
+
+ REG_UPDATE(OTG_H_TIMING_CNTL,
+ OTG_H_TIMING_DIV_BY2, h_div_2);
+
+ /* Enable crtc stereo frame pack tested... todo more
+ */
+ dcn10_do_stereo(tg, &patched_crtc_timing);
+}
+
+/** tg_program_blanking
+ * Only programmed part of OTG_H, OTG_V register for set_plane_config
+ * Assume other OTG registers are programmed by video mode set already.
+ * This function is for underlay. DCN will have new sequence.
+ * This function will be removed. Need remove it from set_plane_config
+ */
+
+static void tg_program_timing(struct timing_generator *tg,
+ const struct dc_crtc_timing *timing,
+ bool use_vbios)
+{
+ tg_program_timing_generator(tg, timing);
+}
+
+/**
+ * unblank_crtc
+ * Call ASIC Control Object to UnBlank CRTC.
+ */
+static void tg_unblank_crtc(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_UPDATE_2(OTG_BLANK_CONTROL,
+ OTG_BLANK_DATA_EN, 0,
+ OTG_BLANK_DE_MODE, 0);
+}
+
+/**
+ * blank_crtc
+ * Call ASIC Control Object to Blank CRTC.
+ */
+
+static void tg_blank_crtc(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_UPDATE_2(OTG_BLANK_CONTROL,
+ OTG_BLANK_DATA_EN, 1,
+ OTG_BLANK_DE_MODE, 0);
+
+ /* todo: why are we waiting for BLANK_DATA_EN? shouldn't we be waiting
+ * for status?
+ */
+ REG_WAIT(OTG_BLANK_CONTROL,
+ OTG_BLANK_DATA_EN, 1,
+ 20000, 200000);
+
+ REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
+ OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
+}
+
+static void tg_set_blank(struct timing_generator *tg,
+ bool enable_blanking)
+{
+ if (enable_blanking)
+ tg_blank_crtc(tg);
+ else
+ tg_unblank_crtc(tg);
+}
+
+static bool tg_is_blanked(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ uint32_t blank_en;
+ uint32_t blank_state;
+
+ REG_GET_2(OTG_BLANK_CONTROL,
+ OTG_BLANK_DATA_EN, &blank_en,
+ OTG_CURRENT_BLANK_STATE, &blank_state);
+
+ return blank_en && blank_state;
+}
+
+static void enable_optc_clock(struct timing_generator *tg, bool enable)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ if (enable) {
+ REG_UPDATE(OPTC_INPUT_CLOCK_CONTROL,
+ OPTC_INPUT_CLK_EN, 1);
+
+ REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
+ OPTC_INPUT_CLK_ON, 1,
+ 20000, 200000);
+
+ /* Enable clock */
+ REG_UPDATE(OTG_CLOCK_CONTROL,
+ OTG_CLOCK_EN, 1);
+
+ REG_WAIT(OTG_CLOCK_CONTROL,
+ OTG_CLOCK_ON, 1,
+ 20000, 200000);
+ } else {
+ REG_UPDATE_2(OTG_CLOCK_CONTROL,
+ OTG_CLOCK_GATE_DIS, 0,
+ OTG_CLOCK_EN, 0);
+
+ REG_WAIT(OTG_CLOCK_CONTROL,
+ OTG_CLOCK_ON, 0,
+ 20000, 200000);
+
+ REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
+ OPTC_INPUT_CLK_GATE_DIS, 0,
+ OPTC_INPUT_CLK_EN, 0);
+
+ REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
+ OPTC_INPUT_CLK_ON, 0,
+ 20000, 200000);
+ }
+}
+
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool tg_enable_crtc(struct timing_generator *tg)
+{
+ /* TODO FPGA wait for answer
+ * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
+ * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
+ */
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ /* opp instance for OTG. For DCN1.0, ODM is remoed.
+ * OPP and OPTC should 1:1 mapping
+ */
+ REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+ OPTC_SRC_SEL, tg->inst);
+
+ /* VTG enable first is for HW workaround */
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 1);
+
+ /* Enable CRTC */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_DISABLE_POINT_CNTL, 3,
+ OTG_MASTER_EN, 1);
+
+ return true;
+}
+
+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
+static bool tg_disable_crtc(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ /* disable otg request until end of the first line
+ * in the vertical blank region
+ */
+ REG_UPDATE_2(OTG_CONTROL,
+ OTG_DISABLE_POINT_CNTL, 3,
+ OTG_MASTER_EN, 0);
+
+ REG_UPDATE(CONTROL,
+ VTG0_ENABLE, 0);
+
+ /* CRTC disabled, so disable clock. */
+ REG_WAIT(OTG_CLOCK_CONTROL,
+ OTG_BUSY, 0,
+ 2000, 20000);
+
+ return true;
+}
+
+
+static void tg_program_blank_color(
+ struct timing_generator *tg,
+ const struct tg_color *black_color)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_SET_3(OTG_BLACK_COLOR, 0,
+ OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
+ OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
+ OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
+}
+
+/**
+ * dcn10_dcn10_timing_generator_disable_vga
+ * Turn OFF VGA Mode and Timing - DxVGA_CONTROL
+ * VGA Mode and VGA Timing is used by VBIOS on CRT Monitors;
+ */
+/* TODO FPGA FPGA setup is done by Diag which does not enable VGA mode.
+ * VGA is disable by ASIC default. This function is not needed for
+ * FPGA story.
+ * usage:
+ * init_hw within dc.c
+ * disable_vga_and_power_gate_all_controllers within dce110_hw_sequencer.c
+ * We may move init_hw into DC specific so that we can remove
+ * .disable_vga from upper layer stack
+ */
+static void dcn10_timing_generator_disable_vga(
+ struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ switch (tgn10->base.inst) {
+ case 0:
+ REG_WRITE(D1VGA_CONTROL, 0);
+ break;
+ case 1:
+ REG_WRITE(D2VGA_CONTROL, 0);
+ break;
+ case 2:
+ REG_WRITE(D2VGA_CONTROL, 0);
+ break;
+ case 3:
+ REG_WRITE(D4VGA_CONTROL, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+static bool tg_validate_timing(
+ struct timing_generator *tg,
+ const struct dc_crtc_timing *timing)
+{
+ uint32_t interlace_factor;
+ uint32_t v_blank;
+ uint32_t h_blank;
+ uint32_t min_v_blank;
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ ASSERT(timing != NULL);
+
+ interlace_factor = timing->flags.INTERLACE ? 2 : 1;
+ v_blank = (timing->v_total - timing->v_addressable -
+ timing->v_border_top - timing->v_border_bottom) *
+ interlace_factor;
+
+ h_blank = (timing->h_total - timing->h_addressable -
+ timing->h_border_right -
+ timing->h_border_left);
+
+ if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
+ timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
+ timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
+ timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
+ timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE)
+ return false;
+
+ /* Temporarily blocking interlacing mode until it's supported */
+ if (timing->flags.INTERLACE == 1)
+ return false;
+
+ /* Check maximum number of pixels supported by Timing Generator
+ * (Currently will never fail, in order to fail needs display which
+ * needs more than 8192 horizontal and
+ * more than 8192 vertical total pixels)
+ */
+ if (timing->h_total > tgn10->max_h_total ||
+ timing->v_total > tgn10->max_v_total)
+ return false;
+
+
+ if (h_blank < tgn10->min_h_blank)
+ return false;
+
+ if (timing->h_sync_width < tgn10->min_h_sync_width ||
+ timing->v_sync_width < tgn10->min_v_sync_width)
+ return false;
+
+ min_v_blank = timing->flags.INTERLACE?tgn10->min_v_blank_interlace:tgn10->min_v_blank;
+
+ if (v_blank < min_v_blank)
+ return false;
+
+ return true;
+
+}
+
+/*
+ * get_vblank_counter
+ *
+ * @brief
+ * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
+ * holds the counter of frames.
+ *
+ * @param
+ * struct timing_generator *tg - [in] timing generator which controls the
+ * desired CRTC
+ *
+ * @return
+ * Counter of frames, which should equal to number of vblanks.
+ */
+static uint32_t tg_get_vblank_counter(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ uint32_t frame_count;
+
+ REG_GET(OTG_STATUS_FRAME_COUNT,
+ OTG_FRAME_COUNT, &frame_count);
+
+ return frame_count;
+}
+
+void dcn10_lock(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+ OTG_MASTER_UPDATE_LOCK, 1);
+}
+
+void dcn10_unlock(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
+ OTG_MASTER_UPDATE_LOCK, 0);
+
+ /* why are we waiting here? */
+ REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL,
+ OTG_UPDATE_PENDING, 0,
+ 20000, 200000);
+}
+
+static void dcn10_get_position(struct timing_generator *tg,
+ struct crtc_position *position)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_GET_2(OTG_STATUS_POSITION,
+ OTG_HORZ_COUNT, &position->horizontal_count,
+ OTG_VERT_COUNT, &position->vertical_count);
+
+ REG_GET(OTG_NOM_VERT_POSITION,
+ OTG_VERT_COUNT_NOM, &position->nominal_vcount);
+}
+
+bool dcn10_is_counter_moving(struct timing_generator *tg)
+{
+ struct crtc_position position1, position2;
+
+ tg->funcs->get_position(tg, &position1);
+ tg->funcs->get_position(tg, &position2);
+
+ if (position1.horizontal_count == position2.horizontal_count &&
+ position1.vertical_count == position2.vertical_count)
+ return false;
+ else
+ return true;
+}
+
+static bool dcn10_did_triggered_reset_occur(
+ struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ uint32_t occurred;
+
+ REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
+ OTG_FORCE_COUNT_NOW_OCCURRED, &occurred);
+
+ return occurred != 0;
+}
+
+static void dcn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ uint32_t falling_edge;
+
+ REG_GET(OTG_V_SYNC_A_CNTL,
+ OTG_V_SYNC_A_POL, &falling_edge);
+
+ if (falling_edge)
+ REG_SET_3(OTG_TRIGA_CNTL, 0,
+ /* vsync signal from selected OTG pipe based
+ * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+ */
+ OTG_TRIGA_SOURCE_SELECT, 20,
+ OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+ /* always detect falling edge */
+ OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
+ else
+ REG_SET_3(OTG_TRIGA_CNTL, 0,
+ /* vsync signal from selected OTG pipe based
+ * on OTG_TRIG_SOURCE_PIPE_SELECT setting
+ */
+ OTG_TRIGA_SOURCE_SELECT, 20,
+ OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
+ /* always detect rising edge */
+ OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
+
+ REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+ /* force H count to H_TOTAL and V count to V_TOTAL in
+ * progressive mode and V_TOTAL-1 in interlaced mode
+ */
+ OTG_FORCE_COUNT_NOW_MODE, 2);
+}
+
+static void dcn10_disable_reset_trigger(struct timing_generator *tg)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ REG_WRITE(OTG_TRIGA_CNTL, 0);
+
+ REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
+ OTG_FORCE_COUNT_NOW_CLEAR, 1);
+}
+
+static void dcn10_wait_for_state(struct timing_generator *tg,
+ enum crtc_state state)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ switch (state) {
+ case CRTC_STATE_VBLANK:
+ REG_WAIT(OTG_STATUS,
+ OTG_V_BLANK, 1,
+ 100, 100000); /* 1 vupdate at 10hz */
+ break;
+
+ case CRTC_STATE_VACTIVE:
+ REG_WAIT(OTG_STATUS,
+ OTG_V_ACTIVE_DISP, 1,
+ 100, 100000); /* 1 vupdate at 10hz */
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void set_early_control(
+ struct timing_generator *tg,
+ uint32_t early_cntl)
+{
+ /* asic design change, do not need this control
+ * empty for share caller logic
+ */
+}
+
+
+static void set_static_screen_control(
+ struct timing_generator *tg,
+ uint32_t value)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ /* Bit 8 is no longer applicable in RV for PSR case,
+ * set bit 8 to 0 if given
+ */
+ if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
+ != 0)
+ value = value &
+ ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
+
+ REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
+ OTG_STATIC_SCREEN_EVENT_MASK, value,
+ OTG_STATIC_SCREEN_FRAME_COUNT, 2);
+}
+
+
+/**
+ *****************************************************************************
+ * Function: set_drr
+ *
+ * @brief
+ * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
+ *
+ *****************************************************************************
+ */
+void dcn10_timing_generator_set_drr(
+ struct timing_generator *tg,
+ const struct drr_params *params)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+
+ if (params != NULL &&
+ params->vertical_total_max > 0 &&
+ params->vertical_total_min > 0) {
+
+ REG_SET(OTG_V_TOTAL_MAX, 0,
+ OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
+
+ REG_SET(OTG_V_TOTAL_MIN, 0,
+ OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
+
+ REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
+ OTG_V_TOTAL_MIN_SEL, 1,
+ OTG_V_TOTAL_MAX_SEL, 1,
+ OTG_FORCE_LOCK_ON_EVENT, 0,
+ OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
+ OTG_SET_V_TOTAL_MIN_MASK, 0);
+ } else {
+ REG_SET(OTG_V_TOTAL_MIN, 0,
+ OTG_V_TOTAL_MIN, 0);
+
+ REG_SET(OTG_V_TOTAL_MAX, 0,
+ OTG_V_TOTAL_MAX, 0);
+
+ REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+ OTG_SET_V_TOTAL_MIN_MASK, 0,
+ OTG_V_TOTAL_MIN_SEL, 0,
+ OTG_V_TOTAL_MAX_SEL, 0,
+ OTG_FORCE_LOCK_ON_EVENT, 0);
+ }
+}
+
+static void dcn10_timing_generator_set_test_pattern(
+ struct timing_generator *tg,
+ /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
+ * because this is not DP-specific (which is probably somewhere in DP
+ * encoder) */
+ enum controller_dp_test_pattern test_pattern,
+ enum dc_color_depth color_depth)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ enum test_pattern_color_format bit_depth;
+ enum test_pattern_dyn_range dyn_range;
+ enum test_pattern_mode mode;
+ uint32_t pattern_mask;
+ uint32_t pattern_data;
+ /* color ramp generator mixes 16-bits color */
+ uint32_t src_bpc = 16;
+ /* requested bpc */
+ uint32_t dst_bpc;
+ uint32_t index;
+ /* RGB values of the color bars.
+ * Produce two RGB colors: RGB0 - white (all Fs)
+ * and RGB1 - black (all 0s)
+ * (three RGB components for two colors)
+ */
+ uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
+ 0x0000, 0x0000};
+ /* dest color (converted to the specified color format) */
+ uint16_t dst_color[6];
+ uint32_t inc_base;
+
+ /* translate to bit depth */
+ switch (color_depth) {
+ case COLOR_DEPTH_666:
+ bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
+ break;
+ case COLOR_DEPTH_888:
+ bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
+ break;
+ case COLOR_DEPTH_101010:
+ bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
+ break;
+ case COLOR_DEPTH_121212:
+ bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
+ break;
+ default:
+ bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
+ break;
+ }
+
+ switch (test_pattern) {
+ case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
+ case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
+ {
+ dyn_range = (test_pattern ==
+ CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
+ TEST_PATTERN_DYN_RANGE_CEA :
+ TEST_PATTERN_DYN_RANGE_VESA);
+ mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
+
+ REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
+ OTG_TEST_PATTERN_VRES, 6,
+ OTG_TEST_PATTERN_HRES, 6);
+
+ REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
+ OTG_TEST_PATTERN_EN, 1,
+ OTG_TEST_PATTERN_MODE, mode,
+ OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
+ OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+ }
+ break;
+
+ case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
+ case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
+ {
+ mode = (test_pattern ==
+ CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
+ TEST_PATTERN_MODE_VERTICALBARS :
+ TEST_PATTERN_MODE_HORIZONTALBARS);
+
+ switch (bit_depth) {
+ case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+ dst_bpc = 6;
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+ dst_bpc = 8;
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+ dst_bpc = 10;
+ break;
+ default:
+ dst_bpc = 8;
+ break;
+ }
+
+ /* adjust color to the required colorFormat */
+ for (index = 0; index < 6; index++) {
+ /* dst = 2^dstBpc * src / 2^srcBpc = src >>
+ * (srcBpc - dstBpc);
+ */
+ dst_color[index] =
+ src_color[index] >> (src_bpc - dst_bpc);
+ /* CRTC_TEST_PATTERN_DATA has 16 bits,
+ * lowest 6 are hardwired to ZERO
+ * color bits should be left aligned aligned to MSB
+ * XXXXXXXXXX000000 for 10 bit,
+ * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
+ */
+ dst_color[index] <<= (16 - dst_bpc);
+ }
+
+ REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
+
+ /* We have to write the mask before data, similar to pipeline.
+ * For example, for 8 bpc, if we want RGB0 to be magenta,
+ * and RGB1 to be cyan,
+ * we need to make 7 writes:
+ * MASK DATA
+ * 000001 00000000 00000000 set mask to R0
+ * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
+ * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
+ * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
+ * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
+ * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
+ * 100000 11111111 00000000 B1 255, 0xFF00
+ *
+ * we will make a loop of 6 in which we prepare the mask,
+ * then write, then prepare the color for next write.
+ * first iteration will write mask only,
+ * but each next iteration color prepared in
+ * previous iteration will be written within new mask,
+ * the last component will written separately,
+ * mask is not changing between 6th and 7th write
+ * and color will be prepared by last iteration
+ */
+
+ /* write color, color values mask in CRTC_TEST_PATTERN_MASK
+ * is B1, G1, R1, B0, G0, R0
+ */
+ pattern_data = 0;
+ for (index = 0; index < 6; index++) {
+ /* prepare color mask, first write PATTERN_DATA
+ * will have all zeros
+ */
+ pattern_mask = (1 << index);
+
+ /* write color component */
+ REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
+ OTG_TEST_PATTERN_MASK, pattern_mask,
+ OTG_TEST_PATTERN_DATA, pattern_data);
+
+ /* prepare next color component,
+ * will be written in the next iteration
+ */
+ pattern_data = dst_color[index];
+ }
+ /* write last color component,
+ * it's been already prepared in the loop
+ */
+ REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
+ OTG_TEST_PATTERN_MASK, pattern_mask,
+ OTG_TEST_PATTERN_DATA, pattern_data);
+
+ /* enable test pattern */
+ REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
+ OTG_TEST_PATTERN_EN, 1,
+ OTG_TEST_PATTERN_MODE, mode,
+ OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
+ OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+ }
+ break;
+
+ case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
+ {
+ mode = (bit_depth ==
+ TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
+ TEST_PATTERN_MODE_DUALRAMP_RGB :
+ TEST_PATTERN_MODE_SINGLERAMP_RGB);
+
+ switch (bit_depth) {
+ case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+ dst_bpc = 6;
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+ dst_bpc = 8;
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+ dst_bpc = 10;
+ break;
+ default:
+ dst_bpc = 8;
+ break;
+ }
+
+ /* increment for the first ramp for one color gradation
+ * 1 gradation for 6-bit color is 2^10
+ * gradations in 16-bit color
+ */
+ inc_base = (src_bpc - dst_bpc);
+
+ switch (bit_depth) {
+ case TEST_PATTERN_COLOR_FORMAT_BPC_6:
+ {
+ REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+ OTG_TEST_PATTERN_INC0, inc_base,
+ OTG_TEST_PATTERN_INC1, 0,
+ OTG_TEST_PATTERN_HRES, 6,
+ OTG_TEST_PATTERN_VRES, 6,
+ OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
+ }
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_8:
+ {
+ REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+ OTG_TEST_PATTERN_INC0, inc_base,
+ OTG_TEST_PATTERN_INC1, 0,
+ OTG_TEST_PATTERN_HRES, 8,
+ OTG_TEST_PATTERN_VRES, 6,
+ OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
+ }
+ break;
+ case TEST_PATTERN_COLOR_FORMAT_BPC_10:
+ {
+ REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
+ OTG_TEST_PATTERN_INC0, inc_base,
+ OTG_TEST_PATTERN_INC1, inc_base + 2,
+ OTG_TEST_PATTERN_HRES, 8,
+ OTG_TEST_PATTERN_VRES, 5,
+ OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
+ }
+ break;
+ default:
+ break;
+ }
+
+ REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
+
+ /* enable test pattern */
+ REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
+
+ REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
+ OTG_TEST_PATTERN_EN, 1,
+ OTG_TEST_PATTERN_MODE, mode,
+ OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
+ OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
+ }
+ break;
+ case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
+ {
+ REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
+ REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
+ REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
+ }
+ break;
+ default:
+ break;
+
+ }
+}
+
+void dcn10_timing_generator_get_crtc_scanoutpos(
+ struct timing_generator *tg,
+ uint32_t *v_blank_start,
+ uint32_t *v_blank_end,
+ uint32_t *h_position,
+ uint32_t *v_position)
+{
+ struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+ struct crtc_position position;
+
+ REG_GET_2(OTG_V_BLANK_START_END,
+ OTG_V_BLANK_START, v_blank_start,
+ OTG_V_BLANK_END, v_blank_end);
+
+ dcn10_get_position(tg, &position);
+
+ *h_position = position.horizontal_count;
+ *v_position = position.vertical_count;
+}
+
+static struct timing_generator_funcs dcn10_tg_funcs = {
+ .validate_timing = tg_validate_timing,
+ .program_timing = tg_program_timing,
+ .program_global_sync = dcn10_program_global_sync,
+ .enable_crtc = tg_enable_crtc,
+ .disable_crtc = tg_disable_crtc,
+ /* used by enable_timing_synchronization. Not need for FPGA */
+ .is_counter_moving = dcn10_is_counter_moving,
+ /* never be called */
+ .get_position = dcn10_get_position,
+ .get_frame_count = tg_get_vblank_counter,
+ .get_scanoutpos = dcn10_timing_generator_get_crtc_scanoutpos,
+ .set_early_control = set_early_control,
+ /* used by enable_timing_synchronization. Not need for FPGA */
+ .wait_for_state = dcn10_wait_for_state,
+ .set_blank = tg_set_blank,
+ .is_blanked = tg_is_blanked,
+ /* never be called */
+ .set_colors = NULL,
+ /* this function will be called by .progam_scaler. dcn and dce
+ * scaler top level functions are different. .program_scaler is
+ * not need for dcn. within program_scaler, dcn will return
+ * early before set_overscan_blank_color is reached
+ */
+ .set_overscan_blank_color = NULL,
+ .set_blank_color = tg_program_blank_color,
+ /* dcn10_timing_generator_disable_vga */
+ .disable_vga = dcn10_timing_generator_disable_vga,
+ .did_triggered_reset_occur = dcn10_did_triggered_reset_occur,
+ .enable_reset_trigger = dcn10_enable_reset_trigger,
+ .disable_reset_trigger = dcn10_disable_reset_trigger,
+ .lock = dcn10_lock,
+ .unlock = dcn10_unlock,
+ /* dcn10_timing_generator_enable_advanced_request*/
+ .enable_advanced_request = NULL,
+ .enable_optc_clock = enable_optc_clock,
+ .set_drr = dcn10_timing_generator_set_drr,
+ .set_static_screen_control = set_static_screen_control,
+ .set_test_pattern = dcn10_timing_generator_set_test_pattern
+};
+
+void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10)
+{
+ tgn10->base.funcs = &dcn10_tg_funcs;
+
+ tgn10->max_h_total = tgn10->tg_mask->OTG_H_TOTAL + 1;
+ tgn10->max_v_total = tgn10->tg_mask->OTG_V_TOTAL + 1;
+
+ tgn10->min_h_blank = 32;
+ tgn10->min_v_blank = 3;
+ tgn10->min_v_blank_interlace = 5;
+ tgn10->min_h_sync_width = 8;
+ tgn10->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
new file mode 100644
index 0000000..85a763a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_TIMING_GENERATOR_DCN10_H__
+#define __DC_TIMING_GENERATOR_DCN10_H__
+
+#include "timing_generator.h"
+
+#define DCN10TG_FROM_TG(tg)\
+ container_of(tg, struct dcn10_timing_generator, base)
+
+#define TG_COMMON_REG_LIST_DCN1_0(inst) \
+ SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+ SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+ SRI(OTG_VREADY_PARAM, OTG, inst),\
+ SRI(OTG_BLANK_CONTROL, OTG, inst),\
+ SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+ SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+ SRI(OTG_H_TOTAL, OTG, inst),\
+ SRI(OTG_H_BLANK_START_END, OTG, inst),\
+ SRI(OTG_H_SYNC_A, OTG, inst),\
+ SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+ SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+ SRI(OTG_V_TOTAL, OTG, inst),\
+ SRI(OTG_V_BLANK_START_END, OTG, inst),\
+ SRI(OTG_V_SYNC_A, OTG, inst),\
+ SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+ SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
+ SRI(OTG_CONTROL, OTG, inst),\
+ SRI(OTG_STEREO_CONTROL, OTG, inst),\
+ SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+ SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+ SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+ SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+ SRI(OTG_TRIGA_CNTL, OTG, inst),\
+ SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+ SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+ SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+ SRI(OTG_STATUS, OTG, inst),\
+ SRI(OTG_STATUS_POSITION, OTG, inst),\
+ SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+ SRI(OTG_BLACK_COLOR, OTG, inst),\
+ SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
+ SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
+ SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
+ SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+ SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+ SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+ SRI(OPPBUF_CONTROL, OPPBUF, inst),\
+ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\
+ SRI(CONTROL, VTG, inst),\
+ SR(D1VGA_CONTROL),\
+ SR(D2VGA_CONTROL),\
+ SR(D3VGA_CONTROL),\
+ SR(D4VGA_CONTROL),\
+
+struct dcn_tg_registers {
+ uint32_t OTG_VSTARTUP_PARAM;
+ uint32_t OTG_VUPDATE_PARAM;
+ uint32_t OTG_VREADY_PARAM;
+ uint32_t OTG_BLANK_CONTROL;
+ uint32_t OTG_MASTER_UPDATE_LOCK;
+ uint32_t OTG_DOUBLE_BUFFER_CONTROL;
+ uint32_t OTG_H_TOTAL;
+ uint32_t OTG_H_BLANK_START_END;
+ uint32_t OTG_H_SYNC_A;
+ uint32_t OTG_H_SYNC_A_CNTL;
+ uint32_t OTG_H_TIMING_CNTL;
+ uint32_t OTG_V_TOTAL;
+ uint32_t OTG_V_BLANK_START_END;
+ uint32_t OTG_V_SYNC_A;
+ uint32_t OTG_V_SYNC_A_CNTL;
+ uint32_t OTG_INTERLACE_CONTROL;
+ uint32_t OTG_CONTROL;
+ uint32_t OTG_STEREO_CONTROL;
+ uint32_t OTG_3D_STRUCTURE_CONTROL;
+ uint32_t OTG_V_TOTAL_MAX;
+ uint32_t OTG_V_TOTAL_MIN;
+ uint32_t OTG_V_TOTAL_CONTROL;
+ uint32_t OTG_TRIGA_CNTL;
+ uint32_t OTG_FORCE_COUNT_NOW_CNTL;
+ uint32_t OTG_STATIC_SCREEN_CONTROL;
+ uint32_t OTG_STATUS_FRAME_COUNT;
+ uint32_t OTG_STATUS;
+ uint32_t OTG_STATUS_POSITION;
+ uint32_t OTG_NOM_VERT_POSITION;
+ uint32_t OTG_BLACK_COLOR;
+ uint32_t OTG_TEST_PATTERN_PARAMETERS;
+ uint32_t OTG_TEST_PATTERN_CONTROL;
+ uint32_t OTG_TEST_PATTERN_COLOR;
+ uint32_t OTG_CLOCK_CONTROL;
+ uint32_t OPTC_INPUT_CLOCK_CONTROL;
+ uint32_t OPTC_DATA_SOURCE_SELECT;
+ uint32_t OPPBUF_CONTROL;
+ uint32_t OPPBUF_3D_PARAMETERS_0;
+ uint32_t CONTROL;
+ /*todo: move VGA to HWSS */
+ uint32_t D1VGA_CONTROL;
+ uint32_t D2VGA_CONTROL;
+ uint32_t D3VGA_CONTROL;
+ uint32_t D4VGA_CONTROL;
+};
+
+#define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
+ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+ SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+ SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+ SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+ SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
+ SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
+ SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
+ SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
+ SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+ SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+ SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+ SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+ SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+ SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+ SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+ SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+ SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+ SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+ SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+ SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
+ SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+ SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+ SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+ SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+ SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+ SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+ SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+ SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
+ SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+ SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+ SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+ SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+ SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+ SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+ SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+ SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+ SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+ SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
+ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
+ SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
+ SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
+ SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+ SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+ SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+ SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+ SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
+ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
+ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\
+ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+
+#define TG_REG_FIELD_LIST(type) \
+ type VSTARTUP_START;\
+ type VUPDATE_OFFSET;\
+ type VUPDATE_WIDTH;\
+ type VREADY_OFFSET;\
+ type OTG_BLANK_DATA_EN;\
+ type OTG_BLANK_DE_MODE;\
+ type OTG_CURRENT_BLANK_STATE;\
+ type OTG_MASTER_UPDATE_LOCK;\
+ type OTG_UPDATE_PENDING;\
+ type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
+ type OTG_H_TOTAL;\
+ type OTG_H_BLANK_START;\
+ type OTG_H_BLANK_END;\
+ type OTG_H_SYNC_A_START;\
+ type OTG_H_SYNC_A_END;\
+ type OTG_H_SYNC_A_POL;\
+ type OTG_H_TIMING_DIV_BY2;\
+ type OTG_V_TOTAL;\
+ type OTG_V_BLANK_START;\
+ type OTG_V_BLANK_END;\
+ type OTG_V_SYNC_A_START;\
+ type OTG_V_SYNC_A_END;\
+ type OTG_V_SYNC_A_POL;\
+ type OTG_INTERLACE_ENABLE;\
+ type OTG_MASTER_EN;\
+ type OTG_START_POINT_CNTL;\
+ type OTG_DISABLE_POINT_CNTL;\
+ type OTG_FIELD_NUMBER_CNTL;\
+ type OTG_STEREO_EN;\
+ type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
+ type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
+ type OTG_STEREO_EYE_FLAG_POLARITY;\
+ type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
+ type OTG_3D_STRUCTURE_EN;\
+ type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
+ type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
+ type OTG_V_TOTAL_MAX;\
+ type OTG_V_TOTAL_MIN;\
+ type OTG_V_TOTAL_MIN_SEL;\
+ type OTG_V_TOTAL_MAX_SEL;\
+ type OTG_FORCE_LOCK_ON_EVENT;\
+ type OTG_SET_V_TOTAL_MIN_MASK_EN;\
+ type OTG_SET_V_TOTAL_MIN_MASK;\
+ type OTG_FORCE_COUNT_NOW_CLEAR;\
+ type OTG_FORCE_COUNT_NOW_MODE;\
+ type OTG_FORCE_COUNT_NOW_OCCURRED;\
+ type OTG_TRIGA_SOURCE_SELECT;\
+ type OTG_TRIGA_SOURCE_PIPE_SELECT;\
+ type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
+ type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
+ type OTG_STATIC_SCREEN_EVENT_MASK;\
+ type OTG_STATIC_SCREEN_FRAME_COUNT;\
+ type OTG_FRAME_COUNT;\
+ type OTG_V_BLANK;\
+ type OTG_V_ACTIVE_DISP;\
+ type OTG_HORZ_COUNT;\
+ type OTG_VERT_COUNT;\
+ type OTG_VERT_COUNT_NOM;\
+ type OTG_BLACK_COLOR_B_CB;\
+ type OTG_BLACK_COLOR_G_Y;\
+ type OTG_BLACK_COLOR_R_CR;\
+ type OTG_TEST_PATTERN_INC0;\
+ type OTG_TEST_PATTERN_INC1;\
+ type OTG_TEST_PATTERN_VRES;\
+ type OTG_TEST_PATTERN_HRES;\
+ type OTG_TEST_PATTERN_RAMP0_OFFSET;\
+ type OTG_TEST_PATTERN_EN;\
+ type OTG_TEST_PATTERN_MODE;\
+ type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
+ type OTG_TEST_PATTERN_COLOR_FORMAT;\
+ type OTG_TEST_PATTERN_MASK;\
+ type OTG_TEST_PATTERN_DATA;\
+ type OTG_BUSY;\
+ type OTG_CLOCK_EN;\
+ type OTG_CLOCK_ON;\
+ type OTG_CLOCK_GATE_DIS;\
+ type OPTC_INPUT_CLK_EN;\
+ type OPTC_INPUT_CLK_ON;\
+ type OPTC_INPUT_CLK_GATE_DIS;\
+ type OPTC_SRC_SEL;\
+ type OPPBUF_ACTIVE_WIDTH;\
+ type OPPBUF_3D_VACT_SPACE1_SIZE;\
+ type VTG0_ENABLE;\
+ type VTG0_FP2;\
+ type VTG0_VCOUNT_INIT;\
+
+struct dcn_tg_shift {
+ TG_REG_FIELD_LIST(uint8_t)
+};
+
+struct dcn_tg_mask {
+ TG_REG_FIELD_LIST(uint32_t)
+};
+
+struct dcn10_timing_generator {
+ struct timing_generator base;
+
+ const struct dcn_tg_registers *tg_regs;
+ const struct dcn_tg_shift *tg_shift;
+ const struct dcn_tg_mask *tg_mask;
+
+ enum controller_id controller_id;
+
+ uint32_t max_h_total;
+ uint32_t max_v_total;
+
+ uint32_t min_h_blank;
+
+ uint32_t min_h_sync_width;
+ uint32_t min_v_sync_width;
+ uint32_t min_v_blank;
+ uint32_t min_v_blank_interlace;
+};
+
+void dcn10_timing_generator_init(struct dcn10_timing_generator *tg);
+
+void dcn10_timing_generator_set_drr(struct timing_generator *tg,
+ const struct drr_params *params);
+
+void dcn10_unlock(struct timing_generator *tg);
+void dcn10_lock(struct timing_generator *tg);
+#endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
new file mode 100644
index 0000000..3718fb5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "core_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/fixed31_32.h"
+#include "include/logger_interface.h"
+
+#include "reg_helper.h"
+#include "dcn10_transform.h"
+#include "basics/conversion.h"
+
+#define NUM_PHASES 64
+#define HORZ_MAX_TAPS 8
+#define VERT_MAX_TAPS 8
+
+#define BLACK_OFFSET_RGB_Y 0x0
+#define BLACK_OFFSET_CBCR 0x8000
+
+#define REG(reg)\
+ xfm->tf_regs->reg
+
+#define CTX \
+ xfm->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ xfm->tf_shift->field_name, xfm->tf_mask->field_name
+
+
+enum dcn10_coef_filter_type_sel {
+ SCL_COEF_LUMA_VERT_FILTER = 0,
+ SCL_COEF_LUMA_HORZ_FILTER = 1,
+ SCL_COEF_CHROMA_VERT_FILTER = 2,
+ SCL_COEF_CHROMA_HORZ_FILTER = 3,
+ SCL_COEF_ALPHA_VERT_FILTER = 4,
+ SCL_COEF_ALPHA_HORZ_FILTER = 5
+};
+
+enum lb_memory_config {
+ /* Enable all 3 pieces of memory */
+ LB_MEMORY_CONFIG_0 = 0,
+
+ /* Enable only the first piece of memory */
+ LB_MEMORY_CONFIG_1 = 1,
+
+ /* Enable only the second piece of memory */
+ LB_MEMORY_CONFIG_2 = 2,
+
+ /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the
+ * last piece of chroma memory used for the luma storage
+ */
+ LB_MEMORY_CONFIG_3 = 3
+};
+
+enum dscl_autocal_mode {
+ AUTOCAL_MODE_OFF = 0,
+
+ /* Autocal calculate the scaling ratio and initial phase and the
+ * DSCL_MODE_SEL must be set to 1
+ */
+ AUTOCAL_MODE_AUTOSCALE = 1,
+ /* Autocal perform auto centering without replication and the
+ * DSCL_MODE_SEL must be set to 0
+ */
+ AUTOCAL_MODE_AUTOCENTER = 2,
+ /* Autocal perform auto centering and auto replication and the
+ * DSCL_MODE_SEL must be set to 0
+ */
+ AUTOCAL_MODE_AUTOREPLICATE = 3
+};
+
+enum dscl_mode_sel {
+ DSCL_MODE_SCALING_444_BYPASS = 0,
+ DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
+ DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
+ DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
+ DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
+ DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
+ DSCL_MODE_DSCL_BYPASS = 6
+};
+
+enum gamut_remap_select {
+ GAMUT_REMAP_BYPASS = 0,
+ GAMUT_REMAP_COEFF,
+ GAMUT_REMAP_COMA_COEFF,
+ GAMUT_REMAP_COMB_COEFF
+};
+
+static void transform_set_overscan(
+ struct dcn10_transform *xfm,
+ const struct scaler_data *data)
+{
+ uint32_t left = data->recout.x;
+ uint32_t top = data->recout.y;
+
+ int right = data->h_active - data->recout.x - data->recout.width;
+ int bottom = data->v_active - data->recout.y - data->recout.height;
+
+ if (right < 0) {
+ BREAK_TO_DEBUGGER();
+ right = 0;
+ }
+ if (bottom < 0) {
+ BREAK_TO_DEBUGGER();
+ bottom = 0;
+ }
+
+ REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
+ EXT_OVERSCAN_LEFT, left,
+ EXT_OVERSCAN_RIGHT, right);
+
+ REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
+ EXT_OVERSCAN_BOTTOM, bottom,
+ EXT_OVERSCAN_TOP, top);
+}
+
+static void transform_set_otg_blank(
+ struct dcn10_transform *xfm, const struct scaler_data *data)
+{
+ uint32_t h_blank_start = data->h_active;
+ uint32_t h_blank_end = 0;
+ uint32_t v_blank_start = data->v_active;
+ uint32_t v_blank_end = 0;
+
+ REG_SET_2(OTG_H_BLANK, 0,
+ OTG_H_BLANK_START, h_blank_start,
+ OTG_H_BLANK_END, h_blank_end);
+
+ REG_SET_2(OTG_V_BLANK, 0,
+ OTG_V_BLANK_START, v_blank_start,
+ OTG_V_BLANK_END, v_blank_end);
+}
+
+static enum dscl_mode_sel get_dscl_mode(const struct scaler_data *data)
+{
+ const long long one = dal_fixed31_32_one.value;
+ bool ycbcr = false;
+ bool format420 = false;
+
+ if (data->format == PIXEL_FORMAT_FP16)
+ return DSCL_MODE_DSCL_BYPASS;
+
+ if (data->format >= PIXEL_FORMAT_VIDEO_BEGIN
+ && data->format <= PIXEL_FORMAT_VIDEO_END)
+ ycbcr = true;
+
+ if (data->format == PIXEL_FORMAT_420BPP12 ||
+ data->format == PIXEL_FORMAT_420BPP15)
+ format420 = true;
+
+ if (data->ratios.horz.value == one
+ && data->ratios.vert.value == one
+ && data->ratios.horz_c.value == one
+ && data->ratios.vert_c.value == one)
+ return DSCL_MODE_SCALING_444_BYPASS;
+
+ if (!format420) {
+ if (ycbcr)
+ return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
+ else
+ return DSCL_MODE_SCALING_444_RGB_ENABLE;
+ }
+ if (data->ratios.horz.value == one && data->ratios.vert.value == one)
+ return DSCL_MODE_SCALING_420_LUMA_BYPASS;
+ if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
+ return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
+
+ return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
+}
+
+static int get_pixel_depth_val(enum lb_pixel_depth depth)
+{
+ if (depth == LB_PIXEL_DEPTH_30BPP)
+ return 0; /* 10 bpc */
+ else if (depth == LB_PIXEL_DEPTH_24BPP)
+ return 1; /* 8 bpc */
+ else if (depth == LB_PIXEL_DEPTH_18BPP)
+ return 2; /* 6 bpc */
+ else if (depth == LB_PIXEL_DEPTH_36BPP)
+ return 3; /* 12 bpc */
+ else {
+ ASSERT(0);
+ return -1; /* Unsupported */
+ }
+}
+
+static void transform_set_lb(
+ struct dcn10_transform *xfm,
+ const struct line_buffer_params *lb_params,
+ enum lb_memory_config mem_size_config)
+{
+ uint32_t pixel_depth = get_pixel_depth_val(lb_params->depth);
+ uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
+ REG_SET_7(LB_DATA_FORMAT, 0,
+ PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
+ PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
+ PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
+ DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
+ DITHER_EN, 0, /* Dithering enable: Disabled */
+ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
+ ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
+
+ REG_SET_2(LB_MEMORY_CTRL, 0,
+ MEMORY_CONFIG, mem_size_config,
+ LB_MAX_PARTITIONS, 63);
+}
+
+static void transform_set_scaler_filter(
+ struct dcn10_transform *xfm,
+ uint32_t taps,
+ enum dcn10_coef_filter_type_sel filter_type,
+ const uint16_t *filter)
+{
+ const int tap_pairs = (taps + 1) / 2;
+ int phase;
+ int pair;
+ uint16_t odd_coef, even_coef;
+
+ REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
+ SCL_COEF_RAM_TAP_PAIR_IDX, 0,
+ SCL_COEF_RAM_PHASE, 0,
+ SCL_COEF_RAM_FILTER_TYPE, filter_type);
+
+ for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
+ for (pair = 0; pair < tap_pairs; pair++) {
+ even_coef = filter[phase * taps + 2 * pair];
+ if ((pair * 2 + 1) < taps)
+ odd_coef = filter[phase * taps + 2 * pair + 1];
+ else
+ odd_coef = 0;
+
+ REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
+ /* Even tap coefficient (bits 1:0 fixed to 0) */
+ SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
+ /* Write/read control for even coefficient */
+ SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
+ /* Odd tap coefficient (bits 1:0 fixed to 0) */
+ SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
+ /* Write/read control for odd coefficient */
+ SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
+ }
+ }
+
+}
+
+#if 0
+bool transform_set_pixel_storage_depth(
+ struct transform *xfm,
+ enum lb_pixel_depth depth,
+ const struct bit_depth_reduction_params *bit_depth_params)
+{
+ struct dcn10_transform *xfm110 = TO_DCN10_TRANSFORM(xfm);
+ bool ret = true;
+ uint32_t value;
+ enum dc_color_depth color_depth;
+
+ value = dm_read_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT));
+ switch (depth) {
+ case LB_PIXEL_DEPTH_18BPP:
+ color_depth = COLOR_DEPTH_666;
+ set_reg_field_value(value, 2, LB_DATA_FORMAT, PIXEL_DEPTH);
+ set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ break;
+ case LB_PIXEL_DEPTH_24BPP:
+ color_depth = COLOR_DEPTH_888;
+ set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_DEPTH);
+ set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ break;
+ case LB_PIXEL_DEPTH_30BPP:
+ color_depth = COLOR_DEPTH_101010;
+ set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_DEPTH);
+ set_reg_field_value(value, 1, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ break;
+ case LB_PIXEL_DEPTH_36BPP:
+ color_depth = COLOR_DEPTH_121212;
+ set_reg_field_value(value, 3, LB_DATA_FORMAT, PIXEL_DEPTH);
+ set_reg_field_value(value, 0, LB_DATA_FORMAT, PIXEL_EXPAN_MODE);
+ break;
+ default:
+ ret = false;
+ break;
+ }
+
+ if (ret == true) {
+ set_denormalization(xfm110, color_depth);
+ ret = program_bit_depth_reduction(xfm110, color_depth,
+ bit_depth_params);
+
+ set_reg_field_value(value, 0, LB_DATA_FORMAT, ALPHA_EN);
+ dm_write_reg(xfm->ctx, LB_REG(mmLB_DATA_FORMAT), value);
+ if (!(xfm110->lb_pixel_depth_supported & depth)) {
+ /* We should use unsupported capabilities
+ * unless it is required by w/a
+ */
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
+ "%s: Capability not supported",
+ __func__);
+ }
+ }
+
+ return ret;
+}
+#endif
+
+static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
+{
+ if (taps == 8)
+ return get_filter_8tap_64p(ratio);
+ else if (taps == 7)
+ return get_filter_7tap_64p(ratio);
+ else if (taps == 6)
+ return get_filter_6tap_64p(ratio);
+ else if (taps == 5)
+ return get_filter_5tap_64p(ratio);
+ else if (taps == 4)
+ return get_filter_4tap_64p(ratio);
+ else if (taps == 3)
+ return get_filter_3tap_64p(ratio);
+ else if (taps == 2)
+ return filter_2tap_64p;
+ else if (taps == 1)
+ return NULL;
+ else {
+ /* should never happen, bug */
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+}
+
+static void transform_set_scl_filter(
+ struct dcn10_transform *xfm,
+ const struct scaler_data *scl_data,
+ bool chroma_coef_mode)
+{
+ bool h_2tap_hardcode_coef_en = false;
+ bool v_2tap_hardcode_coef_en = false;
+ bool h_2tap_sharp_en = false;
+ bool v_2tap_sharp_en = false;
+ uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
+ uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
+ bool coef_ram_current;
+ const uint16_t *filter_h = NULL;
+ const uint16_t *filter_v = NULL;
+ const uint16_t *filter_h_c = NULL;
+ const uint16_t *filter_v_c = NULL;
+
+ h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
+ && scl_data->taps.h_taps_c < 3
+ && (scl_data->taps.h_taps > 1 || scl_data->taps.h_taps_c > 1);
+ v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
+ && scl_data->taps.v_taps_c < 3
+ && (scl_data->taps.v_taps > 1 || scl_data->taps.v_taps_c > 1);
+
+ h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
+ v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
+
+ REG_UPDATE_6(DSCL_2TAP_CONTROL,
+ SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
+ SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
+ SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
+ SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
+ SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
+ SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
+
+ if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
+ bool filter_updated = false;
+
+ filter_h = get_filter_coeffs_64p(
+ scl_data->taps.h_taps, scl_data->ratios.horz);
+ filter_v = get_filter_coeffs_64p(
+ scl_data->taps.v_taps, scl_data->ratios.vert);
+
+ filter_updated = (filter_h && (filter_h != xfm->filter_h))
+ || (filter_v && (filter_v != xfm->filter_v));
+
+ if (chroma_coef_mode) {
+ filter_h_c = get_filter_coeffs_64p(
+ scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
+ filter_v_c = get_filter_coeffs_64p(
+ scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
+ filter_updated = filter_updated || (filter_h_c && (filter_h_c != xfm->filter_h_c))
+ || (filter_v_c && (filter_v_c != xfm->filter_v_c));
+ }
+
+ if (filter_updated) {
+ uint32_t scl_mode = REG_READ(SCL_MODE);
+
+ if (!h_2tap_hardcode_coef_en && filter_h) {
+ transform_set_scaler_filter(
+ xfm, scl_data->taps.h_taps,
+ SCL_COEF_LUMA_HORZ_FILTER, filter_h);
+ }
+ xfm->filter_h = filter_h;
+ if (!v_2tap_hardcode_coef_en && filter_v) {
+ transform_set_scaler_filter(
+ xfm, scl_data->taps.v_taps,
+ SCL_COEF_LUMA_VERT_FILTER, filter_v);
+ }
+ xfm->filter_v = filter_v;
+ if (chroma_coef_mode) {
+ if (!h_2tap_hardcode_coef_en && filter_h_c) {
+ transform_set_scaler_filter(
+ xfm, scl_data->taps.h_taps_c,
+ SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
+ }
+ if (!v_2tap_hardcode_coef_en && filter_v_c) {
+ transform_set_scaler_filter(
+ xfm, scl_data->taps.v_taps_c,
+ SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
+ }
+ }
+ xfm->filter_h_c = filter_h_c;
+ xfm->filter_v_c = filter_v_c;
+
+ coef_ram_current = get_reg_field_value_ex(
+ scl_mode, xfm->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
+ xfm->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
+
+ /* Swap coefficient RAM and set chroma coefficient mode */
+ REG_SET_2(SCL_MODE, scl_mode,
+ SCL_COEF_RAM_SELECT, !coef_ram_current,
+ SCL_CHROMA_COEF_MODE, chroma_coef_mode);
+ }
+ }
+}
+
+static void transform_set_viewport(
+ struct dcn10_transform *xfm,
+ const struct rect *viewport,
+ const struct rect *viewport_c)
+{
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
+ PRI_VIEWPORT_WIDTH, viewport->width,
+ PRI_VIEWPORT_HEIGHT, viewport->height);
+
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
+ PRI_VIEWPORT_X_START, viewport->x,
+ PRI_VIEWPORT_Y_START, viewport->y);
+
+ /*for stereo*/
+ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
+ SEC_VIEWPORT_WIDTH, viewport->width,
+ SEC_VIEWPORT_HEIGHT, viewport->height);
+
+ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
+ SEC_VIEWPORT_X_START, viewport->x,
+ SEC_VIEWPORT_Y_START, viewport->y);
+
+ /* DC supports NV12 only at the moment */
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
+ PRI_VIEWPORT_WIDTH_C, viewport_c->width,
+ PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
+
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
+ PRI_VIEWPORT_X_START_C, viewport_c->x,
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
+}
+
+static int get_lb_depth_bpc(enum lb_pixel_depth depth)
+{
+ if (depth == LB_PIXEL_DEPTH_30BPP)
+ return 10;
+ else if (depth == LB_PIXEL_DEPTH_24BPP)
+ return 8;
+ else if (depth == LB_PIXEL_DEPTH_18BPP)
+ return 6;
+ else if (depth == LB_PIXEL_DEPTH_36BPP)
+ return 12;
+ else {
+ BREAK_TO_DEBUGGER();
+ return -1; /* Unsupported */
+ }
+}
+
+static void calc_lb_num_partitions(
+ const struct scaler_data *scl_data,
+ enum lb_memory_config lb_config,
+ int *num_part_y,
+ int *num_part_c)
+{
+ int line_size = scl_data->viewport.width < scl_data->recout.width ?
+ scl_data->viewport.width : scl_data->recout.width;
+ int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
+ scl_data->viewport_c.width : scl_data->recout.width;
+ int lb_bpc = get_lb_depth_bpc(scl_data->lb_params.depth);
+ int memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
+ int memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
+ int memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
+ int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
+
+ if (lb_config == LB_MEMORY_CONFIG_1) {
+ lb_memory_size = 816;
+ lb_memory_size_c = 816;
+ lb_memory_size_a = 984;
+ } else if (lb_config == LB_MEMORY_CONFIG_2) {
+ lb_memory_size = 1088;
+ lb_memory_size_c = 1088;
+ lb_memory_size_a = 1312;
+ } else if (lb_config == LB_MEMORY_CONFIG_3) {
+ lb_memory_size = 816 + 1088 + 848 + 848 + 848;
+ lb_memory_size_c = 816 + 1088;
+ lb_memory_size_a = 984 + 1312 + 456;
+ } else {
+ lb_memory_size = 816 + 1088 + 848;
+ lb_memory_size_c = 816 + 1088 + 848;
+ lb_memory_size_a = 984 + 1312 + 456;
+ }
+ *num_part_y = lb_memory_size / memory_line_size_y;
+ *num_part_c = lb_memory_size_c / memory_line_size_c;
+ num_partitions_a = lb_memory_size_a / memory_line_size_a;
+
+ if (scl_data->lb_params.alpha_en
+ && (num_partitions_a < *num_part_y))
+ *num_part_y = num_partitions_a;
+
+ if (*num_part_y > 64)
+ *num_part_y = 64;
+ if (*num_part_c > 64)
+ *num_part_c = 64;
+
+}
+
+static bool is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
+{
+ if (ceil_vratio > 2)
+ return vtaps <= (num_partitions - ceil_vratio + 2);
+ else
+ return vtaps <= num_partitions;
+}
+
+/*find first match configuration which meets the min required lb size*/
+static enum lb_memory_config find_lb_memory_config(const struct scaler_data *scl_data)
+{
+ int num_part_y, num_part_c;
+ int vtaps = scl_data->taps.v_taps;
+ int vtaps_c = scl_data->taps.v_taps_c;
+ int ceil_vratio = dal_fixed31_32_ceil(scl_data->ratios.vert);
+ int ceil_vratio_c = dal_fixed31_32_ceil(scl_data->ratios.vert_c);
+
+ calc_lb_num_partitions(
+ scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
+
+ if (is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
+ && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
+ return LB_MEMORY_CONFIG_1;
+
+ calc_lb_num_partitions(
+ scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
+
+ if (is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
+ && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
+ return LB_MEMORY_CONFIG_2;
+
+ if (scl_data->format == PIXEL_FORMAT_420BPP12
+ || scl_data->format == PIXEL_FORMAT_420BPP15) {
+ calc_lb_num_partitions(
+ scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
+
+ if (is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
+ && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
+ return LB_MEMORY_CONFIG_3;
+ }
+
+ calc_lb_num_partitions(
+ scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
+
+ /*Ensure we can support the requested number of vtaps*/
+ ASSERT(is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
+ && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
+
+ return LB_MEMORY_CONFIG_0;
+}
+
+void transform_set_scaler_auto_scale(
+ struct transform *xfm_base,
+ const struct scaler_data *scl_data)
+{
+ enum lb_memory_config lb_config;
+ struct dcn10_transform *xfm = TO_DCN10_TRANSFORM(xfm_base);
+ enum dscl_mode_sel dscl_mode = get_dscl_mode(scl_data);
+ bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
+ && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
+
+ transform_set_overscan(xfm, scl_data);
+
+ transform_set_otg_blank(xfm, scl_data);
+
+ REG_UPDATE(SCL_MODE, DSCL_MODE, get_dscl_mode(scl_data));
+
+ transform_set_viewport(xfm, &scl_data->viewport, &scl_data->viewport_c);
+
+ if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
+ return;
+
+ lb_config = find_lb_memory_config(scl_data);
+ transform_set_lb(xfm, &scl_data->lb_params, lb_config);
+
+ if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
+ return;
+
+ /* TODO: v_min */
+ REG_SET_3(DSCL_AUTOCAL, 0,
+ AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
+ AUTOCAL_NUM_PIPE, 0,
+ AUTOCAL_PIPE_ID, 0);
+
+ /* Black offsets */
+ if (ycbcr)
+ REG_SET_2(SCL_BLACK_OFFSET, 0,
+ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
+ else
+
+ REG_SET_2(SCL_BLACK_OFFSET, 0,
+ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
+
+ REG_SET_4(SCL_TAP_CONTROL, 0,
+ SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
+ SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
+ SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
+ SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
+
+ transform_set_scl_filter(xfm, scl_data, ycbcr);
+}
+
+/* Program gamut remap in bypass mode */
+void transform_set_gamut_remap_bypass(struct dcn10_transform *xfm)
+{
+ REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
+ CM_GAMUT_REMAP_MODE, 0);
+ /* Gamut remap in bypass */
+}
+
+static void transform_set_recout(
+ struct dcn10_transform *xfm, const struct rect *recout)
+{
+ REG_SET_2(RECOUT_START, 0,
+ /* First pixel of RECOUT */
+ RECOUT_START_X, recout->x,
+ /* First line of RECOUT */
+ RECOUT_START_Y, recout->y);
+
+ REG_SET_2(RECOUT_SIZE, 0,
+ /* Number of RECOUT horizontal pixels */
+ RECOUT_WIDTH, recout->width,
+ /* Number of RECOUT vertical lines */
+ RECOUT_HEIGHT, recout->height
+ - xfm->base.ctx->dc->debug.surface_visual_confirm * 2);
+}
+
+static void transform_set_manual_ratio_init(
+ struct dcn10_transform *xfm, const struct scaler_data *data)
+{
+ uint32_t init_frac = 0;
+ uint32_t init_int = 0;
+
+ REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
+ SCL_H_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.horz) << 5);
+
+ REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
+ SCL_V_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.vert) << 5);
+
+ REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
+ SCL_H_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.horz_c) << 5);
+
+ REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
+ SCL_V_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.vert_c) << 5);
+
+ /*
+ * 0.24 format for fraction, first five bits zeroed
+ */
+ init_frac = dal_fixed31_32_u0d19(data->inits.h) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.h);
+ REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
+ SCL_H_INIT_FRAC, init_frac,
+ SCL_H_INIT_INT, init_int);
+
+ init_frac = dal_fixed31_32_u0d19(data->inits.h_c) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.h_c);
+ REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
+ SCL_H_INIT_FRAC_C, init_frac,
+ SCL_H_INIT_INT_C, init_int);
+
+ init_frac = dal_fixed31_32_u0d19(data->inits.v) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.v);
+ REG_SET_2(SCL_VERT_FILTER_INIT, 0,
+ SCL_V_INIT_FRAC, init_frac,
+ SCL_V_INIT_INT, init_int);
+
+ init_frac = dal_fixed31_32_u0d19(data->inits.v_bot) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.v_bot);
+ REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
+ SCL_V_INIT_FRAC_BOT, init_frac,
+ SCL_V_INIT_INT_BOT, init_int);
+
+ init_frac = dal_fixed31_32_u0d19(data->inits.v_c) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.v_c);
+ REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
+ SCL_V_INIT_FRAC_C, init_frac,
+ SCL_V_INIT_INT_C, init_int);
+
+ init_frac = dal_fixed31_32_u0d19(data->inits.v_c_bot) << 5;
+ init_int = dal_fixed31_32_floor(data->inits.v_c_bot);
+ REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
+ SCL_V_INIT_FRAC_BOT_C, init_frac,
+ SCL_V_INIT_INT_BOT_C, init_int);
+}
+
+/* Main function to program scaler and line buffer in manual scaling mode */
+static void transform_set_scaler_manual_scale(
+ struct transform *xfm_base,
+ const struct scaler_data *scl_data)
+{
+ enum lb_memory_config lb_config;
+ struct dcn10_transform *xfm = TO_DCN10_TRANSFORM(xfm_base);
+ enum dscl_mode_sel dscl_mode = get_dscl_mode(scl_data);
+ bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
+ && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
+
+ /* Recout */
+ transform_set_recout(xfm, &scl_data->recout);
+
+ /* MPC Size */
+ REG_SET_2(MPC_SIZE, 0,
+ /* Number of horizontal pixels of MPC */
+ MPC_WIDTH, scl_data->h_active,
+ /* Number of vertical lines of MPC */
+ MPC_HEIGHT, scl_data->v_active);
+
+ /* SCL mode */
+ REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
+
+ /* Viewport */
+ transform_set_viewport(xfm, &scl_data->viewport, &scl_data->viewport_c);
+
+ if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
+ return;
+ /* LB */
+ lb_config = find_lb_memory_config(scl_data);
+ transform_set_lb(xfm, &scl_data->lb_params, lb_config);
+
+ if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
+ return;
+
+ /* Autocal off */
+ REG_SET_3(DSCL_AUTOCAL, 0,
+ AUTOCAL_MODE, AUTOCAL_MODE_OFF,
+ AUTOCAL_NUM_PIPE, 0,
+ AUTOCAL_PIPE_ID, 0);
+
+ /* Black offsets */
+ if (ycbcr)
+ REG_SET_2(SCL_BLACK_OFFSET, 0,
+ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
+ else
+
+ REG_SET_2(SCL_BLACK_OFFSET, 0,
+ SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+ SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
+
+ /* Manually calculate scale ratio and init values */
+ transform_set_manual_ratio_init(xfm, scl_data);
+
+ /* HTaps/VTaps */
+ REG_SET_4(SCL_TAP_CONTROL, 0,
+ SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
+ SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
+ SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
+ SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
+
+ transform_set_scl_filter(xfm, scl_data, ycbcr);
+}
+
+#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
+
+
+static bool transform_get_optimal_number_of_taps(
+ struct transform *xfm,
+ struct scaler_data *scl_data,
+ const struct scaling_taps *in_taps)
+{
+ uint32_t pixel_width;
+
+ if (scl_data->viewport.width > scl_data->recout.width)
+ pixel_width = scl_data->recout.width;
+ else
+ pixel_width = scl_data->viewport.width;
+
+ /* TODO: add lb check */
+
+ /* No support for programming ratio of 4, drop to 3.99999.. */
+ if (scl_data->ratios.horz.value == (4ll << 32))
+ scl_data->ratios.horz.value--;
+ if (scl_data->ratios.vert.value == (4ll << 32))
+ scl_data->ratios.vert.value--;
+ if (scl_data->ratios.horz_c.value == (4ll << 32))
+ scl_data->ratios.horz_c.value--;
+ if (scl_data->ratios.vert_c.value == (4ll << 32))
+ scl_data->ratios.vert_c.value--;
+
+ /* Set default taps if none are provided */
+ if (in_taps->h_taps == 0)
+ scl_data->taps.h_taps = 4;
+ else
+ scl_data->taps.h_taps = in_taps->h_taps;
+ if (in_taps->v_taps == 0)
+ scl_data->taps.v_taps = 4;
+ else
+ scl_data->taps.v_taps = in_taps->v_taps;
+ if (in_taps->v_taps_c == 0)
+ scl_data->taps.v_taps_c = 2;
+ else
+ scl_data->taps.v_taps_c = in_taps->v_taps_c;
+ if (in_taps->h_taps_c == 0)
+ scl_data->taps.h_taps_c = 2;
+ /* Only 1 and even h_taps_c are supported by hw */
+ else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
+ scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
+ else
+ scl_data->taps.h_taps_c = in_taps->h_taps_c;
+
+ if (IDENTITY_RATIO(scl_data->ratios.horz))
+ scl_data->taps.h_taps = 1;
+ if (IDENTITY_RATIO(scl_data->ratios.vert))
+ scl_data->taps.v_taps = 1;
+ if (IDENTITY_RATIO(scl_data->ratios.horz_c))
+ scl_data->taps.h_taps_c = 1;
+ if (IDENTITY_RATIO(scl_data->ratios.vert_c))
+ scl_data->taps.v_taps_c = 1;
+
+ return true;
+}
+
+static void transform_reset(struct transform *xfm_base)
+{
+ struct dcn10_transform *xfm = TO_DCN10_TRANSFORM(xfm_base);
+
+ xfm->filter_h_c = NULL;
+ xfm->filter_v_c = NULL;
+ xfm->filter_h = NULL;
+ xfm->filter_v = NULL;
+
+ /* set boundary mode to 0 */
+ REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
+}
+
+static void program_gamut_remap(
+ struct dcn10_transform *xfm,
+ const uint16_t *regval,
+ enum gamut_remap_select select)
+{
+ uint16_t selection = 0;
+
+ if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
+ REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
+ CM_GAMUT_REMAP_MODE, 0);
+ return;
+ }
+ switch (select) {
+ case GAMUT_REMAP_COEFF:
+ selection = 1;
+ break;
+ case GAMUT_REMAP_COMA_COEFF:
+ selection = 2;
+ break;
+ case GAMUT_REMAP_COMB_COEFF:
+ selection = 3;
+ break;
+ default:
+ break;
+ }
+
+
+ if (select == GAMUT_REMAP_COEFF) {
+
+ REG_SET_2(CM_GAMUT_REMAP_C11_C12, 0,
+ CM_GAMUT_REMAP_C11, regval[0],
+ CM_GAMUT_REMAP_C12, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_GAMUT_REMAP_C13_C14, 0,
+ CM_GAMUT_REMAP_C13, regval[0],
+ CM_GAMUT_REMAP_C14, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_GAMUT_REMAP_C21_C22, 0,
+ CM_GAMUT_REMAP_C21, regval[0],
+ CM_GAMUT_REMAP_C22, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_GAMUT_REMAP_C23_C24, 0,
+ CM_GAMUT_REMAP_C23, regval[0],
+ CM_GAMUT_REMAP_C24, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_GAMUT_REMAP_C31_C32, 0,
+ CM_GAMUT_REMAP_C31, regval[0],
+ CM_GAMUT_REMAP_C32, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_GAMUT_REMAP_C33_C34, 0,
+ CM_GAMUT_REMAP_C33, regval[0],
+ CM_GAMUT_REMAP_C34, regval[1]);
+
+ } else if (select == GAMUT_REMAP_COMA_COEFF) {
+ REG_SET_2(CM_COMA_C11_C12, 0,
+ CM_COMA_C11, regval[0],
+ CM_COMA_C12, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C13_C14, 0,
+ CM_COMA_C13, regval[0],
+ CM_COMA_C14, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C21_C22, 0,
+ CM_COMA_C21, regval[0],
+ CM_COMA_C22, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C23_C24, 0,
+ CM_COMA_C23, regval[0],
+ CM_COMA_C24, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C31_C32, 0,
+ CM_COMA_C31, regval[0],
+ CM_COMA_C32, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMA_C33_C34, 0,
+ CM_COMA_C33, regval[0],
+ CM_COMA_C34, regval[1]);
+
+ } else {
+ REG_SET_2(CM_COMB_C11_C12, 0,
+ CM_COMB_C11, regval[0],
+ CM_COMB_C12, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMB_C13_C14, 0,
+ CM_COMB_C13, regval[0],
+ CM_COMB_C14, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMB_C21_C22, 0,
+ CM_COMB_C21, regval[0],
+ CM_COMB_C22, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMB_C23_C24, 0,
+ CM_COMB_C23, regval[0],
+ CM_COMB_C24, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMB_C31_C32, 0,
+ CM_COMB_C31, regval[0],
+ CM_COMB_C32, regval[1]);
+ regval += 2;
+ REG_SET_2(CM_COMB_C33_C34, 0,
+ CM_COMB_C33, regval[0],
+ CM_COMB_C34, regval[1]);
+ }
+
+ REG_SET(
+ CM_GAMUT_REMAP_CONTROL, 0,
+ CM_GAMUT_REMAP_MODE, selection);
+
+}
+
+static void dcn_transform_set_gamut_remap(
+ struct transform *xfm,
+ const struct xfm_grph_csc_adjustment *adjust)
+{
+ struct dcn10_transform *dcn_xfm = TO_DCN10_TRANSFORM(xfm);
+
+ if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW)
+ /* Bypass if type is bypass or hw */
+ program_gamut_remap(dcn_xfm, NULL, GAMUT_REMAP_BYPASS);
+ else {
+ struct fixed31_32 arr_matrix[12];
+ uint16_t arr_reg_val[12];
+
+ arr_matrix[0] = adjust->temperature_matrix[0];
+ arr_matrix[1] = adjust->temperature_matrix[1];
+ arr_matrix[2] = adjust->temperature_matrix[2];
+ arr_matrix[3] = dal_fixed31_32_zero;
+
+ arr_matrix[4] = adjust->temperature_matrix[3];
+ arr_matrix[5] = adjust->temperature_matrix[4];
+ arr_matrix[6] = adjust->temperature_matrix[5];
+ arr_matrix[7] = dal_fixed31_32_zero;
+
+ arr_matrix[8] = adjust->temperature_matrix[6];
+ arr_matrix[9] = adjust->temperature_matrix[7];
+ arr_matrix[10] = adjust->temperature_matrix[8];
+ arr_matrix[11] = dal_fixed31_32_zero;
+
+ convert_float_matrix(
+ arr_reg_val, arr_matrix, 12);
+
+ program_gamut_remap(dcn_xfm, arr_reg_val, GAMUT_REMAP_COEFF);
+ }
+}
+
+static struct transform_funcs dcn10_transform_funcs = {
+
+ .transform_reset = transform_reset,
+ .transform_set_scaler = transform_set_scaler_manual_scale,
+ .transform_get_optimal_number_of_taps =
+ transform_get_optimal_number_of_taps,
+ .transform_set_gamut_remap = dcn_transform_set_gamut_remap
+};
+
+/*****************************************/
+/* Constructor, Destructor */
+/*****************************************/
+
+bool dcn10_transform_construct(
+ struct dcn10_transform *xfm,
+ struct dc_context *ctx,
+ const struct dcn_transform_registers *tf_regs,
+ const struct dcn_transform_shift *tf_shift,
+ const struct dcn_transform_mask *tf_mask)
+{
+ xfm->base.ctx = ctx;
+
+ xfm->base.funcs = &dcn10_transform_funcs;
+
+ xfm->tf_regs = tf_regs;
+ xfm->tf_shift = tf_shift;
+ xfm->tf_mask = tf_mask;
+
+ xfm->lb_pixel_depth_supported =
+ LB_PIXEL_DEPTH_18BPP |
+ LB_PIXEL_DEPTH_24BPP |
+ LB_PIXEL_DEPTH_30BPP;
+
+ xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY;
+ xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
new file mode 100644
index 0000000..7c0089d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
@@ -0,0 +1,416 @@
+/* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_TRANSFORM_DCN10_H__
+#define __DAL_TRANSFORM_DCN10_H__
+
+#include "transform.h"
+
+#define TO_DCN10_TRANSFORM(transform)\
+ container_of(transform, struct dcn10_transform, base)
+
+/* TODO: Use correct number of taps. Using polaris values for now */
+#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
+#define LB_BITS_PER_ENTRY 144
+
+#define TF_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define TF_REG_LIST_DCN(id) \
+ SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
+ SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
+ SRI(OTG_H_BLANK, DSCL, id), \
+ SRI(OTG_V_BLANK, DSCL, id), \
+ SRI(SCL_MODE, DSCL, id), \
+ SRI(LB_DATA_FORMAT, DSCL, id), \
+ SRI(LB_MEMORY_CTRL, DSCL, id), \
+ SRI(DSCL_AUTOCAL, DSCL, id), \
+ SRI(SCL_BLACK_OFFSET, DSCL, id), \
+ SRI(DSCL_CONTROL, DSCL, id), \
+ SRI(SCL_TAP_CONTROL, DSCL, id), \
+ SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
+ SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
+ SRI(DSCL_2TAP_CONTROL, DSCL, id), \
+ SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
+ SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
+ SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
+ SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
+ SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
+ SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
+ SRI(CM_GAMUT_REMAP_CONTROL, CM, id), \
+ SRI(MPC_SIZE, DSCL, id), \
+ SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
+ SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
+ SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
+ SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
+ SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
+ SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
+ SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
+ SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
+ SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
+ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
+ SRI(RECOUT_START, DSCL, id), \
+ SRI(RECOUT_SIZE, DSCL, id), \
+ SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
+ SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
+ SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
+ SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
+ SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
+ SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
+ SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
+ SRI(CM_COMA_C11_C12, CM, id),\
+ SRI(CM_COMA_C13_C14, CM, id),\
+ SRI(CM_COMA_C21_C22, CM, id),\
+ SRI(CM_COMA_C23_C24, CM, id),\
+ SRI(CM_COMA_C31_C32, CM, id),\
+ SRI(CM_COMA_C33_C34, CM, id),\
+ SRI(CM_COMB_C11_C12, CM, id),\
+ SRI(CM_COMB_C13_C14, CM, id),\
+ SRI(CM_COMB_C21_C22, CM, id),\
+ SRI(CM_COMB_C23_C24, CM, id),\
+ SRI(CM_COMB_C31_C32, CM, id),\
+ SRI(CM_COMB_C33_C34, CM, id)
+
+
+
+#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
+ TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
+ TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
+ TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
+ TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
+ TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
+ TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
+ TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
+ TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
+ TF_SF(DSCL0_LB_DATA_FORMAT, ALPHA_EN, mask_sh),\
+ TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
+ TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
+ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
+ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
+ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
+ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
+ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
+ TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
+ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
+ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
+ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
+ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
+ TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
+ TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
+ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
+ TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
+ TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
+ TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
+ TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
+ TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
+ TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
+ TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
+ TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
+ TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
+ TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
+ TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
+ TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
+ TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
+ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
+ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
+ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
+ TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
+ TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
+ TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
+ TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh),\
+ TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh),\
+ TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh),\
+ TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh),\
+ TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh),\
+ TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh),\
+ TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh),\
+ TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh),\
+ TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
+ TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
+ TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
+ TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
+ TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh),\
+ TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh),\
+ TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh),\
+ TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh),\
+ TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh),\
+ TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh),\
+ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh),\
+ TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
+ TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh),\
+ TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh)
+
+
+#define TF_REG_FIELD_LIST(type) \
+ type EXT_OVERSCAN_LEFT; \
+ type EXT_OVERSCAN_RIGHT; \
+ type EXT_OVERSCAN_BOTTOM; \
+ type EXT_OVERSCAN_TOP; \
+ type OTG_H_BLANK_START; \
+ type OTG_H_BLANK_END; \
+ type OTG_V_BLANK_START; \
+ type OTG_V_BLANK_END; \
+ type PIXEL_DEPTH; \
+ type PIXEL_EXPAN_MODE; \
+ type PIXEL_REDUCE_MODE; \
+ type DYNAMIC_PIXEL_DEPTH; \
+ type DITHER_EN; \
+ type INTERLEAVE_EN; \
+ type ALPHA_EN; \
+ type MEMORY_CONFIG; \
+ type LB_MAX_PARTITIONS; \
+ type AUTOCAL_MODE; \
+ type AUTOCAL_NUM_PIPE; \
+ type AUTOCAL_PIPE_ID; \
+ type SCL_BLACK_OFFSET_RGB_Y; \
+ type SCL_BLACK_OFFSET_CBCR; \
+ type SCL_BOUNDARY_MODE; \
+ type SCL_V_NUM_TAPS; \
+ type SCL_H_NUM_TAPS; \
+ type SCL_V_NUM_TAPS_C; \
+ type SCL_H_NUM_TAPS_C; \
+ type SCL_COEF_RAM_TAP_PAIR_IDX; \
+ type SCL_COEF_RAM_PHASE; \
+ type SCL_COEF_RAM_FILTER_TYPE; \
+ type SCL_COEF_RAM_EVEN_TAP_COEF; \
+ type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
+ type SCL_COEF_RAM_ODD_TAP_COEF; \
+ type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
+ type SCL_H_2TAP_HARDCODE_COEF_EN; \
+ type SCL_H_2TAP_SHARP_EN; \
+ type SCL_H_2TAP_SHARP_FACTOR; \
+ type SCL_V_2TAP_HARDCODE_COEF_EN; \
+ type SCL_V_2TAP_SHARP_EN; \
+ type SCL_V_2TAP_SHARP_FACTOR; \
+ type SCL_COEF_RAM_SELECT; \
+ type PRI_VIEWPORT_WIDTH; \
+ type PRI_VIEWPORT_HEIGHT; \
+ type PRI_VIEWPORT_X_START; \
+ type PRI_VIEWPORT_Y_START; \
+ type SEC_VIEWPORT_WIDTH; \
+ type SEC_VIEWPORT_HEIGHT; \
+ type SEC_VIEWPORT_X_START; \
+ type SEC_VIEWPORT_Y_START; \
+ type PRI_VIEWPORT_WIDTH_C; \
+ type PRI_VIEWPORT_HEIGHT_C; \
+ type PRI_VIEWPORT_X_START_C; \
+ type PRI_VIEWPORT_Y_START_C; \
+ type DSCL_MODE; \
+ type RECOUT_START_X; \
+ type RECOUT_START_Y; \
+ type RECOUT_WIDTH; \
+ type RECOUT_HEIGHT; \
+ type MPC_WIDTH; \
+ type MPC_HEIGHT; \
+ type SCL_H_SCALE_RATIO; \
+ type SCL_V_SCALE_RATIO; \
+ type SCL_H_SCALE_RATIO_C; \
+ type SCL_V_SCALE_RATIO_C; \
+ type SCL_H_INIT_FRAC; \
+ type SCL_H_INIT_INT; \
+ type SCL_H_INIT_FRAC_C; \
+ type SCL_H_INIT_INT_C; \
+ type SCL_V_INIT_FRAC; \
+ type SCL_V_INIT_INT; \
+ type SCL_V_INIT_FRAC_BOT; \
+ type SCL_V_INIT_INT_BOT; \
+ type SCL_V_INIT_FRAC_C; \
+ type SCL_V_INIT_INT_C; \
+ type SCL_V_INIT_FRAC_BOT_C; \
+ type SCL_V_INIT_INT_BOT_C; \
+ type SCL_CHROMA_COEF_MODE; \
+ type SCL_COEF_RAM_SELECT_CURRENT; \
+ type CM_GAMUT_REMAP_MODE; \
+ type CM_GAMUT_REMAP_C11; \
+ type CM_GAMUT_REMAP_C12; \
+ type CM_GAMUT_REMAP_C13; \
+ type CM_GAMUT_REMAP_C14; \
+ type CM_GAMUT_REMAP_C21; \
+ type CM_GAMUT_REMAP_C22; \
+ type CM_GAMUT_REMAP_C23; \
+ type CM_GAMUT_REMAP_C24; \
+ type CM_GAMUT_REMAP_C31; \
+ type CM_GAMUT_REMAP_C32; \
+ type CM_GAMUT_REMAP_C33; \
+ type CM_GAMUT_REMAP_C34; \
+ type CM_COMA_C11; \
+ type CM_COMA_C12; \
+ type CM_COMA_C13; \
+ type CM_COMA_C14; \
+ type CM_COMA_C21; \
+ type CM_COMA_C22; \
+ type CM_COMA_C23; \
+ type CM_COMA_C24; \
+ type CM_COMA_C31; \
+ type CM_COMA_C32; \
+ type CM_COMA_C33; \
+ type CM_COMA_C34; \
+ type CM_COMB_C11; \
+ type CM_COMB_C12; \
+ type CM_COMB_C13; \
+ type CM_COMB_C14; \
+ type CM_COMB_C21; \
+ type CM_COMB_C22; \
+ type CM_COMB_C23; \
+ type CM_COMB_C24; \
+ type CM_COMB_C31; \
+ type CM_COMB_C32; \
+ type CM_COMB_C33; \
+ type CM_COMB_C34
+
+struct dcn_transform_shift {
+ TF_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn_transform_mask {
+ TF_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn_transform_registers {
+ uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
+ uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
+ uint32_t OTG_H_BLANK;
+ uint32_t OTG_V_BLANK;
+ uint32_t SCL_MODE;
+ uint32_t LB_DATA_FORMAT;
+ uint32_t LB_MEMORY_CTRL;
+ uint32_t DSCL_AUTOCAL;
+ uint32_t SCL_BLACK_OFFSET;
+ uint32_t DSCL_CONTROL;
+ uint32_t SCL_TAP_CONTROL;
+ uint32_t SCL_COEF_RAM_TAP_SELECT;
+ uint32_t SCL_COEF_RAM_TAP_DATA;
+ uint32_t DSCL_2TAP_CONTROL;
+ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION;
+ uint32_t DCSURF_PRI_VIEWPORT_START;
+ uint32_t DCSURF_SEC_VIEWPORT_DIMENSION;
+ uint32_t DCSURF_SEC_VIEWPORT_START;
+ uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C;
+ uint32_t DCSURF_PRI_VIEWPORT_START_C;
+ uint32_t MPC_SIZE;
+ uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
+ uint32_t SCL_VERT_FILTER_SCALE_RATIO;
+ uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
+ uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
+ uint32_t SCL_HORZ_FILTER_INIT;
+ uint32_t SCL_HORZ_FILTER_INIT_C;
+ uint32_t SCL_VERT_FILTER_INIT;
+ uint32_t SCL_VERT_FILTER_INIT_BOT;
+ uint32_t SCL_VERT_FILTER_INIT_C;
+ uint32_t SCL_VERT_FILTER_INIT_BOT_C;
+ uint32_t RECOUT_START;
+ uint32_t RECOUT_SIZE;
+ uint32_t CM_GAMUT_REMAP_CONTROL;
+ uint32_t CM_GAMUT_REMAP_C11_C12;
+ uint32_t CM_GAMUT_REMAP_C13_C14;
+ uint32_t CM_GAMUT_REMAP_C21_C22;
+ uint32_t CM_GAMUT_REMAP_C23_C24;
+ uint32_t CM_GAMUT_REMAP_C31_C32;
+ uint32_t CM_GAMUT_REMAP_C33_C34;
+ uint32_t CM_COMA_C11_C12;
+ uint32_t CM_COMA_C13_C14;
+ uint32_t CM_COMA_C21_C22;
+ uint32_t CM_COMA_C23_C24;
+ uint32_t CM_COMA_C31_C32;
+ uint32_t CM_COMA_C33_C34;
+ uint32_t CM_COMB_C11_C12;
+ uint32_t CM_COMB_C13_C14;
+ uint32_t CM_COMB_C21_C22;
+ uint32_t CM_COMB_C23_C24;
+ uint32_t CM_COMB_C31_C32;
+ uint32_t CM_COMB_C33_C34;
+};
+
+struct dcn10_transform {
+ struct transform base;
+
+ const struct dcn_transform_registers *tf_regs;
+ const struct dcn_transform_shift *tf_shift;
+ const struct dcn_transform_mask *tf_mask;
+
+ const uint16_t *filter_v;
+ const uint16_t *filter_h;
+ const uint16_t *filter_v_c;
+ const uint16_t *filter_h_c;
+ int lb_pixel_depth_supported;
+ int lb_memory_size;
+ int lb_bits_per_entry;
+};
+
+bool dcn10_transform_construct(struct dcn10_transform *xfm110,
+ struct dc_context *ctx,
+ const struct dcn_transform_registers *tf_regs,
+ const struct dcn_transform_shift *tf_shift,
+ const struct dcn_transform_mask *tf_mask);
+#endif
--
2.5.5
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 111/117] drm/amdgpu/display: Add dml support for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (101 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 110/117] drm/amdgpu/display: Add core dc support " Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 112/117] drm/amdgpu/display: Add gpio " Alex Deucher
` (6 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
Display mode lib handles clock, watermark, and bandwidth
calculations for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +++++
.../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
.../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 ++
.../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
.../drm/amd/display/dc/dml/display_mode_structs.h | 429 ++++
.../drm/amd/display/dc/dml/display_mode_support.c | 2326 ++++++++++++++++++++
.../drm/amd/display/dc/dml/display_mode_support.h | 199 ++
.../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +++
.../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
.../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +++++++++++++++++++
.../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 ++
.../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +++
.../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
.../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +++++++++++
.../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
.../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 ++
.../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
.../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
.../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
20 files changed, 8717 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
new file mode 100644
index 0000000..9d7791d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for the 'utils' sub-component of DAL.
+# It provides the general basic services required by other DAL
+# subcomponents.
+
+CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_mode_support.o := -mhard-float -msse -mpreferred-stack-boundary=4
+
+
+DML = display_mode_lib.o display_pipe_clocks.o display_rq_dlg_calc.o \
+ display_rq_dlg_helpers.o display_watermark.o \
+ soc_bounding_box.o dml_common_defs.o display_mode_support.o
+
+AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DML)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
new file mode 100644
index 0000000..745c04c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
@@ -0,0 +1,557 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_FEATURES_H__
+#define __DC_FEATURES_H__
+
+#define DC__PRESENT 1
+#define DC__PRESENT__1 1
+#define DC__NUM_DPP 4
+#define DC__NUM_DPP__4 1
+#define DC__NUM_DPP__0_PRESENT 1
+#define DC__NUM_DPP__1_PRESENT 1
+#define DC__NUM_DPP__2_PRESENT 1
+#define DC__NUM_DPP__3_PRESENT 1
+#define DC__NUM_DPP__MAX 8
+#define DC__NUM_DPP__MAX__8 1
+#define DC__PIPE_10BIT 0
+#define DC__PIPE_10BIT__0 1
+#define DC__PIPE_10BIT__MAX 1
+#define DC__PIPE_10BIT__MAX__1 1
+#define DC__NUM_OPP 4
+#define DC__NUM_OPP__4 1
+#define DC__NUM_OPP__0_PRESENT 1
+#define DC__NUM_OPP__1_PRESENT 1
+#define DC__NUM_OPP__2_PRESENT 1
+#define DC__NUM_OPP__3_PRESENT 1
+#define DC__NUM_OPP__MAX 6
+#define DC__NUM_OPP__MAX__6 1
+#define DC__NUM_DSC 0
+#define DC__NUM_DSC__0 1
+#define DC__NUM_DSC__MAX 6
+#define DC__NUM_DSC__MAX__6 1
+#define DC__NUM_ABM 1
+#define DC__NUM_ABM__1 1
+#define DC__NUM_ABM__0_PRESENT 1
+#define DC__NUM_ABM__MAX 2
+#define DC__NUM_ABM__MAX__2 1
+#define DC__ODM_PRESENT 0
+#define DC__ODM_PRESENT__0 1
+#define DC__NUM_OTG 4
+#define DC__NUM_OTG__4 1
+#define DC__NUM_OTG__0_PRESENT 1
+#define DC__NUM_OTG__1_PRESENT 1
+#define DC__NUM_OTG__2_PRESENT 1
+#define DC__NUM_OTG__3_PRESENT 1
+#define DC__NUM_OTG__MAX 6
+#define DC__NUM_OTG__MAX__6 1
+#define DC__NUM_DWB 2
+#define DC__NUM_DWB__2 1
+#define DC__NUM_DWB__0_PRESENT 1
+#define DC__NUM_DWB__1_PRESENT 1
+#define DC__NUM_DWB__MAX 2
+#define DC__NUM_DWB__MAX__2 1
+#define DC__NUM_DIG 4
+#define DC__NUM_DIG__4 1
+#define DC__NUM_DIG__0_PRESENT 1
+#define DC__NUM_DIG__1_PRESENT 1
+#define DC__NUM_DIG__2_PRESENT 1
+#define DC__NUM_DIG__3_PRESENT 1
+#define DC__NUM_DIG__MAX 6
+#define DC__NUM_DIG__MAX__6 1
+#define DC__NUM_AUX 4
+#define DC__NUM_AUX__4 1
+#define DC__NUM_AUX__0_PRESENT 1
+#define DC__NUM_AUX__1_PRESENT 1
+#define DC__NUM_AUX__2_PRESENT 1
+#define DC__NUM_AUX__3_PRESENT 1
+#define DC__NUM_AUX__MAX 6
+#define DC__NUM_AUX__MAX__6 1
+#define DC__NUM_AUDIO_STREAMS 4
+#define DC__NUM_AUDIO_STREAMS__4 1
+#define DC__NUM_AUDIO_STREAMS__0_PRESENT 1
+#define DC__NUM_AUDIO_STREAMS__1_PRESENT 1
+#define DC__NUM_AUDIO_STREAMS__2_PRESENT 1
+#define DC__NUM_AUDIO_STREAMS__3_PRESENT 1
+#define DC__NUM_AUDIO_STREAMS__MAX 8
+#define DC__NUM_AUDIO_STREAMS__MAX__8 1
+#define DC__NUM_AUDIO_ENDPOINTS 6
+#define DC__NUM_AUDIO_ENDPOINTS__6 1
+#define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1
+#define DC__NUM_AUDIO_ENDPOINTS__MAX 8
+#define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1
+#define DC__NUM_AUDIO_INPUT_STREAMS 0
+#define DC__NUM_AUDIO_INPUT_STREAMS__0 1
+#define DC__NUM_AUDIO_INPUT_STREAMS__MAX 8
+#define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1
+#define DC__NUM_AUDIO_INPUT_ENDPOINTS 0
+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1
+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX 8
+#define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1
+#define DC__NUM_CURSOR 1
+#define DC__NUM_CURSOR__1 1
+#define DC__NUM_CURSOR__0_PRESENT 1
+#define DC__NUM_CURSOR__MAX 2
+#define DC__NUM_CURSOR__MAX__2 1
+#define DC__DIGITAL_BYPASS_PRESENT 0
+#define DC__DIGITAL_BYPASS_PRESENT__0 1
+#define DC__HCID_HWMAJVER 1
+#define DC__HCID_HWMAJVER__1 1
+#define DC__HCID_HWMINVER 0
+#define DC__HCID_HWMINVER__0 1
+#define DC__HCID_HWREV 0
+#define DC__HCID_HWREV__0 1
+#define DC__ROMSTRAP_PRESENT 0
+#define DC__ROMSTRAP_PRESENT__0 1
+#define DC__NUM_RBBMIF_DECODES 30
+#define DC__NUM_RBBMIF_DECODES__30 1
+#define DC__NUM_DBG_REGS 36
+#define DC__NUM_DBG_REGS__36 1
+#define DC__NUM_PIPES_UNDERLAY 0
+#define DC__NUM_PIPES_UNDERLAY__0 1
+#define DC__NUM_PIPES_UNDERLAY__MAX 2
+#define DC__NUM_PIPES_UNDERLAY__MAX__2 1
+#define DC__NUM_VCE_ENGINE 1
+#define DC__NUM_VCE_ENGINE__1 1
+#define DC__NUM_VCE_ENGINE__0_PRESENT 1
+#define DC__NUM_VCE_ENGINE__MAX 2
+#define DC__NUM_VCE_ENGINE__MAX__2 1
+#define DC__OTG_EXTERNAL_SYNC_PRESENT 0
+#define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1
+#define DC__OTG_CRC_PRESENT 1
+#define DC__OTG_CRC_PRESENT__1 1
+#define DC__VIP_PRESENT 0
+#define DC__VIP_PRESENT__0 1
+#define DC__DTMTEST_PRESENT 0
+#define DC__DTMTEST_PRESENT__0 1
+#define DC__POWER_GATE_PRESENT 1
+#define DC__POWER_GATE_PRESENT__1 1
+#define DC__MEM_PG 1
+#define DC__MEM_PG__1 1
+#define DC__FMT_SRC_SEL_PRESENT 0
+#define DC__FMT_SRC_SEL_PRESENT__0 1
+#define DC__DIG_FEATURES__HDMI_PRESENT 1
+#define DC__DIG_FEATURES__HDMI_PRESENT__1 1
+#define DC__DIG_FEATURES__DP_PRESENT 1
+#define DC__DIG_FEATURES__DP_PRESENT__1 1
+#define DC__DIG_FEATURES__DP_MST_PRESENT 1
+#define DC__DIG_FEATURES__DP_MST_PRESENT__1 1
+#define DC__DIG_LP_FEATURES__HDMI_PRESENT 0
+#define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1
+#define DC__DIG_LP_FEATURES__DP_PRESENT 1
+#define DC__DIG_LP_FEATURES__DP_PRESENT__1 1
+#define DC__DIG_LP_FEATURES__DP_MST_PRESENT 0
+#define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1
+#define DC__DIG_RESYNC_FIFO_SIZE 14
+#define DC__DIG_RESYNC_FIFO_SIZE__14 1
+#define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1
+#define DC__DIG_RESYNC_FIFO_SIZE__MAX 16
+#define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1
+#define DC__DAC_RESYNC_FIFO_SIZE 12
+#define DC__DAC_RESYNC_FIFO_SIZE__12 1
+#define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1
+#define DC__DAC_RESYNC_FIFO_SIZE__MAX 16
+#define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1
+#define DC__DVO_RESYNC_FIFO_SIZE 12
+#define DC__DVO_RESYNC_FIFO_SIZE__12 1
+#define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1
+#define DC__DVO_RESYNC_FIFO_SIZE__MAX 16
+#define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1
+#define DC__MEM_CDC_PRESENT 1
+#define DC__MEM_CDC_PRESENT__1 1
+#define DC__NUM_HPD 4
+#define DC__NUM_HPD__4 1
+#define DC__NUM_HPD__0_PRESENT 1
+#define DC__NUM_HPD__1_PRESENT 1
+#define DC__NUM_HPD__2_PRESENT 1
+#define DC__NUM_HPD__3_PRESENT 1
+#define DC__NUM_HPD__MAX 6
+#define DC__NUM_HPD__MAX__6 1
+#define DC__NUM_DDC_PAIRS 4
+#define DC__NUM_DDC_PAIRS__4 1
+#define DC__NUM_DDC_PAIRS__0_PRESENT 1
+#define DC__NUM_DDC_PAIRS__1_PRESENT 1
+#define DC__NUM_DDC_PAIRS__2_PRESENT 1
+#define DC__NUM_DDC_PAIRS__3_PRESENT 1
+#define DC__NUM_DDC_PAIRS__MAX 6
+#define DC__NUM_DDC_PAIRS__MAX__6 1
+#define DC__NUM_AUDIO_PLL 0
+#define DC__NUM_AUDIO_PLL__0 1
+#define DC__NUM_AUDIO_PLL__MAX 2
+#define DC__NUM_AUDIO_PLL__MAX__2 1
+#define DC__NUM_PIXEL_PLL 1
+#define DC__NUM_PIXEL_PLL__1 1
+#define DC__NUM_PIXEL_PLL__0_PRESENT 1
+#define DC__NUM_PIXEL_PLL__MAX 4
+#define DC__NUM_PIXEL_PLL__MAX__4 1
+#define DC__NUM_CASCADED_PLL 0
+#define DC__NUM_CASCADED_PLL__0 1
+#define DC__NUM_CASCADED_PLL__MAX 3
+#define DC__NUM_CASCADED_PLL__MAX__3 1
+#define DC__PIXCLK_FROM_PHYPLL 1
+#define DC__PIXCLK_FROM_PHYPLL__1 1
+#define DC__NB_STUTTER_MODE_PRESENT 0
+#define DC__NB_STUTTER_MODE_PRESENT__0 1
+#define DC__I2S0_AND_SPDIF0_PRESENT 0
+#define DC__I2S0_AND_SPDIF0_PRESENT__0 1
+#define DC__I2S1_PRESENT 0
+#define DC__I2S1_PRESENT__0 1
+#define DC__SPDIF1_PRESENT 0
+#define DC__SPDIF1_PRESENT__0 1
+#define DC__DSI_PRESENT 0
+#define DC__DSI_PRESENT__0 1
+#define DC__DACA_PRESENT 0
+#define DC__DACA_PRESENT__0 1
+#define DC__DACB_PRESENT 0
+#define DC__DACB_PRESENT__0 1
+#define DC__NUM_PIPES 4
+#define DC__NUM_PIPES__4 1
+#define DC__NUM_PIPES__0_PRESENT 1
+#define DC__NUM_PIPES__1_PRESENT 1
+#define DC__NUM_PIPES__2_PRESENT 1
+#define DC__NUM_PIPES__3_PRESENT 1
+#define DC__NUM_PIPES__MAX 6
+#define DC__NUM_PIPES__MAX__6 1
+#define DC__NUM_DIG_LP 0
+#define DC__NUM_DIG_LP__0 1
+#define DC__NUM_DIG_LP__MAX 2
+#define DC__NUM_DIG_LP__MAX__2 1
+#define DC__DPDEBUG_PRESENT 0
+#define DC__DPDEBUG_PRESENT__0 1
+#define DC__DISPLAY_WB_PRESENT 1
+#define DC__DISPLAY_WB_PRESENT__1 1
+#define DC__NUM_CWB 0
+#define DC__NUM_CWB__0 1
+#define DC__NUM_CWB__MAX 2
+#define DC__NUM_CWB__MAX__2 1
+#define DC__MVP_PRESENT 0
+#define DC__MVP_PRESENT__0 1
+#define DC__DVO_PRESENT 0
+#define DC__DVO_PRESENT__0 1
+#define DC__ABM_PRESENT 0
+#define DC__ABM_PRESENT__0 1
+#define DC__BPHYC_PLL_PRESENT 0
+#define DC__BPHYC_PLL_PRESENT__0 1
+#define DC__BPHYC_UNIPHY_PRESENT 0
+#define DC__BPHYC_UNIPHY_PRESENT__0 1
+#define DC__PHY_BROADCAST_PRESENT 0
+#define DC__PHY_BROADCAST_PRESENT__0 1
+#define DC__NUM_OF_DCRX_SD 0
+#define DC__NUM_OF_DCRX_SD__0 1
+#define DC__DVO_17BIT_MAPPING 0
+#define DC__DVO_17BIT_MAPPING__0 1
+#define DC__AVSYNC_PRESENT 0
+#define DC__AVSYNC_PRESENT__0 1
+#define DC__NUM_OF_DCRX_PORTS 0
+#define DC__NUM_OF_DCRX_PORTS__0 1
+#define DC__NUM_OF_DCRX_PORTS__MAX 1
+#define DC__NUM_OF_DCRX_PORTS__MAX__1 1
+#define DC__NUM_PHY 4
+#define DC__NUM_PHY__4 1
+#define DC__NUM_PHY__0_PRESENT 1
+#define DC__NUM_PHY__1_PRESENT 1
+#define DC__NUM_PHY__2_PRESENT 1
+#define DC__NUM_PHY__3_PRESENT 1
+#define DC__NUM_PHY__MAX 7
+#define DC__NUM_PHY__MAX__7 1
+#define DC__NUM_PHY_LP 0
+#define DC__NUM_PHY_LP__0 1
+#define DC__NUM_PHY_LP__MAX 2
+#define DC__NUM_PHY_LP__MAX__2 1
+#define DC__SYNC_CELL vid_sync_gf14lpp
+#define DC__SYNC_CELL__VID_SYNC_GF14LPP 1
+#define DC__USE_NEW_VSS 1
+#define DC__USE_NEW_VSS__1 1
+#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_REFCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_SCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_AMCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DSICLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1
+#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES 6
+#define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1
+#define UNIPHYA_PRESENT 1
+#define UNIPHYA_PRESENT__1 1
+#define DC__UNIPHYA_PRESENT 1
+#define DC__UNIPHYA_PRESENT__1 1
+#define UNIPHYB_PRESENT 1
+#define UNIPHYB_PRESENT__1 1
+#define DC__UNIPHYB_PRESENT 1
+#define DC__UNIPHYB_PRESENT__1 1
+#define UNIPHYC_PRESENT 1
+#define UNIPHYC_PRESENT__1 1
+#define DC__UNIPHYC_PRESENT 1
+#define DC__UNIPHYC_PRESENT__1 1
+#define UNIPHYD_PRESENT 1
+#define UNIPHYD_PRESENT__1 1
+#define DC__UNIPHYD_PRESENT 1
+#define DC__UNIPHYD_PRESENT__1 1
+#define UNIPHYE_PRESENT 0
+#define UNIPHYE_PRESENT__0 1
+#define DC__UNIPHYE_PRESENT 0
+#define DC__UNIPHYE_PRESENT__0 1
+#define UNIPHYF_PRESENT 0
+#define UNIPHYF_PRESENT__0 1
+#define DC__UNIPHYF_PRESENT 0
+#define DC__UNIPHYF_PRESENT__0 1
+#define UNIPHYG_PRESENT 0
+#define UNIPHYG_PRESENT__0 1
+#define DC__UNIPHYG_PRESENT 0
+#define DC__UNIPHYG_PRESENT__0 1
+#define DC__TMDS_LINK tmds_link_dual
+#define DC__TMDS_LINK__TMDS_LINK_DUAL 1
+#define DC__WBSCL_PIXBW 8
+#define DC__WBSCL_PIXBW__8 1
+#define DC__DWB_CSC_PRESENT 0
+#define DC__DWB_CSC_PRESENT__0 1
+#define DC__DWB_LUMA_SCL_PRESENT 0
+#define DC__DWB_LUMA_SCL_PRESENT__0 1
+#define DC__DENTIST_INTERFACE_PRESENT 1
+#define DC__DENTIST_INTERFACE_PRESENT__1 1
+#define DC__GENERICA_PRESENT 1
+#define DC__GENERICA_PRESENT__1 1
+#define DC__GENERICB_PRESENT 1
+#define DC__GENERICB_PRESENT__1 1
+#define DC__GENERICC_PRESENT 0
+#define DC__GENERICC_PRESENT__0 1
+#define DC__GENERICD_PRESENT 0
+#define DC__GENERICD_PRESENT__0 1
+#define DC__GENERICE_PRESENT 0
+#define DC__GENERICE_PRESENT__0 1
+#define DC__GENERICF_PRESENT 0
+#define DC__GENERICF_PRESENT__0 1
+#define DC__GENERICG_PRESENT 0
+#define DC__GENERICG_PRESENT__0 1
+#define DC__UNIPHY_VOLTAGE_MODE 1
+#define DC__UNIPHY_VOLTAGE_MODE__1 1
+#define DC__BLON_TYPE dedicated
+#define DC__BLON_TYPE__DEDICATED 1
+#define DC__UNIPHY_STAGGER_CH_PRESENT 1
+#define DC__UNIPHY_STAGGER_CH_PRESENT__1 1
+#define DC__XDMA_PRESENT 0
+#define DC__XDMA_PRESENT__0 1
+#define XDMA__PRESENT 0
+#define XDMA__PRESENT__0 1
+#define DC__DP_MEM_PG 0
+#define DC__DP_MEM_PG__0 1
+#define DP__MEM_PG 0
+#define DP__MEM_PG__0 1
+#define DC__AFMT_MEM_PG 0
+#define DC__AFMT_MEM_PG__0 1
+#define AFMT__MEM_PG 0
+#define AFMT__MEM_PG__0 1
+#define DC__HDMI_MEM_PG 0
+#define DC__HDMI_MEM_PG__0 1
+#define HDMI__MEM_PG 0
+#define HDMI__MEM_PG__0 1
+#define DC__I2C_MEM_PG 0
+#define DC__I2C_MEM_PG__0 1
+#define I2C__MEM_PG 0
+#define I2C__MEM_PG__0 1
+#define DC__DSCL_MEM_PG 0
+#define DC__DSCL_MEM_PG__0 1
+#define DSCL__MEM_PG 0
+#define DSCL__MEM_PG__0 1
+#define DC__CM_MEM_PG 0
+#define DC__CM_MEM_PG__0 1
+#define CM__MEM_PG 0
+#define CM__MEM_PG__0 1
+#define DC__OBUF_MEM_PG 0
+#define DC__OBUF_MEM_PG__0 1
+#define OBUF__MEM_PG 0
+#define OBUF__MEM_PG__0 1
+#define DC__WBIF_MEM_PG 1
+#define DC__WBIF_MEM_PG__1 1
+#define WBIF__MEM_PG 1
+#define WBIF__MEM_PG__1 1
+#define DC__VGA_MEM_PG 0
+#define DC__VGA_MEM_PG__0 1
+#define VGA__MEM_PG 0
+#define VGA__MEM_PG__0 1
+#define DC__FMT_MEM_PG 0
+#define DC__FMT_MEM_PG__0 1
+#define FMT__MEM_PG 0
+#define FMT__MEM_PG__0 1
+#define DC__ODM_MEM_PG 0
+#define DC__ODM_MEM_PG__0 1
+#define ODM__MEM_PG 0
+#define ODM__MEM_PG__0 1
+#define DC__DSI_MEM_PG 0
+#define DC__DSI_MEM_PG__0 1
+#define DSI__MEM_PG 0
+#define DSI__MEM_PG__0 1
+#define DC__AZ_MEM_PG 1
+#define DC__AZ_MEM_PG__1 1
+#define AZ__MEM_PG 1
+#define AZ__MEM_PG__1 1
+#define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1
+#define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1
+#define WBSCL_MEM1P1024X64QS__MEM_PG 1
+#define WBSCL_MEM1P1024X64QS__MEM_PG__1 1
+#define DC__WBSCL_MEM1P528X64QS_MEM_PG 1
+#define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1
+#define WBSCL_MEM1P528X64QS__MEM_PG 1
+#define WBSCL_MEM1P528X64QS__MEM_PG__1 1
+#define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1
+#define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1
+#define DMCU_MEM1P1024X32BQS__MEM_PG 1
+#define DMCU_MEM1P1024X32BQS__MEM_PG__1 1
+#define DC__HUBBUB_SDP_TAG_INT_MEM_PG 0
+#define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1
+#define HUBBUB_SDP_TAG_INT__MEM_PG 0
+#define HUBBUB_SDP_TAG_INT__MEM_PG__0 1
+#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG 0
+#define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1
+#define HUBBUB_SDP_TAG_EXT__MEM_PG 0
+#define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1
+#define DC__HUBBUB_RET_ZERO_MEM_PG 0
+#define DC__HUBBUB_RET_ZERO_MEM_PG__0 1
+#define HUBBUB_RET_ZERO__MEM_PG 0
+#define HUBBUB_RET_ZERO__MEM_PG__0 1
+#define DC__HUBBUB_RET_ROB_MEM_PG 0
+#define DC__HUBBUB_RET_ROB_MEM_PG__0 1
+#define HUBBUB_RET_ROB__MEM_PG 0
+#define HUBBUB_RET_ROB__MEM_PG__0 1
+#define DC__HUBPRET_CUR_ROB_MEM_PG 0
+#define DC__HUBPRET_CUR_ROB_MEM_PG__0 1
+#define HUBPRET_CUR_ROB__MEM_PG 0
+#define HUBPRET_CUR_ROB__MEM_PG__0 1
+#define DC__HUBPRET_CUR_CDC_MEM_PG 0
+#define DC__HUBPRET_CUR_CDC_MEM_PG__0 1
+#define HUBPRET_CUR_CDC__MEM_PG 0
+#define HUBPRET_CUR_CDC__MEM_PG__0 1
+#define DC__HUBPREQ_MPTE_MEM_PG 0
+#define DC__HUBPREQ_MPTE_MEM_PG__0 1
+#define HUBPREQ_MPTE__MEM_PG 0
+#define HUBPREQ_MPTE__MEM_PG__0 1
+#define DC__HUBPREQ_META_MEM_PG 0
+#define DC__HUBPREQ_META_MEM_PG__0 1
+#define HUBPREQ_META__MEM_PG 0
+#define HUBPREQ_META__MEM_PG__0 1
+#define DC__HUBPREQ_DPTE_MEM_PG 0
+#define DC__HUBPREQ_DPTE_MEM_PG__0 1
+#define HUBPREQ_DPTE__MEM_PG 0
+#define HUBPREQ_DPTE__MEM_PG__0 1
+#define DC__HUBPRET_DET_MEM_PG 0
+#define DC__HUBPRET_DET_MEM_PG__0 1
+#define HUBPRET_DET__MEM_PG 0
+#define HUBPRET_DET__MEM_PG__0 1
+#define DC__HUBPRET_PIX_CDC_MEM_PG 0
+#define DC__HUBPRET_PIX_CDC_MEM_PG__0 1
+#define HUBPRET_PIX_CDC__MEM_PG 0
+#define HUBPRET_PIX_CDC__MEM_PG__0 1
+#define DC__TOP_BLKS__DCCG 1
+#define DC__TOP_BLKS__DCHUBBUB 1
+#define DC__TOP_BLKS__DCHUBP 1
+#define DC__TOP_BLKS__HDA 1
+#define DC__TOP_BLKS__DIO 1
+#define DC__TOP_BLKS__DCIO 1
+#define DC__TOP_BLKS__DMU 1
+#define DC__TOP_BLKS__DPP 1
+#define DC__TOP_BLKS__MPC 1
+#define DC__TOP_BLKS__OPP 1
+#define DC__TOP_BLKS__OPTC 1
+#define DC__TOP_BLKS__MMHUBBUB 1
+#define DC__TOP_BLKS__WB 1
+#define DC__TOP_BLKS__MAX 13
+#define DC__TOP_BLKS__MAX__13 1
+#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS 9
+#define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1
+#define DC__DPP_MPC_SF_PIXEL_CREDITS 9
+#define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1
+#define DC__MPC_OPP_SF_PIXEL_CREDITS 8
+#define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1
+#define DC__OPP_OPTC_SF_PIXEL_CREDITS 8
+#define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1
+#define DC__SFR_SFT_ROUND_TRIP_DELAY 5
+#define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1
+#define DC__REPEATER_PROJECT_MAX 8
+#define DC__REPEATER_PROJECT_MAX__8 1
+#define DC__SURFACE_422_CAPABLE 0
+#define DC__SURFACE_422_CAPABLE__0 1
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
new file mode 100644
index 0000000..143a3d4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_ENUMS_H__
+#define __DISPLAY_MODE_ENUMS_H__
+enum output_encoder_class {
+ dm_dp = 0,
+ dm_hdmi = 1,
+ dm_wb = 2
+};
+enum output_format_class {
+ dm_444 = 0,
+ dm_420 = 1
+};
+enum source_format_class {
+ dm_444_16 = 0,
+ dm_444_32 = 1,
+ dm_444_64 = 2,
+ dm_420_8 = 3,
+ dm_420_10 = 4,
+ dm_422_8 = 5,
+ dm_422_10 = 6
+};
+enum output_bpc_class {
+ dm_out_6 = 0,
+ dm_out_8 = 1,
+ dm_out_10 = 2,
+ dm_out_12 = 3,
+ dm_out_16 = 4
+};
+enum scan_direction_class {
+ dm_horz = 0,
+ dm_vert = 1
+};
+enum dm_swizzle_mode {
+ dm_sw_linear = 0,
+ dm_sw_256b_s = 1,
+ dm_sw_256b_d = 2,
+ dm_sw_SPARE_0 = 3,
+ dm_sw_SPARE_1 = 4,
+ dm_sw_4kb_s = 5,
+ dm_sw_4kb_d = 6,
+ dm_sw_SPARE_2 = 7,
+ dm_sw_SPARE_3 = 8,
+ dm_sw_64kb_s = 9,
+ dm_sw_64kb_d = 10,
+ dm_sw_SPARE_4 = 11,
+ dm_sw_SPARE_5 = 12,
+ dm_sw_var_s = 13,
+ dm_sw_var_d = 14,
+ dm_sw_SPARE_6 = 15,
+ dm_sw_SPARE_7 = 16,
+ dm_sw_64kb_s_t = 17,
+ dm_sw_64kb_d_t = 18,
+ dm_sw_SPARE_10 = 19,
+ dm_sw_SPARE_11 = 20,
+ dm_sw_4kb_s_x = 21,
+ dm_sw_4kb_d_x = 22,
+ dm_sw_SPARE_12 = 23,
+ dm_sw_SPARE_13 = 24,
+ dm_sw_64kb_s_x = 25,
+ dm_sw_64kb_d_x = 26,
+ dm_sw_SPARE_14 = 27,
+ dm_sw_SPARE_15 = 28,
+ dm_sw_var_s_x = 29,
+ dm_sw_var_d_x = 30
+};
+enum lb_depth {
+ dm_lb_10 = 30,
+ dm_lb_8 = 24,
+ dm_lb_6 = 18,
+ dm_lb_12 = 36
+};
+enum voltage_state {
+ dm_vmin = 0,
+ dm_vmid = 1,
+ dm_vnom = 2,
+ dm_vmax = 3,
+ dm_vmax_exceeded = 4
+};
+enum source_macro_tile_size {
+ dm_4k_tile = 0,
+ dm_64k_tile = 1,
+ dm_256k_tile = 2
+};
+enum cursor_bpp {
+ dm_cur_2bit = 0,
+ dm_cur_32bit = 1
+};
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
new file mode 100644
index 0000000..c02c552
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "display_mode_lib.h"
+
+static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
+{
+ if (project == DML_PROJECT_RAVEN1) {
+ soc->sr_exit_time_us = 9.0;
+ soc->sr_enter_plus_exit_time_us = 11.0;
+ soc->urgent_latency_us = 4.0;
+ soc->writeback_latency_us = 12.0;
+ soc->ideal_dram_bw_after_urgent_percent = 80.0;
+ soc->max_request_size_bytes = 256;
+
+ soc->vmin.dcfclk_mhz = 300.0;
+ soc->vmin.dispclk_mhz = 608.0;
+ soc->vmin.dppclk_mhz = 435.0;
+ soc->vmin.dram_bw_per_chan_gbps = 12.8;
+ soc->vmin.phyclk_mhz = 540.0;
+ soc->vmin.socclk_mhz = 208.0;
+
+ soc->vmid.dcfclk_mhz = 600.0;
+ soc->vmid.dispclk_mhz = 661.0;
+ soc->vmid.dppclk_mhz = 661.0;
+ soc->vmid.dram_bw_per_chan_gbps = 12.8;
+ soc->vmid.phyclk_mhz = 540.0;
+ soc->vmid.socclk_mhz = 208.0;
+
+ soc->vnom.dcfclk_mhz = 600.0;
+ soc->vnom.dispclk_mhz = 661.0;
+ soc->vnom.dppclk_mhz = 661.0;
+ soc->vnom.dram_bw_per_chan_gbps = 38.4;
+ soc->vnom.phyclk_mhz = 810;
+ soc->vnom.socclk_mhz = 208.0;
+
+ soc->vmax.dcfclk_mhz = 600.0;
+ soc->vmax.dispclk_mhz = 1086.0;
+ soc->vmax.dppclk_mhz = 661.0;
+ soc->vmax.dram_bw_per_chan_gbps = 38.4;
+ soc->vmax.phyclk_mhz = 810.0;
+ soc->vmax.socclk_mhz = 208.0;
+
+ soc->downspread_percent = 0.5;
+ soc->dram_page_open_time_ns = 50.0;
+ soc->dram_rw_turnaround_time_ns = 17.5;
+ soc->dram_return_buffer_per_channel_bytes = 8192;
+ soc->round_trip_ping_latency_dcfclk_cycles = 128;
+ soc->urgent_out_of_order_return_per_channel_bytes = 256;
+ soc->channel_interleave_bytes = 256;
+ soc->num_banks = 8;
+ soc->num_chans = 2;
+ soc->vmm_page_size_bytes = 4096;
+ soc->dram_clock_change_latency_us = 17.0;
+ soc->writeback_dram_clock_change_latency_us = 23.0;
+ soc->return_bus_width_bytes = 64;
+ } else {
+ BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+ }
+}
+
+static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
+{
+ if (project == DML_PROJECT_RAVEN1) {
+ ip->rob_buffer_size_kbytes = 64;
+ ip->det_buffer_size_kbytes = 164;
+ ip->dpte_buffer_size_in_pte_reqs = 42;
+ ip->dpp_output_buffer_pixels = 2560;
+ ip->opp_output_buffer_lines = 1;
+ ip->pixel_chunk_size_kbytes = 8;
+ ip->pte_enable = 1;
+ ip->pte_chunk_size_kbytes = 2;
+ ip->meta_chunk_size_kbytes = 2;
+ ip->writeback_chunk_size_kbytes = 2;
+ ip->line_buffer_size_bits = 589824;
+ ip->max_line_buffer_lines = 12;
+ ip->IsLineBufferBppFixed = 0;
+ ip->LineBufferFixedBpp = -1;
+ ip->writeback_luma_buffer_size_kbytes = 12;
+ ip->writeback_chroma_buffer_size_kbytes = 8;
+ ip->max_num_dpp = 4;
+ ip->max_num_wb = 2;
+ ip->max_dchub_pscl_bw_pix_per_clk = 4;
+ ip->max_pscl_lb_bw_pix_per_clk = 2;
+ ip->max_lb_vscl_bw_pix_per_clk = 4;
+ ip->max_vscl_hscl_bw_pix_per_clk = 4;
+ ip->max_hscl_ratio = 4;
+ ip->max_vscl_ratio = 4;
+ ip->hscl_mults = 4;
+ ip->vscl_mults = 4;
+ ip->max_hscl_taps = 8;
+ ip->max_vscl_taps = 8;
+ ip->dispclk_ramp_margin_percent = 1;
+ ip->underscan_factor = 1.10;
+ ip->min_vblank_lines = 14;
+ ip->dppclk_delay_subtotal = 90;
+ ip->dispclk_delay_subtotal = 42;
+ ip->dcfclk_cstate_latency = 10;
+ ip->max_inter_dcn_tile_repeaters = 8;
+ ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
+ ip->bug_forcing_LC_req_same_size_fixed = 0;
+ } else {
+ BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+ }
+}
+
+static void set_mode_evaluation(struct _vcs_dpi_mode_evaluation_st *me, enum dml_project project)
+{
+ if (project == DML_PROJECT_RAVEN1) {
+ me->voltage_override = dm_vmin;
+ } else {
+ BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+ }
+}
+
+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
+{
+ if (lib->project != project) {
+ set_soc_bounding_box(&lib->soc, project);
+ set_ip_params(&lib->ip, project);
+ set_mode_evaluation(&lib->me, project);
+ lib->project = project;
+ }
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
new file mode 100644
index 0000000..e2e3111
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_LIB_H__
+#define __DISPLAY_MODE_LIB_H__
+
+#include "dml_common_defs.h"
+#include "soc_bounding_box.h"
+#include "display_watermark.h"
+#include "display_pipe_clocks.h"
+#include "display_rq_dlg_calc.h"
+#include "display_mode_support.h"
+
+enum dml_project {
+ DML_PROJECT_UNDEFINED,
+ DML_PROJECT_RAVEN1
+};
+
+struct display_mode_lib {
+ struct _vcs_dpi_ip_params_st ip;
+ struct _vcs_dpi_soc_bounding_box_st soc;
+ struct _vcs_dpi_mode_evaluation_st me;
+ enum dml_project project;
+ struct dml_ms_internal_vars vars;
+ struct _vcs_dpi_wm_calc_pipe_params_st wm_param[DC__NUM_PIPES__MAX];
+ struct dal_logger *logger;
+};
+
+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
new file mode 100644
index 0000000..e589a5e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -0,0 +1,429 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_STRUCTS_H__
+#define __DISPLAY_MODE_STRUCTS_H__
+
+struct _vcs_dpi_voltage_scaling_st {
+ double dcfclk_mhz;
+ double dispclk_mhz;
+ double dppclk_mhz;
+ double dram_bw_per_chan_gbps;
+ double phyclk_mhz;
+ double socclk_mhz;
+};
+
+struct _vcs_dpi_soc_bounding_box_st {
+ double sr_exit_time_us;
+ double sr_enter_plus_exit_time_us;
+ double urgent_latency_us;
+ double writeback_latency_us;
+ double ideal_dram_bw_after_urgent_percent;
+ unsigned int max_request_size_bytes;
+ struct _vcs_dpi_voltage_scaling_st vmin;
+ struct _vcs_dpi_voltage_scaling_st vmid;
+ struct _vcs_dpi_voltage_scaling_st vnom;
+ struct _vcs_dpi_voltage_scaling_st vmax;
+ double downspread_percent;
+ double dram_page_open_time_ns;
+ double dram_rw_turnaround_time_ns;
+ double dram_return_buffer_per_channel_bytes;
+ unsigned int round_trip_ping_latency_dcfclk_cycles;
+ unsigned int urgent_out_of_order_return_per_channel_bytes;
+ unsigned int channel_interleave_bytes;
+ unsigned int num_banks;
+ unsigned int num_chans;
+ unsigned int vmm_page_size_bytes;
+ double dram_clock_change_latency_us;
+ double writeback_dram_clock_change_latency_us;
+ unsigned int return_bus_width_bytes;
+};
+
+struct _vcs_dpi_ip_params_st {
+ unsigned int rob_buffer_size_kbytes;
+ unsigned int det_buffer_size_kbytes;
+ unsigned int dpte_buffer_size_in_pte_reqs;
+ unsigned int dpp_output_buffer_pixels;
+ unsigned int opp_output_buffer_lines;
+ unsigned int pixel_chunk_size_kbytes;
+ unsigned char pte_enable;
+ unsigned int pte_chunk_size_kbytes;
+ unsigned int meta_chunk_size_kbytes;
+ unsigned int writeback_chunk_size_kbytes;
+ unsigned int line_buffer_size_bits;
+ unsigned int max_line_buffer_lines;
+ unsigned int IsLineBufferBppFixed;
+ unsigned int LineBufferFixedBpp;
+ unsigned int writeback_luma_buffer_size_kbytes;
+ unsigned int writeback_chroma_buffer_size_kbytes;
+ unsigned int max_num_dpp;
+ unsigned int max_num_wb;
+ unsigned int max_dchub_pscl_bw_pix_per_clk;
+ unsigned int max_pscl_lb_bw_pix_per_clk;
+ unsigned int max_lb_vscl_bw_pix_per_clk;
+ unsigned int max_vscl_hscl_bw_pix_per_clk;
+ double max_hscl_ratio;
+ double max_vscl_ratio;
+ unsigned int hscl_mults;
+ unsigned int vscl_mults;
+ unsigned int max_hscl_taps;
+ unsigned int max_vscl_taps;
+ double dispclk_ramp_margin_percent;
+ double underscan_factor;
+ unsigned int min_vblank_lines;
+ unsigned int dppclk_delay_subtotal;
+ unsigned int dispclk_delay_subtotal;
+ unsigned int dcfclk_cstate_latency;
+ unsigned int max_inter_dcn_tile_repeaters;
+ unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
+ unsigned int bug_forcing_LC_req_same_size_fixed;
+};
+
+struct _vcs_dpi_display_pipe_source_params_st {
+ int source_format;
+ unsigned char dcc;
+ unsigned int dcc_rate;
+ unsigned char vm;
+ int source_scan;
+ int sw_mode;
+ int macro_tile_size;
+ unsigned char is_display_sw;
+ unsigned int viewport_width;
+ unsigned int viewport_height;
+ unsigned int viewport_width_c;
+ unsigned int viewport_height_c;
+ unsigned int data_pitch;
+ unsigned int data_pitch_c;
+ unsigned int meta_pitch;
+ unsigned int meta_pitch_c;
+ unsigned int cur0_src_width;
+ int cur0_bpp;
+ unsigned char is_hsplit;
+ unsigned int hsplit_grp;
+};
+
+struct _vcs_dpi_display_output_params_st {
+ int output_bpc;
+ int output_type;
+ int output_format;
+ int output_standard;
+};
+
+struct _vcs_dpi_display_bandwidth_st {
+ double total_bw_consumed_gbps;
+ double guaranteed_urgent_return_bw_gbps;
+};
+
+struct _vcs_dpi_scaler_ratio_depth_st {
+ double hscl_ratio;
+ double vscl_ratio;
+ double hscl_ratio_c;
+ double vscl_ratio_c;
+ double vinit;
+ double vinit_c;
+ double vinit_bot;
+ double vinit_bot_c;
+ int lb_depth;
+};
+
+struct _vcs_dpi_scaler_taps_st {
+ unsigned int htaps;
+ unsigned int vtaps;
+ unsigned int htaps_c;
+ unsigned int vtaps_c;
+};
+
+struct _vcs_dpi_display_pipe_dest_params_st {
+ unsigned int recout_width;
+ unsigned int recout_height;
+ unsigned int full_recout_width;
+ unsigned int full_recout_height;
+ unsigned int hblank_start;
+ unsigned int hblank_end;
+ unsigned int vblank_start;
+ unsigned int vblank_end;
+ unsigned int htotal;
+ unsigned int vtotal;
+ unsigned int vactive;
+ unsigned int vstartup_start;
+ unsigned int vupdate_offset;
+ unsigned int vupdate_width;
+ unsigned int vready_offset;
+ unsigned int vsync_plus_back_porch;
+ unsigned char interlaced;
+ unsigned char underscan;
+ double pixel_rate_mhz;
+ unsigned char syncronized_vblank_all_planes;
+};
+
+struct _vcs_dpi_display_pipe_params_st {
+ struct _vcs_dpi_display_pipe_source_params_st src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps;
+};
+
+struct _vcs_dpi_display_clocks_and_cfg_st {
+ int voltage;
+ double dppclk_mhz;
+ double refclk_mhz;
+ double dispclk_mhz;
+ double dcfclk_mhz;
+ double socclk_mhz;
+};
+
+struct _vcs_dpi_display_e2e_pipe_params_st {
+ struct _vcs_dpi_display_pipe_params_st pipe;
+ struct _vcs_dpi_display_output_params_st dout;
+ struct _vcs_dpi_display_clocks_and_cfg_st clks_cfg;
+};
+
+struct _vcs_dpi_dchub_buffer_sizing_st {
+ unsigned int swath_width_y;
+ unsigned int swath_height_y;
+ unsigned int swath_height_c;
+ unsigned int detail_buffer_size_y;
+};
+
+struct _vcs_dpi_watermarks_perf_st {
+ double stutter_eff_in_active_region_percent;
+ double urgent_latency_supported_us;
+ double non_urgent_latency_supported_us;
+ double dram_clock_change_margin_us;
+ double dram_access_eff_percent;
+};
+
+struct _vcs_dpi_cstate_pstate_watermarks_st {
+ double cstate_exit_us;
+ double cstate_enter_plus_exit_us;
+ double pstate_change_us;
+};
+
+struct _vcs_dpi_wm_calc_pipe_params_st {
+ unsigned int num_dpp;
+ int voltage;
+ int output_type;
+ double dcfclk_mhz;
+ double socclk_mhz;
+ double dppclk_mhz;
+ double pixclk_mhz;
+ unsigned char interlace_en;
+ unsigned char pte_enable;
+ unsigned char dcc_enable;
+ double dcc_rate;
+ double bytes_per_pixel_c;
+ double bytes_per_pixel_y;
+ unsigned int swath_width_y;
+ unsigned int swath_height_y;
+ unsigned int swath_height_c;
+ unsigned int det_buffer_size_y;
+ double h_ratio;
+ double v_ratio;
+ unsigned int h_taps;
+ unsigned int h_total;
+ unsigned int v_total;
+ unsigned int v_active;
+ unsigned int e2e_index;
+ double display_pipe_line_delivery_time;
+ double read_bw;
+ unsigned int lines_in_det_y;
+ unsigned int lines_in_det_y_rounded_down_to_swath;
+ double full_det_buffering_time;
+ double dcfclk_deepsleep_mhz_per_plane;
+};
+
+struct _vcs_dpi_vratio_pre_st {
+ double vratio_pre_l;
+ double vratio_pre_c;
+};
+
+struct _vcs_dpi_display_data_rq_misc_params_st {
+ unsigned int full_swath_bytes;
+ unsigned int stored_swath_bytes;
+ unsigned int blk256_height;
+ unsigned int blk256_width;
+ unsigned int req_height;
+ unsigned int req_width;
+};
+
+struct _vcs_dpi_display_data_rq_sizing_params_st {
+ unsigned int chunk_bytes;
+ unsigned int min_chunk_bytes;
+ unsigned int meta_chunk_bytes;
+ unsigned int min_meta_chunk_bytes;
+ unsigned int mpte_group_bytes;
+ unsigned int dpte_group_bytes;
+};
+
+struct _vcs_dpi_display_data_rq_dlg_params_st {
+ unsigned int swath_width_ub;
+ unsigned int swath_height;
+ unsigned int req_per_swath_ub;
+ unsigned int meta_pte_bytes_per_frame_ub;
+ unsigned int dpte_req_per_row_ub;
+ unsigned int dpte_groups_per_row_ub;
+ unsigned int dpte_row_height;
+ unsigned int dpte_bytes_per_row_ub;
+ unsigned int meta_chunks_per_row_ub;
+ unsigned int meta_req_per_row_ub;
+ unsigned int meta_row_height;
+ unsigned int meta_bytes_per_row_ub;
+};
+
+struct _vcs_dpi_display_cur_rq_dlg_params_st {
+ unsigned char enable;
+ unsigned int swath_height;
+ unsigned int req_per_line;
+};
+
+struct _vcs_dpi_display_rq_dlg_params_st {
+ struct _vcs_dpi_display_data_rq_dlg_params_st rq_l;
+ struct _vcs_dpi_display_data_rq_dlg_params_st rq_c;
+ struct _vcs_dpi_display_cur_rq_dlg_params_st rq_cur0;
+};
+
+struct _vcs_dpi_display_rq_sizing_params_st {
+ struct _vcs_dpi_display_data_rq_sizing_params_st rq_l;
+ struct _vcs_dpi_display_data_rq_sizing_params_st rq_c;
+};
+
+struct _vcs_dpi_display_rq_misc_params_st {
+ struct _vcs_dpi_display_data_rq_misc_params_st rq_l;
+ struct _vcs_dpi_display_data_rq_misc_params_st rq_c;
+};
+
+struct _vcs_dpi_display_rq_params_st {
+ unsigned char yuv420;
+ unsigned char yuv420_10bpc;
+ struct _vcs_dpi_display_rq_misc_params_st misc;
+ struct _vcs_dpi_display_rq_sizing_params_st sizing;
+ struct _vcs_dpi_display_rq_dlg_params_st dlg;
+};
+
+struct _vcs_dpi_display_dlg_regs_st {
+ unsigned int refcyc_h_blank_end;
+ unsigned int dlg_vblank_end;
+ unsigned int min_dst_y_next_start;
+ unsigned int refcyc_per_htotal;
+ unsigned int refcyc_x_after_scaler;
+ unsigned int dst_y_after_scaler;
+ unsigned int dst_y_prefetch;
+ unsigned int dst_y_per_vm_vblank;
+ unsigned int dst_y_per_row_vblank;
+ unsigned int ref_freq_to_pix_freq;
+ unsigned int vratio_prefetch;
+ unsigned int vratio_prefetch_c;
+ unsigned int refcyc_per_pte_group_vblank_l;
+ unsigned int refcyc_per_pte_group_vblank_c;
+ unsigned int refcyc_per_meta_chunk_vblank_l;
+ unsigned int refcyc_per_meta_chunk_vblank_c;
+ unsigned int dst_y_per_pte_row_nom_l;
+ unsigned int dst_y_per_pte_row_nom_c;
+ unsigned int refcyc_per_pte_group_nom_l;
+ unsigned int refcyc_per_pte_group_nom_c;
+ unsigned int dst_y_per_meta_row_nom_l;
+ unsigned int dst_y_per_meta_row_nom_c;
+ unsigned int refcyc_per_meta_chunk_nom_l;
+ unsigned int refcyc_per_meta_chunk_nom_c;
+ unsigned int refcyc_per_line_delivery_pre_l;
+ unsigned int refcyc_per_line_delivery_pre_c;
+ unsigned int refcyc_per_line_delivery_l;
+ unsigned int refcyc_per_line_delivery_c;
+ unsigned int chunk_hdl_adjust_cur0;
+};
+
+struct _vcs_dpi_display_ttu_regs_st {
+ unsigned int qos_level_low_wm;
+ unsigned int qos_level_high_wm;
+ unsigned int min_ttu_vblank;
+ unsigned int qos_level_flip;
+ unsigned int refcyc_per_req_delivery_l;
+ unsigned int refcyc_per_req_delivery_c;
+ unsigned int refcyc_per_req_delivery_cur0;
+ unsigned int refcyc_per_req_delivery_pre_l;
+ unsigned int refcyc_per_req_delivery_pre_c;
+ unsigned int refcyc_per_req_delivery_pre_cur0;
+ unsigned int qos_level_fixed_l;
+ unsigned int qos_level_fixed_c;
+ unsigned int qos_level_fixed_cur0;
+ unsigned int qos_ramp_disable_l;
+ unsigned int qos_ramp_disable_c;
+ unsigned int qos_ramp_disable_cur0;
+};
+
+struct _vcs_dpi_display_data_rq_regs_st {
+ unsigned int chunk_size;
+ unsigned int min_chunk_size;
+ unsigned int meta_chunk_size;
+ unsigned int min_meta_chunk_size;
+ unsigned int dpte_group_size;
+ unsigned int mpte_group_size;
+ unsigned int swath_height;
+ unsigned int pte_row_height_linear;
+};
+
+struct _vcs_dpi_display_rq_regs_st {
+ struct _vcs_dpi_display_data_rq_regs_st rq_regs_l;
+ struct _vcs_dpi_display_data_rq_regs_st rq_regs_c;
+ unsigned int drq_expansion_mode;
+ unsigned int prq_expansion_mode;
+ unsigned int mrq_expansion_mode;
+ unsigned int crq_expansion_mode;
+ unsigned int plane1_base_address;
+};
+
+struct _vcs_dpi_display_dlg_sys_params_st {
+ double t_mclk_wm_us;
+ double t_urg_wm_us;
+ double t_sr_wm_us;
+ double t_extra_us;
+ double t_srx_delay_us;
+ double deepsleep_dcfclk_mhz;
+ double total_flip_bw;
+ unsigned int total_flip_bytes;
+};
+
+struct _vcs_dpi_display_dlg_prefetch_param_st {
+ double prefetch_bw;
+ unsigned int flip_bytes;
+};
+
+struct _vcs_dpi_display_pipe_clock_st {
+ double dcfclk_mhz;
+ double dispclk_mhz;
+ double dppclk_mhz[4];
+ unsigned char dppclk_div[4];
+};
+
+struct _vcs_dpi_display_arb_params_st {
+ int max_req_outstanding;
+ int min_req_outstanding;
+ int sat_level_us;
+};
+
+struct _vcs_dpi_mode_evaluation_st {
+ int voltage_override;
+};
+
+#endif /*__DISPLAY_MODE_STRUCTS_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
new file mode 100644
index 0000000..3b4ee74
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
@@ -0,0 +1,2326 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "display_mode_support.h"
+#include "display_mode_lib.h"
+
+int dml_ms_check(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ int num_pipes)
+{
+ struct _vcs_dpi_ip_params_st *ip;
+ struct _vcs_dpi_soc_bounding_box_st *soc;
+ struct _vcs_dpi_mode_evaluation_st *me;
+ struct dml_ms_internal_vars *v;
+ int num_planes, i, j, ij, k, ijk;
+
+ ip = &(mode_lib->ip);
+ soc = &(mode_lib->soc);
+ me = &(mode_lib->me);
+ v = &(mode_lib->vars);
+ num_planes = dml_wm_e2e_to_wm(mode_lib, e2e, num_pipes, v->planes);
+
+ //instantiating variables to zero
+ v->MacroTileBlockWidthC = 0;
+ v->SwathWidthGranularityC = 0;
+
+ v->DCFCLKPerState[5] = 0;
+ v->DCFCLKPerState[4] = 0;
+ v->DCFCLKPerState[3] = 0;
+ v->DCFCLKPerState[2] = 0;
+ v->DCFCLKPerState[1] = 0;
+ v->DCFCLKPerState[0] = 0;
+
+ if (soc->vmin.dcfclk_mhz > 0) {
+ v->DCFCLKPerState[5] = soc->vmin.dcfclk_mhz;
+ v->DCFCLKPerState[4] = soc->vmin.dcfclk_mhz;
+ v->DCFCLKPerState[3] = soc->vmin.dcfclk_mhz;
+ v->DCFCLKPerState[2] = soc->vmin.dcfclk_mhz;
+ v->DCFCLKPerState[1] = soc->vmin.dcfclk_mhz;
+ v->DCFCLKPerState[0] = soc->vmin.dcfclk_mhz;
+ }
+
+ if (soc->vmid.dcfclk_mhz > 0) {
+ v->DCFCLKPerState[5] = soc->vmid.dcfclk_mhz;
+ v->DCFCLKPerState[4] = soc->vmid.dcfclk_mhz;
+ v->DCFCLKPerState[3] = soc->vmid.dcfclk_mhz;
+ v->DCFCLKPerState[2] = soc->vmid.dcfclk_mhz;
+ v->DCFCLKPerState[1] = soc->vmid.dcfclk_mhz;
+ }
+
+ if (soc->vnom.dcfclk_mhz > 0) {
+ v->DCFCLKPerState[5] = soc->vnom.dcfclk_mhz;
+ v->DCFCLKPerState[4] = soc->vnom.dcfclk_mhz;
+ v->DCFCLKPerState[3] = soc->vnom.dcfclk_mhz;
+ v->DCFCLKPerState[2] = soc->vnom.dcfclk_mhz;
+ }
+
+ if (soc->vmax.dcfclk_mhz > 0) {
+ v->DCFCLKPerState[5] = soc->vmax.dcfclk_mhz;
+ v->DCFCLKPerState[4] = soc->vmax.dcfclk_mhz;
+ v->DCFCLKPerState[3] = soc->vmax.dcfclk_mhz;
+ }
+
+ v->FabricAndDRAMBandwidthPerState[5] = 0;
+ v->FabricAndDRAMBandwidthPerState[4] = 0;
+ v->FabricAndDRAMBandwidthPerState[3] = 0;
+ v->FabricAndDRAMBandwidthPerState[2] = 0;
+ v->FabricAndDRAMBandwidthPerState[1] = 0;
+ v->FabricAndDRAMBandwidthPerState[0] = 0;
+
+ if (soc->vmin.dram_bw_per_chan_gbps > 0) {
+ v->FabricAndDRAMBandwidthPerState[5] = soc->vmin.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[4] = soc->vmin.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[3] = soc->vmin.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[2] = soc->vmin.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[1] = soc->vmin.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[0] = soc->vmin.dram_bw_per_chan_gbps;
+ }
+
+ if (soc->vmid.dram_bw_per_chan_gbps > 0) {
+ v->FabricAndDRAMBandwidthPerState[5] = soc->vmid.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[4] = soc->vmid.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[3] = soc->vmid.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[2] = soc->vmid.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[1] = soc->vmid.dram_bw_per_chan_gbps;
+ }
+
+ if (soc->vnom.dram_bw_per_chan_gbps > 0) {
+ v->FabricAndDRAMBandwidthPerState[5] = soc->vnom.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[4] = soc->vnom.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[3] = soc->vnom.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[2] = soc->vnom.dram_bw_per_chan_gbps;
+ }
+
+ if (soc->vmax.dram_bw_per_chan_gbps > 0) {
+ v->FabricAndDRAMBandwidthPerState[5] = soc->vmax.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[4] = soc->vmax.dram_bw_per_chan_gbps;
+ v->FabricAndDRAMBandwidthPerState[3] = soc->vmax.dram_bw_per_chan_gbps;
+ }
+
+ v->PHYCLKPerState[5] = 0;
+ v->PHYCLKPerState[4] = 0;
+ v->PHYCLKPerState[3] = 0;
+ v->PHYCLKPerState[2] = 0;
+ v->PHYCLKPerState[1] = 0;
+ v->PHYCLKPerState[0] = 0;
+
+ if (soc->vmin.phyclk_mhz > 0) {
+ v->PHYCLKPerState[5] = soc->vmin.phyclk_mhz;
+ v->PHYCLKPerState[4] = soc->vmin.phyclk_mhz;
+ v->PHYCLKPerState[3] = soc->vmin.phyclk_mhz;
+ v->PHYCLKPerState[2] = soc->vmin.phyclk_mhz;
+ v->PHYCLKPerState[1] = soc->vmin.phyclk_mhz;
+ v->PHYCLKPerState[0] = soc->vmin.phyclk_mhz;
+ }
+
+ if (soc->vmid.phyclk_mhz > 0) {
+ v->PHYCLKPerState[5] = soc->vmid.phyclk_mhz;
+ v->PHYCLKPerState[4] = soc->vmid.phyclk_mhz;
+ v->PHYCLKPerState[3] = soc->vmid.phyclk_mhz;
+ v->PHYCLKPerState[2] = soc->vmid.phyclk_mhz;
+ v->PHYCLKPerState[1] = soc->vmid.phyclk_mhz;
+ }
+
+ if (soc->vnom.phyclk_mhz > 0) {
+ v->PHYCLKPerState[5] = soc->vnom.phyclk_mhz;
+ v->PHYCLKPerState[4] = soc->vnom.phyclk_mhz;
+ v->PHYCLKPerState[3] = soc->vnom.phyclk_mhz;
+ v->PHYCLKPerState[2] = soc->vnom.phyclk_mhz;
+ }
+
+ if (soc->vmax.phyclk_mhz > 0) {
+ v->PHYCLKPerState[5] = soc->vmax.phyclk_mhz;
+ v->PHYCLKPerState[4] = soc->vmax.phyclk_mhz;
+ v->PHYCLKPerState[3] = soc->vmax.phyclk_mhz;
+ }
+
+ v->MaxDispclk[5] = 0;
+ v->MaxDispclk[4] = 0;
+ v->MaxDispclk[3] = 0;
+ v->MaxDispclk[2] = 0;
+ v->MaxDispclk[1] = 0;
+ v->MaxDispclk[0] = 0;
+
+ if (soc->vmin.dispclk_mhz > 0) {
+ v->MaxDispclk[5] = soc->vmin.dispclk_mhz;
+ v->MaxDispclk[4] = soc->vmin.dispclk_mhz;
+ v->MaxDispclk[3] = soc->vmin.dispclk_mhz;
+ v->MaxDispclk[2] = soc->vmin.dispclk_mhz;
+ v->MaxDispclk[1] = soc->vmin.dispclk_mhz;
+ v->MaxDispclk[0] = soc->vmin.dispclk_mhz;
+ }
+
+ if (soc->vmid.dispclk_mhz > 0) {
+ v->MaxDispclk[5] = soc->vmid.dispclk_mhz;
+ v->MaxDispclk[4] = soc->vmid.dispclk_mhz;
+ v->MaxDispclk[3] = soc->vmid.dispclk_mhz;
+ v->MaxDispclk[2] = soc->vmid.dispclk_mhz;
+ v->MaxDispclk[1] = soc->vmid.dispclk_mhz;
+ }
+
+ if (soc->vnom.dispclk_mhz > 0) {
+ v->MaxDispclk[5] = soc->vnom.dispclk_mhz;
+ v->MaxDispclk[4] = soc->vnom.dispclk_mhz;
+ v->MaxDispclk[3] = soc->vnom.dispclk_mhz;
+ v->MaxDispclk[2] = soc->vnom.dispclk_mhz;
+ }
+
+ if (soc->vmax.dispclk_mhz > 0) {
+ v->MaxDispclk[5] = soc->vmax.dispclk_mhz;
+ v->MaxDispclk[4] = soc->vmax.dispclk_mhz;
+ v->MaxDispclk[3] = soc->vmax.dispclk_mhz;
+ }
+
+ v->MaxDppclk[5] = 0;
+ v->MaxDppclk[4] = 0;
+ v->MaxDppclk[3] = 0;
+ v->MaxDppclk[2] = 0;
+ v->MaxDppclk[1] = 0;
+ v->MaxDppclk[0] = 0;
+
+ if (soc->vmin.dppclk_mhz > 0) {
+ v->MaxDppclk[5] = soc->vmin.dppclk_mhz;
+ v->MaxDppclk[4] = soc->vmin.dppclk_mhz;
+ v->MaxDppclk[3] = soc->vmin.dppclk_mhz;
+ v->MaxDppclk[2] = soc->vmin.dppclk_mhz;
+ v->MaxDppclk[1] = soc->vmin.dppclk_mhz;
+ v->MaxDppclk[0] = soc->vmin.dppclk_mhz;
+ }
+
+ if (soc->vmid.dppclk_mhz > 0) {
+ v->MaxDppclk[5] = soc->vmid.dppclk_mhz;
+ v->MaxDppclk[4] = soc->vmid.dppclk_mhz;
+ v->MaxDppclk[3] = soc->vmid.dppclk_mhz;
+ v->MaxDppclk[2] = soc->vmid.dppclk_mhz;
+ v->MaxDppclk[1] = soc->vmid.dppclk_mhz;
+ }
+
+ if (soc->vnom.dppclk_mhz > 0) {
+ v->MaxDppclk[5] = soc->vnom.dppclk_mhz;
+ v->MaxDppclk[4] = soc->vnom.dppclk_mhz;
+ v->MaxDppclk[3] = soc->vnom.dppclk_mhz;
+ v->MaxDppclk[2] = soc->vnom.dppclk_mhz;
+ }
+
+ if (soc->vmax.dppclk_mhz > 0) {
+ v->MaxDppclk[5] = soc->vmax.dppclk_mhz;
+ v->MaxDppclk[4] = soc->vmax.dppclk_mhz;
+ v->MaxDppclk[3] = soc->vmax.dppclk_mhz;
+ }
+
+ if (me->voltage_override == dm_vmax) {
+ v->VoltageOverrideLevel = NumberOfStates - 1;
+ } else if (me->voltage_override == dm_vnom) {
+ v->VoltageOverrideLevel = NumberOfStates - 2;
+ } else if (me->voltage_override == dm_vmid) {
+ v->VoltageOverrideLevel = NumberOfStates - 3;
+ } else {
+ v->VoltageOverrideLevel = 0;
+ }
+
+ // Scale Ratio Support Check
+
+ v->ScaleRatioSupport = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps =
+ e2e[v->planes[k].e2e_index].pipe.scale_taps;
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+
+ if (scale_ratio_depth.hscl_ratio > ip->max_hscl_ratio
+ || scale_ratio_depth.vscl_ratio > ip->max_vscl_ratio
+ || scale_ratio_depth.hscl_ratio > scale_taps.htaps
+ || scale_ratio_depth.vscl_ratio > scale_taps.vtaps
+ || (src.source_format != dm_444_64 && src.source_format != dm_444_32
+ && src.source_format != dm_444_16
+ && ((scale_ratio_depth.hscl_ratio / 2
+ > scale_taps.htaps_c)
+ || (scale_ratio_depth.vscl_ratio / 2
+ > scale_taps.vtaps_c))))
+
+ {
+ v->ScaleRatioSupport = 0;
+ }
+ }
+
+ // Source Format, Pixel Format and Scan Support Check
+
+ v->SourceFormatPixelAndScanSupport = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+
+ if ((src.sw_mode == dm_sw_linear && src.source_scan != dm_horz)
+ || ((src.sw_mode == dm_sw_4kb_d || src.sw_mode == dm_sw_4kb_d_x
+ || src.sw_mode == dm_sw_64kb_d
+ || src.sw_mode == dm_sw_64kb_d_t
+ || src.sw_mode == dm_sw_64kb_d_x
+ || src.sw_mode == dm_sw_var_d
+ || src.sw_mode == dm_sw_var_d_x)
+ && (src.source_format != dm_444_64))) {
+ v->SourceFormatPixelAndScanSupport = 0;
+ }
+ }
+
+ // Bandwidth Support Check
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+
+ if (src.source_scan == dm_horz) {
+ v->SwathWidthYSingleDPP[k] = src.viewport_width;
+ } else {
+ v->SwathWidthYSingleDPP[k] = src.viewport_height;
+ }
+
+ if (src.source_format == dm_444_64) {
+ v->BytePerPixelInDETY[k] = 8;
+ v->BytePerPixelInDETC[k] = 0;
+ } else if (src.source_format == dm_444_32) {
+ v->BytePerPixelInDETY[k] = 4;
+ v->BytePerPixelInDETC[k] = 0;
+ } else if (src.source_format == dm_444_16) {
+ v->BytePerPixelInDETY[k] = 2;
+ v->BytePerPixelInDETC[k] = 0;
+ } else if (src.source_format == dm_420_8) {
+ v->BytePerPixelInDETY[k] = 1;
+ v->BytePerPixelInDETC[k] = 2;
+ } else {
+ v->BytePerPixelInDETY[k] = 4.00 / 3.00;
+ v->BytePerPixelInDETC[k] = 8.00 / 3.00;
+ }
+ }
+
+ v->TotalReadBandwidthConsumedGBytePerSecond = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+
+ v->ReadBandwidth[k] =
+ v->SwathWidthYSingleDPP[k]
+ * (dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ * scale_ratio_depth.vscl_ratio
+ + (dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2) / 2)
+ * (scale_ratio_depth.vscl_ratio
+ / 2))
+ / (dest.htotal / dest.pixel_rate_mhz);
+
+ if (src.dcc == 1) {
+ v->ReadBandwidth[k] = v->ReadBandwidth[k] * (1 + 1 / 256);
+ }
+
+ if (ip->pte_enable == 1 && src.source_scan != dm_horz
+ && (src.sw_mode == dm_sw_4kb_s || src.sw_mode == dm_sw_4kb_s_x
+ || src.sw_mode == dm_sw_4kb_d
+ || src.sw_mode == dm_sw_4kb_d_x)) {
+ v->ReadBandwidth[k] = v->ReadBandwidth[k] * (1 + 1 / 64);
+ } else if (ip->pte_enable == 1 && src.source_scan == dm_horz
+ && (src.source_format == dm_444_64 || src.source_format == dm_444_32)
+ && (src.sw_mode == dm_sw_64kb_s || src.sw_mode == dm_sw_64kb_s_t
+ || src.sw_mode == dm_sw_64kb_s_x
+ || src.sw_mode == dm_sw_64kb_d
+ || src.sw_mode == dm_sw_64kb_d_t
+ || src.sw_mode == dm_sw_64kb_d_x)) {
+ v->ReadBandwidth[k] = v->ReadBandwidth[k] * (1 + 1 / 256);
+ } else if (ip->pte_enable == 1) {
+ v->ReadBandwidth[k] = v->ReadBandwidth[k] * (1 + 1 / 512);
+ }
+
+ v->TotalReadBandwidthConsumedGBytePerSecond =
+ v->TotalReadBandwidthConsumedGBytePerSecond
+ + v->ReadBandwidth[k] / 1000;
+ }
+
+ v->TotalWriteBandwidthConsumedGBytePerSecond = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_display_output_params_st dout = e2e[v->planes[k].e2e_index].dout;
+
+ if (dout.output_type == dm_wb && dout.output_format == dm_444) {
+ v->WriteBandwidth[k] = dest.recout_width
+ / (dest.htotal / dest.pixel_rate_mhz) * 4;
+ } else if (dout.output_type == dm_wb) {
+ v->WriteBandwidth[k] = dest.recout_width
+ / (dest.htotal / dest.pixel_rate_mhz) * 1.5;
+ } else {
+ v->WriteBandwidth[k] = 0;
+ }
+
+ v->TotalWriteBandwidthConsumedGBytePerSecond =
+ v->TotalWriteBandwidthConsumedGBytePerSecond
+ + v->WriteBandwidth[k] / 1000;
+ }
+
+ v->TotalBandwidthConsumedGBytePerSecond = v->TotalReadBandwidthConsumedGBytePerSecond
+ + v->TotalWriteBandwidthConsumedGBytePerSecond;
+
+ v->DCCEnabledInAnyPlane = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+
+ if (src.dcc == 1) {
+ v->DCCEnabledInAnyPlane = 1;
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ v->ReturnBWToDCNPerState = dml_min(
+ soc->return_bus_width_bytes * v->DCFCLKPerState[i],
+ v->FabricAndDRAMBandwidthPerState[i] * 1000
+ * soc->ideal_dram_bw_after_urgent_percent / 100);
+
+ v->ReturnBWPerState[i] = v->ReturnBWToDCNPerState;
+
+ if (v->DCCEnabledInAnyPlane == 1
+ && v->ReturnBWToDCNPerState
+ > (v->DCFCLKPerState[i]
+ * soc->return_bus_width_bytes / 4)) {
+ v->ReturnBWPerState[i] =
+ dml_min(
+ v->ReturnBWPerState[i],
+ v->ReturnBWToDCNPerState * 4
+ * (1
+ - soc->urgent_latency_us
+ / ((ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024
+ / (v->ReturnBWToDCNPerState
+ - v->DCFCLKPerState[i]
+ * soc->return_bus_width_bytes
+ / 4)
+ + soc->urgent_latency_us)));
+ }
+
+ v->CriticalPoint = 2 * soc->return_bus_width_bytes * v->DCFCLKPerState[i]
+ * soc->urgent_latency_us
+ / (v->ReturnBWToDCNPerState * soc->urgent_latency_us
+ + (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024);
+
+ if (v->DCCEnabledInAnyPlane == 1 && v->CriticalPoint > 1 && v->CriticalPoint < 4) {
+ v->ReturnBWPerState[i] =
+ dml_min(
+ v->ReturnBWPerState[i],
+ 4 * v->ReturnBWToDCNPerState
+ * (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024
+ * soc->return_bus_width_bytes
+ * v->DCFCLKPerState[i]
+ * soc->urgent_latency_us
+ / dml_pow(
+ (v->ReturnBWToDCNPerState
+ * soc->urgent_latency_us
+ + (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024),
+ 2));
+ }
+
+ v->ReturnBWToDCNPerState = dml_min(
+ soc->return_bus_width_bytes * v->DCFCLKPerState[i],
+ v->FabricAndDRAMBandwidthPerState[i] * 1000);
+
+ if (v->DCCEnabledInAnyPlane == 1
+ && v->ReturnBWToDCNPerState
+ > (v->DCFCLKPerState[i]
+ * soc->return_bus_width_bytes / 4)) {
+ v->ReturnBWPerState[i] =
+ dml_min(
+ v->ReturnBWPerState[i],
+ v->ReturnBWToDCNPerState * 4
+ * (1
+ - soc->urgent_latency_us
+ / ((ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024
+ / (v->ReturnBWToDCNPerState
+ - v->DCFCLKPerState[i]
+ * soc->return_bus_width_bytes
+ / 4)
+ + soc->urgent_latency_us)));
+ }
+
+ v->CriticalPoint = 2 * soc->return_bus_width_bytes * v->DCFCLKPerState[i]
+ * soc->urgent_latency_us
+ / (v->ReturnBWToDCNPerState * soc->urgent_latency_us
+ + (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024);
+
+ if (v->DCCEnabledInAnyPlane == 1 && v->CriticalPoint > 1 && v->CriticalPoint < 4) {
+ v->ReturnBWPerState[i] =
+ dml_min(
+ v->ReturnBWPerState[i],
+ 4 * v->ReturnBWToDCNPerState
+ * (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024
+ * soc->return_bus_width_bytes
+ * v->DCFCLKPerState[i]
+ * soc->urgent_latency_us
+ / dml_pow(
+ (v->ReturnBWToDCNPerState
+ * soc->urgent_latency_us
+ + (ip->rob_buffer_size_kbytes
+ - ip->pixel_chunk_size_kbytes)
+ * 1024),
+ 2));
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ if ((v->TotalReadBandwidthConsumedGBytePerSecond * 1000 <= v->ReturnBWPerState[i])
+ && (v->TotalBandwidthConsumedGBytePerSecond * 1000
+ <= v->FabricAndDRAMBandwidthPerState[i] * 1000
+ * soc->ideal_dram_bw_after_urgent_percent
+ / 100)) {
+ v->BandwidthSupport[i] = 1;
+ } else {
+ v->BandwidthSupport[i] = 0;
+ }
+ }
+
+ // Writeback Latency support check
+
+ v->WritebackLatencySupport = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_display_output_params_st dout = e2e[v->planes[k].e2e_index].dout;
+
+ if (dout.output_type == dm_wb && dout.output_format == dm_444
+ && (dest.recout_width / (dest.htotal / dest.pixel_rate_mhz) * 4)
+ > ((ip->writeback_luma_buffer_size_kbytes
+ + ip->writeback_chroma_buffer_size_kbytes)
+ * 1024 / soc->writeback_latency_us)) {
+ v->WritebackLatencySupport = 0;
+ } else if (dout.output_type == dm_wb
+ && (dest.recout_width / (dest.htotal / dest.pixel_rate_mhz))
+ > (dml_min(
+ ip->writeback_luma_buffer_size_kbytes,
+ 2
+ * ip->writeback_chroma_buffer_size_kbytes)
+ * 1024 / soc->writeback_latency_us)) {
+ v->WritebackLatencySupport = 0;
+ }
+ }
+
+ // Re-ordering Buffer Support Check
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ v->UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
+ (soc->round_trip_ping_latency_dcfclk_cycles + 32)
+ / v->DCFCLKPerState[i]
+ + soc->urgent_out_of_order_return_per_channel_bytes
+ * soc->num_chans
+ / v->ReturnBWPerState[i];
+
+ if ((ip->rob_buffer_size_kbytes - ip->pixel_chunk_size_kbytes) * 1024
+ / v->ReturnBWPerState[i]
+ > v->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
+ v->ROBSupport[i] = 1;
+ } else {
+ v->ROBSupport[i] = 0;
+ }
+ }
+
+ // Display IO Support Check
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_display_output_params_st dout = e2e[v->planes[k].e2e_index].dout;
+
+ if (dout.output_format == dm_420) {
+ v->RequiredOutputBW = dest.pixel_rate_mhz * 3 / 2;
+ } else {
+ v->RequiredOutputBW = dest.pixel_rate_mhz * 3;
+ }
+
+ if (dout.output_type == dm_hdmi) {
+ v->RequiredPHYCLK[k] = v->RequiredOutputBW / 3;
+ } else if (dout.output_type == dm_dp) {
+ v->RequiredPHYCLK[k] = v->RequiredOutputBW / 4;
+ } else {
+ v->RequiredPHYCLK[k] = 0;
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ v->DIOSupport[i] = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_output_params_st dout =
+ e2e[v->planes[k].e2e_index].dout;
+
+ if ((v->RequiredPHYCLK[k] > v->PHYCLKPerState[i])
+ || (dout.output_type == dm_hdmi
+ && v->RequiredPHYCLK[k] > 600)) {
+ v->DIOSupport[i] = 0;
+ }
+ }
+ }
+
+ // Total Available Writeback Support Check
+
+ v->TotalNumberOfActiveWriteback = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_output_params_st dout = e2e[v->planes[k].e2e_index].dout;
+
+ if (dout.output_type == dm_wb) {
+ v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1;
+ }
+ }
+
+ if (v->TotalNumberOfActiveWriteback <= ip->max_num_wb) {
+ v->TotalAvailableWritebackSupport = 1;
+ } else {
+ v->TotalAvailableWritebackSupport = 0;
+ }
+
+ // Maximum DISPCLK/DPPCLK Support check
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps =
+ e2e[v->planes[k].e2e_index].pipe.scale_taps;
+
+ if (scale_ratio_depth.hscl_ratio > 1) {
+ v->PSCL_FACTOR[k] = dml_min(
+ ip->max_dchub_pscl_bw_pix_per_clk,
+ ip->max_pscl_lb_bw_pix_per_clk
+ * scale_ratio_depth.hscl_ratio
+ / dml_ceil_ex(scale_taps.htaps / 6, 1));
+ } else {
+ v->PSCL_FACTOR[k] = dml_min(
+ ip->max_dchub_pscl_bw_pix_per_clk,
+ ip->max_pscl_lb_bw_pix_per_clk);
+ }
+
+ if (v->BytePerPixelInDETC[k] == 0) {
+ v->PSCL_FACTOR_CHROMA[k] = 0;
+ v->MinDPPCLKUsingSingleDPP[k] =
+ dest.pixel_rate_mhz
+ * dml_max(
+ scale_taps.vtaps / 6
+ * dml_min(
+ 1,
+ scale_ratio_depth.hscl_ratio),
+ dml_max(
+ scale_ratio_depth.hscl_ratio
+ * scale_ratio_depth.vscl_ratio
+ / v->PSCL_FACTOR[k],
+ 1));
+
+ } else {
+ if (scale_ratio_depth.hscl_ratio / 2 > 1) {
+ v->PSCL_FACTOR_CHROMA[k] = dml_min(
+ ip->max_dchub_pscl_bw_pix_per_clk,
+ ip->max_pscl_lb_bw_pix_per_clk
+ * scale_ratio_depth.hscl_ratio / 2
+ / dml_ceil_ex(
+ scale_taps.htaps_c
+ / 6,
+ 1));
+ } else {
+ v->PSCL_FACTOR_CHROMA[k] = dml_min(
+ ip->max_dchub_pscl_bw_pix_per_clk,
+ ip->max_pscl_lb_bw_pix_per_clk);
+ }
+ v->MinDPPCLKUsingSingleDPP[k] =
+ dest.pixel_rate_mhz
+ * dml_max(
+ dml_max(
+ scale_taps.vtaps
+ / 6
+ * dml_min(
+ 1,
+ scale_ratio_depth.hscl_ratio),
+ scale_ratio_depth.hscl_ratio
+ * scale_ratio_depth.vscl_ratio
+ / v->PSCL_FACTOR[k]),
+ dml_max(
+ dml_max(
+ scale_taps.vtaps_c
+ / 6
+ * dml_min(
+ 1,
+ scale_ratio_depth.hscl_ratio
+ / 2),
+ scale_ratio_depth.hscl_ratio
+ * scale_ratio_depth.vscl_ratio
+ / 4
+ / v->PSCL_FACTOR_CHROMA[k]),
+ 1));
+
+ }
+ }
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps =
+ e2e[v->planes[k].e2e_index].pipe.scale_taps;
+
+ if (src.source_format == dm_444_64 || src.source_format == dm_444_32
+ || src.source_format == dm_444_16) {
+ if (src.sw_mode == dm_sw_linear) {
+ v->Read256BlockHeightY[k] = 1;
+ } else if (src.source_format == dm_444_64) {
+ v->Read256BlockHeightY[k] = 4;
+ } else {
+ v->Read256BlockHeightY[k] = 8;
+ }
+
+ v->Read256BlockWidthY[k] = 256 / dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ / v->Read256BlockHeightY[k];
+ v->Read256BlockHeightC[k] = 0;
+ v->Read256BlockWidthC[k] = 0;
+ } else {
+ if (src.sw_mode == dm_sw_linear) {
+ v->Read256BlockHeightY[k] = 1;
+ v->Read256BlockHeightC[k] = 1;
+ } else if (src.source_format == dm_420_8) {
+ v->Read256BlockHeightY[k] = 16;
+ v->Read256BlockHeightC[k] = 8;
+ } else {
+ v->Read256BlockHeightY[k] = 8;
+ v->Read256BlockHeightC[k] = 8;
+ }
+
+ v->Read256BlockWidthY[k] = 256 / dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ / v->Read256BlockHeightY[k];
+ v->Read256BlockWidthC[k] = 256 / dml_ceil_ex(v->BytePerPixelInDETC[k], 2)
+ / v->Read256BlockHeightC[k];
+ }
+
+ if (src.source_scan == dm_horz) {
+ v->MaxSwathHeightY[k] = v->Read256BlockHeightY[k];
+ v->MaxSwathHeightC[k] = v->Read256BlockHeightC[k];
+ } else {
+ v->MaxSwathHeightY[k] = v->Read256BlockWidthY[k];
+ v->MaxSwathHeightC[k] = v->Read256BlockWidthC[k];
+ }
+
+ if (src.source_format == dm_444_64 || src.source_format == dm_444_32
+ || src.source_format == dm_444_16) {
+ if (src.sw_mode == dm_sw_linear
+ || (src.source_format == dm_444_64
+ && (src.sw_mode == dm_sw_4kb_s
+ || src.sw_mode
+ == dm_sw_4kb_s_x
+ || src.sw_mode
+ == dm_sw_64kb_s
+ || src.sw_mode
+ == dm_sw_64kb_s_t
+ || src.sw_mode
+ == dm_sw_64kb_s_x
+ || src.sw_mode
+ == dm_sw_var_s
+ || src.sw_mode
+ == dm_sw_var_s_x)
+ && src.source_scan == dm_horz)) {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k];
+ } else {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k] / 2;
+ }
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k];
+ } else {
+ if (src.sw_mode == dm_sw_linear) {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k];
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k];
+ } else if (src.source_format == dm_420_8 && src.source_scan == dm_horz) {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k] / 2;
+ if (ip->bug_forcing_LC_req_same_size_fixed == 1) {
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k];
+ } else {
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k] / 2;
+ }
+ } else if (src.source_format == dm_420_10 && src.source_scan == dm_horz) {
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k] / 2;
+ if (ip->bug_forcing_LC_req_same_size_fixed == 1) {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k];
+ } else {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k] / 2;
+ }
+ } else {
+ v->MinSwathHeightY[k] = v->MaxSwathHeightY[k];
+ v->MinSwathHeightC[k] = v->MaxSwathHeightC[k];
+ }
+ }
+
+ if (src.sw_mode == dm_sw_linear) {
+ v->MaximumSwathWidth = 8192;
+ } else {
+ v->MaximumSwathWidth = 5120;
+ }
+
+ v->NumberOfDPPRequiredForDETSize =
+ dml_ceil_ex(
+ v->SwathWidthYSingleDPP[k]
+ / dml_min(
+ v->MaximumSwathWidth,
+ ip->det_buffer_size_kbytes
+ * 1024
+ / 2
+ / (v->BytePerPixelInDETY[k]
+ * v->MinSwathHeightY[k]
+ + v->BytePerPixelInDETC[k]
+ / 2
+ * v->MinSwathHeightC[k])),
+ 1);
+
+ if (v->BytePerPixelInDETC[k] == 0) {
+ v->NumberOfDPPRequiredForLBSize =
+ dml_ceil_ex(
+ (scale_taps.vtaps
+ + dml_max(
+ dml_ceil_ex(
+ scale_ratio_depth.vscl_ratio,
+ 1)
+ - 2,
+ 0))
+ * v->SwathWidthYSingleDPP[k]
+ / dml_max(
+ scale_ratio_depth.hscl_ratio,
+ 1)
+ * scale_ratio_depth.lb_depth
+ / ip->line_buffer_size_bits,
+ 1);
+ } else {
+ v->NumberOfDPPRequiredForLBSize =
+ dml_max(
+ dml_ceil_ex(
+ (scale_taps.vtaps
+ + dml_max(
+ dml_ceil_ex(
+ scale_ratio_depth.vscl_ratio,
+ 1)
+ - 2,
+ 0))
+ * v->SwathWidthYSingleDPP[k]
+ / dml_max(
+ scale_ratio_depth.hscl_ratio,
+ 1)
+ * scale_ratio_depth.lb_depth
+ / ip->line_buffer_size_bits,
+ 1),
+ dml_ceil_ex(
+ (scale_taps.vtaps_c
+ + dml_max(
+ dml_ceil_ex(
+ scale_ratio_depth.vscl_ratio
+ / 2,
+ 1)
+ - 2,
+ 0))
+ * v->SwathWidthYSingleDPP[k]
+ / 2
+ / dml_max(
+ scale_ratio_depth.hscl_ratio
+ / 2,
+ 1)
+ * scale_ratio_depth.lb_depth
+ / ip->line_buffer_size_bits,
+ 1));
+ }
+
+ v->NumberOfDPPRequiredForDETAndLBSize[k] = dml_max(
+ v->NumberOfDPPRequiredForDETSize,
+ v->NumberOfDPPRequiredForLBSize);
+
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i] = 0;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] = 0;
+ v->DISPCLK_DPPCLK_Support[j * NumberOfStatesPlusTwo + i] = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ v->MinDispclkUsingSingleDPP = dml_max(
+ dest.pixel_rate_mhz,
+ v->MinDPPCLKUsingSingleDPP[k] * (j + 1))
+ * (1 + soc->downspread_percent / 100);
+ v->MinDispclkUsingDualDPP = dml_max(
+ dest.pixel_rate_mhz,
+ v->MinDPPCLKUsingSingleDPP[k] / 2 * (j + 1))
+ * (1 + soc->downspread_percent / 100);
+
+ if (i < NumberOfStates) {
+ v->MinDispclkUsingSingleDPP =
+ v->MinDispclkUsingSingleDPP
+ * (1
+ + ip->dispclk_ramp_margin_percent
+ / 100);
+ v->MinDispclkUsingDualDPP =
+ v->MinDispclkUsingDualDPP
+ * (1
+ + ip->dispclk_ramp_margin_percent
+ / 100);
+ }
+
+ if (v->MinDispclkUsingSingleDPP
+ <= dml_min(
+ v->MaxDispclk[i],
+ (j + 1) * v->MaxDppclk[i])
+ && v->NumberOfDPPRequiredForDETAndLBSize[k] <= 1) {
+ v->NoOfDPP[ijk] = 1;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] = dml_max(
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo
+ + i],
+ v->MinDispclkUsingSingleDPP);
+ } else if (v->MinDispclkUsingDualDPP
+ <= dml_min(
+ v->MaxDispclk[i],
+ (j + 1) * v->MaxDppclk[i])) {
+ v->NoOfDPP[ijk] = 2;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] = dml_max(
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo
+ + i],
+ v->MinDispclkUsingDualDPP);
+ } else {
+ v->NoOfDPP[ijk] = 2;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] = dml_max(
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo
+ + i],
+ v->MinDispclkUsingDualDPP);
+ v->DISPCLK_DPPCLK_Support[j * NumberOfStatesPlusTwo + i] =
+ 0;
+ }
+
+ v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i] =
+ v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo
+ + i] + v->NoOfDPP[ijk];
+ }
+
+ if (v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i]
+ > ip->max_num_dpp) {
+ v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i] = 0;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] = 0;
+ v->DISPCLK_DPPCLK_Support[j * NumberOfStatesPlusTwo + i] = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ ijk = k * 2 * NumberOfStatesPlusTwo
+ + j * NumberOfStatesPlusTwo + i;
+
+ v->MinDispclkUsingSingleDPP = dml_max(
+ dest.pixel_rate_mhz,
+ v->MinDPPCLKUsingSingleDPP[k] * (j + 1))
+ * (1 + soc->downspread_percent / 100);
+ v->MinDispclkUsingDualDPP = dml_max(
+ dest.pixel_rate_mhz,
+ v->MinDPPCLKUsingSingleDPP[k] / 2 * (j + 1))
+ * (1 + soc->downspread_percent / 100);
+
+ if (i < NumberOfStates) {
+ v->MinDispclkUsingSingleDPP =
+ v->MinDispclkUsingSingleDPP
+ * (1
+ + ip->dispclk_ramp_margin_percent
+ / 100);
+ v->MinDispclkUsingDualDPP =
+ v->MinDispclkUsingDualDPP
+ * (1
+ + ip->dispclk_ramp_margin_percent
+ / 100);
+ }
+
+ if (v->NumberOfDPPRequiredForDETAndLBSize[k] <= 1) {
+ v->NoOfDPP[ijk] = 1;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] =
+ dml_max(
+ v->RequiredDISPCLK[j
+ * NumberOfStatesPlusTwo
+ + i],
+ v->MinDispclkUsingSingleDPP);
+ if (v->MinDispclkUsingSingleDPP
+ > dml_min(
+ v->MaxDispclk[i],
+ (j + 1)
+ * v->MaxDppclk[i])) {
+ v->DISPCLK_DPPCLK_Support[j
+ * NumberOfStatesPlusTwo + i] =
+ 0;
+ }
+ } else {
+ v->NoOfDPP[ijk] = 2;
+ v->RequiredDISPCLK[j * NumberOfStatesPlusTwo + i] =
+ dml_max(
+ v->RequiredDISPCLK[j
+ * NumberOfStatesPlusTwo
+ + i],
+ v->MinDispclkUsingDualDPP);
+ if (v->MinDispclkUsingDualDPP
+ > dml_min(
+ v->MaxDispclk[i],
+ (j + 1)
+ * v->MaxDppclk[i])) {
+ v->DISPCLK_DPPCLK_Support[j
+ * NumberOfStatesPlusTwo + i] =
+ 0;
+ }
+ }
+ v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i] =
+ v->TotalNumberOfActiveDPP[j
+ * NumberOfStatesPlusTwo + i]
+ + v->NoOfDPP[ijk];
+ }
+ }
+ }
+ }
+
+ // Viewport Size Check
+
+ v->ViewportSizeSupport = 1;
+
+ for (k = 0; k < num_planes; k++) {
+ if (v->NumberOfDPPRequiredForDETAndLBSize[k] > 2) {
+ v->ViewportSizeSupport = 0;
+ }
+ }
+
+ // Total Available Pipes Support Check
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ if (v->TotalNumberOfActiveDPP[j * NumberOfStatesPlusTwo + i]
+ <= ip->max_num_dpp) {
+ v->TotalAvailablePipesSupport[j * NumberOfStatesPlusTwo + i] = 1;
+ } else {
+ v->TotalAvailablePipesSupport[j * NumberOfStatesPlusTwo + i] = 0;
+ }
+ }
+ }
+
+ // Urgent Latency Support Check
+
+ for (j = 0; j < 2; j++) {
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps =
+ e2e[v->planes[k].e2e_index].pipe.scale_taps;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ v->SwathWidthYPerState[ijk] = v->SwathWidthYSingleDPP[k]
+ / v->NoOfDPP[ijk];
+
+ v->SwathWidthGranularityY = 256
+ / dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ / v->MaxSwathHeightY[k];
+ v->RoundedUpMaxSwathSizeBytesY = (dml_ceil_ex(
+ v->SwathWidthYPerState[ijk] - 1,
+ v->SwathWidthGranularityY)
+ + v->SwathWidthGranularityY)
+ * v->BytePerPixelInDETY[k] * v->MaxSwathHeightY[k];
+ if (src.source_format == dm_420_10) {
+ v->RoundedUpMaxSwathSizeBytesY = dml_ceil_ex(
+ v->RoundedUpMaxSwathSizeBytesY,
+ 256) + 256;
+ }
+ if (v->MaxSwathHeightC[k] > 0) {
+ v->SwathWidthGranularityC = 256
+ / dml_ceil_ex(v->BytePerPixelInDETC[k], 2)
+ / v->MaxSwathHeightC[k];
+ }
+ v->RoundedUpMaxSwathSizeBytesC = (dml_ceil_ex(
+ v->SwathWidthYPerState[ijk] / 2 - 1,
+ v->SwathWidthGranularityC)
+ + v->SwathWidthGranularityC)
+ * v->BytePerPixelInDETC[k] * v->MaxSwathHeightC[k];
+ if (src.source_format == dm_420_10) {
+ v->RoundedUpMaxSwathSizeBytesC = dml_ceil_ex(
+ v->RoundedUpMaxSwathSizeBytesC,
+ 256) + 256;
+ }
+
+ if (v->RoundedUpMaxSwathSizeBytesY + v->RoundedUpMaxSwathSizeBytesC
+ <= ip->det_buffer_size_kbytes * 1024 / 2) {
+ v->SwathHeightYPerState[ijk] = v->MaxSwathHeightY[k];
+ v->SwathHeightCPerState[ijk] = v->MaxSwathHeightC[k];
+ } else {
+ v->SwathHeightYPerState[ijk] = v->MinSwathHeightY[k];
+ v->SwathHeightCPerState[ijk] = v->MinSwathHeightC[k];
+ }
+
+ if (v->BytePerPixelInDETC[k] == 0) {
+ v->LinesInDETLuma = ip->det_buffer_size_kbytes * 1024
+ / v->BytePerPixelInDETY[k]
+ / v->SwathWidthYPerState[ijk];
+
+ v->LinesInDETChroma = 0;
+ } else if (v->SwathHeightYPerState[ijk]
+ <= v->SwathHeightCPerState[ijk]) {
+ v->LinesInDETLuma = ip->det_buffer_size_kbytes * 1024 / 2
+ / v->BytePerPixelInDETY[k]
+ / v->SwathWidthYPerState[ijk];
+ v->LinesInDETChroma = ip->det_buffer_size_kbytes * 1024 / 2
+ / v->BytePerPixelInDETC[k]
+ / (v->SwathWidthYPerState[ijk] / 2);
+ } else {
+ v->LinesInDETLuma = ip->det_buffer_size_kbytes * 1024 * 2
+ / 3 / v->BytePerPixelInDETY[k]
+ / v->SwathWidthYPerState[ijk];
+ v->LinesInDETChroma = ip->det_buffer_size_kbytes * 1024 / 3
+ / v->BytePerPixelInDETY[k]
+ / (v->SwathWidthYPerState[ijk] / 2);
+ }
+
+ v->EffectiveLBLatencyHidingSourceLinesLuma =
+ dml_min(
+ ip->max_line_buffer_lines,
+ dml_floor_ex(
+ ip->line_buffer_size_bits
+ / scale_ratio_depth.lb_depth
+ / (v->SwathWidthYPerState[ijk]
+ / dml_max(
+ scale_ratio_depth.hscl_ratio,
+ 1)),
+ 1))
+ - (scale_taps.vtaps - 1);
+
+ v->EffectiveLBLatencyHidingSourceLinesChroma =
+ dml_min(
+ ip->max_line_buffer_lines,
+ dml_floor_ex(
+ ip->line_buffer_size_bits
+ / scale_ratio_depth.lb_depth
+ / (v->SwathWidthYPerState[ijk]
+ / 2
+ / dml_max(
+ scale_ratio_depth.hscl_ratio
+ / 2,
+ 1)),
+ 1))
+ - (scale_taps.vtaps_c - 1);
+
+ v->EffectiveDETLBLinesLuma =
+ dml_floor_ex(
+ v->LinesInDETLuma
+ + dml_min(
+ v->LinesInDETLuma
+ * v->RequiredDISPCLK[ij]
+ * v->BytePerPixelInDETY[k]
+ * v->PSCL_FACTOR[k]
+ / v->ReturnBWPerState[i],
+ v->EffectiveLBLatencyHidingSourceLinesLuma),
+ v->SwathHeightYPerState[ijk]);
+
+ v->EffectiveDETLBLinesChroma =
+ dml_floor_ex(
+ v->LinesInDETChroma
+ + dml_min(
+ v->LinesInDETChroma
+ * v->RequiredDISPCLK[ij]
+ * v->BytePerPixelInDETC[k]
+ * v->PSCL_FACTOR_CHROMA[k]
+ / v->ReturnBWPerState[i],
+ v->EffectiveLBLatencyHidingSourceLinesChroma),
+ v->SwathHeightCPerState[ijk]);
+
+ if (v->BytePerPixelInDETC[k] == 0) {
+ v->UrgentLatencySupportUsPerState[ijk] =
+ v->EffectiveDETLBLinesLuma
+ * (dest.htotal
+ / dest.pixel_rate_mhz)
+ / scale_ratio_depth.vscl_ratio
+ - v->EffectiveDETLBLinesLuma
+ * v->SwathWidthYPerState[ijk]
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / (v->ReturnBWPerState[i]
+ / v->NoOfDPP[ijk]);
+ } else {
+ v->UrgentLatencySupportUsPerState[ijk] =
+ dml_min(
+ v->EffectiveDETLBLinesLuma
+ * (dest.htotal
+ / dest.pixel_rate_mhz)
+ / scale_ratio_depth.vscl_ratio
+ - v->EffectiveDETLBLinesLuma
+ * v->SwathWidthYPerState[ijk]
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / (v->ReturnBWPerState[i]
+ / v->NoOfDPP[ijk]),
+ v->EffectiveDETLBLinesChroma
+ * (dest.htotal
+ / dest.pixel_rate_mhz)
+ / (scale_ratio_depth.vscl_ratio
+ / 2)
+ - v->EffectiveDETLBLinesChroma
+ * v->SwathWidthYPerState[ijk]
+ / 2
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / (v->ReturnBWPerState[i]
+ / v->NoOfDPP[ijk]));
+ }
+
+ }
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+
+ v->UrgentLatencySupport[ij] = 1;
+ for (k = 0; k < num_planes; k++) {
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (v->UrgentLatencySupportUsPerState[ijk]
+ < soc->urgent_latency_us / 1) {
+ v->UrgentLatencySupport[ij] = 0;
+ }
+ }
+ }
+ }
+
+ // Prefetch Check
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+
+ v->TotalNumberOfDCCActiveDPP[ij] = 0;
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (src.dcc == 1) {
+ v->TotalNumberOfDCCActiveDPP[ij] =
+ v->TotalNumberOfDCCActiveDPP[ij]
+ + v->NoOfDPP[ijk];
+ }
+ }
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+
+ v->ProjectedDCFCLKDeepSleep = 8;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ v->ProjectedDCFCLKDeepSleep = dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ dest.pixel_rate_mhz / 16);
+ if (v->BytePerPixelInDETC[k] == 0) {
+ if (scale_ratio_depth.vscl_ratio <= 1) {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 64
+ * scale_ratio_depth.hscl_ratio
+ * dest.pixel_rate_mhz
+ / v->NoOfDPP[ijk]);
+ } else {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 64
+ * v->PSCL_FACTOR[k]
+ * v->RequiredDISPCLK[ij]
+ / (1
+ + j));
+ }
+
+ } else {
+ if (scale_ratio_depth.vscl_ratio <= 1) {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 32
+ * scale_ratio_depth.hscl_ratio
+ * dest.pixel_rate_mhz
+ / v->NoOfDPP[ijk]);
+ } else {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 32
+ * v->PSCL_FACTOR[k]
+ * v->RequiredDISPCLK[ij]
+ / (1
+ + j));
+ }
+ if ((scale_ratio_depth.vscl_ratio / 2) <= 1) {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 32
+ * scale_ratio_depth.hscl_ratio
+ / 2
+ * dest.pixel_rate_mhz
+ / v->NoOfDPP[ijk]);
+ } else {
+ v->ProjectedDCFCLKDeepSleep =
+ dml_max(
+ v->ProjectedDCFCLKDeepSleep,
+ 1.1
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 32
+ * v->PSCL_FACTOR_CHROMA[k]
+ * v->RequiredDISPCLK[ij]
+ / (1
+ + j));
+ }
+
+ }
+ }
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ struct _vcs_dpi_scaler_ratio_depth_st scale_ratio_depth =
+ e2e[v->planes[k].e2e_index].pipe.scale_ratio_depth;
+ struct _vcs_dpi_scaler_taps_st scale_taps =
+ e2e[v->planes[k].e2e_index].pipe.scale_taps;
+ struct _vcs_dpi_display_output_params_st dout =
+ e2e[v->planes[k].e2e_index].dout;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (src.dcc == 1) {
+ v->MetaReqHeightY = 8 * v->Read256BlockHeightY[k];
+ v->MetaReqWidthY = 64 * 256
+ / dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ / v->MetaReqHeightY;
+ v->MetaSurfaceWidthY = dml_ceil_ex(
+ src.viewport_width / v->NoOfDPP[ijk] - 1,
+ v->MetaReqWidthY) + v->MetaReqWidthY;
+ v->MetaSurfaceHeightY = dml_ceil_ex(
+ src.viewport_height - 1,
+ v->MetaReqHeightY) + v->MetaReqHeightY;
+ if (ip->pte_enable == 1) {
+ v->MetaPteBytesPerFrameY =
+ (dml_ceil_ex(
+ (v->MetaSurfaceWidthY
+ * v->MetaSurfaceHeightY
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 256.0
+ - 4096)
+ / 8
+ / 4096,
+ 1) + 1) * 64;
+ } else {
+ v->MetaPteBytesPerFrameY = 0;
+ }
+ if (src.source_scan == dm_horz) {
+ v->MetaRowBytesY =
+ v->MetaSurfaceWidthY
+ * v->MetaReqHeightY
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 256;
+ } else {
+ v->MetaRowBytesY =
+ v->MetaSurfaceHeightY
+ * v->MetaReqWidthY
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ / 256;
+ }
+ } else {
+ v->MetaPteBytesPerFrameY = 0;
+ v->MetaRowBytesY = 0;
+ }
+
+ if (ip->pte_enable == 1) {
+ if (src.sw_mode == dm_sw_linear) {
+ v->MacroTileBlockSizeBytesY = 256;
+ v->MacroTileBlockHeightY = 1;
+ } else if (src.sw_mode == dm_sw_4kb_s
+ || src.sw_mode == dm_sw_4kb_s_x
+ || src.sw_mode == dm_sw_4kb_d
+ || src.sw_mode == dm_sw_4kb_d_x) {
+ v->MacroTileBlockSizeBytesY = 4096;
+ v->MacroTileBlockHeightY = 4
+ * v->Read256BlockHeightY[k];
+ } else if (src.sw_mode == dm_sw_64kb_s
+ || src.sw_mode == dm_sw_64kb_s_t
+ || src.sw_mode == dm_sw_64kb_s_x
+ || src.sw_mode == dm_sw_64kb_d
+ || src.sw_mode == dm_sw_64kb_d_t
+ || src.sw_mode == dm_sw_64kb_d_x) {
+ v->MacroTileBlockSizeBytesY = 64 * 1024;
+ v->MacroTileBlockHeightY = 16
+ * v->Read256BlockHeightY[k];
+ } else {
+ v->MacroTileBlockSizeBytesY = 256 * 1024;
+ v->MacroTileBlockHeightY = 32
+ * v->Read256BlockHeightY[k];
+ }
+ if (v->MacroTileBlockSizeBytesY <= 65536) {
+ v->DataPTEReqHeightY = v->MacroTileBlockHeightY;
+ } else {
+ v->DataPTEReqHeightY = 16
+ * v->Read256BlockHeightY[k];
+ }
+ v->DataPTEReqWidthY = 4096
+ / dml_ceil_ex(v->BytePerPixelInDETY[k], 1)
+ / v->DataPTEReqHeightY * 8;
+ if (src.sw_mode == dm_sw_linear) {
+ v->DPTEBytesPerRowY =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_width
+ / v->NoOfDPP[ijk]
+ * dml_min(
+ 128,
+ dml_pow(
+ 2,
+ dml_floor_ex(
+ dml_log(
+ ip->dpte_buffer_size_in_pte_reqs
+ * v->DataPTEReqWidthY
+ / (src.viewport_width
+ / v->NoOfDPP[ijk]),
+ 2),
+ 1)))
+ - 1)
+ / v->DataPTEReqWidthY,
+ 1)
+ + 1);
+ } else if (src.source_scan == dm_horz) {
+ v->DPTEBytesPerRowY =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_width
+ / v->NoOfDPP[ijk]
+ - 1)
+ / v->DataPTEReqWidthY,
+ 1)
+ + 1);
+ } else {
+ v->DPTEBytesPerRowY =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_height
+ - 1)
+ / v->DataPTEReqHeightY,
+ 1)
+ + 1);
+ }
+ } else {
+ v->DPTEBytesPerRowY = 0;
+ }
+
+ if (src.source_format != dm_444_64 && src.source_format != dm_444_32
+ && src.source_format != dm_444_16) {
+ if (src.dcc == 1) {
+ v->MetaReqHeightC = 8 * v->Read256BlockHeightC[k];
+ v->MetaReqWidthC =
+ 64 * 256
+ / dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / v->MetaReqHeightC;
+ v->MetaSurfaceWidthC = dml_ceil_ex(
+ src.viewport_width / v->NoOfDPP[ijk]
+ / 2 - 1,
+ v->MetaReqWidthC)
+ + v->MetaReqWidthC;
+ v->MetaSurfaceHeightC = dml_ceil_ex(
+ src.viewport_height / 2 - 1,
+ v->MetaReqHeightC)
+ + v->MetaReqHeightC;
+ if (ip->pte_enable == 1) {
+ v->MetaPteBytesPerFrameC =
+ (dml_ceil_ex(
+ (v->MetaSurfaceWidthC
+ * v->MetaSurfaceHeightC
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 256.0
+ - 4096)
+ / 8
+ / 4096,
+ 1) + 1)
+ * 64;
+ } else {
+ v->MetaPteBytesPerFrameC = 0;
+ }
+ if (src.source_scan == dm_horz) {
+ v->MetaRowBytesC =
+ v->MetaSurfaceWidthC
+ * v->MetaReqHeightC
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 256;
+ } else {
+ v->MetaRowBytesC =
+ v->MetaSurfaceHeightC
+ * v->MetaReqWidthC
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 256;
+ }
+ } else {
+ v->MetaPteBytesPerFrameC = 0;
+ v->MetaRowBytesC = 0;
+ }
+
+ if (ip->pte_enable == 1) {
+ if (src.sw_mode == dm_sw_linear) {
+ v->MacroTileBlockSizeBytesC = 256;
+ v->MacroTileBlockHeightC = 1;
+ } else if (src.sw_mode == dm_sw_4kb_s
+ || src.sw_mode == dm_sw_4kb_s_x
+ || src.sw_mode == dm_sw_4kb_d
+ || src.sw_mode == dm_sw_4kb_d_x) {
+ v->MacroTileBlockSizeBytesC = 4096;
+ v->MacroTileBlockHeightC = 4
+ * v->Read256BlockHeightC[k];
+ } else if (src.sw_mode == dm_sw_64kb_s
+ || src.sw_mode == dm_sw_64kb_s_t
+ || src.sw_mode == dm_sw_64kb_s_x
+ || src.sw_mode == dm_sw_64kb_d
+ || src.sw_mode == dm_sw_64kb_d_t
+ || src.sw_mode == dm_sw_64kb_d_x) {
+ v->MacroTileBlockSizeBytesC = 64 * 1024;
+ v->MacroTileBlockHeightC = 16
+ * v->Read256BlockHeightC[k];
+ } else {
+ v->MacroTileBlockSizeBytesC = 256 * 1024;
+ v->MacroTileBlockHeightC = 32
+ * v->Read256BlockHeightC[k];
+ }
+ v->MacroTileBlockWidthC =
+ v->MacroTileBlockSizeBytesC
+ / dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / v->MacroTileBlockHeightC;
+ if (v->MacroTileBlockSizeBytesC <= 65536) {
+ v->DataPTEReqHeightC =
+ v->MacroTileBlockHeightC;
+ } else {
+ v->DataPTEReqHeightC = 16
+ * v->Read256BlockHeightC[k];
+ }
+ v->DataPTEReqWidthC =
+ 4096
+ / dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / v->DataPTEReqHeightC
+ * 8;
+ if (src.sw_mode == dm_sw_linear) {
+ v->DPTEBytesPerRowC =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_width
+ / v->NoOfDPP[ijk]
+ / 2
+ * dml_min(
+ 128,
+ dml_pow(
+ 2,
+ dml_floor_ex(
+ dml_log(
+ ip->dpte_buffer_size_in_pte_reqs
+ * v->DataPTEReqWidthC
+ / (src.viewport_width
+ / v->NoOfDPP[ijk]
+ / 2),
+ 2),
+ 1)))
+ - 1)
+ / v->DataPTEReqWidthC,
+ 1)
+ + 1);
+ } else if (src.source_scan == dm_horz) {
+ v->DPTEBytesPerRowC =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_width
+ / v->NoOfDPP[ijk]
+ / 2
+ - 1)
+ / v->DataPTEReqWidthC,
+ 1)
+ + 1);
+ } else {
+ v->DPTEBytesPerRowC =
+ 64
+ * (dml_ceil_ex(
+ (src.viewport_height
+ / 2
+ - 1)
+ / v->DataPTEReqHeightC,
+ 1)
+ + 1);
+ }
+ } else {
+ v->DPTEBytesPerRowC = 0;
+ }
+ } else {
+ v->DPTEBytesPerRowC = 0;
+ v->MetaPteBytesPerFrameC = 0;
+ v->MetaRowBytesC = 0;
+ }
+
+ v->DPTEBytesPerRow[k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
+ v->MetaPTEBytesPerFrame[k] = v->MetaPteBytesPerFrameY
+ + v->MetaPteBytesPerFrameC;
+ v->MetaRowBytes[k] = v->MetaRowBytesY + v->MetaRowBytesC;
+
+ v->VInitY = (scale_ratio_depth.vscl_ratio + scale_taps.vtaps + 1
+ + dest.interlaced * 0.5
+ * scale_ratio_depth.vscl_ratio)
+ / 2.0;
+ v->PrefillY[k] = dml_floor_ex(v->VInitY, 1);
+ v->MaxNumSwY[k] = dml_ceil_ex(
+ (v->PrefillY[k] - 1.0)
+ / v->SwathHeightYPerState[ijk],
+ 1) + 1.0;
+
+ if (v->PrefillY[k] > 1) {
+ v->MaxPartialSwY = ((int) (v->PrefillY[k] - 2))
+ % ((int) v->SwathHeightYPerState[ijk]);
+ } else {
+ v->MaxPartialSwY = ((int) (v->PrefillY[k]
+ + v->SwathHeightYPerState[ijk] - 2))
+ % ((int) v->SwathHeightYPerState[ijk]);
+ }
+ v->MaxPartialSwY = dml_max(1, v->MaxPartialSwY);
+
+ v->PrefetchLinesY[k] = v->MaxNumSwY[k]
+ * v->SwathHeightYPerState[ijk] + v->MaxPartialSwY;
+
+ if (src.source_format != dm_444_64 && src.source_format != dm_444_32
+ && src.source_format != dm_444_16) {
+ v->VInitC =
+ (scale_ratio_depth.vscl_ratio / 2
+ + scale_taps.vtaps + 1
+ + dest.interlaced * 0.5
+ * scale_ratio_depth.vscl_ratio
+ / 2) / 2.0;
+ v->PrefillC[k] = dml_floor_ex(v->VInitC, 1);
+ v->MaxNumSwC[k] =
+ dml_ceil_ex(
+ (v->PrefillC[k] - 1.0)
+ / v->SwathHeightCPerState[ijk],
+ 1) + 1.0;
+ if (v->PrefillC[k] > 1) {
+ v->MaxPartialSwC =
+ ((int) (v->PrefillC[k] - 2))
+ % ((int) v->SwathHeightCPerState[ijk]);
+ } else {
+ v->MaxPartialSwC =
+ ((int) (v->PrefillC[k]
+ + v->SwathHeightCPerState[ijk]
+ - 2))
+ % ((int) v->SwathHeightCPerState[ijk]);
+ }
+ v->MaxPartialSwC = dml_max(1, v->MaxPartialSwC);
+
+ v->PrefetchLinesC[k] = v->MaxNumSwC[k]
+ * v->SwathHeightCPerState[ijk]
+ + v->MaxPartialSwC;
+ } else {
+ v->PrefetchLinesC[k] = 0;
+ }
+
+ v->dst_x_after_scaler = 90 * dest.pixel_rate_mhz
+ / (v->RequiredDISPCLK[ij] / (j + 1))
+ + 42 * dest.pixel_rate_mhz / v->RequiredDISPCLK[ij];
+ if (v->NoOfDPP[ijk] > 1) {
+ v->dst_x_after_scaler = v->dst_x_after_scaler
+ + dest.recout_width / 2.0;
+ }
+
+ if (dout.output_format == dm_420) {
+ v->dst_y_after_scaler = 1;
+ } else {
+ v->dst_y_after_scaler = 0;
+ }
+
+ v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep;
+
+ v->VUpdateOffset = dml_ceil_ex(dest.htotal / 4, 1);
+ v->TotalRepeaterDelay = ip->max_inter_dcn_tile_repeaters
+ * (2 / (v->RequiredDISPCLK[ij] / (j + 1))
+ + 3 / v->RequiredDISPCLK[ij]);
+ v->VUpdateWidth = (14 / v->ProjectedDCFCLKDeepSleep
+ + 12 / (v->RequiredDISPCLK[ij] / (j + 1))
+ + v->TotalRepeaterDelay) * dest.pixel_rate_mhz;
+ v->VReadyOffset =
+ dml_max(
+ 150
+ / (v->RequiredDISPCLK[ij]
+ / (j
+ + 1)),
+ v->TotalRepeaterDelay
+ + 20
+ / v->ProjectedDCFCLKDeepSleep
+ + 10
+ / (v->RequiredDISPCLK[ij]
+ / (j
+ + 1)))
+ * dest.pixel_rate_mhz;
+
+ v->TimeSetup =
+ (v->VUpdateOffset + v->VUpdateWidth
+ + v->VReadyOffset)
+ / dest.pixel_rate_mhz;
+
+ v->ExtraLatency =
+ v->UrgentRoundTripAndOutOfOrderLatencyPerState[i]
+ + (v->TotalNumberOfActiveDPP[ij]
+ * ip->pixel_chunk_size_kbytes
+ + v->TotalNumberOfDCCActiveDPP[ij]
+ * ip->meta_chunk_size_kbytes)
+ * 1024
+ / v->ReturnBWPerState[i];
+
+ if (ip->pte_enable == 1) {
+ v->ExtraLatency = v->ExtraLatency
+ + v->TotalNumberOfActiveDPP[ij]
+ * ip->pte_chunk_size_kbytes
+ * 1024
+ / v->ReturnBWPerState[i];
+ }
+
+ if (ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one
+ == 1) {
+ v->MaximumVStartup = dest.vtotal - dest.vactive - 1;
+ } else {
+ v->MaximumVStartup = dest.vsync_plus_back_porch - 1;
+ }
+
+ v->LineTimesForPrefetch[k] =
+ v->MaximumVStartup
+ - soc->urgent_latency_us
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ - (v->TimeCalc + v->TimeSetup)
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ - (v->dst_y_after_scaler
+ + v->dst_x_after_scaler
+ / dest.htotal);
+
+ v->LineTimesForPrefetch[k] = dml_floor_ex(
+ 4.0 * (v->LineTimesForPrefetch[k] + 0.125),
+ 1) / 4;
+
+ v->PrefetchBW[k] =
+ (v->MetaPTEBytesPerFrame[k] + 2 * v->MetaRowBytes[k]
+ + 2 * v->DPTEBytesPerRow[k]
+ + v->PrefetchLinesY[k]
+ * v->SwathWidthYPerState[ijk]
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ + v->PrefetchLinesC[k]
+ * v->SwathWidthYPerState[ijk]
+ / 2
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2))
+ / (v->LineTimesForPrefetch[k]
+ * dest.htotal
+ / dest.pixel_rate_mhz);
+ }
+
+ v->BWAvailableForImmediateFlip = v->ReturnBWPerState[i];
+
+ for (k = 0; k < num_planes; k++) {
+ v->BWAvailableForImmediateFlip = v->BWAvailableForImmediateFlip
+ - dml_max(v->ReadBandwidth[k], v->PrefetchBW[k]);
+ }
+
+ v->TotalImmediateFlipBytes = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+
+ if (src.source_format != dm_420_8
+ && src.source_format != dm_420_10) {
+ v->TotalImmediateFlipBytes = v->TotalImmediateFlipBytes
+ + v->MetaPTEBytesPerFrame[k]
+ + v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k];
+ }
+ }
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (ip->pte_enable == 1 && src.dcc == 1) {
+ v->TimeForMetaPTEWithImmediateFlip =
+ dml_max(
+ v->MetaPTEBytesPerFrame[k]
+ / v->PrefetchBW[k],
+ dml_max(
+ v->MetaPTEBytesPerFrame[k]
+ * v->TotalImmediateFlipBytes
+ / (v->BWAvailableForImmediateFlip
+ * (v->MetaPTEBytesPerFrame[k]
+ + v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])),
+ dml_max(
+ v->ExtraLatency,
+ dml_max(
+ soc->urgent_latency_us,
+ dest.htotal
+ / dest.pixel_rate_mhz
+ / 4))));
+
+ v->TimeForMetaPTEWithoutImmediateFlip =
+ dml_max(
+ v->MetaPTEBytesPerFrame[k]
+ / v->PrefetchBW[k],
+ dml_max(
+ v->ExtraLatency,
+ dest.htotal
+ / dest.pixel_rate_mhz
+ / 4));
+ } else {
+ v->TimeForMetaPTEWithImmediateFlip = dest.htotal
+ / dest.pixel_rate_mhz / 4;
+ v->TimeForMetaPTEWithoutImmediateFlip = dest.htotal
+ / dest.pixel_rate_mhz / 4;
+ }
+
+ if (ip->pte_enable == 1 || src.dcc == 1) {
+ v->TimeForMetaAndDPTERowWithImmediateFlip =
+ dml_max(
+ (v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])
+ / v->PrefetchBW[k],
+ dml_max(
+ (v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])
+ * v->TotalImmediateFlipBytes
+ / (v->BWAvailableForImmediateFlip
+ * (v->MetaPTEBytesPerFrame[k]
+ + v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])),
+ dml_max(
+ dest.htotal
+ / dest.pixel_rate_mhz
+ - v->TimeForMetaPTEWithImmediateFlip,
+ dml_max(
+ v->ExtraLatency,
+ 2
+ * soc->urgent_latency_us))));
+
+ v->TimeForMetaAndDPTERowWithoutImmediateFlip =
+ dml_max(
+ (v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])
+ / v->PrefetchBW[k],
+ dml_max(
+ dest.htotal
+ / dest.pixel_rate_mhz
+ - v->TimeForMetaPTEWithoutImmediateFlip,
+ v->ExtraLatency));
+ } else {
+ v->TimeForMetaAndDPTERowWithImmediateFlip =
+ dml_max(
+ dest.htotal
+ / dest.pixel_rate_mhz
+ - v->TimeForMetaPTEWithImmediateFlip,
+ v->ExtraLatency
+ - v->TimeForMetaPTEWithImmediateFlip);
+ v->TimeForMetaAndDPTERowWithoutImmediateFlip =
+ dml_max(
+ dest.htotal
+ / dest.pixel_rate_mhz
+ - v->TimeForMetaPTEWithoutImmediateFlip,
+ v->ExtraLatency
+ - v->TimeForMetaPTEWithoutImmediateFlip);
+ }
+
+ v->LinesForMetaPTEWithImmediateFlip[k] =
+ dml_floor_ex(
+ 4.0
+ * (v->TimeForMetaPTEWithImmediateFlip
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ + 0.125),
+ 1) / 4.0;
+
+ v->LinesForMetaPTEWithoutImmediateFlip[k] =
+ dml_floor_ex(
+ 4.0
+ * (v->TimeForMetaPTEWithoutImmediateFlip
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ + 0.125),
+ 1) / 4.0;
+
+ v->LinesForMetaAndDPTERowWithImmediateFlip[k] =
+ dml_floor_ex(
+ 4.0
+ * (v->TimeForMetaAndDPTERowWithImmediateFlip
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ + 0.125),
+ 1) / 4.0;
+
+ v->LinesForMetaAndDPTERowWithoutImmediateFlip[k] =
+ dml_floor_ex(
+ 4.0
+ * (v->TimeForMetaAndDPTERowWithoutImmediateFlip
+ / (dest.htotal
+ / dest.pixel_rate_mhz)
+ + 0.125),
+ 1) / 4.0;
+
+ v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip =
+ v->LineTimesForPrefetch[k]
+ - v->LinesForMetaPTEWithImmediateFlip[k]
+ - v->LinesForMetaAndDPTERowWithImmediateFlip[k];
+
+ v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip =
+ v->LineTimesForPrefetch[k]
+ - v->LinesForMetaPTEWithoutImmediateFlip[k]
+ - v->LinesForMetaAndDPTERowWithoutImmediateFlip[k];
+
+ if (v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip > 0) {
+ v->VRatioPreYWithImmediateFlip[ijk] =
+ v->PrefetchLinesY[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
+ if (v->SwathHeightYPerState[ijk] > 4) {
+ if (v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ - (v->PrefillY[k] - 3.0) / 2.0
+ > 0) {
+ v->VRatioPreYWithImmediateFlip[ijk] =
+ dml_max(
+ v->VRatioPreYWithImmediateFlip[ijk],
+ (v->MaxNumSwY[k]
+ * v->SwathHeightYPerState[ijk])
+ / (v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ - (v->PrefillY[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->VRatioPreYWithImmediateFlip[ijk] =
+ 999999;
+ }
+ }
+ v->VRatioPreCWithImmediateFlip[ijk] =
+ v->PrefetchLinesC[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
+ if (v->SwathHeightCPerState[ijk] > 4) {
+ if (v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ - (v->PrefillC[k] - 3.0) / 2.0
+ > 0) {
+ v->VRatioPreCWithImmediateFlip[ijk] =
+ dml_max(
+ v->VRatioPreCWithImmediateFlip[ijk],
+ (v->MaxNumSwC[k]
+ * v->SwathHeightCPerState[ijk])
+ / (v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ - (v->PrefillC[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->VRatioPreCWithImmediateFlip[ijk] =
+ 999999;
+ }
+ }
+
+ v->RequiredPrefetchPixelDataBWWithImmediateFlip[ijk] =
+ v->NoOfDPP[ijk]
+ * (v->PrefetchLinesY[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ + v->PrefetchLinesC[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithImmediateFlip
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 2)
+ * v->SwathWidthYPerState[ijk]
+ / (dest.htotal
+ / dest.pixel_rate_mhz);
+ } else {
+ v->VRatioPreYWithImmediateFlip[ijk] = 999999;
+ v->VRatioPreCWithImmediateFlip[ijk] = 999999;
+ v->RequiredPrefetchPixelDataBWWithImmediateFlip[ijk] =
+ 999999;
+ }
+
+ if (v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ > 0) {
+ v->VRatioPreYWithoutImmediateFlip[ijk] =
+ v->PrefetchLinesY[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
+ if (v->SwathHeightYPerState[ijk] > 4) {
+ if (v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ - (v->PrefillY[k] - 3.0) / 2.0
+ > 0) {
+ v->VRatioPreYWithoutImmediateFlip[ijk] =
+ dml_max(
+ v->VRatioPreYWithoutImmediateFlip[ijk],
+ (v->MaxNumSwY[k]
+ * v->SwathHeightYPerState[ijk])
+ / (v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ - (v->PrefillY[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->VRatioPreYWithoutImmediateFlip[ijk] =
+ 999999;
+ }
+ }
+ v->VRatioPreCWithoutImmediateFlip[ijk] =
+ v->PrefetchLinesC[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
+ if (v->SwathHeightCPerState[ijk] > 4) {
+ if (v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ - (v->PrefillC[k] - 3.0) / 2.0
+ > 0) {
+ v->VRatioPreCWithoutImmediateFlip[ijk] =
+ dml_max(
+ v->VRatioPreCWithoutImmediateFlip[ijk],
+ (v->MaxNumSwC[k]
+ * v->SwathHeightCPerState[ijk])
+ / (v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ - (v->PrefillC[k]
+ - 3.0)
+ / 2.0));
+ } else {
+ v->VRatioPreCWithoutImmediateFlip[ijk] =
+ 999999;
+ }
+ }
+
+ v->RequiredPrefetchPixelDataBWWithoutImmediateFlip[ijk] =
+ v->NoOfDPP[ijk]
+ * (v->PrefetchLinesY[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ * dml_ceil_ex(
+ v->BytePerPixelInDETY[k],
+ 1)
+ + v->PrefetchLinesC[k]
+ / v->LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip
+ * dml_ceil_ex(
+ v->BytePerPixelInDETC[k],
+ 2)
+ / 2)
+ * v->SwathWidthYPerState[ijk]
+ / (dest.htotal
+ / dest.pixel_rate_mhz);
+ } else {
+ v->VRatioPreYWithoutImmediateFlip[ijk] = 999999;
+ v->VRatioPreCWithoutImmediateFlip[ijk] = 999999;
+ v->RequiredPrefetchPixelDataBWWithoutImmediateFlip[ijk] =
+ 999999;
+ }
+ }
+
+ v->MaximumReadBandwidthWithPrefetchWithImmediateFlip = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ struct _vcs_dpi_display_pipe_dest_params_st dest =
+ e2e[v->planes[k].e2e_index].pipe.dest;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (src.source_format != dm_420_8
+ && src.source_format != dm_420_10) {
+ v->MaximumReadBandwidthWithPrefetchWithImmediateFlip =
+ v->MaximumReadBandwidthWithPrefetchWithImmediateFlip
+ + dml_max(
+ v->ReadBandwidth[k],
+ v->RequiredPrefetchPixelDataBWWithImmediateFlip[ijk])
+ + dml_max(
+ v->MetaPTEBytesPerFrame[k]
+ / (v->LinesForMetaPTEWithImmediateFlip[k]
+ * dest.htotal
+ / dest.pixel_rate_mhz),
+ (v->MetaRowBytes[k]
+ + v->DPTEBytesPerRow[k])
+ / (v->LinesForMetaAndDPTERowWithImmediateFlip[k]
+ * dest.htotal
+ / dest.pixel_rate_mhz));
+ } else {
+ v->MaximumReadBandwidthWithPrefetchWithImmediateFlip =
+ v->MaximumReadBandwidthWithPrefetchWithImmediateFlip
+ + dml_max(
+ v->ReadBandwidth[k],
+ v->RequiredPrefetchPixelDataBWWithoutImmediateFlip[ijk]);
+ }
+ }
+
+ v->MaximumReadBandwidthWithPrefetchWithoutImmediateFlip = 0;
+
+ for (k = 0; k < num_planes; k++) {
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ v->MaximumReadBandwidthWithPrefetchWithoutImmediateFlip =
+ v->MaximumReadBandwidthWithPrefetchWithoutImmediateFlip
+ + dml_max(
+ v->ReadBandwidth[k],
+ v->RequiredPrefetchPixelDataBWWithoutImmediateFlip[ijk]);
+ }
+
+ v->PrefetchSupportedWithImmediateFlip[ij] = 1;
+ if (v->MaximumReadBandwidthWithPrefetchWithImmediateFlip
+ > v->ReturnBWPerState[i]) {
+ v->PrefetchSupportedWithImmediateFlip[ij] = 0;
+ }
+ for (k = 0; k < num_planes; k++) {
+ if (v->LineTimesForPrefetch[k] < 2
+ || v->LinesForMetaPTEWithImmediateFlip[k] >= 8
+ || v->LinesForMetaAndDPTERowWithImmediateFlip[k]
+ >= 16) {
+ v->PrefetchSupportedWithImmediateFlip[ij] = 0;
+ }
+ }
+
+ v->PrefetchSupportedWithoutImmediateFlip[ij] = 1;
+ if (v->MaximumReadBandwidthWithPrefetchWithoutImmediateFlip
+ > v->ReturnBWPerState[i]) {
+ v->PrefetchSupportedWithoutImmediateFlip[ij] = 0;
+ }
+ for (k = 0; k < num_planes; k++) {
+ if (v->LineTimesForPrefetch[k] < 2
+ || v->LinesForMetaPTEWithoutImmediateFlip[k] >= 8
+ || v->LinesForMetaAndDPTERowWithoutImmediateFlip[k]
+ >= 16) {
+ v->PrefetchSupportedWithoutImmediateFlip[ij] = 0;
+ }
+ }
+ }
+ }
+
+ for (i = 0; i < NumberOfStatesPlusTwo; i++) {
+ for (j = 0; j < 2; j++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+
+ v->VRatioInPrefetchSupportedWithImmediateFlip[ij] = 1;
+ for (k = 0; k < num_planes; k++) {
+ struct _vcs_dpi_display_pipe_source_params_st src =
+ e2e[v->planes[k].e2e_index].pipe.src;
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (((src.source_format != dm_420_8
+ && src.source_format != dm_420_10)
+ && (v->VRatioPreYWithImmediateFlip[ijk] > 4
+ || v->VRatioPreCWithImmediateFlip[ijk]
+ > 4))
+ || ((src.source_format == dm_420_8
+ || src.source_format == dm_420_10)
+ && (v->VRatioPreYWithoutImmediateFlip[ijk]
+ > 4
+ || v->VRatioPreCWithoutImmediateFlip[ijk]
+ > 4))) {
+ v->VRatioInPrefetchSupportedWithImmediateFlip[ij] = 0;
+ }
+ }
+ v->VRatioInPrefetchSupportedWithoutImmediateFlip[ij] = 1;
+ for (k = 0; k < num_planes; k++) {
+ ijk = k * 2 * NumberOfStatesPlusTwo + j * NumberOfStatesPlusTwo + i;
+
+ if (v->VRatioPreYWithoutImmediateFlip[ijk] > 4
+ || v->VRatioPreCWithoutImmediateFlip[ijk] > 4) {
+ v->VRatioInPrefetchSupportedWithoutImmediateFlip[ij] = 0;
+ }
+ }
+ }
+ }
+
+ // Mode Support, Voltage State and SOC Configuration
+
+ for (i = (NumberOfStatesPlusTwo - 1); i >= 0; i--) // use int type here
+ {
+ for (j = 0; j < 2; j++) {
+ ij = j * NumberOfStatesPlusTwo + i;
+
+ if (v->ScaleRatioSupport == 1 && v->SourceFormatPixelAndScanSupport == 1
+ && v->ViewportSizeSupport == 1
+ && v->BandwidthSupport[i] == 1 && v->DIOSupport[i] == 1
+ && v->UrgentLatencySupport[ij] == 1 && v->ROBSupport[i] == 1
+ && v->DISPCLK_DPPCLK_Support[ij] == 1
+ && v->TotalAvailablePipesSupport[ij] == 1
+ && v->TotalAvailableWritebackSupport == 1
+ && v->WritebackLatencySupport == 1) {
+ if (v->PrefetchSupportedWithImmediateFlip[ij] == 1
+ && v->VRatioInPrefetchSupportedWithImmediateFlip[ij]
+ == 1) {
+ v->ModeSupportWithImmediateFlip[ij] = 1;
+ } else {
+ v->ModeSupportWithImmediateFlip[ij] = 0;
+ }
+ if (v->PrefetchSupportedWithoutImmediateFlip[ij] == 1
+ && v->VRatioInPrefetchSupportedWithoutImmediateFlip[ij]
+ == 1) {
+ v->ModeSupportWithoutImmediateFlip[ij] = 1;
+ } else {
+ v->ModeSupportWithoutImmediateFlip[ij] = 0;
+ }
+ } else {
+ v->ModeSupportWithImmediateFlip[ij] = 0;
+ v->ModeSupportWithoutImmediateFlip[ij] = 0;
+ }
+ }
+ }
+
+ for (i = (NumberOfStatesPlusTwo - 1); i >= 0; i--) // use int type here
+ {
+ if ((i == (NumberOfStatesPlusTwo - 1)
+ || v->ModeSupportWithImmediateFlip[1 * NumberOfStatesPlusTwo + i]
+ == 1
+ || v->ModeSupportWithImmediateFlip[0 * NumberOfStatesPlusTwo + i]
+ == 1) && i >= v->VoltageOverrideLevel) {
+ v->VoltageLevelWithImmediateFlip = i;
+ }
+ }
+
+ for (i = (NumberOfStatesPlusTwo - 1); i >= 0; i--) // use int type here
+ {
+ if ((i == (NumberOfStatesPlusTwo - 1)
+ || v->ModeSupportWithoutImmediateFlip[1 * NumberOfStatesPlusTwo + i]
+ == 1
+ || v->ModeSupportWithoutImmediateFlip[0 * NumberOfStatesPlusTwo + i]
+ == 1) && i >= v->VoltageOverrideLevel) {
+ v->VoltageLevelWithoutImmediateFlip = i;
+ }
+ }
+
+ if (v->VoltageLevelWithImmediateFlip == (NumberOfStatesPlusTwo - 1)) {
+ v->ImmediateFlipSupported = 0;
+ v->VoltageLevel = v->VoltageLevelWithoutImmediateFlip;
+ } else {
+ v->ImmediateFlipSupported = 1;
+ v->VoltageLevel = v->VoltageLevelWithImmediateFlip;
+ }
+
+ v->DCFCLK = v->DCFCLKPerState[(int) v->VoltageLevel];
+ v->FabricAndDRAMBandwidth = v->FabricAndDRAMBandwidthPerState[(int) v->VoltageLevel];
+
+ for (j = 0; j < 2; j++) {
+ v->RequiredDISPCLKPerRatio[j] = v->RequiredDISPCLK[j * NumberOfStatesPlusTwo
+ + (int) v->VoltageLevel];
+ for (k = 0; k < num_planes; k++) {
+ v->DPPPerPlanePerRatio[k * 2 + j] = v->NoOfDPP[k * 2 * NumberOfStatesPlusTwo
+ + j * NumberOfStatesPlusTwo + (int) v->VoltageLevel];
+ }
+ v->DISPCLK_DPPCLK_SupportPerRatio[j] = v->DISPCLK_DPPCLK_Support[j
+ * NumberOfStatesPlusTwo + (int) v->VoltageLevel];
+ }
+
+ ASSERT(v->ImmediateFlipSupported || v->MacroTileBlockWidthC || v->DCFCLK || v->FabricAndDRAMBandwidth);
+
+ return (v->VoltageLevel);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
new file mode 100644
index 0000000..ead4942
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_SUPPORT_H__
+#define __DISPLAY_MODE_SUPPORT_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+#define NumberOfStates 4
+#define NumberOfStatesPlusTwo (NumberOfStates+2)
+
+struct dml_ms_internal_vars {
+ double ScaleRatioSupport;
+ double SourceFormatPixelAndScanSupport;
+ double TotalReadBandwidthConsumedGBytePerSecond;
+ double TotalWriteBandwidthConsumedGBytePerSecond;
+ double TotalBandwidthConsumedGBytePerSecond;
+ double DCCEnabledInAnyPlane;
+ double ReturnBWToDCNPerState;
+ double CriticalPoint;
+ double WritebackLatencySupport;
+ double RequiredOutputBW;
+ double TotalNumberOfActiveWriteback;
+ double TotalAvailableWritebackSupport;
+ double MaximumSwathWidth;
+ double NumberOfDPPRequiredForDETSize;
+ double NumberOfDPPRequiredForLBSize;
+ double MinDispclkUsingSingleDPP;
+ double MinDispclkUsingDualDPP;
+ double ViewportSizeSupport;
+ double SwathWidthGranularityY;
+ double RoundedUpMaxSwathSizeBytesY;
+ double SwathWidthGranularityC;
+ double RoundedUpMaxSwathSizeBytesC;
+ double LinesInDETLuma;
+ double LinesInDETChroma;
+ double EffectiveLBLatencyHidingSourceLinesLuma;
+ double EffectiveLBLatencyHidingSourceLinesChroma;
+ double EffectiveDETLBLinesLuma;
+ double EffectiveDETLBLinesChroma;
+ double ProjectedDCFCLKDeepSleep;
+ double MetaReqHeightY;
+ double MetaReqWidthY;
+ double MetaSurfaceWidthY;
+ double MetaSurfaceHeightY;
+ double MetaPteBytesPerFrameY;
+ double MetaRowBytesY;
+ double MacroTileBlockSizeBytesY;
+ double MacroTileBlockHeightY;
+ double DataPTEReqHeightY;
+ double DataPTEReqWidthY;
+ double DPTEBytesPerRowY;
+ double MetaReqHeightC;
+ double MetaReqWidthC;
+ double MetaSurfaceWidthC;
+ double MetaSurfaceHeightC;
+ double MetaPteBytesPerFrameC;
+ double MetaRowBytesC;
+ double MacroTileBlockSizeBytesC;
+ double MacroTileBlockHeightC;
+ double MacroTileBlockWidthC;
+ double DataPTEReqHeightC;
+ double DataPTEReqWidthC;
+ double DPTEBytesPerRowC;
+ double VInitY;
+ double MaxPartialSwY;
+ double VInitC;
+ double MaxPartialSwC;
+ double dst_x_after_scaler;
+ double dst_y_after_scaler;
+ double TimeCalc;
+ double VUpdateOffset;
+ double TotalRepeaterDelay;
+ double VUpdateWidth;
+ double VReadyOffset;
+ double TimeSetup;
+ double ExtraLatency;
+ double MaximumVStartup;
+ double BWAvailableForImmediateFlip;
+ double TotalImmediateFlipBytes;
+ double TimeForMetaPTEWithImmediateFlip;
+ double TimeForMetaPTEWithoutImmediateFlip;
+ double TimeForMetaAndDPTERowWithImmediateFlip;
+ double TimeForMetaAndDPTERowWithoutImmediateFlip;
+ double LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
+ double LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
+ double MaximumReadBandwidthWithPrefetchWithImmediateFlip;
+ double MaximumReadBandwidthWithPrefetchWithoutImmediateFlip;
+ double VoltageOverrideLevel;
+ double VoltageLevelWithImmediateFlip;
+ double VoltageLevelWithoutImmediateFlip;
+ double ImmediateFlipSupported;
+ double VoltageLevel;
+ double DCFCLK;
+ double FabricAndDRAMBandwidth;
+ double SwathWidthYSingleDPP[DC__NUM_PIPES__MAX];
+ double BytePerPixelInDETY[DC__NUM_PIPES__MAX];
+ double BytePerPixelInDETC[DC__NUM_PIPES__MAX];
+ double ReadBandwidth[DC__NUM_PIPES__MAX];
+ double WriteBandwidth[DC__NUM_PIPES__MAX];
+ double DCFCLKPerState[NumberOfStatesPlusTwo];
+ double FabricAndDRAMBandwidthPerState[NumberOfStatesPlusTwo];
+ double ReturnBWPerState[NumberOfStatesPlusTwo];
+ double BandwidthSupport[NumberOfStatesPlusTwo];
+ double UrgentRoundTripAndOutOfOrderLatencyPerState[NumberOfStatesPlusTwo];
+ double ROBSupport[NumberOfStatesPlusTwo];
+ double RequiredPHYCLK[DC__NUM_PIPES__MAX];
+ double DIOSupport[NumberOfStatesPlusTwo];
+ double PHYCLKPerState[NumberOfStatesPlusTwo];
+ double PSCL_FACTOR[DC__NUM_PIPES__MAX];
+ double PSCL_FACTOR_CHROMA[DC__NUM_PIPES__MAX];
+ double MinDPPCLKUsingSingleDPP[DC__NUM_PIPES__MAX];
+ double Read256BlockHeightY[DC__NUM_PIPES__MAX];
+ double Read256BlockWidthY[DC__NUM_PIPES__MAX];
+ double Read256BlockHeightC[DC__NUM_PIPES__MAX];
+ double Read256BlockWidthC[DC__NUM_PIPES__MAX];
+ double MaxSwathHeightY[DC__NUM_PIPES__MAX];
+ double MaxSwathHeightC[DC__NUM_PIPES__MAX];
+ double MinSwathHeightY[DC__NUM_PIPES__MAX];
+ double MinSwathHeightC[DC__NUM_PIPES__MAX];
+ double NumberOfDPPRequiredForDETAndLBSize[DC__NUM_PIPES__MAX];
+ double TotalNumberOfActiveDPP[NumberOfStatesPlusTwo * 2];
+ double RequiredDISPCLK[NumberOfStatesPlusTwo * 2];
+ double DISPCLK_DPPCLK_Support[NumberOfStatesPlusTwo * 2];
+ double MaxDispclk[NumberOfStatesPlusTwo];
+ double MaxDppclk[NumberOfStatesPlusTwo];
+ double NoOfDPP[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double TotalAvailablePipesSupport[NumberOfStatesPlusTwo * 2];
+ double SwathWidthYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double SwathHeightYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double SwathHeightCPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double DETBufferSizeYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double UrgentLatencySupportUsPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double UrgentLatencySupport[NumberOfStatesPlusTwo * 2];
+ double TotalNumberOfDCCActiveDPP[NumberOfStatesPlusTwo * 2];
+ double DPTEBytesPerRow[DC__NUM_PIPES__MAX];
+ double MetaPTEBytesPerFrame[DC__NUM_PIPES__MAX];
+ double MetaRowBytes[DC__NUM_PIPES__MAX];
+ double PrefillY[DC__NUM_PIPES__MAX];
+ double MaxNumSwY[DC__NUM_PIPES__MAX];
+ double PrefetchLinesY[DC__NUM_PIPES__MAX];
+ double PrefillC[DC__NUM_PIPES__MAX];
+ double MaxNumSwC[DC__NUM_PIPES__MAX];
+ double PrefetchLinesC[DC__NUM_PIPES__MAX];
+ double LineTimesForPrefetch[DC__NUM_PIPES__MAX];
+ double PrefetchBW[DC__NUM_PIPES__MAX];
+ double LinesForMetaPTEWithImmediateFlip[DC__NUM_PIPES__MAX];
+ double LinesForMetaPTEWithoutImmediateFlip[DC__NUM_PIPES__MAX];
+ double LinesForMetaAndDPTERowWithImmediateFlip[DC__NUM_PIPES__MAX];
+ double LinesForMetaAndDPTERowWithoutImmediateFlip[DC__NUM_PIPES__MAX];
+ double VRatioPreYWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double VRatioPreCWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double RequiredPrefetchPixelDataBWWithImmediateFlip[NumberOfStatesPlusTwo * 2
+ * DC__NUM_PIPES__MAX];
+ double VRatioPreYWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double VRatioPreCWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+ double RequiredPrefetchPixelDataBWWithoutImmediateFlip[NumberOfStatesPlusTwo * 2
+ * DC__NUM_PIPES__MAX];
+ double PrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double PrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double VRatioInPrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double VRatioInPrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double ModeSupportWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double ModeSupportWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+ double RequiredDISPCLKPerRatio[2];
+ double DPPPerPlanePerRatio[2 * DC__NUM_PIPES__MAX];
+ double DISPCLK_DPPCLK_SupportPerRatio[2];
+ struct _vcs_dpi_wm_calc_pipe_params_st planes[DC__NUM_PIPES__MAX];
+};
+
+int dml_ms_check(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ int num_pipes);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c b/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
new file mode 100644
index 0000000..2e4dc57
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
@@ -0,0 +1,367 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "display_pipe_clocks.h"
+#include "display_mode_lib.h"
+#include "soc_bounding_box.h"
+
+static enum voltage_state power_state(
+ struct display_mode_lib *mode_lib,
+ double dispclk,
+ double dppclk)
+{
+ enum voltage_state state1;
+ enum voltage_state state2;
+
+ if (dispclk <= mode_lib->soc.vmin.dispclk_mhz)
+ state1 = dm_vmin;
+ else if (dispclk <= mode_lib->soc.vnom.dispclk_mhz)
+ state1 = dm_vnom;
+ else if (dispclk <= mode_lib->soc.vmax.dispclk_mhz)
+ state1 = dm_vmax;
+ else
+ state1 = dm_vmax_exceeded;
+
+ if (dppclk <= mode_lib->soc.vmin.dppclk_mhz)
+ state2 = dm_vmin;
+ else if (dppclk <= mode_lib->soc.vnom.dppclk_mhz)
+ state2 = dm_vnom;
+ else if (dppclk <= mode_lib->soc.vmax.dppclk_mhz)
+ state2 = dm_vmax;
+ else
+ state2 = dm_vmax_exceeded;
+
+ if (state1 > state2)
+ return state1;
+ else
+ return state2;
+}
+
+static unsigned int dpp_in_grp(
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes,
+ unsigned int hsplit_grp)
+{
+ unsigned int num_dpp = 0;
+ unsigned int i;
+
+ for (i = 0; i < num_pipes; i++) {
+ if (e2e[i].pipe.src.is_hsplit) {
+ if (e2e[i].pipe.src.hsplit_grp == hsplit_grp) {
+ num_dpp++;
+ }
+ }
+ }
+
+ if (0 == num_dpp)
+ num_dpp = 1;
+
+ return num_dpp;
+}
+
+static void calculate_pipe_clk_requirement(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_dpp_in_grp,
+ double *dppclk,
+ double *dispclk,
+ bool *dppdiv)
+{
+ double pscl_throughput = 0.0;
+ double max_hratio = e2e->pipe.scale_ratio_depth.hscl_ratio;
+ double max_vratio = e2e->pipe.scale_ratio_depth.vscl_ratio;
+ double max_htaps = e2e->pipe.scale_taps.htaps;
+ double max_vtaps = e2e->pipe.scale_taps.vtaps;
+ double dpp_clock_divider = (double) num_dpp_in_grp;
+ double dispclk_dppclk_ratio;
+ double dispclk_ramp_margin_percent;
+
+ if (max_hratio > 1.0) {
+ double pscl_to_lb = ((double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk * max_hratio)
+ / dml_ceil(max_htaps / 6.0);
+ pscl_throughput = dml_min(
+ pscl_to_lb,
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk);
+ } else {
+ pscl_throughput = dml_min(
+ (double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk,
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk);
+ }
+
+ DTRACE("pscl_throughput: %f pix per clk", pscl_throughput);
+ DTRACE("vtaps: %f hratio: %f vratio: %f", max_vtaps, max_hratio, max_vratio);
+ *dppclk = dml_max(
+ max_vtaps / 6.0 * dml_min(1.0, max_hratio),
+ max_hratio * max_vratio / pscl_throughput);
+ DTRACE("pixel rate multiplier: %f", *dppclk);
+ *dppclk = dml_max(*dppclk, 1.0);
+ DTRACE("pixel rate multiplier clamped: %f", *dppclk);
+ *dppclk = *dppclk * e2e->pipe.dest.pixel_rate_mhz;
+
+ *dppclk = *dppclk / dpp_clock_divider;
+ DTRACE("dppclk after split: %f", *dppclk);
+
+ if (dpp_clock_divider > 1.0 && (*dppclk < e2e->pipe.dest.pixel_rate_mhz)) {
+ dispclk_dppclk_ratio = 2.0;
+ *dppdiv = true;
+ } else {
+ dispclk_dppclk_ratio = 1.0;
+ *dppdiv = false;
+ }
+
+ dispclk_ramp_margin_percent = mode_lib->ip.dispclk_ramp_margin_percent;
+
+ /* Comment this out because of Gabes possible bug in spreadsheet,
+ * just to make other cases evident during debug
+ *
+ *if(e2e->clks_cfg.voltage == dm_vmax)
+ * dispclk_ramp_margin_percent = 0.0;
+ */
+
+ /* account for ramping margin and downspread */
+ *dispclk = dml_max(*dppclk * dispclk_dppclk_ratio, e2e->pipe.dest.pixel_rate_mhz)
+ * (1.0 + (double) mode_lib->soc.downspread_percent / 100.0)
+ * (1.0 + (double) dispclk_ramp_margin_percent / 100.0);
+
+ return;
+}
+
+bool dml_clks_pipe_clock_requirement_fit_power_constraint(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_dpp_in_grp)
+{
+ double dppclk = 0;
+ double dispclk = 0;
+ bool dppdiv = 0;
+
+ calculate_pipe_clk_requirement(mode_lib, e2e, num_dpp_in_grp, &dppclk, &dispclk, &dppdiv);
+
+ if (power_state(mode_lib, dispclk, dppclk) > e2e->clks_cfg.voltage) {
+ return false;
+ }
+
+ return true;
+}
+
+static void get_plane_clks(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes,
+ double *dppclks,
+ double *dispclks,
+ bool *dppdiv)
+{
+ /* it is assumed that the scale ratios passed into the e2e pipe params have already been calculated
+ * for any split pipe configurations, where extra pixels inthe overlap region do not contribute to
+ * the scale ratio. This means that we can simply calculate the dppclk for each dpp independently
+ * and we would expect the same result on any split pipes, which would be handled
+ */
+ unsigned int i;
+
+ for (i = 0; i < num_pipes; i++) {
+ double num_dpp_in_grp;
+ double dispclk_ramp_margin_percent;
+ double dispclk_margined;
+
+ if (e2e[i].pipe.src.is_hsplit)
+ num_dpp_in_grp = (double) dpp_in_grp(
+ e2e,
+ num_pipes,
+ e2e[i].pipe.src.hsplit_grp);
+ else
+ num_dpp_in_grp = 1;
+
+ calculate_pipe_clk_requirement(
+ mode_lib,
+ &e2e[i],
+ num_dpp_in_grp,
+ &dppclks[i],
+ &dispclks[i],
+ &dppdiv[i]);
+
+ dispclk_ramp_margin_percent = mode_lib->ip.dispclk_ramp_margin_percent;
+
+ dispclk_margined = e2e[i].pipe.dest.pixel_rate_mhz
+ * (1.0 + (double) mode_lib->soc.downspread_percent / 100.0)
+ * (1.0 + (double) dispclk_ramp_margin_percent / 100.0);
+
+ DTRACE("p%d: requested power state: %d", i, (int) e2e[0].clks_cfg.voltage);
+
+ if (power_state(mode_lib, dispclks[i], dppclks[i])
+ > power_state(mode_lib, dispclk_margined, dispclk_margined)
+ && dispclk_margined > dppclks[i]) {
+ if (power_state(mode_lib, dispclks[i], dppclks[i])
+ > e2e[0].clks_cfg.voltage) {
+ dispclks[i] = dispclk_margined;
+ dppclks[i] = dispclk_margined;
+ dppdiv[i] = false;
+ }
+ }
+
+ DTRACE("p%d: dispclk: %f", i, dispclks[i]);
+ }
+}
+
+static void get_dcfclk(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes,
+ double *dcfclk_mhz)
+{
+ double bytes_per_pixel_det_y[DC__NUM_PIPES__MAX];
+ double bytes_per_pixel_det_c[DC__NUM_PIPES__MAX];
+ double swath_width_y[DC__NUM_PIPES__MAX];
+ unsigned int i;
+ double total_read_bandwidth_gbps = 0.0;
+
+ for (i = 0; i < num_pipes; i++) {
+ if (e2e[i].pipe.src.source_scan == dm_horz) {
+ swath_width_y[i] = e2e[i].pipe.src.viewport_width * 1.0;
+ } else {
+ swath_width_y[i] = e2e[i].pipe.src.viewport_height * 1.0;
+ }
+
+ switch (e2e[i].pipe.src.source_format) {
+ case dm_444_64:
+ bytes_per_pixel_det_y[i] = 8.0;
+ bytes_per_pixel_det_c[i] = 0.0;
+ break;
+ case dm_444_32:
+ bytes_per_pixel_det_y[i] = 4.0;
+ bytes_per_pixel_det_c[i] = 0.0;
+ break;
+ case dm_444_16:
+ bytes_per_pixel_det_y[i] = 2.0;
+ bytes_per_pixel_det_c[i] = 0.0;
+ break;
+ case dm_422_8:
+ bytes_per_pixel_det_y[i] = 2.0;
+ bytes_per_pixel_det_c[i] = 0.0;
+ break;
+ case dm_422_10:
+ bytes_per_pixel_det_y[i] = 4.0;
+ bytes_per_pixel_det_c[i] = 0.0;
+ break;
+ case dm_420_8:
+ bytes_per_pixel_det_y[i] = 1.0;
+ bytes_per_pixel_det_c[i] = 2.0;
+ break;
+ case dm_420_10:
+ bytes_per_pixel_det_y[i] = 4.0 / 3.0;
+ bytes_per_pixel_det_c[i] = 8.0 / 3.0;
+ break;
+ default:
+ BREAK_TO_DEBUGGER(); /* invalid src_format in get_dcfclk */
+ }
+ }
+
+ for (i = 0; i < num_pipes; i++) {
+ double read_bandwidth_plane_mbps = 0.0;
+ read_bandwidth_plane_mbps = (double) swath_width_y[i]
+ * ((double) bytes_per_pixel_det_y[i]
+ + (double) bytes_per_pixel_det_c[i] / 2.0)
+ / ((double) e2e[i].pipe.dest.htotal
+ / (double) e2e[i].pipe.dest.pixel_rate_mhz)
+ * e2e[i].pipe.scale_ratio_depth.vscl_ratio;
+
+ if (e2e[i].pipe.src.dcc) {
+ read_bandwidth_plane_mbps += (read_bandwidth_plane_mbps / 1000.0 / 256.0);
+ }
+
+ if (e2e[i].pipe.src.vm) {
+ read_bandwidth_plane_mbps += (read_bandwidth_plane_mbps / 1000.0 / 512.0);
+ }
+
+ total_read_bandwidth_gbps = total_read_bandwidth_gbps
+ + read_bandwidth_plane_mbps / 1000.0;
+ }
+
+ DTRACE("total bandwidth = %f gbps", total_read_bandwidth_gbps);
+
+ (*dcfclk_mhz) = (total_read_bandwidth_gbps * 1000.0) / mode_lib->soc.return_bus_width_bytes;
+
+ DTRACE(
+ "minimum theoretical dcfclk without stutter and full utilization = %f MHz",
+ (*dcfclk_mhz));
+
+}
+
+struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_display_pipe_clock_st clocks;
+ double max_dispclk = 0.0;
+ double dcfclk;
+ double dispclks[DC__NUM_PIPES__MAX];
+ double dppclks[DC__NUM_PIPES__MAX];
+ bool dppdiv[DC__NUM_PIPES__MAX];
+ unsigned int i;
+
+ DTRACE("Calculating pipe clocks...");
+
+ /* this is the theoretical minimum, have to adjust based on valid values for soc */
+ get_dcfclk(mode_lib, e2e, num_pipes, &dcfclk);
+
+ /* if(dcfclk > soc.vnom.dcfclk_mhz)
+ * dcfclk = soc.vmax.dcfclk_mhz;
+ * else if(dcfclk > soc.vmin.dcfclk_mhz)
+ * dcfclk = soc.vnom.dcfclk_mhz;
+ * else
+ * dcfclk = soc.vmin.dcfclk_mhz;
+ */
+
+ dcfclk = dml_socbb_voltage_scaling(
+ &mode_lib->soc,
+ (enum voltage_state) e2e[0].clks_cfg.voltage).dcfclk_mhz;
+ clocks.dcfclk_mhz = dcfclk;
+
+ get_plane_clks(mode_lib, e2e, num_pipes, dppclks, dispclks, dppdiv);
+
+ for (i = 0; i < num_pipes; i++) {
+ max_dispclk = dml_max(max_dispclk, dispclks[i]);
+ }
+
+ clocks.dispclk_mhz = max_dispclk;
+ DTRACE("dispclk: %f Mhz", clocks.dispclk_mhz);
+ DTRACE("dcfclk: %f Mhz", clocks.dcfclk_mhz);
+
+ for (i = 0; i < num_pipes; i++) {
+ if (dppclks[i] * 2 < max_dispclk)
+ dppdiv[i] = 1;
+
+ if (dppdiv[i])
+ clocks.dppclk_div[i] = 1;
+ else
+ clocks.dppclk_div[i] = 0;
+
+ clocks.dppclk_mhz[i] = max_dispclk / ((dppdiv[i]) ? 2.0 : 1.0);
+ DTRACE("dppclk%d: %f Mhz", i, clocks.dppclk_mhz[i]);
+ }
+
+ return clocks;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h b/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
new file mode 100644
index 0000000..aed5f33
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_PIPE_CLOCKS_H__
+#define __DISPLAY_PIPE_CLOCKS_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes);
+
+bool dml_clks_pipe_clock_requirement_fit_power_constraint(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_dpp_in_grp);
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
new file mode 100644
index 0000000..9fccbbf
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
@@ -0,0 +1,2254 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "display_rq_dlg_calc.h"
+#include "display_mode_lib.h"
+
+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
+{
+ unsigned int ret_val = 0;
+
+ if (source_format == dm_444_16) {
+ if (!is_chroma)
+ ret_val = 2;
+ } else if (source_format == dm_444_32) {
+ if (!is_chroma)
+ ret_val = 4;
+ } else if (source_format == dm_444_64) {
+ if (!is_chroma)
+ ret_val = 8;
+ } else if (source_format == dm_420_8) {
+ if (is_chroma)
+ ret_val = 2;
+ else
+ ret_val = 1;
+ } else if (source_format == dm_420_10) {
+ if (is_chroma)
+ ret_val = 4;
+ else
+ ret_val = 2;
+ }
+ return ret_val;
+}
+
+static bool is_dual_plane(enum source_format_class source_format)
+{
+ bool ret_val = 0;
+
+ if ((source_format == dm_420_8) || (source_format == dm_420_10))
+ ret_val = 1;
+
+ return ret_val;
+}
+
+static void get_blk256_size(
+ unsigned int *blk256_width,
+ unsigned int *blk256_height,
+ unsigned int bytes_per_element)
+{
+ if (bytes_per_element == 1) {
+ *blk256_width = 16;
+ *blk256_height = 16;
+ } else if (bytes_per_element == 2) {
+ *blk256_width = 16;
+ *blk256_height = 8;
+ } else if (bytes_per_element == 4) {
+ *blk256_width = 8;
+ *blk256_height = 8;
+ } else if (bytes_per_element == 8) {
+ *blk256_width = 8;
+ *blk256_height = 4;
+ }
+}
+
+static double get_refcyc_per_delivery(
+ struct display_mode_lib *mode_lib,
+ double refclk_freq_in_mhz,
+ double pclk_freq_in_mhz,
+ int unsigned recout_width,
+ double vratio,
+ double hscale_pixel_rate,
+ int unsigned delivery_width,
+ int unsigned req_per_swath_ub)
+{
+ double refcyc_per_delivery = 0.0;
+ if (vratio <= 1.0) {
+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
+ / pclk_freq_in_mhz / (double) req_per_swath_ub;
+ } else {
+ refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
+ / (double) hscale_pixel_rate / (double) req_per_swath_ub;
+ }
+
+ DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz);
+ DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz);
+ DTRACE("DLG: %s: recout_width = %d", __func__, recout_width);
+ DTRACE("DLG: %s: vratio = %3.2f", __func__, vratio);
+ DTRACE("DLG: %s: req_per_swath_ub = %d", __func__, req_per_swath_ub);
+ DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery);
+
+ return refcyc_per_delivery;
+
+}
+
+static double get_vratio_pre(
+ struct display_mode_lib *mode_lib,
+ unsigned int max_num_sw,
+ unsigned int max_partial_sw,
+ unsigned int swath_height,
+ double vinit,
+ double l_sw)
+{
+ double prefill = dml_floor(vinit);
+ double vratio_pre = 1.0;
+
+ vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw;
+
+ if (swath_height > 4) {
+ double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0);
+ if (tmp0 > vratio_pre)
+ vratio_pre = tmp0;
+ }
+
+ DTRACE("DLG: %s: max_num_sw = %0d", __func__, max_num_sw);
+ DTRACE("DLG: %s: max_partial_sw = %0d", __func__, max_partial_sw);
+ DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
+ DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit);
+ DTRACE("DLG: %s: vratio_pre = %3.2f", __func__, vratio_pre);
+
+ if (vratio_pre < 1.0) {
+ DTRACE("WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre);
+ vratio_pre = 1.0;
+ }
+
+ if (vratio_pre > 4.0) {
+ DTRACE(
+ "WARNING_DLG: %s: vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0",
+ __func__,
+ vratio_pre);
+ vratio_pre = 4.0;
+ }
+
+ return vratio_pre;
+}
+
+static void get_swath_need(
+ struct display_mode_lib *mode_lib,
+ unsigned int *max_num_sw,
+ unsigned int *max_partial_sw,
+ unsigned int swath_height,
+ double vinit)
+{
+ double prefill = dml_floor(vinit);
+ unsigned int max_partial_sw_int;
+
+ DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
+ DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit);
+
+ ASSERT(prefill > 0.0 && prefill <= 8.0);
+
+ *max_num_sw = (int unsigned) (dml_ceil((prefill - 1.0) / (double) swath_height) + 1.0); /* prefill has to be >= 1 */
+ max_partial_sw_int =
+ (prefill == 1) ?
+ (swath_height - 1) :
+ ((int unsigned) (prefill - 2.0) % swath_height);
+ *max_partial_sw = (max_partial_sw_int < 1) ? 1 : max_partial_sw_int; /* ensure minimum of 1 is used */
+
+ DTRACE("DLG: %s: max_num_sw = %0d", __func__, *max_num_sw);
+ DTRACE("DLG: %s: max_partial_sw = %0d", __func__, *max_partial_sw);
+}
+
+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
+{
+ if (tile_size == dm_256k_tile)
+ return (256 * 1024);
+ else if (tile_size == dm_64k_tile)
+ return (64 * 1024);
+ else
+ return (4 * 1024);
+}
+
+static void extract_rq_sizing_regs(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_regs_st *rq_regs,
+ const struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing)
+{
+ DTRACE("DLG: %s: rq_sizing param", __func__);
+ print__data_rq_sizing_params_st(mode_lib, rq_sizing);
+
+ rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
+
+ if (rq_sizing.min_chunk_bytes == 0)
+ rq_regs->min_chunk_size = 0;
+ else
+ rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
+
+ rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
+ if (rq_sizing.min_meta_chunk_bytes == 0)
+ rq_regs->min_meta_chunk_size = 0;
+ else
+ rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
+
+ rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
+ rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
+}
+
+void extract_rq_regs(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ const struct _vcs_dpi_display_rq_params_st rq_param)
+{
+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+ unsigned int detile_buf_plane1_addr = 0;
+
+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
+ if (rq_param.yuv420)
+ extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
+
+ rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+ rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+
+ /* FIXME: take the max between luma, chroma chunk size?
+ * okay for now, as we are setting chunk_bytes to 8kb anyways
+ */
+ if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */
+ rq_regs->drq_expansion_mode = 0;
+ } else {
+ rq_regs->drq_expansion_mode = 2;
+ }
+ rq_regs->prq_expansion_mode = 1;
+ rq_regs->mrq_expansion_mode = 1;
+ rq_regs->crq_expansion_mode = 1;
+
+ if (rq_param.yuv420) {
+ if ((double) rq_param.misc.rq_l.stored_swath_bytes
+ / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
+ detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */
+ } else {
+ detile_buf_plane1_addr = dml_round_to_multiple(
+ (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
+ 256,
+ 0) / 64.0; /* 2/3 to chroma */
+ }
+ }
+ rq_regs->plane1_base_address = detile_buf_plane1_addr;
+}
+
+static void handle_det_buf_split(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_params_st *rq_param,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
+{
+ unsigned int total_swath_bytes = 0;
+ unsigned int swath_bytes_l = 0;
+ unsigned int swath_bytes_c = 0;
+ unsigned int full_swath_bytes_packed_l = 0;
+ unsigned int full_swath_bytes_packed_c = 0;
+ bool req128_l = 0;
+ bool req128_c = 0;
+ bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
+ bool surf_vert = (pipe_src_param.source_scan == dm_vert);
+ unsigned int log2_swath_height_l = 0;
+ unsigned int log2_swath_height_c = 0;
+ unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+
+ full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
+ full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
+
+ if (rq_param->yuv420_10bpc) {
+ full_swath_bytes_packed_l = dml_round_to_multiple(
+ rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
+ 256,
+ 1) + 256;
+ full_swath_bytes_packed_c = dml_round_to_multiple(
+ rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
+ 256,
+ 1) + 256;
+ }
+
+ if (rq_param->yuv420) {
+ total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
+
+ if (total_swath_bytes <= detile_buf_size_in_bytes) { /*full 256b request */
+ req128_l = 0;
+ req128_c = 0;
+ swath_bytes_l = full_swath_bytes_packed_l;
+ swath_bytes_c = full_swath_bytes_packed_c;
+ } else { /*128b request (for luma only for yuv420 8bpc) */
+ req128_l = 1;
+ req128_c = 0;
+ swath_bytes_l = full_swath_bytes_packed_l / 2;
+ swath_bytes_c = full_swath_bytes_packed_c;
+ }
+
+ /* Bug workaround, luma and chroma req size needs to be the same. (see: DEGVIDCN10-137)
+ * TODO: Remove after rtl fix
+ */
+ if (req128_l == 1) {
+ req128_c = 1;
+ DTRACE("DLG: %s: bug workaround DEGVIDCN10-137", __func__);
+ }
+
+ /* Note: assumption, the config that pass in will fit into
+ * the detiled buffer.
+ */
+ } else {
+ total_swath_bytes = 2 * full_swath_bytes_packed_l;
+
+ if (total_swath_bytes <= detile_buf_size_in_bytes)
+ req128_l = 0;
+ else
+ req128_l = 1;
+
+ swath_bytes_l = total_swath_bytes;
+ swath_bytes_c = 0;
+ }
+ rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
+ rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
+
+ if (surf_linear) {
+ log2_swath_height_l = 0;
+ log2_swath_height_c = 0;
+ } else if (!surf_vert) {
+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
+ } else {
+ log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
+ log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
+ }
+ rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
+ rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
+
+ DTRACE("DLG: %s: req128_l = %0d", __func__, req128_l);
+ DTRACE("DLG: %s: req128_c = %0d", __func__, req128_c);
+ DTRACE("DLG: %s: full_swath_bytes_packed_l = %0d", __func__, full_swath_bytes_packed_l);
+ DTRACE("DLG: %s: full_swath_bytes_packed_c = %0d", __func__, full_swath_bytes_packed_c);
+}
+
+/* Need refactor. */
+void dml_rq_dlg_get_row_heights(
+ struct display_mode_lib *mode_lib,
+ unsigned int *o_dpte_row_height,
+ unsigned int *o_meta_row_height,
+ unsigned int vp_width,
+ unsigned int data_pitch,
+ int source_format,
+ int tiling,
+ int macro_tile_size,
+ int source_scan,
+ int is_chroma)
+{
+ bool surf_linear = (tiling == dm_sw_linear);
+ bool surf_vert = (source_scan == dm_vert);
+
+ unsigned int bytes_per_element = get_bytes_per_element(
+ (enum source_format_class) source_format,
+ is_chroma);
+ unsigned int log2_bytes_per_element = dml_log2(bytes_per_element);
+ unsigned int blk256_width = 0;
+ unsigned int blk256_height = 0;
+
+ unsigned int log2_blk256_height;
+ unsigned int blk_bytes;
+ unsigned int log2_blk_bytes;
+ unsigned int log2_blk_height;
+ unsigned int log2_blk_width;
+ unsigned int log2_meta_req_bytes;
+ unsigned int log2_meta_req_height;
+ unsigned int log2_meta_req_width;
+ unsigned int log2_meta_row_height;
+ unsigned int log2_vmpg_bytes;
+ unsigned int dpte_buf_in_pte_reqs;
+ unsigned int log2_vmpg_height;
+ unsigned int log2_vmpg_width;
+ unsigned int log2_dpte_req_height_ptes;
+ unsigned int log2_dpte_req_width_ptes;
+ unsigned int log2_dpte_req_height;
+ unsigned int log2_dpte_req_width;
+ unsigned int log2_dpte_row_height_linear;
+ unsigned int log2_dpte_row_height;
+ unsigned int dpte_req_width;
+
+ if (surf_linear) {
+ blk256_width = 256;
+ blk256_height = 1;
+ } else {
+ get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
+ }
+
+ log2_blk256_height = dml_log2((double) blk256_height);
+ blk_bytes = surf_linear ?
+ 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
+ log2_blk_bytes = dml_log2((double) blk_bytes);
+ log2_blk_height = 0;
+ log2_blk_width = 0;
+
+ /* remember log rule
+ * "+" in log is multiply
+ * "-" in log is divide
+ * "/2" is like square root
+ * blk is vertical biased
+ */
+ if (tiling != dm_sw_linear)
+ log2_blk_height = log2_blk256_height
+ + dml_ceil((double) (log2_blk_bytes - 8) / 2.0);
+ else
+ log2_blk_height = 0; /* blk height of 1 */
+
+ log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
+
+ /* ------- */
+ /* meta */
+ /* ------- */
+ log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
+
+ /* each 64b meta request for dcn is 8x8 meta elements and
+ * a meta element covers one 256b block of the the data surface.
+ */
+ log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 */
+ log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
+ - log2_meta_req_height;
+ log2_meta_row_height = 0;
+
+ /* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
+ * calculate upper bound of the meta_row_width
+ */
+ if (!surf_vert)
+ log2_meta_row_height = log2_meta_req_height;
+ else
+ log2_meta_row_height = log2_meta_req_width;
+
+ *o_meta_row_height = 1 << log2_meta_row_height;
+
+ /* ------ */
+ /* dpte */
+ /* ------ */
+ log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
+ dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+
+ log2_vmpg_height = 0;
+ log2_vmpg_width = 0;
+ log2_dpte_req_height_ptes = 0;
+ log2_dpte_req_width_ptes = 0;
+ log2_dpte_req_height = 0;
+ log2_dpte_req_width = 0;
+ log2_dpte_row_height_linear = 0;
+ log2_dpte_row_height = 0;
+ dpte_req_width = 0; /* 64b dpte req width in data element */
+
+ if (surf_linear) {
+ log2_vmpg_height = 0; /* one line high */
+ } else {
+ log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
+ }
+ log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
+
+ /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
+ if (log2_blk_bytes <= log2_vmpg_bytes)
+ log2_dpte_req_height_ptes = 0;
+ else if (log2_blk_height - log2_vmpg_height >= 2)
+ log2_dpte_req_height_ptes = 2;
+ else
+ log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
+ log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
+
+ ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
+ (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
+ (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
+
+ /* the dpte request dimensions in data elements is dpte_req_width x dpte_req_height
+ * log2_wmpg_width is how much 1 pte represent, now trying to calculate how much 64b pte req represent
+ */
+ log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
+ log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
+ dpte_req_width = 1 << log2_dpte_req_width;
+
+ /* calculate pitch dpte row buffer can hold
+ * round the result down to a power of two.
+ */
+ if (surf_linear) {
+ log2_dpte_row_height_linear = dml_floor(
+ dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch));
+
+ ASSERT(log2_dpte_row_height_linear >= 3);
+
+ if (log2_dpte_row_height_linear > 7)
+ log2_dpte_row_height_linear = 7;
+
+ log2_dpte_row_height = log2_dpte_row_height_linear;
+ } else {
+ /* the upper bound of the dpte_row_width without dependency on viewport position follows. */
+ if (!surf_vert) {
+ log2_dpte_row_height = log2_dpte_req_height;
+ } else {
+ log2_dpte_row_height =
+ (log2_blk_width < log2_dpte_req_width) ?
+ log2_blk_width : log2_dpte_req_width;
+ }
+ }
+
+ /* From programming guide:
+ * There is a special case of saving only half of ptes returned due to buffer space limits.
+ * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
+ * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
+ */
+ if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
+ && log2_blk_bytes >= 16) {
+ log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
+ }
+
+ *o_dpte_row_height = 1 << log2_dpte_row_height;
+}
+
+static void get_surf_rq_param(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param,
+ struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param,
+ struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param,
+ bool is_chroma)
+{
+ bool mode_422 = 0;
+ unsigned int vp_width = 0;
+ unsigned int vp_height = 0;
+ unsigned int data_pitch = 0;
+ unsigned int meta_pitch = 0;
+ unsigned int ppe = mode_422 ? 2 : 1;
+ bool surf_linear;
+ bool surf_vert;
+ unsigned int bytes_per_element;
+ unsigned int log2_bytes_per_element;
+ unsigned int blk256_width;
+ unsigned int blk256_height;
+ unsigned int log2_blk256_width;
+ unsigned int log2_blk256_height;
+ unsigned int blk_bytes;
+ unsigned int log2_blk_bytes;
+ unsigned int log2_blk_height;
+ unsigned int log2_blk_width;
+ unsigned int log2_meta_req_bytes;
+ unsigned int log2_meta_req_height;
+ unsigned int log2_meta_req_width;
+ unsigned int meta_req_width;
+ unsigned int meta_req_height;
+ unsigned int log2_meta_row_height;
+ unsigned int meta_row_width_ub;
+ unsigned int log2_meta_chunk_bytes;
+ unsigned int log2_meta_chunk_height;
+ unsigned int log2_meta_chunk_width;
+ unsigned int log2_min_meta_chunk_bytes;
+ unsigned int min_meta_chunk_width;
+ unsigned int meta_chunk_width;
+ unsigned int meta_chunk_per_row_int;
+ unsigned int meta_row_remainder;
+ unsigned int meta_chunk_threshold;
+ unsigned int meta_blk_bytes;
+ unsigned int meta_blk_height;
+ unsigned int meta_blk_width;
+ unsigned int meta_surface_bytes;
+ unsigned int vmpg_bytes;
+ unsigned int meta_pte_req_per_frame_ub;
+ unsigned int meta_pte_bytes_per_frame_ub;
+ unsigned int log2_vmpg_bytes;
+ unsigned int dpte_buf_in_pte_reqs;
+ unsigned int log2_vmpg_height;
+ unsigned int log2_vmpg_width;
+ unsigned int log2_dpte_req_height_ptes;
+ unsigned int log2_dpte_req_width_ptes;
+ unsigned int log2_dpte_req_height;
+ unsigned int log2_dpte_req_width;
+ unsigned int log2_dpte_row_height_linear;
+ unsigned int log2_dpte_row_height;
+ unsigned int log2_dpte_group_width;
+ unsigned int dpte_row_width_ub;
+ unsigned int dpte_row_height;
+ unsigned int dpte_req_height;
+ unsigned int dpte_req_width;
+ unsigned int dpte_group_width;
+ unsigned int log2_dpte_group_bytes;
+ unsigned int log2_dpte_group_length;
+ unsigned int func_meta_row_height, func_dpte_row_height;
+
+ /* FIXME check if ppe apply for both luma and chroma in 422 case */
+ if (is_chroma) {
+ vp_width = pipe_src_param.viewport_width_c / ppe;
+ vp_height = pipe_src_param.viewport_height_c;
+ data_pitch = pipe_src_param.data_pitch_c;
+ meta_pitch = pipe_src_param.meta_pitch_c;
+ } else {
+ vp_width = pipe_src_param.viewport_width / ppe;
+ vp_height = pipe_src_param.viewport_height;
+ data_pitch = pipe_src_param.data_pitch;
+ meta_pitch = pipe_src_param.meta_pitch;
+ }
+
+ rq_sizing_param->chunk_bytes = 8192;
+
+ if (rq_sizing_param->chunk_bytes == 64 * 1024)
+ rq_sizing_param->min_chunk_bytes = 0;
+ else
+ rq_sizing_param->min_chunk_bytes = 1024;
+
+ rq_sizing_param->meta_chunk_bytes = 2048;
+ rq_sizing_param->min_meta_chunk_bytes = 256;
+
+ rq_sizing_param->mpte_group_bytes = 2048;
+
+ surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
+ surf_vert = (pipe_src_param.source_scan == dm_vert);
+
+ bytes_per_element = get_bytes_per_element(
+ (enum source_format_class) pipe_src_param.source_format,
+ is_chroma);
+ log2_bytes_per_element = dml_log2(bytes_per_element);
+ blk256_width = 0;
+ blk256_height = 0;
+
+ if (surf_linear) {
+ blk256_width = 256 / bytes_per_element;
+ blk256_height = 1;
+ } else {
+ get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
+ }
+
+ DTRACE("DLG: %s: surf_linear = %d", __func__, surf_linear);
+ DTRACE("DLG: %s: surf_vert = %d", __func__, surf_vert);
+ DTRACE("DLG: %s: blk256_width = %d", __func__, blk256_width);
+ DTRACE("DLG: %s: blk256_height = %d", __func__, blk256_height);
+
+ log2_blk256_width = dml_log2((double) blk256_width);
+ log2_blk256_height = dml_log2((double) blk256_height);
+ blk_bytes =
+ surf_linear ? 256 : get_blk_size_bytes(
+ (enum source_macro_tile_size) pipe_src_param.macro_tile_size);
+ log2_blk_bytes = dml_log2((double) blk_bytes);
+ log2_blk_height = 0;
+ log2_blk_width = 0;
+
+ /* remember log rule
+ * "+" in log is multiply
+ * "-" in log is divide
+ * "/2" is like square root
+ * blk is vertical biased
+ */
+ if (pipe_src_param.sw_mode != dm_sw_linear)
+ log2_blk_height = log2_blk256_height
+ + dml_ceil((double) (log2_blk_bytes - 8) / 2.0);
+ else
+ log2_blk_height = 0; /* blk height of 1 */
+
+ log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
+
+ if (!surf_vert) {
+ rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
+ + blk256_width;
+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
+ } else {
+ rq_dlg_param->swath_width_ub = dml_round_to_multiple(
+ vp_height - 1,
+ blk256_height,
+ 1) + blk256_height;
+ rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
+ }
+
+ if (!surf_vert)
+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
+ * bytes_per_element;
+ else
+ rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
+ * bytes_per_element;
+
+ rq_misc_param->blk256_height = blk256_height;
+ rq_misc_param->blk256_width = blk256_width;
+
+ /* ------- */
+ /* meta */
+ /* ------- */
+ log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
+
+ /* each 64b meta request for dcn is 8x8 meta elements and
+ * a meta element covers one 256b block of the the data surface.
+ */
+ log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 byte, each byte represent 1 blk256 */
+ log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
+ - log2_meta_req_height;
+ meta_req_width = 1 << log2_meta_req_width;
+ meta_req_height = 1 << log2_meta_req_height;
+ log2_meta_row_height = 0;
+ meta_row_width_ub = 0;
+
+ /* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
+ * calculate upper bound of the meta_row_width
+ */
+ if (!surf_vert) {
+ log2_meta_row_height = log2_meta_req_height;
+ meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
+ + meta_req_width;
+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
+ } else {
+ log2_meta_row_height = log2_meta_req_width;
+ meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
+ + meta_req_height;
+ rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
+ }
+ rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
+
+ log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
+ log2_meta_chunk_height = log2_meta_row_height;
+
+ /*full sized meta chunk width in unit of data elements */
+ log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
+ - log2_meta_chunk_height;
+ log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
+ min_meta_chunk_width = 1
+ << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
+ - log2_meta_chunk_height);
+ meta_chunk_width = 1 << log2_meta_chunk_width;
+ meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
+ meta_row_remainder = meta_row_width_ub % meta_chunk_width;
+ meta_chunk_threshold = 0;
+ meta_blk_bytes = 4096;
+ meta_blk_height = blk256_height * 64;
+ meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
+ meta_surface_bytes = meta_pitch
+ * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
+ + meta_blk_height) * bytes_per_element / 256;
+ vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
+ meta_pte_req_per_frame_ub = (dml_round_to_multiple(
+ meta_surface_bytes - vmpg_bytes,
+ 8 * vmpg_bytes,
+ 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
+ meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; /*64B mpte request */
+ rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
+
+ DTRACE("DLG: %s: meta_blk_height = %d", __func__, meta_blk_height);
+ DTRACE("DLG: %s: meta_blk_width = %d", __func__, meta_blk_width);
+ DTRACE("DLG: %s: meta_surface_bytes = %d", __func__, meta_surface_bytes);
+ DTRACE("DLG: %s: meta_pte_req_per_frame_ub = %d", __func__, meta_pte_req_per_frame_ub);
+ DTRACE("DLG: %s: meta_pte_bytes_per_frame_ub = %d", __func__, meta_pte_bytes_per_frame_ub);
+
+ if (!surf_vert)
+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
+ else
+ meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
+
+ if (meta_row_remainder <= meta_chunk_threshold)
+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+ else
+ rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+
+ rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
+
+ /* ------ */
+ /* dpte */
+ /* ------ */
+ log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
+ dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+
+ log2_vmpg_height = 0;
+ log2_vmpg_width = 0;
+ log2_dpte_req_height_ptes = 0;
+ log2_dpte_req_width_ptes = 0;
+ log2_dpte_req_height = 0;
+ log2_dpte_req_width = 0;
+ log2_dpte_row_height_linear = 0;
+ log2_dpte_row_height = 0;
+ log2_dpte_group_width = 0;
+ dpte_row_width_ub = 0;
+ dpte_row_height = 0;
+ dpte_req_height = 0; /* 64b dpte req height in data element */
+ dpte_req_width = 0; /* 64b dpte req width in data element */
+ dpte_group_width = 0;
+ log2_dpte_group_bytes = 0;
+ log2_dpte_group_length = 0;
+
+ if (surf_linear) {
+ log2_vmpg_height = 0; /* one line high */
+ } else {
+ log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
+ }
+ log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
+
+ /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
+ if (log2_blk_bytes <= log2_vmpg_bytes)
+ log2_dpte_req_height_ptes = 0;
+ else if (log2_blk_height - log2_vmpg_height >= 2)
+ log2_dpte_req_height_ptes = 2;
+ else
+ log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
+ log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
+
+ /* Ensure we only have the 3 shapes */
+ ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
+ (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
+ (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
+
+ /* The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
+ * log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
+ * That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
+ */
+ log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
+ log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
+ dpte_req_height = 1 << log2_dpte_req_height;
+ dpte_req_width = 1 << log2_dpte_req_width;
+
+ /* calculate pitch dpte row buffer can hold
+ * round the result down to a power of two.
+ */
+ if (surf_linear) {
+ log2_dpte_row_height_linear = dml_floor(
+ dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch));
+
+ ASSERT(log2_dpte_row_height_linear >= 3);
+
+ if (log2_dpte_row_height_linear > 7)
+ log2_dpte_row_height_linear = 7;
+
+ log2_dpte_row_height = log2_dpte_row_height_linear;
+ rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
+
+ /* For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
+ * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
+ */
+ dpte_row_width_ub = dml_round_to_multiple(
+ data_pitch * dpte_row_height - 1,
+ dpte_req_width,
+ 1) + dpte_req_width;
+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+ } else {
+ /* for tiled mode, row height is the same as req height and row store up to vp size upper bound */
+ if (!surf_vert) {
+ log2_dpte_row_height = log2_dpte_req_height;
+ dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
+ + dpte_req_width;
+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+ } else {
+ log2_dpte_row_height =
+ (log2_blk_width < log2_dpte_req_width) ?
+ log2_blk_width : log2_dpte_req_width;
+ dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
+ + dpte_req_height;
+ rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
+ }
+ rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
+ }
+ rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64;
+
+ /* From programming guide:
+ * There is a special case of saving only half of ptes returned due to buffer space limits.
+ * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
+ * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
+ */
+ if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
+ && log2_blk_bytes >= 16) {
+ log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
+ rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
+ }
+
+ /* the dpte_group_bytes is reduced for the specific case of vertical
+ * access of a tile surface that has dpte request of 8x1 ptes.
+ */
+ if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) /*reduced, in this case, will have page fault within a group */
+ rq_sizing_param->dpte_group_bytes = 512;
+ else
+ /*full size */
+ rq_sizing_param->dpte_group_bytes = 2048;
+
+ /*since pte request size is 64byte, the number of data pte requests per full sized group is as follows. */
+ log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
+ log2_dpte_group_length = log2_dpte_group_bytes - 6; /*length in 64b requests */
+
+ /* full sized data pte group width in elements */
+ if (!surf_vert)
+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
+ else
+ log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
+
+ dpte_group_width = 1 << log2_dpte_group_width;
+
+ /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
+ * the upper bound for the dpte groups per row is as follows.
+ */
+ rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
+ (double) dpte_row_width_ub / dpte_group_width);
+
+ dml_rq_dlg_get_row_heights(
+ mode_lib,
+ &func_dpte_row_height,
+ &func_meta_row_height,
+ vp_width,
+ data_pitch,
+ pipe_src_param.source_format,
+ pipe_src_param.sw_mode,
+ pipe_src_param.macro_tile_size,
+ pipe_src_param.source_scan,
+ is_chroma);
+
+ /* Just a check to make sure this function and the new one give the same
+ * result. The standalone get_row_heights() function is based off of the
+ * code in this function so the same changes need to be made to both.
+ */
+ if (rq_dlg_param->meta_row_height != func_meta_row_height) {
+ DTRACE(
+ "MISMATCH: rq_dlg_param->meta_row_height = %d",
+ rq_dlg_param->meta_row_height);
+ DTRACE("MISMATCH: func_meta_row_height = %d", func_meta_row_height);
+ ASSERT(0);
+ }
+
+ if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
+ DTRACE(
+ "MISMATCH: rq_dlg_param->dpte_row_height = %d",
+ rq_dlg_param->dpte_row_height);
+ DTRACE("MISMATCH: func_dpte_row_height = %d", func_dpte_row_height);
+ ASSERT(0);
+ }
+}
+
+void dml_rq_dlg_get_rq_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_params_st *rq_param,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
+{
+ /* get param for luma surface */
+ rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
+ || pipe_src_param.source_format == dm_420_10;
+ rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
+
+ get_surf_rq_param(
+ mode_lib,
+ &(rq_param->sizing.rq_l),
+ &(rq_param->dlg.rq_l),
+ &(rq_param->misc.rq_l),
+ pipe_src_param,
+ 0);
+
+ if (is_dual_plane((enum source_format_class) pipe_src_param.source_format)) {
+ /* get param for chroma surface */
+ get_surf_rq_param(
+ mode_lib,
+ &(rq_param->sizing.rq_c),
+ &(rq_param->dlg.rq_c),
+ &(rq_param->misc.rq_c),
+ pipe_src_param,
+ 1);
+ }
+
+ /* calculate how to split the det buffer space between luma and chroma */
+ handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
+ print__rq_params_st(mode_lib, *rq_param);
+}
+
+void dml_rq_dlg_get_rq_reg(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
+{
+ struct _vcs_dpi_display_rq_params_st rq_param = {0};
+
+ memset(rq_regs, 0, sizeof(*rq_regs));
+
+ dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_src_param);
+ extract_rq_regs(mode_lib, rq_regs, rq_param);
+
+ print__rq_regs_st(mode_lib, *rq_regs);
+}
+
+/* TODO: Need refactor, so this is used by dml_rq_dlg_get_dlg_params as well
+ * The problem is that there are some intermediate terms that would need by
+ * some dlg calculation (i.e. rest of prefetch and active prog guide calculation)
+ */
+void dml_rq_dlg_get_dlg_params_prefetch(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_prefetch_param_st *prefetch_param,
+ struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+ struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en)
+{
+ /* Prefetch */
+ unsigned int htotal = e2e_pipe_param.pipe.dest.htotal;
+ bool interlaced = e2e_pipe_param.pipe.dest.interlaced;
+ unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
+ const double prefetch_xy_calc_in_dcfclk = 24.0; /* FIXME: ip_param */
+ double min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
+ double t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz;
+
+ bool dcc_en = e2e_pipe_param.pipe.src.dcc;
+ bool dual_plane = is_dual_plane(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format);
+ unsigned int bytes_per_element_l = get_bytes_per_element(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
+ 0);
+ unsigned int bytes_per_element_c = get_bytes_per_element(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
+ 1);
+
+ double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz;
+ double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz;
+ double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz;
+
+ double line_time_in_us = (htotal / pclk_freq_in_mhz);
+ double vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;
+ double vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;
+ double vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;
+ double vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;
+
+ unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height;
+ unsigned int swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
+ unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
+ unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
+ unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
+
+ unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height;
+ unsigned int swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
+ unsigned int dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
+ unsigned int vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;
+ unsigned int vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;
+ unsigned int vready_offset = e2e_pipe_param.pipe.dest.vready_offset;
+
+ const unsigned int dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
+ const unsigned int dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
+ unsigned int pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz
+ / dppclk_freq_in_mhz
+ + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
+ unsigned int dst_y_after_scaler = 0;
+ unsigned int dst_x_after_scaler = 0;
+
+ unsigned int vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start;
+
+ double line_wait;
+ double line_o;
+ double line_setup;
+ double line_calc;
+ double dst_y_prefetch;
+ double t_pre_us;
+ int unsigned vm_bytes;
+ int unsigned meta_row_bytes;
+ int unsigned max_num_sw_l;
+ int unsigned max_num_sw_c;
+ int unsigned max_partial_sw_l;
+ int unsigned max_partial_sw_c;
+
+ double max_vinit_l;
+ double max_vinit_c;
+ int unsigned lsw_l;
+ int unsigned lsw_c;
+ int unsigned sw_bytes_ub_l;
+ int unsigned sw_bytes_ub_c;
+ int unsigned sw_bytes;
+ int unsigned dpte_row_bytes;
+
+ if (interlaced)
+ vstartup_start = vstartup_start / 2;
+
+ if (vstartup_start >= min_vblank) {
+ min_vblank = vstartup_start + 1;
+ DTRACE(
+ "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d",
+ __func__,
+ vstartup_start,
+ min_vblank);
+ }
+
+ if (e2e_pipe_param.pipe.src.is_hsplit)
+ dst_x_after_scaler = pixel_rate_delay_subtotal
+ + e2e_pipe_param.pipe.dest.recout_width;
+ else
+ dst_x_after_scaler = pixel_rate_delay_subtotal;
+
+ if (e2e_pipe_param.dout.output_format == dm_420)
+ dst_y_after_scaler = 1;
+ else
+ dst_y_after_scaler = 0;
+
+ if (dst_x_after_scaler >= htotal) {
+ dst_x_after_scaler = dst_x_after_scaler - htotal;
+ dst_y_after_scaler = dst_y_after_scaler + 1;
+ }
+
+ DTRACE("DLG: %s: htotal = %d", __func__, htotal);
+ DTRACE(
+ "DLG: %s: pixel_rate_delay_subtotal = %d",
+ __func__,
+ pixel_rate_delay_subtotal);
+ DTRACE("DLG: %s: dst_x_after_scaler = %d", __func__, dst_x_after_scaler);
+ DTRACE("DLG: %s: dst_y_after_scaler = %d", __func__, dst_y_after_scaler);
+
+ line_wait = mode_lib->soc.urgent_latency_us;
+ if (cstate_en)
+ line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
+ if (pstate_en)
+ line_wait = dml_max(
+ mode_lib->soc.dram_clock_change_latency_us
+ + mode_lib->soc.urgent_latency_us,
+ line_wait);
+ line_wait = line_wait / line_time_in_us;
+
+ line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal;
+ line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
+ line_calc = t_calc_us / line_time_in_us;
+
+ DTRACE(
+ "DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f",
+ __func__,
+ (double) mode_lib->soc.sr_enter_plus_exit_time_us);
+ DTRACE(
+ "DLG: %s: soc.dram_clock_change_latency_us = %3.2f",
+ __func__,
+ (double) mode_lib->soc.dram_clock_change_latency_us);
+
+ DTRACE("DLG: %s: urgent_latency_us = %3.2f", __func__, mode_lib->soc.urgent_latency_us);
+ DTRACE(
+ "DLG: %s: t_srx_delay_us = %3.2f",
+ __func__,
+ (double) dlg_sys_param.t_srx_delay_us);
+ DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us);
+ DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset);
+ DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width);
+ DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset);
+ DTRACE("DLG: %s: line_wait = %3.2f", __func__, line_wait);
+ DTRACE("DLG: %s: line_o = %3.2f", __func__, line_o);
+ DTRACE("DLG: %s: line_setup = %3.2f", __func__, line_setup);
+ DTRACE("DLG: %s: line_calc = %3.2f", __func__, line_calc);
+
+ dst_y_prefetch = ((double) min_vblank - 1.0)
+ - (line_setup + line_calc + line_wait + line_o);
+ DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch);
+ ASSERT(dst_y_prefetch >= 2.0);
+
+ dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125)) / 4;
+ DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch);
+
+ t_pre_us = dst_y_prefetch * line_time_in_us;
+ vm_bytes = 0;
+ meta_row_bytes = 0;
+
+ if (dcc_en && vm_en)
+ vm_bytes = meta_pte_bytes_per_frame_ub_l;
+ if (dcc_en)
+ meta_row_bytes = meta_bytes_per_row_ub_l;
+
+ max_num_sw_l = 0;
+ max_num_sw_c = 0;
+ max_partial_sw_l = 0;
+ max_partial_sw_c = 0;
+
+ max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l;
+ max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c;
+
+ get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l);
+ if (dual_plane)
+ get_swath_need(
+ mode_lib,
+ &max_num_sw_c,
+ &max_partial_sw_c,
+ swath_height_c,
+ max_vinit_c);
+
+ lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l;
+ lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c;
+ sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l;
+ sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c;
+ sw_bytes = 0;
+ dpte_row_bytes = 0;
+
+ if (vm_en) {
+ if (dual_plane)
+ dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c;
+ else
+ dpte_row_bytes = dpte_bytes_per_row_ub_l;
+ } else {
+ dpte_row_bytes = 0;
+ }
+
+ if (dual_plane)
+ sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c;
+ else
+ sw_bytes = sw_bytes_ub_l;
+
+ DTRACE("DLG: %s: sw_bytes_ub_l = %d", __func__, sw_bytes_ub_l);
+ DTRACE("DLG: %s: sw_bytes_ub_c = %d", __func__, sw_bytes_ub_c);
+ DTRACE("DLG: %s: sw_bytes = %d", __func__, sw_bytes);
+ DTRACE("DLG: %s: vm_bytes = %d", __func__, vm_bytes);
+ DTRACE("DLG: %s: meta_row_bytes = %d", __func__, meta_row_bytes);
+ DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes);
+
+ prefetch_param->prefetch_bw =
+ (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us;
+ prefetch_param->flip_bytes = (vm_bytes + dpte_row_bytes + meta_row_bytes);
+}
+
+/* Note: currently taken in as is.
+ * Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
+ */
+void dml_rq_dlg_get_dlg_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs,
+ const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+ const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+ const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en,
+ const bool iflip_en)
+{
+ /* Timing */
+ unsigned int htotal = e2e_pipe_param.pipe.dest.htotal;
+ unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end;
+ unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start;
+ unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end;
+ bool interlaced = e2e_pipe_param.pipe.dest.interlaced;
+ unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
+
+ double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz;
+ double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz;
+ double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz;
+ double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz;
+
+ double ref_freq_to_pix_freq;
+ double prefetch_xy_calc_in_dcfclk;
+ double min_dcfclk_mhz;
+ double t_calc_us;
+ double min_ttu_vblank;
+ double min_dst_y_ttu_vblank;
+ int unsigned dlg_vblank_start;
+ bool dcc_en;
+ bool dual_plane;
+ bool mode_422;
+ unsigned int access_dir;
+ unsigned int bytes_per_element_l;
+ unsigned int bytes_per_element_c;
+ unsigned int vp_height_l;
+ unsigned int vp_width_l;
+ unsigned int vp_height_c;
+ unsigned int vp_width_c;
+ unsigned int htaps_l;
+ unsigned int htaps_c;
+ double hratios_l;
+ double hratios_c;
+ double vratio_l;
+ double vratio_c;
+ double line_time_in_us;
+ double vinit_l;
+ double vinit_c;
+ double vinit_bot_l;
+ double vinit_bot_c;
+ unsigned int swath_height_l;
+ unsigned int swath_width_ub_l;
+ unsigned int dpte_bytes_per_row_ub_l;
+ unsigned int dpte_groups_per_row_ub_l;
+ unsigned int meta_pte_bytes_per_frame_ub_l;
+ unsigned int meta_bytes_per_row_ub_l;
+ unsigned int swath_height_c;
+ unsigned int swath_width_ub_c;
+ unsigned int dpte_bytes_per_row_ub_c;
+ unsigned int dpte_groups_per_row_ub_c;
+ unsigned int meta_chunks_per_row_ub_l;
+ unsigned int vupdate_offset;
+ unsigned int vupdate_width;
+ unsigned int vready_offset;
+ unsigned int dppclk_delay_subtotal;
+ unsigned int dispclk_delay_subtotal;
+ unsigned int pixel_rate_delay_subtotal;
+ unsigned int vstartup_start;
+ unsigned int dst_x_after_scaler;
+ unsigned int dst_y_after_scaler;
+ double line_wait;
+ double line_o;
+ double line_setup;
+ double line_calc;
+ double dst_y_prefetch;
+ double t_pre_us;
+ int unsigned vm_bytes;
+ int unsigned meta_row_bytes;
+ int unsigned max_num_sw_l;
+ int unsigned max_num_sw_c;
+ int unsigned max_partial_sw_l;
+ int unsigned max_partial_sw_c;
+ double max_vinit_l;
+ double max_vinit_c;
+ int unsigned lsw_l;
+ int unsigned lsw_c;
+ int unsigned sw_bytes_ub_l;
+ int unsigned sw_bytes_ub_c;
+ int unsigned sw_bytes;
+ int unsigned dpte_row_bytes;
+ double prefetch_bw;
+ double flip_bw;
+ double t_vm_us;
+ double t_r0_us;
+ double dst_y_per_vm_vblank;
+ double dst_y_per_row_vblank;
+ double min_dst_y_per_vm_vblank;
+ double min_dst_y_per_row_vblank;
+ double lsw;
+ double vratio_pre_l;
+ double vratio_pre_c;
+ unsigned int req_per_swath_ub_l;
+ unsigned int req_per_swath_ub_c;
+ unsigned int meta_row_height_l;
+ unsigned int swath_width_pixels_ub_l;
+ unsigned int swath_width_pixels_ub_c;
+ unsigned int scaler_rec_in_width_l;
+ unsigned int scaler_rec_in_width_c;
+ unsigned int dpte_row_height_l;
+ unsigned int dpte_row_height_c;
+ double hscale_pixel_rate_l;
+ double hscale_pixel_rate_c;
+ double min_hratio_fact_l;
+ double min_hratio_fact_c;
+ double refcyc_per_line_delivery_pre_l;
+ double refcyc_per_line_delivery_pre_c;
+ double refcyc_per_line_delivery_l;
+ double refcyc_per_line_delivery_c;
+ double refcyc_per_req_delivery_pre_l;
+ double refcyc_per_req_delivery_pre_c;
+ double refcyc_per_req_delivery_l;
+ double refcyc_per_req_delivery_c;
+ double refcyc_per_req_delivery_pre_cur0;
+ double refcyc_per_req_delivery_cur0;
+ int unsigned full_recout_width;
+ double hratios_cur0;
+ unsigned int cur0_src_width;
+ enum cursor_bpp cur0_bpp;
+ unsigned int cur0_req_size;
+ unsigned int cur0_req_width;
+ double cur0_width_ub;
+ double cur0_req_per_width;
+ double hactive_cur0;
+
+ memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
+ memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
+
+ DTRACE("DLG: %s: cstate_en = %d", __func__, cstate_en);
+ DTRACE("DLG: %s: pstate_en = %d", __func__, pstate_en);
+ DTRACE("DLG: %s: vm_en = %d", __func__, vm_en);
+ DTRACE("DLG: %s: iflip_en = %d", __func__, iflip_en);
+
+ /* ------------------------- */
+ /* Section 1.5.2.1: OTG dependent Params */
+ /* ------------------------- */
+ DTRACE("DLG: %s: dppclk_freq_in_mhz = %3.2f", __func__, dppclk_freq_in_mhz);
+ DTRACE("DLG: %s: dispclk_freq_in_mhz = %3.2f", __func__, dispclk_freq_in_mhz);
+ DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz);
+ DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz);
+ DTRACE("DLG: %s: interlaced = %d", __func__, interlaced);
+
+ ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
+ ASSERT(ref_freq_to_pix_freq < 4.0);
+ disp_dlg_regs->ref_freq_to_pix_freq =
+ (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
+ disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
+ * dml_pow(2, 8));
+ disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
+ * (double) ref_freq_to_pix_freq);
+ ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
+ disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */
+
+ prefetch_xy_calc_in_dcfclk = 24.0; /* FIXME: ip_param */
+ min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
+ t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz;
+ min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
+ if (cstate_en)
+ min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank);
+ if (pstate_en)
+ min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank);
+ min_ttu_vblank = min_ttu_vblank + t_calc_us;
+
+ min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
+ dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
+
+ disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
+ + min_dst_y_ttu_vblank) * dml_pow(2, 2));
+ ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
+
+ DTRACE("DLG: %s: min_dcfclk_mhz = %3.2f", __func__, min_dcfclk_mhz);
+ DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank);
+ DTRACE(
+ "DLG: %s: min_dst_y_ttu_vblank = %3.2f",
+ __func__,
+ min_dst_y_ttu_vblank);
+ DTRACE("DLG: %s: t_calc_us = %3.2f", __func__, t_calc_us);
+ DTRACE(
+ "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x",
+ __func__,
+ disp_dlg_regs->min_dst_y_next_start);
+ DTRACE(
+ "DLG: %s: ref_freq_to_pix_freq = %3.2f",
+ __func__,
+ ref_freq_to_pix_freq);
+
+ /* ------------------------- */
+ /* Section 1.5.2.2: Prefetch, Active and TTU */
+ /* ------------------------- */
+ /* Prefetch Calc */
+ /* Source */
+ dcc_en = e2e_pipe_param.pipe.src.dcc;
+ dual_plane = is_dual_plane(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format);
+ mode_422 = 0; /* FIXME */
+ access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
+ bytes_per_element_l = get_bytes_per_element(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
+ 0);
+ bytes_per_element_c = get_bytes_per_element(
+ (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
+ 1);
+ vp_height_l = e2e_pipe_param.pipe.src.viewport_height;
+ vp_width_l = e2e_pipe_param.pipe.src.viewport_width;
+ vp_height_c = e2e_pipe_param.pipe.src.viewport_height_c;
+ vp_width_c = e2e_pipe_param.pipe.src.viewport_width_c;
+
+ /* Scaling */
+ htaps_l = e2e_pipe_param.pipe.scale_taps.htaps;
+ htaps_c = e2e_pipe_param.pipe.scale_taps.htaps_c;
+ hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
+ hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c;
+ vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio;
+ vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c;
+
+ line_time_in_us = (htotal / pclk_freq_in_mhz);
+ vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;
+ vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;
+ vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;
+ vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;
+
+ swath_height_l = rq_dlg_param.rq_l.swath_height;
+ swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
+ dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
+ dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
+ meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
+ meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
+
+ swath_height_c = rq_dlg_param.rq_c.swath_height;
+ swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
+ dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
+ dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
+
+ meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
+ vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;
+ vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;
+ vready_offset = e2e_pipe_param.pipe.dest.vready_offset;
+
+ dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
+ dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
+ pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
+ + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
+
+ vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start;
+
+ if (interlaced)
+ vstartup_start = vstartup_start / 2;
+
+ if (vstartup_start >= min_vblank) {
+ DTRACE(
+ "WARNING_DLG: %s: vblank_start=%d vblank_end=%d",
+ __func__,
+ vblank_start,
+ vblank_end);
+ DTRACE(
+ "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d",
+ __func__,
+ vstartup_start,
+ min_vblank);
+ min_vblank = vstartup_start + 1;
+ DTRACE(
+ "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d",
+ __func__,
+ vstartup_start,
+ min_vblank);
+ }
+
+ dst_x_after_scaler = 0;
+ dst_y_after_scaler = 0;
+
+ if (e2e_pipe_param.pipe.src.is_hsplit)
+ dst_x_after_scaler = pixel_rate_delay_subtotal
+ + e2e_pipe_param.pipe.dest.recout_width;
+ else
+ dst_x_after_scaler = pixel_rate_delay_subtotal;
+
+ if (e2e_pipe_param.dout.output_format == dm_420)
+ dst_y_after_scaler = 1;
+ else
+ dst_y_after_scaler = 0;
+
+ if (dst_x_after_scaler >= htotal) {
+ dst_x_after_scaler = dst_x_after_scaler - htotal;
+ dst_y_after_scaler = dst_y_after_scaler + 1;
+ }
+
+ DTRACE("DLG: %s: htotal = %d", __func__, htotal);
+ DTRACE(
+ "DLG: %s: pixel_rate_delay_subtotal = %d",
+ __func__,
+ pixel_rate_delay_subtotal);
+ DTRACE("DLG: %s: dst_x_after_scaler = %d", __func__, dst_x_after_scaler);
+ DTRACE("DLG: %s: dst_y_after_scaler = %d", __func__, dst_y_after_scaler);
+
+ line_wait = mode_lib->soc.urgent_latency_us;
+ if (cstate_en)
+ line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
+ if (pstate_en)
+ line_wait = dml_max(
+ mode_lib->soc.dram_clock_change_latency_us
+ + mode_lib->soc.urgent_latency_us,
+ line_wait);
+ line_wait = line_wait / line_time_in_us;
+
+ line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal;
+ line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
+ line_calc = t_calc_us / line_time_in_us;
+
+ DTRACE(
+ "DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f",
+ __func__,
+ (double) mode_lib->soc.sr_enter_plus_exit_time_us);
+ DTRACE(
+ "DLG: %s: soc.dram_clock_change_latency_us = %3.2f",
+ __func__,
+ (double) mode_lib->soc.dram_clock_change_latency_us);
+ DTRACE(
+ "DLG: %s: soc.urgent_latency_us = %3.2f",
+ __func__,
+ mode_lib->soc.urgent_latency_us);
+
+ DTRACE("DLG: %s: swath_height_l = %d", __func__, swath_height_l);
+ if (dual_plane)
+ DTRACE("DLG: %s: swath_height_c = %d", __func__, swath_height_c);
+
+ DTRACE(
+ "DLG: %s: t_srx_delay_us = %3.2f",
+ __func__,
+ (double) dlg_sys_param.t_srx_delay_us);
+ DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us);
+ DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset);
+ DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width);
+ DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset);
+ DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, line_time_in_us);
+ DTRACE("DLG: %s: line_wait = %3.2f", __func__, line_wait);
+ DTRACE("DLG: %s: line_o = %3.2f", __func__, line_o);
+ DTRACE("DLG: %s: line_setup = %3.2f", __func__, line_setup);
+ DTRACE("DLG: %s: line_calc = %3.2f", __func__, line_calc);
+
+ dst_y_prefetch = ((double) min_vblank - 1.0)
+ - (line_setup + line_calc + line_wait + line_o);
+ DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch);
+ ASSERT(dst_y_prefetch >= 2.0);
+
+ dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125)) / 4;
+ DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch);
+
+ t_pre_us = dst_y_prefetch * line_time_in_us;
+ vm_bytes = 0;
+ meta_row_bytes = 0;
+
+ if (dcc_en && vm_en)
+ vm_bytes = meta_pte_bytes_per_frame_ub_l;
+ if (dcc_en)
+ meta_row_bytes = meta_bytes_per_row_ub_l;
+
+ max_num_sw_l = 0;
+ max_num_sw_c = 0;
+ max_partial_sw_l = 0;
+ max_partial_sw_c = 0;
+
+ max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l;
+ max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c;
+
+ get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l);
+ if (dual_plane)
+ get_swath_need(
+ mode_lib,
+ &max_num_sw_c,
+ &max_partial_sw_c,
+ swath_height_c,
+ max_vinit_c);
+
+ lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l;
+ lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c;
+ sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l;
+ sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c;
+ sw_bytes = 0;
+ dpte_row_bytes = 0;
+
+ if (vm_en) {
+ if (dual_plane)
+ dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c;
+ else
+ dpte_row_bytes = dpte_bytes_per_row_ub_l;
+ } else {
+ dpte_row_bytes = 0;
+ }
+
+ if (dual_plane)
+ sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c;
+ else
+ sw_bytes = sw_bytes_ub_l;
+
+ DTRACE("DLG: %s: sw_bytes_ub_l = %d", __func__, sw_bytes_ub_l);
+ DTRACE("DLG: %s: sw_bytes_ub_c = %d", __func__, sw_bytes_ub_c);
+ DTRACE("DLG: %s: sw_bytes = %d", __func__, sw_bytes);
+ DTRACE("DLG: %s: vm_bytes = %d", __func__, vm_bytes);
+ DTRACE("DLG: %s: meta_row_bytes = %d", __func__, meta_row_bytes);
+ DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes);
+
+ prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us;
+ flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param.total_flip_bw)
+ / (double) dlg_sys_param.total_flip_bytes;
+ t_vm_us = line_time_in_us / 4.0;
+ if (vm_en && dcc_en) {
+ t_vm_us = dml_max(
+ dlg_sys_param.t_extra_us,
+ dml_max((double) vm_bytes / prefetch_bw, t_vm_us));
+
+ if (iflip_en && !dual_plane) {
+ t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us);
+ if (flip_bw > 0.)
+ t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us);
+ }
+ }
+
+ t_r0_us = dml_max(dlg_sys_param.t_extra_us - t_vm_us, line_time_in_us - t_vm_us);
+
+ if (vm_en || dcc_en) {
+ t_r0_us = dml_max(
+ (double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw,
+ dlg_sys_param.t_extra_us);
+ t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us);
+
+ if (iflip_en && !dual_plane) {
+ t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us);
+ if (flip_bw > 0.)
+ t_r0_us = dml_max(
+ (dpte_row_bytes + meta_row_bytes) / flip_bw,
+ t_r0_us);
+ }
+ }
+
+ disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */
+ disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */
+ ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
+ DTRACE(
+ "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x",
+ __func__,
+ disp_dlg_regs->dst_y_after_scaler);
+ DTRACE(
+ "DLG: %s: disp_dlg_regs->refcyc_x_after_scaler = 0x%0x",
+ __func__,
+ disp_dlg_regs->refcyc_x_after_scaler);
+
+ disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
+ DTRACE(
+ "DLG: %s: disp_dlg_regs->dst_y_prefetch = %d",
+ __func__,
+ disp_dlg_regs->dst_y_prefetch);
+
+ dst_y_per_vm_vblank = 0.0;
+ dst_y_per_row_vblank = 0.0;
+
+ dst_y_per_vm_vblank = t_vm_us / line_time_in_us;
+ dst_y_per_vm_vblank = dml_floor(4.0 * (dst_y_per_vm_vblank + 0.125)) / 4.0;
+ disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
+
+ dst_y_per_row_vblank = t_r0_us / line_time_in_us;
+ dst_y_per_row_vblank = dml_floor(4.0 * (dst_y_per_row_vblank + 0.125)) / 4.0;
+ disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
+
+ DTRACE("DLG: %s: lsw_l = %d", __func__, lsw_l);
+ DTRACE("DLG: %s: lsw_c = %d", __func__, lsw_c);
+ DTRACE("DLG: %s: dpte_bytes_per_row_ub_l = %d", __func__, dpte_bytes_per_row_ub_l);
+ DTRACE("DLG: %s: dpte_bytes_per_row_ub_c = %d", __func__, dpte_bytes_per_row_ub_c);
+
+ DTRACE("DLG: %s: prefetch_bw = %3.2f", __func__, prefetch_bw);
+ DTRACE("DLG: %s: flip_bw = %3.2f", __func__, flip_bw);
+ DTRACE("DLG: %s: t_pre_us = %3.2f", __func__, t_pre_us);
+ DTRACE("DLG: %s: t_vm_us = %3.2f", __func__, t_vm_us);
+ DTRACE("DLG: %s: t_r0_us = %3.2f", __func__, t_r0_us);
+ DTRACE("DLG: %s: dst_y_per_vm_vblank = %3.2f", __func__, dst_y_per_vm_vblank);
+ DTRACE("DLG: %s: dst_y_per_row_vblank = %3.2f", __func__, dst_y_per_row_vblank);
+ DTRACE("DLG: %s: dst_y_prefetch = %3.2f", __func__, dst_y_prefetch);
+
+ min_dst_y_per_vm_vblank = 8.0;
+ min_dst_y_per_row_vblank = 16.0;
+ if (htotal <= 75) {
+ min_vblank = 300;
+ min_dst_y_per_vm_vblank = 100.0;
+ min_dst_y_per_row_vblank = 100.0;
+ }
+
+ ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
+ ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
+
+ ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
+ lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
+
+ DTRACE("DLG: %s: lsw = %3.2f", __func__, lsw);
+
+ vratio_pre_l = get_vratio_pre(
+ mode_lib,
+ max_num_sw_l,
+ max_partial_sw_l,
+ swath_height_l,
+ max_vinit_l,
+ lsw);
+ vratio_pre_c = 1.0;
+ if (dual_plane)
+ vratio_pre_c = get_vratio_pre(
+ mode_lib,
+ max_num_sw_c,
+ max_partial_sw_c,
+ swath_height_c,
+ max_vinit_c,
+ lsw);
+
+ DTRACE("DLG: %s: vratio_pre_l=%3.2f", __func__, vratio_pre_l);
+ DTRACE("DLG: %s: vratio_pre_c=%3.2f", __func__, vratio_pre_c);
+
+ ASSERT(vratio_pre_l <= 4.0);
+ if (vratio_pre_l >= 4.0)
+ disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1;
+ else
+ disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
+
+ ASSERT(vratio_pre_c <= 4.0);
+ if (vratio_pre_c >= 4.0)
+ disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1;
+ else
+ disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
+
+ disp_dlg_regs->refcyc_per_pte_group_vblank_l =
+ (unsigned int) (dst_y_per_row_vblank * (double) htotal
+ * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
+
+ disp_dlg_regs->refcyc_per_pte_group_vblank_c =
+ (unsigned int) (dst_y_per_row_vblank * (double) htotal
+ * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
+ ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));
+
+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
+ (unsigned int) (dst_y_per_row_vblank * (double) htotal
+ * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
+ ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
+
+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
+ disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
+
+ /* Active */
+ req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
+ req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
+ meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
+ swath_width_pixels_ub_l = 0;
+ swath_width_pixels_ub_c = 0;
+ scaler_rec_in_width_l = 0;
+ scaler_rec_in_width_c = 0;
+ dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
+ dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
+
+ disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
+ / (double) vratio_l * dml_pow(2, 2));
+ ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
+
+ disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
+ / (double) vratio_c * dml_pow(2, 2));
+ ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));
+
+ disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
+ / (double) vratio_l * dml_pow(2, 2));
+ ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
+
+ disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
+
+ disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+ / (double) dpte_groups_per_row_ub_l);
+ if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
+ disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
+
+ disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c
+ / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
+ / (double) dpte_groups_per_row_ub_c);
+ if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
+ disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
+
+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
+ / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+ / (double) meta_chunks_per_row_ub_l);
+ if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
+ disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
+
+ if (mode_422) {
+ swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */
+ swath_width_pixels_ub_c = swath_width_ub_c * 2;
+ } else {
+ swath_width_pixels_ub_l = swath_width_ub_l * 1;
+ swath_width_pixels_ub_c = swath_width_ub_c * 1;
+ }
+
+ hscale_pixel_rate_l = 0.;
+ hscale_pixel_rate_c = 0.;
+ min_hratio_fact_l = 1.0;
+ min_hratio_fact_c = 1.0;
+
+ if (htaps_l <= 1)
+ min_hratio_fact_l = 2.0;
+ else if (htaps_l <= 6) {
+ if ((hratios_l * 2.0) > 4.0)
+ min_hratio_fact_l = 4.0;
+ else
+ min_hratio_fact_l = hratios_l * 2.0;
+ } else {
+ if (hratios_l > 4.0)
+ min_hratio_fact_l = 4.0;
+ else
+ min_hratio_fact_l = hratios_l;
+ }
+
+ hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
+
+ if (htaps_c <= 1)
+ min_hratio_fact_c = 2.0;
+ else if (htaps_c <= 6) {
+ if ((hratios_c * 2.0) > 4.0)
+ min_hratio_fact_c = 4.0;
+ else
+ min_hratio_fact_c = hratios_c * 2.0;
+ } else {
+ if (hratios_c > 4.0)
+ min_hratio_fact_c = 4.0;
+ else
+ min_hratio_fact_c = hratios_c;
+ }
+
+ hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
+
+ refcyc_per_line_delivery_pre_l = 0.;
+ refcyc_per_line_delivery_pre_c = 0.;
+ refcyc_per_line_delivery_l = 0.;
+ refcyc_per_line_delivery_c = 0.;
+
+ refcyc_per_req_delivery_pre_l = 0.;
+ refcyc_per_req_delivery_pre_c = 0.;
+ refcyc_per_req_delivery_l = 0.;
+ refcyc_per_req_delivery_c = 0.;
+ refcyc_per_req_delivery_pre_cur0 = 0.;
+ refcyc_per_req_delivery_cur0 = 0.;
+
+ full_recout_width = 0;
+ if (e2e_pipe_param.pipe.src.is_hsplit) {
+ if (e2e_pipe_param.pipe.dest.full_recout_width == 0) {
+ DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__);
+ full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */
+ } else
+ full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width;
+ } else
+ full_recout_width = e2e_pipe_param.pipe.dest.recout_width;
+
+ refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_pre_l,
+ hscale_pixel_rate_l,
+ swath_width_pixels_ub_l,
+ 1); /* per line */
+
+ refcyc_per_line_delivery_l = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_l,
+ hscale_pixel_rate_l,
+ swath_width_pixels_ub_l,
+ 1); /* per line */
+
+ DTRACE("DLG: %s: full_recout_width = %d", __func__, full_recout_width);
+ DTRACE("DLG: %s: hscale_pixel_rate_l = %3.2f", __func__, hscale_pixel_rate_l);
+ DTRACE(
+ "DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f",
+ __func__,
+ refcyc_per_line_delivery_pre_l);
+ DTRACE(
+ "DLG: %s: refcyc_per_line_delivery_l = %3.2f",
+ __func__,
+ refcyc_per_line_delivery_l);
+
+ disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
+ refcyc_per_line_delivery_pre_l);
+ disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
+ refcyc_per_line_delivery_l);
+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
+
+ if (dual_plane) {
+ refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_pre_c,
+ hscale_pixel_rate_c,
+ swath_width_pixels_ub_c,
+ 1); /* per line */
+
+ refcyc_per_line_delivery_c = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_c,
+ hscale_pixel_rate_c,
+ swath_width_pixels_ub_c,
+ 1); /* per line */
+
+ DTRACE(
+ "DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f",
+ __func__,
+ refcyc_per_line_delivery_pre_c);
+ DTRACE(
+ "DLG: %s: refcyc_per_line_delivery_c = %3.2f",
+ __func__,
+ refcyc_per_line_delivery_c);
+
+ disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
+ refcyc_per_line_delivery_pre_c);
+ disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
+ refcyc_per_line_delivery_c);
+ ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
+ }
+ disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
+
+ /* TTU - Luma / Chroma */
+ if (access_dir) { /* vertical access */
+ scaler_rec_in_width_l = vp_height_l;
+ scaler_rec_in_width_c = vp_height_c;
+ } else {
+ scaler_rec_in_width_l = vp_width_l;
+ scaler_rec_in_width_c = vp_width_c;
+ }
+
+ refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_pre_l,
+ hscale_pixel_rate_l,
+ scaler_rec_in_width_l,
+ req_per_swath_ub_l); /* per req */
+ refcyc_per_req_delivery_l = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_l,
+ hscale_pixel_rate_l,
+ scaler_rec_in_width_l,
+ req_per_swath_ub_l); /* per req */
+
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_pre_l);
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_l = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_l);
+
+ disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
+ * dml_pow(2, 10));
+ disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
+ * dml_pow(2, 10));
+
+ ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
+ ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
+
+ if (dual_plane) {
+ refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_pre_c,
+ hscale_pixel_rate_c,
+ scaler_rec_in_width_c,
+ req_per_swath_ub_c); /* per req */
+ refcyc_per_req_delivery_c = get_refcyc_per_delivery(
+ mode_lib,
+ refclk_freq_in_mhz,
+ pclk_freq_in_mhz,
+ full_recout_width,
+ vratio_c,
+ hscale_pixel_rate_c,
+ scaler_rec_in_width_c,
+ req_per_swath_ub_c); /* per req */
+
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_pre_c);
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_c = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_c);
+
+ disp_ttu_regs->refcyc_per_req_delivery_pre_c =
+ (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
+ disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
+ * dml_pow(2, 10));
+
+ ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
+ ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
+ }
+
+ /* TTU - Cursor */
+ hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
+ cur0_src_width = e2e_pipe_param.pipe.src.cur0_src_width; /* cursor source width */
+ cur0_bpp = (enum cursor_bpp) e2e_pipe_param.pipe.src.cur0_bpp;
+ cur0_req_size = 0;
+ cur0_req_width = 0;
+ cur0_width_ub = 0.0;
+ cur0_req_per_width = 0.0;
+ hactive_cur0 = 0.0;
+
+ ASSERT(cur0_src_width <= 256);
+
+ if (cur0_src_width > 0) {
+ unsigned int cur0_bit_per_pixel = 0;
+
+ if (cur0_bpp == dm_cur_2bit) {
+ cur0_req_size = 64; /* byte */
+ cur0_bit_per_pixel = 2;
+ } else { /* 32bit */
+ cur0_bit_per_pixel = 32;
+ if (cur0_src_width >= 1 && cur0_src_width <= 16)
+ cur0_req_size = 64;
+ else if (cur0_src_width >= 17 && cur0_src_width <= 31)
+ cur0_req_size = 128;
+ else
+ cur0_req_size = 256;
+ }
+
+ cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0);
+ cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width)
+ * (double) cur0_req_width;
+ cur0_req_per_width = cur0_width_ub / (double) cur0_req_width;
+ hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* FIXME: oswin to think about what to do for cursor */
+
+ if (vratio_pre_l <= 1.0) {
+ refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq
+ / (double) cur0_req_per_width;
+ } else {
+ refcyc_per_req_delivery_pre_cur0 = (double) refclk_freq_in_mhz
+ * (double) cur0_src_width / hscale_pixel_rate_l
+ / (double) cur0_req_per_width;
+ }
+
+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
+ (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
+ ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));
+
+ if (vratio_l <= 1.0) {
+ refcyc_per_req_delivery_cur0 = hactive_cur0 * ref_freq_to_pix_freq
+ / (double) cur0_req_per_width;
+ } else {
+ refcyc_per_req_delivery_cur0 = (double) refclk_freq_in_mhz
+ * (double) cur0_src_width / hscale_pixel_rate_l
+ / (double) cur0_req_per_width;
+ }
+
+ DTRACE("DLG: %s: cur0_req_width = %d", __func__, cur0_req_width);
+ DTRACE(
+ "DLG: %s: cur0_width_ub = %3.2f",
+ __func__,
+ cur0_width_ub);
+ DTRACE(
+ "DLG: %s: cur0_req_per_width = %3.2f",
+ __func__,
+ cur0_req_per_width);
+ DTRACE(
+ "DLG: %s: hactive_cur0 = %3.2f",
+ __func__,
+ hactive_cur0);
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_pre_cur0);
+ DTRACE(
+ "DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f",
+ __func__,
+ refcyc_per_req_delivery_cur0);
+
+ disp_ttu_regs->refcyc_per_req_delivery_cur0 =
+ (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
+ ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));
+ } else {
+ disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0;
+ disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0;
+ }
+
+ /* TTU - Misc */
+ disp_ttu_regs->qos_level_low_wm = 0;
+ ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
+ disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
+ * ref_freq_to_pix_freq);
+ ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
+
+ disp_ttu_regs->qos_level_flip = 14;
+ disp_ttu_regs->qos_level_fixed_l = 8;
+ disp_ttu_regs->qos_level_fixed_c = 8;
+ disp_ttu_regs->qos_level_fixed_cur0 = 8;
+ disp_ttu_regs->qos_ramp_disable_l = 0;
+ disp_ttu_regs->qos_ramp_disable_c = 0;
+ disp_ttu_regs->qos_ramp_disable_cur0 = 0;
+
+ disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
+ ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
+
+ print__ttu_regs_st(mode_lib, *disp_ttu_regs);
+ print__dlg_regs_st(mode_lib, *disp_dlg_regs);
+}
+
+void dml_rq_dlg_get_dlg_reg(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
+ const int unsigned num_pipes,
+ const int unsigned pipe_idx,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en,
+ const bool iflip_en)
+{
+ struct _vcs_dpi_display_rq_params_st rq_param = {0};
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm_param = mode_lib->wm_param;
+ struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_wm;
+ struct _vcs_dpi_display_dlg_prefetch_param_st prefetch_param;
+ double total_ret_bw;
+ double total_active_bw;
+ double total_prefetch_bw;
+ int unsigned total_flip_bytes;
+ int unsigned num_planes;
+ int i;
+
+ memset(wm_param, 0, sizeof(mode_lib->wm_param));
+
+ /* Get watermark and Tex. */
+ DTRACE("DLG: Start calculating system setting related parameters. num_pipes=%d", num_pipes);
+ num_planes = dml_wm_e2e_to_wm(mode_lib, e2e_pipe_param, num_pipes, wm_param);
+
+ cstate_pstate_wm = dml_wm_cstate_pstate_e2e(mode_lib, e2e_pipe_param, num_pipes);
+ dlg_sys_param.t_mclk_wm_us = cstate_pstate_wm.pstate_change_us;
+ dlg_sys_param.t_sr_wm_us = cstate_pstate_wm.cstate_enter_plus_exit_us;
+ dlg_sys_param.t_urg_wm_us = dml_wm_urgent_e2e(mode_lib, e2e_pipe_param, num_pipes);
+ dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
+ / dml_wm_dcfclk_deepsleep_mhz_e2e(mode_lib, e2e_pipe_param, num_pipes);
+ dlg_sys_param.t_extra_us = dml_wm_urgent_extra(mode_lib, wm_param, num_planes);
+ dlg_sys_param.deepsleep_dcfclk_mhz = dml_wm_dcfclk_deepsleep_mhz_e2e(
+ mode_lib,
+ e2e_pipe_param,
+ num_pipes);
+
+ print__dlg_sys_params_st(mode_lib, dlg_sys_param);
+
+ DTRACE("DLG: Start calculating total prefetch bw. num_planes=%d", num_planes);
+ total_ret_bw = dml_wm_calc_return_bw(mode_lib, wm_param, num_planes);
+ total_active_bw = dml_wm_calc_total_data_read_bw(mode_lib, wm_param, num_planes);
+ total_prefetch_bw = 0.0;
+ total_flip_bytes = 0;
+
+ for (i = 0; i < num_pipes; i++) {
+ dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[i].pipe.src);
+ dml_rq_dlg_get_dlg_params_prefetch(
+ mode_lib,
+ &prefetch_param,
+ rq_param.dlg,
+ dlg_sys_param,
+ e2e_pipe_param[i],
+ cstate_en,
+ pstate_en,
+ vm_en);
+ total_prefetch_bw += prefetch_param.prefetch_bw;
+ total_flip_bytes += prefetch_param.flip_bytes;
+ DTRACE(
+ "DLG: pipe=%d, total_prefetch_bw=%3.2f total_flip_bytes=%d",
+ i,
+ total_prefetch_bw,
+ total_flip_bytes);
+ }
+
+ dlg_sys_param.total_flip_bw = total_ret_bw - dml_max(total_active_bw, total_prefetch_bw);
+
+ DTRACE("DLG: Done calculating total prefetch bw");
+ DTRACE("DLG: num_pipes = %d", num_pipes);
+ DTRACE("DLG: total_ret_bw = %3.2f", total_ret_bw);
+ DTRACE("DLG: total_active_bw = %3.2f", total_active_bw);
+ DTRACE("DLG: total_prefetch_bw = %3.2f", total_prefetch_bw);
+ DTRACE("DLG: total_flip_bw = %3.2f", dlg_sys_param.total_flip_bw);
+
+ if (dlg_sys_param.total_flip_bw < 0.0 && iflip_en) {
+ DTRACE("WARNING_DLG Insufficient bw for immediate flip!");
+ dlg_sys_param.total_flip_bw = 0;
+ }
+
+ dlg_sys_param.total_flip_bytes = total_flip_bytes;
+ DTRACE("DLG: total_flip_bytes = %d", dlg_sys_param.total_flip_bytes);
+ DTRACE("DLG: Done calculating system setting related parameters.");
+
+ /* system parameter calculation done */
+
+ DTRACE("DLG: Calculation for pipe[%d] start", pipe_idx);
+ dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
+ dml_rq_dlg_get_dlg_params(
+ mode_lib,
+ dlg_regs,
+ ttu_regs,
+ rq_param.dlg,
+ dlg_sys_param,
+ e2e_pipe_param[pipe_idx],
+ cstate_en,
+ pstate_en,
+ vm_en,
+ iflip_en);
+ DTRACE("DLG: Calculation for pipe[%d] end", pipe_idx);
+}
+
+void dml_rq_dlg_get_arb_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_arb_params_st *arb_param)
+{
+ memset(arb_param, 0, sizeof(*arb_param));
+ arb_param->max_req_outstanding = 256;
+ arb_param->min_req_outstanding = 68;
+ arb_param->sat_level_us = 60;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
new file mode 100644
index 0000000..e63b13f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_RQ_DLG_CALC_H__
+#define __DISPLAY_RQ_DLG_CALC_H__
+
+#include "dml_common_defs.h"
+#include "display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+void extract_rq_regs(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ const struct _vcs_dpi_display_rq_params_st rq_param);
+/* Function: dml_rq_dlg_get_rq_params
+ * Calculate requestor related parameters that register definition agnostic
+ * (i.e. this layer does try to separate real values from register defintion)
+ * Input:
+ * pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
+ * Output:
+ * rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
+ */
+void dml_rq_dlg_get_rq_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_params_st *rq_param,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
+
+/* Function: dml_rq_dlg_get_rq_reg
+ * Main entry point for test to get the register values out of this DML class.
+ * This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
+ * and then populate the rq_regs struct
+ * Input:
+ * pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
+ * Output:
+ * rq_regs - struct that holds all the RQ registers field value.
+ * See also: <display_rq_regs_st>
+ */
+void dml_rq_dlg_get_rq_reg(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
+
+/* Function: dml_rq_dlg_get_dlg_params
+ * Calculate deadline related parameters
+ */
+void dml_rq_dlg_get_dlg_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+ const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+ const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+ const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en,
+ const bool iflip_en);
+
+/* Function: dml_rq_dlg_get_dlg_param_prefetch
+ * For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
+ * for ALL pipes and use this info to calculate the prefetch programming.
+ * Output: prefetch_param.prefetch_bw and flip_bytes
+ */
+void dml_rq_dlg_get_dlg_params_prefetch(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_prefetch_param_st *prefetch_param,
+ struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+ struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en);
+
+/* Function: dml_rq_dlg_get_dlg_reg
+ * Calculate and return DLG and TTU register struct given the system setting
+ * Output:
+ * dlg_regs - output DLG register struct
+ * ttu_regs - output DLG TTU register struct
+ * Input:
+ * e2e_pipe_param - "compacted" array of e2e pipe param struct
+ * num_pipes - num of active "pipe" or "route"
+ * pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+ * cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+ * Added for legacy or unrealistic timing tests.
+ */
+void dml_rq_dlg_get_dlg_reg(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
+ const unsigned int num_pipes,
+ const unsigned int pipe_idx,
+ const bool cstate_en,
+ const bool pstate_en,
+ const bool vm_en,
+ const bool iflip_en);
+
+/* Function: dml_rq_dlg_get_row_heights
+ * Calculate dpte and meta row heights
+ */
+void dml_rq_dlg_get_row_heights(
+ struct display_mode_lib *mode_lib,
+ unsigned int *o_dpte_row_height,
+ unsigned int *o_meta_row_height,
+ unsigned int vp_width,
+ unsigned int data_pitch,
+ int source_format,
+ int tiling,
+ int macro_tile_size,
+ int source_scan,
+ int is_chroma);
+
+/* Function: dml_rq_dlg_get_arb_params */
+void dml_rq_dlg_get_arb_params(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_arb_params_st *arb_param);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
new file mode 100644
index 0000000..3dc1136
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "display_rq_dlg_helpers.h"
+
+void print__rq_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_params_st rq_param)
+{
+ DTRACE("RQ_DLG_CALC: *************************** ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: <LUMA>");
+ print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_l);
+ DTRACE("RQ_DLG_CALC: <CHROMA> === ");
+ print__data_rq_sizing_params_st(mode_lib, rq_param.sizing.rq_c);
+
+ DTRACE("RQ_DLG_CALC: <LUMA>");
+ print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_l);
+ DTRACE("RQ_DLG_CALC: <CHROMA>");
+ print__data_rq_dlg_params_st(mode_lib, rq_param.dlg.rq_c);
+
+ DTRACE("RQ_DLG_CALC: <LUMA>");
+ print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_l);
+ DTRACE("RQ_DLG_CALC: <CHROMA>");
+ print__data_rq_misc_params_st(mode_lib, rq_param.misc.rq_c);
+ DTRACE("RQ_DLG_CALC: *************************** ");
+}
+
+void print__data_rq_sizing_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: chunk_bytes = %0d", rq_sizing.chunk_bytes);
+ DTRACE("RQ_DLG_CALC: min_chunk_bytes = %0d", rq_sizing.min_chunk_bytes);
+ DTRACE("RQ_DLG_CALC: meta_chunk_bytes = %0d", rq_sizing.meta_chunk_bytes);
+ DTRACE("RQ_DLG_CALC: min_meta_chunk_bytes = %0d", rq_sizing.min_meta_chunk_bytes);
+ DTRACE("RQ_DLG_CALC: mpte_group_bytes = %0d", rq_sizing.mpte_group_bytes);
+ DTRACE("RQ_DLG_CALC: dpte_group_bytes = %0d", rq_sizing.dpte_group_bytes);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__data_rq_dlg_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: swath_width_ub = %0d", rq_dlg_param.swath_width_ub);
+ DTRACE("RQ_DLG_CALC: swath_height = %0d", rq_dlg_param.swath_height);
+ DTRACE("RQ_DLG_CALC: req_per_swath_ub = %0d", rq_dlg_param.req_per_swath_ub);
+ DTRACE(
+ "RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = %0d",
+ rq_dlg_param.meta_pte_bytes_per_frame_ub);
+ DTRACE(
+ "RQ_DLG_CALC: dpte_req_per_row_ub = %0d",
+ rq_dlg_param.dpte_req_per_row_ub);
+ DTRACE(
+ "RQ_DLG_CALC: dpte_groups_per_row_ub = %0d",
+ rq_dlg_param.dpte_groups_per_row_ub);
+ DTRACE("RQ_DLG_CALC: dpte_row_height = %0d", rq_dlg_param.dpte_row_height);
+ DTRACE(
+ "RQ_DLG_CALC: dpte_bytes_per_row_ub = %0d",
+ rq_dlg_param.dpte_bytes_per_row_ub);
+ DTRACE(
+ "RQ_DLG_CALC: meta_chunks_per_row_ub = %0d",
+ rq_dlg_param.meta_chunks_per_row_ub);
+ DTRACE(
+ "RQ_DLG_CALC: meta_req_per_row_ub = %0d",
+ rq_dlg_param.meta_req_per_row_ub);
+ DTRACE("RQ_DLG_CALC: meta_row_height = %0d", rq_dlg_param.meta_row_height);
+ DTRACE(
+ "RQ_DLG_CALC: meta_bytes_per_row_ub = %0d",
+ rq_dlg_param.meta_bytes_per_row_ub);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__data_rq_misc_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: full_swath_bytes = %0d", rq_misc_param.full_swath_bytes);
+ DTRACE("RQ_DLG_CALC: stored_swath_bytes = %0d", rq_misc_param.stored_swath_bytes);
+ DTRACE("RQ_DLG_CALC: blk256_width = %0d", rq_misc_param.blk256_width);
+ DTRACE("RQ_DLG_CALC: blk256_height = %0d", rq_misc_param.blk256_height);
+ DTRACE("RQ_DLG_CALC: req_width = %0d", rq_misc_param.req_width);
+ DTRACE("RQ_DLG_CALC: req_height = %0d", rq_misc_param.req_height);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__rq_dlg_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: <LUMA> ");
+ print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_l);
+ DTRACE("RQ_DLG_CALC: <CHROMA> ");
+ print__data_rq_dlg_params_st(mode_lib, rq_dlg_param.rq_c);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__dlg_sys_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST");
+ DTRACE("RQ_DLG_CALC: t_mclk_wm_us = %3.2f", dlg_sys_param.t_mclk_wm_us);
+ DTRACE("RQ_DLG_CALC: t_urg_wm_us = %3.2f", dlg_sys_param.t_urg_wm_us);
+ DTRACE("RQ_DLG_CALC: t_sr_wm_us = %3.2f", dlg_sys_param.t_sr_wm_us);
+ DTRACE("RQ_DLG_CALC: t_extra_us = %3.2f", dlg_sys_param.t_extra_us);
+ DTRACE("RQ_DLG_CALC: t_srx_delay_us = %3.2f", dlg_sys_param.t_srx_delay_us);
+ DTRACE("RQ_DLG_CALC: deepsleep_dcfclk_mhz = %3.2f", dlg_sys_param.deepsleep_dcfclk_mhz);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__data_rq_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_regs_st rq_regs)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST");
+ DTRACE("RQ_DLG_CALC: chunk_size = 0x%0x", rq_regs.chunk_size);
+ DTRACE("RQ_DLG_CALC: min_chunk_size = 0x%0x", rq_regs.min_chunk_size);
+ DTRACE("RQ_DLG_CALC: meta_chunk_size = 0x%0x", rq_regs.meta_chunk_size);
+ DTRACE("RQ_DLG_CALC: min_meta_chunk_size = 0x%0x", rq_regs.min_meta_chunk_size);
+ DTRACE("RQ_DLG_CALC: dpte_group_size = 0x%0x", rq_regs.dpte_group_size);
+ DTRACE("RQ_DLG_CALC: mpte_group_size = 0x%0x", rq_regs.mpte_group_size);
+ DTRACE("RQ_DLG_CALC: swath_height = 0x%0x", rq_regs.swath_height);
+ DTRACE("RQ_DLG_CALC: pte_row_height_linear = 0x%0x", rq_regs.pte_row_height_linear);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__rq_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st rq_regs)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_RQ_REGS_ST");
+ DTRACE("RQ_DLG_CALC: <LUMA> ");
+ print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l);
+ DTRACE("RQ_DLG_CALC: <CHROMA> ");
+ print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_c);
+ DTRACE("RQ_DLG_CALC: drq_expansion_mode = 0x%0x", rq_regs.drq_expansion_mode);
+ DTRACE("RQ_DLG_CALC: prq_expansion_mode = 0x%0x", rq_regs.prq_expansion_mode);
+ DTRACE("RQ_DLG_CALC: mrq_expansion_mode = 0x%0x", rq_regs.mrq_expansion_mode);
+ DTRACE("RQ_DLG_CALC: crq_expansion_mode = 0x%0x", rq_regs.crq_expansion_mode);
+ DTRACE("RQ_DLG_CALC: plane1_base_address = 0x%0x", rq_regs.plane1_base_address);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__dlg_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st dlg_regs)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_DLG_REGS_ST ");
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_h_blank_end = 0x%0x",
+ dlg_regs.refcyc_h_blank_end);
+ DTRACE("RQ_DLG_CALC: dlg_vblank_end = 0x%0x", dlg_regs.dlg_vblank_end);
+ DTRACE(
+ "RQ_DLG_CALC: min_dst_y_next_start = 0x%0x",
+ dlg_regs.min_dst_y_next_start);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_htotal = 0x%0x",
+ dlg_regs.refcyc_per_htotal);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_x_after_scaler = 0x%0x",
+ dlg_regs.refcyc_x_after_scaler);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_after_scaler = 0x%0x",
+ dlg_regs.dst_y_after_scaler);
+ DTRACE("RQ_DLG_CALC: dst_y_prefetch = 0x%0x", dlg_regs.dst_y_prefetch);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_vm_vblank = 0x%0x",
+ dlg_regs.dst_y_per_vm_vblank);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_row_vblank = 0x%0x",
+ dlg_regs.dst_y_per_row_vblank);
+ DTRACE(
+ "RQ_DLG_CALC: ref_freq_to_pix_freq = 0x%0x",
+ dlg_regs.ref_freq_to_pix_freq);
+ DTRACE("RQ_DLG_CALC: vratio_prefetch = 0x%0x", dlg_regs.vratio_prefetch);
+ DTRACE(
+ "RQ_DLG_CALC: vratio_prefetch_c = 0x%0x",
+ dlg_regs.vratio_prefetch_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x%0x",
+ dlg_regs.refcyc_per_pte_group_vblank_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x%0x",
+ dlg_regs.refcyc_per_pte_group_vblank_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x",
+ dlg_regs.refcyc_per_meta_chunk_vblank_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x%0x",
+ dlg_regs.refcyc_per_meta_chunk_vblank_c);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x%0x",
+ dlg_regs.dst_y_per_pte_row_nom_l);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x%0x",
+ dlg_regs.dst_y_per_pte_row_nom_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x%0x",
+ dlg_regs.refcyc_per_pte_group_nom_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x%0x",
+ dlg_regs.refcyc_per_pte_group_nom_c);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x%0x",
+ dlg_regs.dst_y_per_meta_row_nom_l);
+ DTRACE(
+ "RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x%0x",
+ dlg_regs.dst_y_per_meta_row_nom_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x%0x",
+ dlg_regs.refcyc_per_meta_chunk_nom_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x%0x",
+ dlg_regs.refcyc_per_meta_chunk_nom_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0x%0x",
+ dlg_regs.refcyc_per_line_delivery_pre_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x%0x",
+ dlg_regs.refcyc_per_line_delivery_pre_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_line_delivery_l = 0x%0x",
+ dlg_regs.refcyc_per_line_delivery_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x%0x",
+ dlg_regs.refcyc_per_line_delivery_c);
+ DTRACE(
+ "RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x%0x",
+ dlg_regs.chunk_hdl_adjust_cur0);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
+
+void print__ttu_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_ttu_regs_st ttu_regs)
+{
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+ DTRACE("RQ_DLG_CALC: DISPLAY_TTU_REGS_ST ");
+ DTRACE(
+ "RQ_DLG_CALC: qos_level_low_wm = 0x%0x",
+ ttu_regs.qos_level_low_wm);
+ DTRACE(
+ "RQ_DLG_CALC: qos_level_high_wm = 0x%0x",
+ ttu_regs.qos_level_high_wm);
+ DTRACE("RQ_DLG_CALC: min_ttu_vblank = 0x%0x", ttu_regs.min_ttu_vblank);
+ DTRACE("RQ_DLG_CALC: qos_level_flip = 0x%0x", ttu_regs.qos_level_flip);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_pre_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_l);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_pre_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_c);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_cur0);
+ DTRACE(
+ "RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x%0x",
+ ttu_regs.refcyc_per_req_delivery_pre_cur0);
+ DTRACE(
+ "RQ_DLG_CALC: qos_level_fixed_l = 0x%0x",
+ ttu_regs.qos_level_fixed_l);
+ DTRACE(
+ "RQ_DLG_CALC: qos_ramp_disable_l = 0x%0x",
+ ttu_regs.qos_ramp_disable_l);
+ DTRACE(
+ "RQ_DLG_CALC: qos_level_fixed_c = 0x%0x",
+ ttu_regs.qos_level_fixed_c);
+ DTRACE(
+ "RQ_DLG_CALC: qos_ramp_disable_c = 0x%0x",
+ ttu_regs.qos_ramp_disable_c);
+ DTRACE(
+ "RQ_DLG_CALC: qos_level_fixed_cur0 = 0x%0x",
+ ttu_regs.qos_level_fixed_cur0);
+ DTRACE(
+ "RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x%0x",
+ ttu_regs.qos_ramp_disable_cur0);
+ DTRACE("RQ_DLG_CALC: ===================================== ");
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
new file mode 100644
index 0000000..7403cca
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_RQ_DLG_HELPERS_H__
+#define __DISPLAY_RQ_DLG_HELPERS_H__
+
+#include "dml_common_defs.h"
+#include "display_mode_lib.h"
+
+/* Function: Printer functions
+ * Print various struct
+ */
+void print__rq_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_params_st rq_param);
+void print__data_rq_sizing_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing);
+void print__data_rq_dlg_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param);
+void print__data_rq_misc_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param);
+void print__rq_dlg_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param);
+void print__dlg_sys_params_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param);
+
+void print__data_rq_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_data_rq_regs_st data_rq_regs);
+void print__rq_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_rq_regs_st rq_regs);
+void print__dlg_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_dlg_regs_st dlg_regs);
+void print__ttu_regs_st(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_ttu_regs_st ttu_regs);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_watermark.c b/drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
new file mode 100644
index 0000000..390f093
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
@@ -0,0 +1,1281 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "display_watermark.h"
+#include "display_mode_lib.h"
+
+static void get_bytes_per_pixel(
+ enum source_format_class format,
+ struct _vcs_dpi_wm_calc_pipe_params_st *plane)
+{
+ switch (format) {
+ case dm_444_64:
+ plane->bytes_per_pixel_y = 8.0;
+ plane->bytes_per_pixel_c = 0.0;
+ break;
+ case dm_444_32:
+ plane->bytes_per_pixel_y = 4.0;
+ plane->bytes_per_pixel_c = 0.0;
+ break;
+ case dm_444_16:
+ plane->bytes_per_pixel_y = 2.0;
+ plane->bytes_per_pixel_c = 0.0;
+ break;
+ case dm_422_10:
+ plane->bytes_per_pixel_y = 4.0;
+ plane->bytes_per_pixel_c = 0.0;
+ break;
+ case dm_422_8:
+ plane->bytes_per_pixel_y = 2.0;
+ plane->bytes_per_pixel_c = 0.0;
+ break;
+ case dm_420_8:
+ plane->bytes_per_pixel_y = 1.0;
+ plane->bytes_per_pixel_c = 2.0;
+ break;
+ case dm_420_10:
+ plane->bytes_per_pixel_y = 4.0 / 3;
+ plane->bytes_per_pixel_c = 8.0 / 3;
+ break;
+ default:
+ BREAK_TO_DEBUGGER(); /* invalid format in get_bytes_per_pixel */
+ }
+}
+
+static unsigned int get_swath_width_y(
+ struct _vcs_dpi_display_pipe_source_params_st *src_param,
+ unsigned int num_dpp)
+{
+ unsigned int val;
+
+ /* note that we don't divide by num_dpp here because we have an interface which has already split
+ * any viewports
+ */
+ if (src_param->source_scan == dm_horz) {
+ val = src_param->viewport_width;
+ } else {
+ val = src_param->viewport_height;
+ }
+
+ return val;
+}
+
+static void get_swath_height(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_pipe_source_params_st *src_param,
+ struct _vcs_dpi_wm_calc_pipe_params_st *plane,
+ unsigned int swath_width_y)
+{
+ double buffer_width;
+
+ if (src_param->source_format == dm_444_64 || src_param->source_format == dm_444_32
+ || src_param->source_format == dm_444_16) {
+ if (src_param->sw_mode == dm_sw_linear) {
+ plane->swath_height_y = 1;
+ } else if (src_param->source_format == dm_444_64) {
+ plane->swath_height_y = 4;
+ } else {
+ plane->swath_height_y = 8;
+ }
+
+ if (src_param->source_scan != dm_horz) {
+ plane->swath_height_y = 256 / (unsigned int) plane->bytes_per_pixel_y
+ / plane->swath_height_y;
+ }
+
+ plane->swath_height_c = 0;
+
+ } else {
+ if (src_param->sw_mode == dm_sw_linear) {
+ plane->swath_height_y = 1;
+ plane->swath_height_c = 1;
+ } else if (src_param->source_format == dm_420_8) {
+ plane->swath_height_y = 16;
+ plane->swath_height_c = 8;
+ } else {
+ plane->swath_height_y = 8;
+ plane->swath_height_c = 8;
+ }
+
+ if (src_param->source_scan != dm_horz) {
+ double bytes_per_pixel_c_ceil;
+
+ plane->swath_height_y = 256 / dml_ceil(plane->bytes_per_pixel_y)
+ / plane->swath_height_y;
+
+ bytes_per_pixel_c_ceil = dml_ceil_2(plane->bytes_per_pixel_c);
+
+ plane->swath_height_c = 256 / bytes_per_pixel_c_ceil
+ / plane->swath_height_c;
+ }
+ }
+
+ /* use swath height min if buffer isn't big enough */
+
+ buffer_width = ((double) mode_lib->ip.det_buffer_size_kbytes * 1024.0 / 2.0)
+ / (plane->bytes_per_pixel_y * (double) plane->swath_height_y
+ + (plane->bytes_per_pixel_c / 2.0
+ * (double) plane->swath_height_c));
+
+ if ((double) swath_width_y <= buffer_width) {
+ /* do nothing, just keep code structure from Gabes vba */
+ } else {
+ /* substitute swath height with swath height min */
+ if (src_param->source_format == dm_444_64 || src_param->source_format == dm_444_32
+ || src_param->source_format == dm_444_16) {
+ if ((src_param->sw_mode == dm_sw_linear)
+ || (src_param->source_format == dm_444_64
+ && (src_param->sw_mode == dm_sw_4kb_s
+ || src_param->sw_mode
+ == dm_sw_4kb_s_x
+ || src_param->sw_mode
+ == dm_sw_64kb_s
+ || src_param->sw_mode
+ == dm_sw_64kb_s_t
+ || src_param->sw_mode
+ == dm_sw_64kb_s_x
+ || src_param->sw_mode
+ == dm_sw_var_s
+ || src_param->sw_mode
+ == dm_sw_var_s_x)
+ && src_param->source_scan == dm_horz)) {
+ /* do nothing, just keep code structure from Gabes vba */
+ } else {
+ plane->swath_height_y = plane->swath_height_y / 2;
+ }
+ } else {
+ if (src_param->sw_mode == dm_sw_linear) {
+ /* do nothing, just keep code structure from Gabes vba */
+ } else if (src_param->source_format == dm_420_8
+ && src_param->source_scan == dm_horz) {
+ plane->swath_height_y = plane->swath_height_y / 2;
+ } else if (src_param->source_format == dm_420_10
+ && src_param->source_scan == dm_horz) {
+ plane->swath_height_c = plane->swath_height_c / 2;
+ }
+ }
+ }
+
+ if (plane->swath_height_c == 0) {
+ plane->det_buffer_size_y = mode_lib->ip.det_buffer_size_kbytes * 1024.0;
+ } else if (plane->swath_height_c <= plane->swath_height_y) {
+ plane->det_buffer_size_y = mode_lib->ip.det_buffer_size_kbytes * 1024.0 / 2.0;
+ } else {
+ plane->det_buffer_size_y = mode_lib->ip.det_buffer_size_kbytes * 1024.0 * 2.0 / 3.0;
+ }
+}
+
+static void calc_display_pipe_line_delivery_time(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].v_ratio <= 1.0) {
+ planes[i].display_pipe_line_delivery_time = planes[i].swath_width_y
+ * planes[i].num_dpp / planes[i].h_ratio
+ / planes[i].pixclk_mhz;
+ } else {
+ double dchub_pscl_bw_per_clk;
+
+ if (planes[i].h_ratio > 1) {
+ double num_hscl_kernels;
+
+ num_hscl_kernels = dml_ceil((double) planes[i].h_taps / 6);
+ dchub_pscl_bw_per_clk =
+ dml_min(
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk,
+ mode_lib->ip.max_pscl_lb_bw_pix_per_clk
+ * planes[i].h_ratio
+ / num_hscl_kernels);
+ } else {
+ dchub_pscl_bw_per_clk =
+ dml_min(
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk,
+ (double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk);
+ }
+
+ planes[i].display_pipe_line_delivery_time = planes[i].swath_width_y
+ / dchub_pscl_bw_per_clk / planes[i].dppclk_mhz;
+ }
+ }
+}
+
+static double calc_total_data_read_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ double val = 0.0;
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ double swath_width_y_plane = planes[i].swath_width_y * planes[i].num_dpp;
+
+ planes[i].read_bw = swath_width_y_plane
+ * (dml_ceil(planes[i].bytes_per_pixel_y)
+ + dml_ceil_2(planes[i].bytes_per_pixel_c) / 2)
+ / (planes[i].h_total / planes[i].pixclk_mhz) * planes[i].v_ratio;
+
+ val += planes[i].read_bw;
+
+ DTRACE("plane[%d] start", i);
+ DTRACE("read_bw = %f", planes[i].read_bw);
+ DTRACE("plane[%d] end", i);
+ }
+
+ return val;
+}
+
+double dml_wm_calc_total_data_read_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ return calc_total_data_read_bw(mode_lib, planes, num_planes);
+}
+
+static double calc_dcfclk_mhz(
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ double dcfclk_mhz = -1.0;
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ /* voltage and dcfclk must be the same for all pipes */
+ ASSERT(dcfclk_mhz == -1.0 || dcfclk_mhz == planes[i].dcfclk_mhz);
+ dcfclk_mhz = planes[i].dcfclk_mhz;
+ }
+
+ return dcfclk_mhz;
+}
+
+static enum voltage_state find_voltage(
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ int voltage = -1;
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ ASSERT(voltage == -1 || voltage == planes[i].voltage);
+ voltage = planes[i].voltage;
+ }
+
+ return (enum voltage_state) voltage;
+}
+
+static bool find_dcc_enable(struct _vcs_dpi_wm_calc_pipe_params_st *planes, unsigned int num_planes)
+{
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].dcc_enable) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static double calc_return_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ struct _vcs_dpi_soc_bounding_box_st *soc;
+ double return_bw_mbps;
+ double dcfclk_mhz;
+ double return_bus_bw;
+ enum voltage_state voltage;
+ double return_bw_to_dcn;
+ bool dcc_enable;
+ double rob_chunk_diff;
+ double urgent_latency_traffic;
+ double critical_compression;
+ struct _vcs_dpi_voltage_scaling_st state;
+
+ soc = &mode_lib->soc;
+
+ dcfclk_mhz = calc_dcfclk_mhz(planes, num_planes);
+ return_bus_bw = dcfclk_mhz * soc->return_bus_width_bytes;
+
+ DTRACE("INTERMEDIATE dcfclk_mhz = %f", dcfclk_mhz);
+ DTRACE("INTERMEDIATE return_bus_bw = %f", return_bus_bw);
+
+ voltage = find_voltage(planes, num_planes);
+ return_bw_to_dcn = dml_socbb_return_bw_mhz(soc, voltage);
+
+ dcc_enable = find_dcc_enable(planes, num_planes);
+
+ return_bw_mbps = return_bw_to_dcn;
+ DTRACE("INTERMEDIATE return_bw_mbps = %f", return_bw_mbps);
+
+ rob_chunk_diff =
+ (mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes)
+ * 1024.0;
+ DTRACE("INTERMEDIATE rob_chunk_diff = %f", rob_chunk_diff);
+
+ if (dcc_enable && return_bw_to_dcn > return_bus_bw / 4) {
+ double dcc_return_bw =
+ return_bw_to_dcn * 4.0
+ * (1.0
+ - soc->urgent_latency_us
+ / (rob_chunk_diff
+ / (return_bw_to_dcn
+ - return_bus_bw
+ / 4.0)
+ + soc->urgent_latency_us));
+ return_bw_mbps = dml_min(return_bw_mbps, dcc_return_bw);
+ DTRACE("INTERMEDIATE dcc_return_bw = %f", dcc_return_bw);
+ }
+
+ urgent_latency_traffic = return_bus_bw * soc->urgent_latency_us;
+ DTRACE("INTERMEDIATE urgent_latency_traffic = %f", urgent_latency_traffic);
+ critical_compression = 2.0 * urgent_latency_traffic
+ / (return_bw_to_dcn * soc->urgent_latency_us + rob_chunk_diff);
+ DTRACE("INTERMEDIATE critical_compression = %f", critical_compression);
+
+ if (dcc_enable && critical_compression > 1.0 && critical_compression < 4.0) {
+ double crit_return_bw = (4 * return_bw_to_dcn * rob_chunk_diff
+ * urgent_latency_traffic);
+ crit_return_bw = crit_return_bw
+ / dml_pow(
+ return_bw_to_dcn * soc->urgent_latency_us
+ + rob_chunk_diff,
+ 2);
+ DTRACE("INTERMEDIATE critical_return_bw = %f", crit_return_bw);
+ return_bw_mbps = dml_min(return_bw_mbps, crit_return_bw);
+ }
+
+ /* Gabe does this again for some reason using the value of return_bw_mpbs from the previous calculation
+ * and a lightly different return_bw_to_dcn
+ */
+
+ state = dml_socbb_voltage_scaling(soc, voltage);
+ return_bw_to_dcn = dml_min(
+ soc->return_bus_width_bytes * dcfclk_mhz,
+ state.dram_bw_per_chan_gbps * 1000.0 * (double) soc->num_chans);
+
+ DTRACE("INTERMEDIATE rob_chunk_diff = %f", rob_chunk_diff);
+
+ if (dcc_enable && return_bw_to_dcn > return_bus_bw / 4) {
+ double dcc_return_bw =
+ return_bw_to_dcn * 4.0
+ * (1.0
+ - soc->urgent_latency_us
+ / (rob_chunk_diff
+ / (return_bw_to_dcn
+ - return_bus_bw
+ / 4.0)
+ + soc->urgent_latency_us));
+ return_bw_mbps = dml_min(return_bw_mbps, dcc_return_bw);
+ DTRACE("INTERMEDIATE dcc_return_bw = %f", dcc_return_bw);
+ }
+
+ urgent_latency_traffic = return_bus_bw * soc->urgent_latency_us;
+ DTRACE("INTERMEDIATE urgent_latency_traffic = %f", urgent_latency_traffic);
+ critical_compression = 2.0 * urgent_latency_traffic
+ / (return_bw_to_dcn * soc->urgent_latency_us + rob_chunk_diff);
+ DTRACE("INTERMEDIATE critical_compression = %f", critical_compression);
+
+ /* problem here? */
+ if (dcc_enable && critical_compression > 1.0 && critical_compression < 4.0) {
+ double crit_return_bw = (4 * return_bw_to_dcn * rob_chunk_diff
+ * urgent_latency_traffic);
+ crit_return_bw = crit_return_bw
+ / dml_pow(
+ return_bw_to_dcn * soc->urgent_latency_us
+ + rob_chunk_diff,
+ 2);
+ DTRACE("INTERMEDIATE critical_return_bw = %f", crit_return_bw);
+ DTRACE("INTERMEDIATE return_bw_to_dcn = %f", return_bw_to_dcn);
+ DTRACE("INTERMEDIATE rob_chunk_diff = %f", rob_chunk_diff);
+ DTRACE("INTERMEDIATE urgent_latency_traffic = %f", urgent_latency_traffic);
+
+ return_bw_mbps = dml_min(return_bw_mbps, crit_return_bw);
+ }
+
+ DTRACE("INTERMEDIATE final return_bw_mbps = %f", return_bw_mbps);
+ return return_bw_mbps;
+}
+
+double dml_wm_calc_return_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ return calc_return_bw(mode_lib, planes, num_planes);
+}
+
+static double calc_last_pixel_of_line_extra_wm_us(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ double val = 0.0;
+ double total_data_read_bw = calc_total_data_read_bw(mode_lib, planes, num_planes);
+ int voltage = -1;
+ unsigned int i;
+ double return_bw_mbps;
+
+ for (i = 0; i < num_planes; i++) {
+ /* voltage mode must be the same for all pipes */
+ ASSERT(voltage == -1 || voltage == planes[i].voltage);
+ voltage = planes[i].voltage;
+ }
+ return_bw_mbps = calc_return_bw(mode_lib, planes, num_planes);
+
+ for (i = 0; i < num_planes; i++) {
+ double bytes_pp_y = dml_ceil(planes[i].bytes_per_pixel_y);
+ double bytes_pp_c = dml_ceil_2(planes[i].bytes_per_pixel_c);
+ double swath_bytes_y = (double) planes[i].swath_width_y
+ * (double) planes[i].swath_height_y * (double) bytes_pp_y;
+ double swath_bytes_c = ((double) planes[i].swath_width_y / 2.0)
+ * (double) planes[i].swath_height_c * (double) bytes_pp_c;
+ double data_fabric_line_delivery_time = (swath_bytes_y + swath_bytes_c)
+ / (return_bw_mbps * planes[i].read_bw / (double) planes[i].num_dpp
+ / total_data_read_bw);
+
+ DTRACE(
+ "bytes_pp_y = %f, swath_width_y = %f, swath_height_y = %f, swath_bytes_y = %f",
+ bytes_pp_y,
+ (double) planes[i].swath_width_y,
+ (double) planes[i].swath_height_y,
+ swath_bytes_y);
+ DTRACE(
+ "bytes_pp_c = %f, swath_width_c = %f, swath_height_c = %f, swath_bytes_c = %f",
+ bytes_pp_c,
+ ((double) planes[i].swath_width_y / 2.0),
+ (double) planes[i].swath_height_c,
+ swath_bytes_c);
+ DTRACE(
+ "return_bw_mbps = %f, read_bw = %f, num_dpp = %d, total_data_read_bw = %f",
+ return_bw_mbps,
+ planes[i].read_bw,
+ planes[i].num_dpp,
+ total_data_read_bw);
+ DTRACE("data_fabric_line_delivery_time = %f", data_fabric_line_delivery_time);
+ DTRACE(
+ "display_pipe_line_delivery_time = %f",
+ planes[i].display_pipe_line_delivery_time);
+
+ val = dml_max(
+ val,
+ data_fabric_line_delivery_time
+ - planes[i].display_pipe_line_delivery_time);
+ }
+
+ DTRACE("last_pixel_of_line_extra_wm is %f us", val);
+ return val;
+}
+
+static bool calc_pte_enable(struct _vcs_dpi_wm_calc_pipe_params_st *planes, unsigned int num_planes)
+{
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].pte_enable) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static void calc_lines_in_det_y(struct _vcs_dpi_wm_calc_pipe_params_st *plane)
+{
+ plane->lines_in_det_y = plane->det_buffer_size_y / plane->bytes_per_pixel_y
+ / plane->swath_width_y;
+ plane->lines_in_det_y_rounded_down_to_swath = dml_floor(
+ (double) plane->lines_in_det_y / plane->swath_height_y)
+ * plane->swath_height_y;
+ plane->full_det_buffering_time = plane->lines_in_det_y_rounded_down_to_swath
+ * (plane->h_total / plane->pixclk_mhz);
+}
+
+/* CHECKME: not obviously 1:1 with calculation described in architectural
+ * document or spreadsheet */
+static void calc_dcfclk_deepsleep_mhz_per_plane(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *plane)
+{
+ double bus_width_per_pixel;
+
+ if (plane->swath_height_c == 0) {
+ bus_width_per_pixel = dml_ceil(plane->bytes_per_pixel_y) / 64;
+ } else {
+ double bus_width_per_pixel_c;
+
+ bus_width_per_pixel = dml_ceil(plane->bytes_per_pixel_y) / 32;
+ bus_width_per_pixel_c = dml_ceil(plane->bytes_per_pixel_c) / 32;
+ if (bus_width_per_pixel < bus_width_per_pixel_c)
+ bus_width_per_pixel = bus_width_per_pixel_c;
+ }
+
+ if (plane->v_ratio <= 1) {
+ plane->dcfclk_deepsleep_mhz_per_plane = 1.1 * plane->pixclk_mhz / plane->num_dpp
+ * plane->h_ratio * bus_width_per_pixel;
+ } else if (plane->h_ratio > 1) {
+ double num_hscl_kernels = dml_ceil((double) plane->h_taps / 6);
+ double dchub_pscl_bw_per_clk = dml_min(
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk,
+ mode_lib->ip.max_pscl_lb_bw_pix_per_clk * plane->h_ratio
+ / num_hscl_kernels);
+
+ plane->dcfclk_deepsleep_mhz_per_plane = 1.1 * plane->dppclk_mhz
+ * dchub_pscl_bw_per_clk * bus_width_per_pixel;
+ } else {
+ double dchub_pscl_bw_per_clk = dml_min(
+ (double) mode_lib->ip.max_dchub_pscl_bw_pix_per_clk,
+ (double) mode_lib->ip.max_pscl_lb_bw_pix_per_clk);
+
+ plane->dcfclk_deepsleep_mhz_per_plane = 1.1 * plane->dppclk_mhz
+ * dchub_pscl_bw_per_clk * bus_width_per_pixel;
+ }
+
+ plane->dcfclk_deepsleep_mhz_per_plane = dml_max(
+ plane->dcfclk_deepsleep_mhz_per_plane,
+ plane->pixclk_mhz / 16);
+}
+
+/* Implementation of expected stutter efficiency from DCN1_Display_Mode.docx */
+double dml_wm_expected_stutter_eff_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes)
+{
+ double min_full_det_buffering_time_us;
+ double frame_time_for_min_full_det_buffering_time_us = 0.0;
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes = mode_lib->wm_param;
+ unsigned int num_planes;
+ unsigned int i;
+ double total_data_read_bw_mbps;
+ double average_read_bw_gbps;
+ double min_full_det_buffer_size_bytes;
+ double rob_fill_size_bytes;
+ double part_of_burst_that_fits_in_rob;
+ int voltage;
+ double dcfclk_mhz;
+ unsigned int total_writeback;
+ double return_bw_mbps;
+ double stutter_burst_time_us;
+ double stutter_eff_not_including_vblank;
+ double smallest_vblank_us;
+ double stutter_eff;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ DTRACE("calculating expected stutter efficiency");
+
+ num_planes = dml_wm_e2e_to_wm(mode_lib, e2e, num_pipes, planes);
+
+ for (i = 0; i < num_planes; i++) {
+ calc_lines_in_det_y(&planes[i]);
+
+ DTRACE("swath width y plane %d = %d", i, planes[i].swath_width_y);
+ DTRACE("swath height y plane %d = %d", i, planes[i].swath_height_y);
+ DTRACE(
+ "bytes per pixel det y plane %d = %f",
+ i,
+ planes[i].bytes_per_pixel_y);
+ DTRACE(
+ "bytes per pixel det c plane %d = %f",
+ i,
+ planes[i].bytes_per_pixel_c);
+ DTRACE(
+ "det buffer size plane %d = %d",
+ i,
+ planes[i].det_buffer_size_y);
+ DTRACE("lines in det plane %d = %d", i, planes[i].lines_in_det_y);
+ DTRACE(
+ "lines in det rounded to swaths plane %d = %d",
+ i,
+ planes[i].lines_in_det_y_rounded_down_to_swath);
+ }
+
+ min_full_det_buffering_time_us = 9999.0;
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].full_det_buffering_time < min_full_det_buffering_time_us) {
+ min_full_det_buffering_time_us = planes[i].full_det_buffering_time;
+ frame_time_for_min_full_det_buffering_time_us = (double) planes[i].v_total
+ * planes[i].h_total / planes[i].pixclk_mhz;
+ }
+ }
+
+ DTRACE("INTERMEDIATE: min_full_det_buffering_time_us = %f", min_full_det_buffering_time_us);
+
+ total_data_read_bw_mbps = calc_total_data_read_bw(mode_lib, planes, num_planes);
+
+ average_read_bw_gbps = 0.0;
+
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].dcc_enable) {
+ average_read_bw_gbps += planes[i].read_bw / planes[i].dcc_rate / 1000;
+ } else {
+ average_read_bw_gbps += planes[i].read_bw / 1000;
+ }
+
+ if (planes[i].dcc_enable) {
+ average_read_bw_gbps += planes[i].read_bw / 1000 / 256;
+ }
+
+ if (planes[i].pte_enable) {
+ average_read_bw_gbps += planes[i].read_bw / 1000 / 512;
+ }
+ }
+
+ min_full_det_buffer_size_bytes = min_full_det_buffering_time_us * total_data_read_bw_mbps;
+ rob_fill_size_bytes = mode_lib->ip.rob_buffer_size_kbytes * 1024 * total_data_read_bw_mbps
+ / (average_read_bw_gbps * 1000);
+ part_of_burst_that_fits_in_rob = dml_min(
+ min_full_det_buffer_size_bytes,
+ rob_fill_size_bytes);
+
+ voltage = -1;
+ dcfclk_mhz = -1.0;
+ total_writeback = 0;
+
+ for (i = 0; i < num_pipes; i++) {
+ /* voltage and dcfclk must be the same for all pipes */
+ ASSERT(voltage == -1 || voltage == e2e[i].clks_cfg.voltage);
+ voltage = e2e[i].clks_cfg.voltage;
+ ASSERT(dcfclk_mhz == -1.0 || dcfclk_mhz == e2e[i].clks_cfg.dcfclk_mhz);
+ dcfclk_mhz = e2e[i].clks_cfg.dcfclk_mhz;
+
+ if (e2e[i].dout.output_type == dm_wb)
+ total_writeback++;
+ }
+
+ return_bw_mbps = calc_return_bw(mode_lib, planes, num_planes);
+
+ DTRACE("INTERMEDIATE: part_of_burst_that_fits_in_rob = %f", part_of_burst_that_fits_in_rob);
+ DTRACE("INTERMEDIATE: average_read_bw_gbps = %f", average_read_bw_gbps);
+ DTRACE("INTERMEDIATE: total_data_read_bw_mbps = %f", total_data_read_bw_mbps);
+ DTRACE("INTERMEDIATE: return_bw_mbps = %f", return_bw_mbps);
+
+ stutter_burst_time_us = part_of_burst_that_fits_in_rob * (average_read_bw_gbps * 1000)
+ / total_data_read_bw_mbps / return_bw_mbps
+ + (min_full_det_buffering_time_us * total_data_read_bw_mbps
+ - part_of_burst_that_fits_in_rob) / (dcfclk_mhz * 64);
+ DTRACE("INTERMEDIATE: stutter_burst_time_us = %f", stutter_burst_time_us);
+
+ if (total_writeback == 0) {
+ stutter_eff_not_including_vblank = (1.0
+ - ((mode_lib->soc.sr_exit_time_us + stutter_burst_time_us)
+ / min_full_det_buffering_time_us)) * 100.0;
+ } else {
+ stutter_eff_not_including_vblank = 0.0;
+ }
+
+ DTRACE("stutter_efficiency_not_including_vblank = %f", stutter_eff_not_including_vblank);
+
+ smallest_vblank_us = 9999.0;
+
+ for (i = 0; i < num_pipes; i++) {
+ double vblank_us;
+ if (e2e[i].pipe.dest.syncronized_vblank_all_planes != 0 || num_pipes == 1) {
+ vblank_us = (double) (e2e[i].pipe.dest.vtotal + 1
+ - e2e[i].pipe.dest.vblank_start
+ + e2e[i].pipe.dest.vblank_end * e2e[i].pipe.dest.htotal)
+ / e2e[i].pipe.dest.pixel_rate_mhz;
+ } else {
+ vblank_us = 0.0;
+ }
+
+ smallest_vblank_us = dml_min(smallest_vblank_us, vblank_us);
+ }
+
+ DTRACE("smallest vblank = %f us", smallest_vblank_us);
+
+ stutter_eff = 100.0
+ * (((stutter_eff_not_including_vblank / 100.0)
+ * (frame_time_for_min_full_det_buffering_time_us
+ - smallest_vblank_us) + smallest_vblank_us)
+ / frame_time_for_min_full_det_buffering_time_us);
+
+ DTRACE("stutter_efficiency = %f", stutter_eff);
+
+ return stutter_eff_not_including_vblank;
+}
+
+double dml_wm_expected_stutter_eff_e2e_with_vblank(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes)
+{
+ double min_full_det_buffering_time_us;
+ double frame_time_for_min_full_det_buffering_time_us = 0.0;
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes = mode_lib->wm_param;
+ unsigned int num_planes;
+ unsigned int i;
+ double total_data_read_bw_mbps;
+ double average_read_bw_gbps;
+ double min_full_det_buffer_size_bytes;
+ double rob_fill_size_bytes;
+ double part_of_burst_that_fits_in_rob;
+ int voltage;
+ double dcfclk_mhz;
+ unsigned int total_writeback;
+ double return_bw_mbps;
+ double stutter_burst_time_us;
+ double stutter_eff_not_including_vblank;
+ double smallest_vblank_us;
+ double stutter_eff;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ num_planes = dml_wm_e2e_to_wm(mode_lib, e2e, num_pipes, planes);
+
+ for (i = 0; i < num_planes; i++) {
+ calc_lines_in_det_y(&planes[i]);
+ }
+
+ min_full_det_buffering_time_us = 9999.0;
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].full_det_buffering_time < min_full_det_buffering_time_us) {
+ min_full_det_buffering_time_us = planes[i].full_det_buffering_time;
+ frame_time_for_min_full_det_buffering_time_us = (double) planes[i].v_total
+ * planes[i].h_total / planes[i].pixclk_mhz;
+ }
+ }
+
+ total_data_read_bw_mbps = calc_total_data_read_bw(mode_lib, planes, num_planes);
+ average_read_bw_gbps = 0.0;
+
+ for (i = 0; i < num_planes; i++) {
+ if (planes[i].dcc_enable) {
+ average_read_bw_gbps += planes[i].read_bw / planes[i].dcc_rate / 1000;
+ } else {
+ average_read_bw_gbps += planes[i].read_bw / 1000;
+ }
+
+ if (planes[i].dcc_enable) {
+ average_read_bw_gbps += planes[i].read_bw / 1000 / 256;
+ }
+
+ if (planes[i].pte_enable) {
+ average_read_bw_gbps += planes[i].read_bw / 1000 / 512;
+ }
+ }
+
+ min_full_det_buffer_size_bytes = min_full_det_buffering_time_us * total_data_read_bw_mbps;
+ rob_fill_size_bytes = mode_lib->ip.rob_buffer_size_kbytes * 1024 * total_data_read_bw_mbps
+ / (average_read_bw_gbps * 1000);
+ part_of_burst_that_fits_in_rob = dml_min(
+ min_full_det_buffer_size_bytes,
+ rob_fill_size_bytes);
+
+ voltage = -1;
+ dcfclk_mhz = -1.0;
+ total_writeback = 0;
+
+ for (i = 0; i < num_pipes; i++) {
+ /* voltage and dcfclk must be the same for all pipes */
+ ASSERT(voltage == -1 || voltage == e2e[i].clks_cfg.voltage);
+ voltage = e2e[i].clks_cfg.voltage;
+ ASSERT(dcfclk_mhz == -1.0 || dcfclk_mhz == e2e[i].clks_cfg.dcfclk_mhz);
+ dcfclk_mhz = e2e[i].clks_cfg.dcfclk_mhz;
+
+ if (e2e[i].dout.output_type == dm_wb)
+ total_writeback++;
+ }
+
+ return_bw_mbps = calc_return_bw(mode_lib, planes, num_planes);
+
+ stutter_burst_time_us = part_of_burst_that_fits_in_rob * (average_read_bw_gbps * 1000)
+ / total_data_read_bw_mbps / return_bw_mbps
+ + (min_full_det_buffering_time_us * total_data_read_bw_mbps
+ - part_of_burst_that_fits_in_rob) / (dcfclk_mhz * 64);
+
+ if (total_writeback == 0) {
+ stutter_eff_not_including_vblank = (1.0
+ - ((mode_lib->soc.sr_exit_time_us + stutter_burst_time_us)
+ / min_full_det_buffering_time_us)) * 100.0;
+ } else {
+ stutter_eff_not_including_vblank = 0.0;
+ }
+
+ smallest_vblank_us = 9999.0;
+
+ for (i = 0; i < num_pipes; i++) {
+ double vblank_us;
+ if (e2e[i].pipe.dest.syncronized_vblank_all_planes != 0 || num_pipes == 1) {
+ vblank_us = (double) (e2e[i].pipe.dest.vtotal + 1
+ - e2e[i].pipe.dest.vblank_start
+ + e2e[i].pipe.dest.vblank_end * e2e[i].pipe.dest.htotal)
+ / e2e[i].pipe.dest.pixel_rate_mhz;
+ } else {
+ vblank_us = 0.0;
+ }
+
+ smallest_vblank_us = dml_min(smallest_vblank_us, vblank_us);
+ }
+
+ stutter_eff = 100.0
+ * (((stutter_eff_not_including_vblank / 100.0)
+ * (frame_time_for_min_full_det_buffering_time_us
+ - smallest_vblank_us) + smallest_vblank_us)
+ / frame_time_for_min_full_det_buffering_time_us);
+
+
+ return stutter_eff;
+}
+
+double urgent_extra_calc(
+ struct display_mode_lib *mode_lib,
+ double dcfclk_mhz,
+ double return_bw_mbps,
+ unsigned int total_active_dpp,
+ unsigned int total_dcc_active_dpp)
+{
+ double urgent_extra_latency_us = 0.0;
+ double urgent_round_trip_ooo_latency_us;
+
+ urgent_round_trip_ooo_latency_us =
+ (((double) mode_lib->soc.round_trip_ping_latency_dcfclk_cycles + 32)
+ / dcfclk_mhz)
+ + (((double) (mode_lib->soc.urgent_out_of_order_return_per_channel_bytes
+ * mode_lib->soc.num_chans)) / return_bw_mbps);
+
+ DTRACE(
+ "INTERMEDIATE round_trip_ping_latency_dcfclk_cycles = %d",
+ mode_lib->soc.round_trip_ping_latency_dcfclk_cycles);
+ DTRACE("INTERMEDIATE dcfclk_mhz = %f", dcfclk_mhz);
+ DTRACE(
+ "INTERMEDIATE urgent_out_of_order_return_per_channel_bytes = %d",
+ mode_lib->soc.urgent_out_of_order_return_per_channel_bytes);
+
+ urgent_extra_latency_us = urgent_round_trip_ooo_latency_us
+ + ((double) total_active_dpp * mode_lib->ip.pixel_chunk_size_kbytes
+ + (double) total_dcc_active_dpp
+ * mode_lib->ip.meta_chunk_size_kbytes)
+ * 1024.0 / return_bw_mbps; /* to us */
+
+ DTRACE(
+ "INTERMEDIATE urgent_round_trip_ooo_latency_us = %f",
+ urgent_round_trip_ooo_latency_us);
+ DTRACE("INTERMEDIATE total_active_dpp = %d", total_active_dpp);
+ DTRACE(
+ "INTERMEDIATE pixel_chunk_size_kbytes = %d",
+ mode_lib->ip.pixel_chunk_size_kbytes);
+ DTRACE("INTERMEDIATE total_dcc_active_dpp = %d", total_dcc_active_dpp);
+ DTRACE(
+ "INTERMEDIATE meta_chunk_size_kbyte = %d",
+ mode_lib->ip.meta_chunk_size_kbytes);
+ DTRACE("INTERMEDIATE return_bw_mbps = %f", return_bw_mbps);
+
+ return urgent_extra_latency_us;
+}
+
+double dml_wm_urgent_extra_max(struct display_mode_lib *mode_lib)
+{
+ unsigned int total_active_dpp = DC__NUM_DPP;
+ unsigned int total_dcc_active_dpp = total_active_dpp;
+ double urgent_extra_latency_us = 0.0;
+ double dcfclk_mhz = 0.0;
+ double return_bw_mbps = 0.0;
+ int voltage = dm_vmin;
+
+ /* use minimum voltage */
+ return_bw_mbps = dml_socbb_return_bw_mhz(&mode_lib->soc, (enum voltage_state) voltage);
+ /* use minimum dcfclk */
+ dcfclk_mhz = mode_lib->soc.vmin.dcfclk_mhz;
+ /* use max dpps and dpps with dcc */
+
+ urgent_extra_latency_us = urgent_extra_calc(
+ mode_lib,
+ dcfclk_mhz,
+ return_bw_mbps,
+ total_active_dpp,
+ total_dcc_active_dpp);
+
+ DTRACE("urgent extra max = %f", urgent_extra_latency_us);
+ return urgent_extra_latency_us;
+}
+
+double dml_wm_urgent_extra(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ unsigned int total_active_dpp = 0;
+ unsigned int total_dcc_active_dpp = 0;
+ double urgent_extra_latency_us = 0.0;
+ double dcfclk_mhz = 0.0;
+ double return_bw_mbps = 0.0;
+ int voltage = -1;
+ bool pte_enable = false;
+ unsigned int i;
+
+ for (i = 0; i < num_pipes; i++) {
+ /* num_dpp must be greater than 0 */
+ ASSERT(pipes[i].num_dpp > 0);
+
+ /* voltage mode must be the same for all pipes */
+ ASSERT(voltage == -1 || voltage == pipes[i].voltage);
+ voltage = pipes[i].voltage;
+
+ /* dcfclk for all pipes must be the same */
+ ASSERT(dcfclk_mhz == 0.0 || dcfclk_mhz == pipes[i].dcfclk_mhz);
+ dcfclk_mhz = pipes[i].dcfclk_mhz;
+
+ total_active_dpp += pipes[i].num_dpp;
+
+ if (pipes[i].dcc_enable) {
+ total_dcc_active_dpp += pipes[i].num_dpp;
+ }
+ }
+
+ DTRACE("total active dpps %d", total_active_dpp);
+ DTRACE("total active dpps with dcc %d", total_dcc_active_dpp);
+ DTRACE("voltage state is %d", voltage);
+
+ return_bw_mbps = calc_return_bw(mode_lib, pipes, num_pipes);
+
+ DTRACE("return_bandwidth is %f MBps", return_bw_mbps);
+
+ pte_enable = calc_pte_enable(pipes, num_pipes);
+
+ /* calculate the maximum extra latency just for comparison purposes */
+ /* dml_wm_urgent_extra_max(); */
+ urgent_extra_latency_us = urgent_extra_calc(
+ mode_lib,
+ dcfclk_mhz,
+ return_bw_mbps,
+ total_active_dpp,
+ total_dcc_active_dpp);
+
+ DTRACE("INTERMEDIATE urgent_extra_latency_us_before_pte = %f", urgent_extra_latency_us);
+
+ if (pte_enable) {
+ urgent_extra_latency_us += total_active_dpp * mode_lib->ip.pte_chunk_size_kbytes
+ * 1024.0 / return_bw_mbps;
+
+ DTRACE("INTERMEDIATE pte_enable = true");
+ DTRACE("INTERMEDIATE total_active_dpp = %d", total_active_dpp);
+ DTRACE(
+ "INTERMEDIATE pte_chunk_size_kbytes = %d",
+ mode_lib->ip.pte_chunk_size_kbytes);
+ DTRACE("INTERMEDIATE return_bw_mbps = %f", return_bw_mbps);
+ }
+
+ return urgent_extra_latency_us;
+}
+
+double dml_wm_urgent_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm = mode_lib->wm_param;
+ unsigned int combined_pipes;
+ double urgent_wm;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ combined_pipes = dml_wm_e2e_to_wm(mode_lib, pipes, num_pipes, wm);
+
+ urgent_wm = dml_wm_urgent(mode_lib, wm, combined_pipes);
+
+ return urgent_wm;
+}
+
+double dml_wm_urgent(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ double urgent_watermark;
+ double urgent_extra_latency_us;
+ double last_pixel_of_line_extra_wm_us = 0.0;
+
+ DTRACE("calculating urgent watermark");
+ calc_display_pipe_line_delivery_time(mode_lib, planes, num_planes);
+ urgent_extra_latency_us = dml_wm_urgent_extra(mode_lib, planes, num_planes);
+
+ last_pixel_of_line_extra_wm_us = calc_last_pixel_of_line_extra_wm_us(
+ mode_lib,
+ planes,
+ num_planes);
+
+ urgent_watermark = mode_lib->soc.urgent_latency_us + last_pixel_of_line_extra_wm_us
+ + urgent_extra_latency_us;
+
+ DTRACE("INTERMEDIATE urgent_latency_us = %f", mode_lib->soc.urgent_latency_us);
+ DTRACE("INTERMEDIATE last_pixel_of_line_extra_wm_us = %f", last_pixel_of_line_extra_wm_us);
+ DTRACE("INTERMEDIATE urgent_extra_latency_us = %f", urgent_extra_latency_us);
+
+ DTRACE("urgent_watermark_us = %f", urgent_watermark);
+ return urgent_watermark;
+}
+
+double dml_wm_pte_meta_urgent(struct display_mode_lib *mode_lib, double urgent_wm_us)
+{
+ double val;
+
+ val = urgent_wm_us + 2.0 * mode_lib->soc.urgent_latency_us;
+ DTRACE("pte_meta_urgent_watermark_us = %f", val);
+
+ return val;
+}
+
+double dml_wm_dcfclk_deepsleep_mhz_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes = mode_lib->wm_param;
+ unsigned int num_planes;
+ double val;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ num_planes = dml_wm_e2e_to_wm(mode_lib, pipes, num_pipes, planes);
+
+ val = dml_wm_dcfclk_deepsleep_mhz(mode_lib, planes, num_planes);
+
+ return val;
+}
+
+double dml_wm_dcfclk_deepsleep_mhz(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes)
+{
+ double val = 8.0;
+ unsigned int i;
+
+ for (i = 0; i < num_planes; i++) {
+ calc_dcfclk_deepsleep_mhz_per_plane(mode_lib, &planes[i]);
+
+ if (val < planes[i].dcfclk_deepsleep_mhz_per_plane) {
+ val = planes[i].dcfclk_deepsleep_mhz_per_plane;
+ }
+
+ DTRACE("plane[%d] start", i);
+ DTRACE("dcfclk_deepsleep_per_plane = %f", planes[i].dcfclk_deepsleep_mhz_per_plane);
+ DTRACE("plane[%d] end", i);
+ }
+
+ DTRACE("dcfclk_deepsleep_mhz = %f", val);
+
+ return val;
+}
+
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm = mode_lib->wm_param;
+ unsigned int combined_pipes;
+ struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_wm;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ combined_pipes = dml_wm_e2e_to_wm(mode_lib, pipes, num_pipes, wm);
+ cstate_pstate_wm = dml_wm_cstate_pstate(mode_lib, wm, combined_pipes);
+
+
+ return cstate_pstate_wm;
+}
+
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_cstate_pstate_watermarks_st wm;
+ double urgent_extra_latency_us;
+ double urgent_watermark_us;
+ double last_pixel_of_line_extra_wm_us;
+ double dcfclk_deepsleep_freq;
+
+ DTRACE("calculating cstate and pstate watermarks");
+ urgent_extra_latency_us = dml_wm_urgent_extra(mode_lib, pipes, num_pipes);
+ urgent_watermark_us = dml_wm_urgent(mode_lib, pipes, num_pipes);
+
+ last_pixel_of_line_extra_wm_us = calc_last_pixel_of_line_extra_wm_us(
+ mode_lib,
+ pipes,
+ num_pipes);
+ dcfclk_deepsleep_freq = dml_wm_dcfclk_deepsleep_mhz(mode_lib, pipes, num_pipes);
+
+ wm.cstate_exit_us = mode_lib->soc.sr_exit_time_us + last_pixel_of_line_extra_wm_us
+ + urgent_extra_latency_us
+ + mode_lib->ip.dcfclk_cstate_latency / dcfclk_deepsleep_freq;
+ wm.cstate_enter_plus_exit_us = mode_lib->soc.sr_enter_plus_exit_time_us
+ + last_pixel_of_line_extra_wm_us + urgent_extra_latency_us;
+ wm.pstate_change_us = mode_lib->soc.dram_clock_change_latency_us + urgent_watermark_us;
+
+ DTRACE("stutter_exit_watermark_us = %f", wm.cstate_exit_us);
+ DTRACE("stutter_enter_plus_exit_watermark_us = %f", wm.cstate_enter_plus_exit_us);
+ DTRACE("dram_clock_change_watermark_us = %f", wm.pstate_change_us);
+
+ return wm;
+}
+
+double dml_wm_writeback_pstate_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm = mode_lib->wm_param;
+ unsigned int combined_pipes;
+
+ memset(mode_lib->wm_param, 0, sizeof(mode_lib->wm_param));
+ combined_pipes = dml_wm_e2e_to_wm(mode_lib, pipes, num_pipes, wm);
+
+
+ return dml_wm_writeback_pstate(mode_lib, wm, combined_pipes);
+}
+
+double dml_wm_writeback_pstate(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes)
+{
+ unsigned int total_active_wb = 0;
+ double wm = 0.0;
+ double socclk_mhz = 0.0;
+ unsigned int i;
+
+ DTRACE("calculating wb pstate watermark");
+ for (i = 0; i < num_pipes; i++) {
+ if (pipes[i].output_type == dm_wb)
+ total_active_wb++;
+ ASSERT(socclk_mhz == 0.0 || socclk_mhz == pipes[i].socclk_mhz);
+ socclk_mhz = pipes[i].socclk_mhz;
+ }
+
+ DTRACE("total wb outputs %d", total_active_wb);
+ DTRACE("socclk frequency %f Mhz", socclk_mhz);
+
+ if (total_active_wb <= 1) {
+ wm = mode_lib->soc.writeback_dram_clock_change_latency_us;
+ } else {
+ wm = mode_lib->soc.writeback_dram_clock_change_latency_us
+ + (mode_lib->ip.writeback_chunk_size_kbytes * 1024.0) / 32.0
+ / socclk_mhz;
+ }
+
+ DTRACE("wb pstate watermark %f us", wm);
+ return wm;
+}
+
+unsigned int dml_wm_e2e_to_wm(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes,
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm)
+{
+ unsigned int num_planes = 0;
+ bool visited[DC__NUM_PIPES];
+ unsigned int i, j;
+
+ for (i = 0; i < num_pipes; i++) {
+ visited[i] = false;
+ }
+
+ for (i = 0; i < num_pipes; i++) {
+ unsigned int num_dpp = 1;
+
+ if (visited[i]) {
+ continue;
+ }
+
+ visited[i] = true;
+
+ if (e2e[i].pipe.src.is_hsplit) {
+ for (j = i + 1; j < num_pipes; j++) {
+ if (e2e[j].pipe.src.is_hsplit && !visited[j]
+ && (e2e[i].pipe.src.hsplit_grp
+ == e2e[j].pipe.src.hsplit_grp)) {
+ num_dpp++;
+ visited[j] = true;
+ }
+ }
+ }
+
+ wm[num_planes].num_dpp = num_dpp;
+ wm[num_planes].voltage = e2e[i].clks_cfg.voltage;
+ wm[num_planes].output_type = e2e[i].dout.output_type;
+ wm[num_planes].dcfclk_mhz = e2e[i].clks_cfg.dcfclk_mhz;
+ wm[num_planes].socclk_mhz = e2e[i].clks_cfg.socclk_mhz;
+ wm[num_planes].dppclk_mhz = e2e[i].clks_cfg.dppclk_mhz;
+ wm[num_planes].pixclk_mhz = e2e[i].pipe.dest.pixel_rate_mhz;
+
+ wm[num_planes].pte_enable = e2e[i].pipe.src.vm;
+ wm[num_planes].dcc_enable = e2e[i].pipe.src.dcc;
+ wm[num_planes].dcc_rate = e2e[i].pipe.src.dcc_rate;
+
+ get_bytes_per_pixel(
+ (enum source_format_class) e2e[i].pipe.src.source_format,
+ &wm[num_planes]);
+ wm[num_planes].swath_width_y = get_swath_width_y(&e2e[i].pipe.src, num_dpp);
+ get_swath_height(
+ mode_lib,
+ &e2e[i].pipe.src,
+ &wm[num_planes],
+ wm[num_planes].swath_width_y);
+
+ wm[num_planes].interlace_en = e2e[i].pipe.dest.interlaced;
+ wm[num_planes].h_ratio = e2e[i].pipe.scale_ratio_depth.hscl_ratio;
+ wm[num_planes].v_ratio = e2e[i].pipe.scale_ratio_depth.vscl_ratio;
+ if (wm[num_planes].interlace_en) {
+ wm[num_planes].v_ratio = 2 * wm[num_planes].v_ratio;
+ }
+ wm[num_planes].h_taps = e2e[i].pipe.scale_taps.htaps;
+ wm[num_planes].h_total = e2e[i].pipe.dest.htotal;
+ wm[num_planes].v_total = e2e[i].pipe.dest.vtotal;
+ wm[num_planes].v_active = e2e[i].pipe.dest.vactive;
+ wm[num_planes].e2e_index = i;
+ num_planes++;
+ }
+
+ for (i = 0; i < num_planes; i++) {
+ DTRACE("plane[%d] start", i);
+ DTRACE("voltage = %d", wm[i].voltage);
+ DTRACE("v_active = %d", wm[i].v_active);
+ DTRACE("h_total = %d", wm[i].h_total);
+ DTRACE("v_total = %d", wm[i].v_total);
+ DTRACE("pixclk_mhz = %f", wm[i].pixclk_mhz);
+ DTRACE("dcfclk_mhz = %f", wm[i].dcfclk_mhz);
+ DTRACE("dppclk_mhz = %f", wm[i].dppclk_mhz);
+ DTRACE("h_ratio = %f", wm[i].h_ratio);
+ DTRACE("v_ratio = %f", wm[i].v_ratio);
+ DTRACE("interlaced = %d", wm[i].interlace_en);
+ DTRACE("h_taps = %d", wm[i].h_taps);
+ DTRACE("num_dpp = %d", wm[i].num_dpp);
+ DTRACE("swath_width_y = %d", wm[i].swath_width_y);
+ DTRACE("swath_height_y = %d", wm[i].swath_height_y);
+ DTRACE("swath_height_c = %d", wm[i].swath_height_c);
+ DTRACE("det_buffer_size_y = %d", wm[i].det_buffer_size_y);
+ DTRACE("dcc_rate = %f", wm[i].dcc_rate);
+ DTRACE("dcc_enable = %s", wm[i].dcc_enable ? "true" : "false");
+ DTRACE("pte_enable = %s", wm[i].pte_enable ? "true" : "false");
+ DTRACE("plane[%d] end", i);
+ }
+
+ return num_planes;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_watermark.h b/drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
new file mode 100644
index 0000000..94cde8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_WATERMARK_H__
+#define __DISPLAY_WATERMARK_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+double dml_wm_urgent_extra(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes);
+double dml_wm_urgent_extra_max(struct display_mode_lib *mode_lib);
+
+double dml_wm_urgent_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes);
+double dml_wm_urgent(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes);
+double dml_wm_pte_meta_urgent(struct display_mode_lib *mode_lib, double urgent_wm_us);
+double dml_wm_dcfclk_deepsleep_mhz_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes);
+double dml_wm_dcfclk_deepsleep_mhz(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes);
+
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes);
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes);
+
+double dml_wm_writeback_pstate_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+ unsigned int num_pipes);
+double dml_wm_writeback_pstate(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+ unsigned int num_pipes);
+
+double dml_wm_expected_stutter_eff_e2e(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes);
+double dml_wm_expected_stutter_eff_e2e_with_vblank(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes);
+
+unsigned int dml_wm_e2e_to_wm(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+ unsigned int num_pipes,
+ struct _vcs_dpi_wm_calc_pipe_params_st *wm);
+
+double dml_wm_calc_total_data_read_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes);
+double dml_wm_calc_return_bw(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+ unsigned int num_planes);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
new file mode 100644
index 0000000..21349a02
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dml_common_defs.h"
+#include "../calcs/dcn_calc_math.h"
+
+double dml_min(double a, double b)
+{
+ return (double) dcn_bw_min2(a, b);
+}
+
+double dml_max(double a, double b)
+{
+ return (double) dcn_bw_max2(a, b);
+}
+
+double dml_ceil(double a)
+{
+ return (double) dcn_bw_ceil2(a, 1);
+}
+
+double dml_floor(double a)
+{
+ return (double) dcn_bw_floor2(a, 1);
+}
+
+double dml_round(double a)
+{
+ double round_pt = 0.5;
+ double ceil = dml_ceil(a);
+ double floor = dml_floor(a);
+
+ if (a - floor >= round_pt)
+ return ceil;
+ else
+ return floor;
+}
+
+int dml_log2(double x)
+{
+ return dml_round((double)dcn_bw_log(x, 2));
+}
+
+double dml_pow(double a, int exp)
+{
+ return (double) dcn_bw_pow(a, exp);
+}
+
+unsigned int dml_round_to_multiple(
+ unsigned int num,
+ unsigned int multiple,
+ bool up)
+{
+ unsigned int remainder;
+
+ if (multiple == 0)
+ return num;
+
+ remainder = num % multiple;
+
+ if (remainder == 0)
+ return num;
+
+ if (up)
+ return (num + multiple - remainder);
+ else
+ return (num - remainder);
+}
+
+double dml_fmod(double f, int val)
+{
+ return (double) dcn_bw_mod(f, val);
+}
+
+double dml_ceil_2(double f)
+{
+ return (double) dcn_bw_ceil2(f, 2);
+}
+
+bool dml_util_is_420(enum source_format_class sorce_format)
+{
+ bool val = false;
+
+ switch (sorce_format) {
+ case dm_444_16:
+ val = false;
+ break;
+ case dm_444_32:
+ val = false;
+ break;
+ case dm_444_64:
+ val = false;
+ break;
+ case dm_420_8:
+ val = true;
+ break;
+ case dm_420_10:
+ val = true;
+ break;
+ case dm_422_8:
+ val = false;
+ break;
+ case dm_422_10:
+ val = false;
+ break;
+ default:
+ BREAK_TO_DEBUGGER();
+ }
+
+ return val;
+}
+
+double dml_ceil_ex(double x, double granularity)
+{
+ return (double) dcn_bw_ceil2(x, granularity);
+}
+
+double dml_floor_ex(double x, double granularity)
+{
+ return (double) dcn_bw_floor2(x, granularity);
+}
+
+double dml_log(double x, double base)
+{
+ return (double) dcn_bw_log(x, base);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
new file mode 100644
index 0000000..c5340d4
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_COMMON_DEFS_H__
+#define __DC_COMMON_DEFS_H__
+
+#include "dm_services.h"
+#include "dc_features.h"
+#include "display_mode_structs.h"
+#include "display_mode_enums.h"
+
+#define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__);
+
+double dml_min(double a, double b);
+double dml_max(double a, double b);
+bool dml_util_is_420(enum source_format_class sorce_format);
+double dml_ceil_ex(double x, double granularity);
+double dml_floor_ex(double x, double granularity);
+double dml_log(double x, double base);
+double dml_ceil(double a);
+double dml_floor(double a);
+double dml_round(double a);
+int dml_log2(double x);
+double dml_pow(double a, int exp);
+unsigned int dml_round_to_multiple(
+ unsigned int num, unsigned int multiple, bool up);
+double dml_fmod(double f, int val);
+double dml_ceil_2(double f);
+
+#endif /* __DC_COMMON_DEFS_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
new file mode 100644
index 0000000..cb143d3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "soc_bounding_box.h"
+#include "display_mode_lib.h"
+
+void dml_socbb_set_latencies(
+ struct display_mode_lib *mode_lib,
+ struct _vcs_dpi_soc_bounding_box_st *from_box)
+{
+ struct _vcs_dpi_soc_bounding_box_st *to_box = &mode_lib->soc;
+
+ to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
+ to_box->sr_exit_time_us = from_box->sr_exit_time_us;
+ to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
+ to_box->urgent_latency_us = from_box->urgent_latency_us;
+ to_box->writeback_latency_us = from_box->writeback_latency_us;
+ DTRACE("box.dram_clock_change_latency_us: %f", from_box->dram_clock_change_latency_us);
+ DTRACE("box.sr_exit_time_us: %f", from_box->sr_exit_time_us);
+ DTRACE("box.sr_enter_plus_exit_time_us: %f", from_box->sr_enter_plus_exit_time_us);
+ DTRACE("box.urgent_latency_us: %f", from_box->urgent_latency_us);
+ DTRACE("box.writeback_latency_us: %f", from_box->writeback_latency_us);
+
+}
+
+struct _vcs_dpi_voltage_scaling_st dml_socbb_voltage_scaling(
+ struct _vcs_dpi_soc_bounding_box_st *box,
+ enum voltage_state voltage)
+{
+ switch (voltage) {
+ case dm_vmin:
+ return box->vmin;
+ case dm_vnom:
+ return box->vnom;
+ case dm_vmax:
+ default:
+ return box->vmax;
+ }
+}
+
+double dml_socbb_return_bw_mhz(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage)
+{
+ double return_bw;
+
+ struct _vcs_dpi_voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
+
+ return_bw = dml_min(
+ ((double) box->return_bus_width_bytes) * state.dcfclk_mhz,
+ state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
+ * box->ideal_dram_bw_after_urgent_percent / 100.0);
+ return return_bw;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
new file mode 100644
index 0000000..7bbae33
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __SOC_BOUNDING_BOX_H__
+#define __SOC_BOUNDING_BOX_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+void dml_socbb_set_latencies(struct display_mode_lib *mode_lib, struct _vcs_dpi_soc_bounding_box_st *from_box);
+struct _vcs_dpi_voltage_scaling_st dml_socbb_voltage_scaling(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage);
+double dml_socbb_return_bw_mhz(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage);
+
+#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 112/117] drm/amdgpu/display: Add gpio support for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (102 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 111/117] drm/amdgpu/display: Add dml " Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 113/117] drm/amdgpu/display: Add i2c/aux " Alex Deucher
` (5 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
GPIOs are used for i2c and other things.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 ++++++++++
.../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 ++
.../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +++++++++++++++++++++
.../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 ++
4 files changed, 666 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
new file mode 100644
index 0000000..409763c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "hw_factory_dcn10.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#define block HPD
+#define reg_num 0
+
+/* set field name */
+#define SF_HPD(reg_name, field_name, post_fix)\
+ .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define REG(reg_name)\
+ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define REGI(reg_name, block, id)\
+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(0),
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5)
+};
+
+static const struct hpd_sh_mask hpd_shift = {
+ HPD_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct hpd_sh_mask hpd_mask = {
+ HPD_MASK_SH_LIST(_MASK)
+};
+
+#include "../ddc_regs.h"
+
+ /* set field name */
+#define SF_DDC(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+static const struct ddc_registers ddc_data_regs[] = {
+ ddc_data_regs(1),
+ ddc_data_regs(2),
+ ddc_data_regs(3),
+ ddc_data_regs(4),
+ ddc_data_regs(5),
+ ddc_data_regs(6),
+ ddc_vga_data_regs,
+ ddc_i2c_data_regs
+};
+
+static const struct ddc_registers ddc_clk_regs[] = {
+ ddc_clk_regs(1),
+ ddc_clk_regs(2),
+ ddc_clk_regs(3),
+ ddc_clk_regs(4),
+ ddc_clk_regs(5),
+ ddc_clk_regs(6),
+ ddc_vga_clk_regs,
+ ddc_i2c_clk_regs
+};
+
+static const struct ddc_sh_mask ddc_shift = {
+ DDC_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct ddc_sh_mask ddc_mask = {
+ DDC_MASK_SH_LIST(_MASK)
+};
+
+static void define_ddc_registers(
+ struct hw_gpio_pin *pin,
+ uint32_t en)
+{
+ struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
+
+ switch (pin->id) {
+ case GPIO_ID_DDC_DATA:
+ ddc->regs = &ddc_data_regs[en];
+ ddc->base.regs = &ddc_data_regs[en].gpio;
+ break;
+ case GPIO_ID_DDC_CLOCK:
+ ddc->regs = &ddc_clk_regs[en];
+ ddc->base.regs = &ddc_clk_regs[en].gpio;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ return;
+ }
+
+ ddc->shifts = &ddc_shift;
+ ddc->masks = &ddc_mask;
+
+}
+
+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+ struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
+
+ hpd->regs = &hpd_regs[en];
+ hpd->shifts = &hpd_shift;
+ hpd->masks = &hpd_mask;
+ hpd->base.regs = &hpd_regs[en].gpio;
+}
+
+
+/* fucntion table */
+static const struct hw_factory_funcs funcs = {
+ .create_ddc_data = dal_hw_ddc_create,
+ .create_ddc_clock = dal_hw_ddc_create,
+ .create_generic = NULL,
+ .create_hpd = dal_hw_hpd_create,
+ .create_sync = NULL,
+ .create_gsl = NULL,
+ .define_hpd_registers = define_hpd_registers,
+ .define_ddc_registers = define_ddc_registers
+};
+/*
+ * dal_hw_factory_dcn10_init
+ *
+ * @brief
+ * Initialize HW factory function pointers and pin info
+ *
+ * @param
+ * struct hw_factory *factory - [out] struct of function pointers
+ */
+void dal_hw_factory_dcn10_init(struct hw_factory *factory)
+{
+ /*TODO check ASIC CAPs*/
+ factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
+ factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
+ factory->number_of_pins[GPIO_ID_GENERIC] = 7;
+ factory->number_of_pins[GPIO_ID_HPD] = 6;
+ factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
+ factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
+ factory->number_of_pins[GPIO_ID_SYNC] = 2;
+ factory->number_of_pins[GPIO_ID_GSL] = 4;
+
+ factory->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
new file mode 100644
index 0000000..2cc7a58
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_FACTORY_DCN10_H__
+#define __DAL_HW_FACTORY_DCN10_H__
+
+/* Initialize HW factory function pointers and pin info */
+void dal_hw_factory_dcn10_init(struct hw_factory *factory);
+
+#endif /* __DAL_HW_FACTORY_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
new file mode 100644
index 0000000..64a6915
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+/*
+ * Pre-requisites: headers required by header of this unit
+ */
+
+#include "hw_translate_dcn10.h"
+
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_translate.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define REG(reg_name)\
+ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define REGI(reg_name, block, id)\
+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+static bool offset_to_id(
+ uint32_t offset,
+ uint32_t mask,
+ enum gpio_id *id,
+ uint32_t *en)
+{
+ switch (offset) {
+ /* GENERIC */
+ case REG(DC_GPIO_GENERIC_A):
+ *id = GPIO_ID_GENERIC;
+ switch (mask) {
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
+ *en = GPIO_GENERIC_A;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
+ *en = GPIO_GENERIC_B;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
+ *en = GPIO_GENERIC_C;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
+ *en = GPIO_GENERIC_D;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
+ *en = GPIO_GENERIC_E;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
+ *en = GPIO_GENERIC_F;
+ return true;
+ case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
+ *en = GPIO_GENERIC_G;
+ return true;
+ default:
+ ASSERT_CRITICAL(false);
+ return false;
+ }
+ break;
+ /* HPD */
+ case REG(DC_GPIO_HPD_A):
+ *id = GPIO_ID_HPD;
+ switch (mask) {
+ case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
+ *en = GPIO_HPD_1;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
+ *en = GPIO_HPD_2;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
+ *en = GPIO_HPD_3;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
+ *en = GPIO_HPD_4;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
+ *en = GPIO_HPD_5;
+ return true;
+ case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
+ *en = GPIO_HPD_6;
+ return true;
+ default:
+ ASSERT_CRITICAL(false);
+ return false;
+ }
+ break;
+ /* SYNCA */
+ case REG(DC_GPIO_SYNCA_A):
+ *id = GPIO_ID_SYNC;
+ switch (mask) {
+ case DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK:
+ *en = GPIO_SYNC_HSYNC_A;
+ return true;
+ case DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK:
+ *en = GPIO_SYNC_VSYNC_A;
+ return true;
+ default:
+ ASSERT_CRITICAL(false);
+ return false;
+ }
+ break;
+ /* REG(DC_GPIO_GENLK_MASK */
+ case REG(DC_GPIO_GENLK_A):
+ *id = GPIO_ID_GSL;
+ switch (mask) {
+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
+ *en = GPIO_GSL_GENLOCK_CLOCK;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
+ *en = GPIO_GSL_GENLOCK_VSYNC;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
+ *en = GPIO_GSL_SWAPLOCK_A;
+ return true;
+ case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
+ *en = GPIO_GSL_SWAPLOCK_B;
+ return true;
+ default:
+ ASSERT_CRITICAL(false);
+ return false;
+ }
+ break;
+ /* DDC */
+ /* we don't care about the GPIO_ID for DDC
+ * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
+ * directly in the create method */
+ case REG(DC_GPIO_DDC1_A):
+ *en = GPIO_DDC_LINE_DDC1;
+ return true;
+ case REG(DC_GPIO_DDC2_A):
+ *en = GPIO_DDC_LINE_DDC2;
+ return true;
+ case REG(DC_GPIO_DDC3_A):
+ *en = GPIO_DDC_LINE_DDC3;
+ return true;
+ case REG(DC_GPIO_DDC4_A):
+ *en = GPIO_DDC_LINE_DDC4;
+ return true;
+ case REG(DC_GPIO_DDC5_A):
+ *en = GPIO_DDC_LINE_DDC5;
+ return true;
+ case REG(DC_GPIO_DDC6_A):
+ *en = GPIO_DDC_LINE_DDC6;
+ return true;
+ case REG(DC_GPIO_DDCVGA_A):
+ *en = GPIO_DDC_LINE_DDC_VGA;
+ return true;
+ /* GPIO_I2CPAD */
+ case REG(DC_GPIO_I2CPAD_A):
+ *en = GPIO_DDC_LINE_I2C_PAD;
+ return true;
+ /* Not implemented */
+ case REG(DC_GPIO_PWRSEQ_A):
+ case REG(DC_GPIO_PAD_STRENGTH_1):
+ case REG(DC_GPIO_PAD_STRENGTH_2):
+ case REG(DC_GPIO_DEBUG):
+ return false;
+ /* UNEXPECTED */
+ default:
+ ASSERT_CRITICAL(false);
+ return false;
+ }
+}
+
+static bool id_to_offset(
+ enum gpio_id id,
+ uint32_t en,
+ struct gpio_pin_info *info)
+{
+ bool result = true;
+
+ switch (id) {
+ case GPIO_ID_DDC_DATA:
+ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
+ switch (en) {
+ case GPIO_DDC_LINE_DDC1:
+ info->offset = REG(DC_GPIO_DDC1_A);
+ break;
+ case GPIO_DDC_LINE_DDC2:
+ info->offset = REG(DC_GPIO_DDC2_A);
+ break;
+ case GPIO_DDC_LINE_DDC3:
+ info->offset = REG(DC_GPIO_DDC3_A);
+ break;
+ case GPIO_DDC_LINE_DDC4:
+ info->offset = REG(DC_GPIO_DDC4_A);
+ break;
+ case GPIO_DDC_LINE_DDC5:
+ info->offset = REG(DC_GPIO_DDC5_A);
+ break;
+ case GPIO_DDC_LINE_DDC6:
+ info->offset = REG(DC_GPIO_DDC6_A);
+ break;
+ case GPIO_DDC_LINE_DDC_VGA:
+ info->offset = REG(DC_GPIO_DDCVGA_A);
+ break;
+ case GPIO_DDC_LINE_I2C_PAD:
+ info->offset = REG(DC_GPIO_I2CPAD_A);
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_DDC_CLOCK:
+ info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
+ switch (en) {
+ case GPIO_DDC_LINE_DDC1:
+ info->offset = REG(DC_GPIO_DDC1_A);
+ break;
+ case GPIO_DDC_LINE_DDC2:
+ info->offset = REG(DC_GPIO_DDC2_A);
+ break;
+ case GPIO_DDC_LINE_DDC3:
+ info->offset = REG(DC_GPIO_DDC3_A);
+ break;
+ case GPIO_DDC_LINE_DDC4:
+ info->offset = REG(DC_GPIO_DDC4_A);
+ break;
+ case GPIO_DDC_LINE_DDC5:
+ info->offset = REG(DC_GPIO_DDC5_A);
+ break;
+ case GPIO_DDC_LINE_DDC6:
+ info->offset = REG(DC_GPIO_DDC6_A);
+ break;
+ case GPIO_DDC_LINE_DDC_VGA:
+ info->offset = REG(DC_GPIO_DDCVGA_A);
+ break;
+ case GPIO_DDC_LINE_I2C_PAD:
+ info->offset = REG(DC_GPIO_I2CPAD_A);
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_GENERIC:
+ info->offset = REG(DC_GPIO_GENERIC_A);
+ switch (en) {
+ case GPIO_GENERIC_A:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
+ break;
+ case GPIO_GENERIC_B:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
+ break;
+ case GPIO_GENERIC_C:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
+ break;
+ case GPIO_GENERIC_D:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
+ break;
+ case GPIO_GENERIC_E:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
+ break;
+ case GPIO_GENERIC_F:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
+ break;
+ case GPIO_GENERIC_G:
+ info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_HPD:
+ info->offset = REG(DC_GPIO_HPD_A);
+ switch (en) {
+ case GPIO_HPD_1:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
+ break;
+ case GPIO_HPD_2:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
+ break;
+ case GPIO_HPD_3:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
+ break;
+ case GPIO_HPD_4:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
+ break;
+ case GPIO_HPD_5:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
+ break;
+ case GPIO_HPD_6:
+ info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_SYNC:
+ switch (en) {
+ case GPIO_SYNC_HSYNC_A:
+ info->offset = REG(DC_GPIO_SYNCA_A);
+ info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK;
+ break;
+ case GPIO_SYNC_VSYNC_A:
+ info->offset = REG(DC_GPIO_SYNCA_A);
+ info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK;
+ break;
+ case GPIO_SYNC_HSYNC_B:
+ case GPIO_SYNC_VSYNC_B:
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_GSL:
+ switch (en) {
+ case GPIO_GSL_GENLOCK_CLOCK:
+ info->offset = REG(DC_GPIO_GENLK_A);
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK;
+ break;
+ case GPIO_GSL_GENLOCK_VSYNC:
+ info->offset = REG(DC_GPIO_GENLK_A);
+ info->mask =
+ DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK;
+ break;
+ case GPIO_GSL_SWAPLOCK_A:
+ info->offset = REG(DC_GPIO_GENLK_A);
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK;
+ break;
+ case GPIO_GSL_SWAPLOCK_B:
+ info->offset = REG(DC_GPIO_GENLK_A);
+ info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK;
+ break;
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+ break;
+ case GPIO_ID_VIP_PAD:
+ default:
+ ASSERT_CRITICAL(false);
+ result = false;
+ }
+
+ if (result) {
+ info->offset_y = info->offset + 2;
+ info->offset_en = info->offset + 1;
+ info->offset_mask = info->offset - 1;
+
+ info->mask_y = info->mask;
+ info->mask_en = info->mask;
+ info->mask_mask = info->mask;
+ }
+
+ return result;
+}
+
+/* function table */
+static const struct hw_translate_funcs funcs = {
+ .offset_to_id = offset_to_id,
+ .id_to_offset = id_to_offset,
+};
+
+/*
+ * dal_hw_translate_dcn10_init
+ *
+ * @brief
+ * Initialize Hw translate function pointers.
+ *
+ * @param
+ * struct hw_translate *tr - [out] struct of function pointers
+ *
+ */
+void dal_hw_translate_dcn10_init(struct hw_translate *tr)
+{
+ tr->funcs = &funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
new file mode 100644
index 0000000..9edef53
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_HW_TRANSLATE_DCN10_H__
+#define __DAL_HW_TRANSLATE_DCN10_H__
+
+struct hw_translate;
+
+/* Initialize Hw translate function pointers */
+void dal_hw_translate_dcn10_init(struct hw_translate *tr);
+
+#endif /* __DAL_HW_TRANSLATE_DCN10_H__ */
--
2.5.5
_______________________________________________
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^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 113/117] drm/amdgpu/display: Add i2c/aux support for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (103 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 112/117] drm/amdgpu/display: Add gpio " Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 114/117] drm/amdgpu/display: Add irq " Alex Deucher
` (4 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
Implement support for i2c and aux on DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +++++++++++++++++++++
.../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 ++++++
2 files changed, 157 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
new file mode 100644
index 0000000..9f17d2e
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/i2caux_interface.h"
+#include "../i2caux.h"
+#include "../engine.h"
+#include "../i2c_engine.h"
+#include "../i2c_sw_engine.h"
+#include "../i2c_hw_engine.h"
+
+#include "../dce110/aux_engine_dce110.h"
+#include "../dce110/i2c_hw_engine_dce110.h"
+#include "../dce110/i2caux_dce110.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file */
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SR(reg_name)\
+ .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+ mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+ .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+/* macros to expend register list macro defined in HW object header file
+ * end *********************/
+
+#define aux_regs(id)\
+[id] = {\
+ AUX_COMMON_REG_LIST(id), \
+ .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
+}
+
+#define hw_engine_regs(id)\
+{\
+ I2C_HW_ENGINE_COMMON_REG_LIST(id) \
+}
+
+static const struct dce110_aux_registers dcn10_aux_regs[] = {
+ aux_regs(0),
+ aux_regs(1),
+ aux_regs(2),
+ aux_regs(3),
+ aux_regs(4),
+ aux_regs(5),
+};
+
+static const struct dce110_i2c_hw_engine_registers dcn10_hw_engine_regs[] = {
+ hw_engine_regs(1),
+ hw_engine_regs(2),
+ hw_engine_regs(3),
+ hw_engine_regs(4),
+ hw_engine_regs(5),
+ hw_engine_regs(6)
+};
+
+static const struct dce110_i2c_hw_engine_shift i2c_shift = {
+ I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce110_i2c_hw_engine_mask i2c_mask = {
+ I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
+struct i2caux *dal_i2caux_dcn10_create(
+ struct dc_context *ctx)
+{
+ struct i2caux_dce110 *i2caux_dce110 =
+ dm_alloc(sizeof(struct i2caux_dce110));
+
+ if (!i2caux_dce110) {
+ ASSERT_CRITICAL(false);
+ return NULL;
+ }
+
+ if (dal_i2caux_dce110_construct(
+ i2caux_dce110,
+ ctx,
+ dcn10_aux_regs,
+ dcn10_hw_engine_regs,
+ &i2c_shift,
+ &i2c_mask))
+ return &i2caux_dce110->base;
+
+ ASSERT_CRITICAL(false);
+
+ dm_free(i2caux_dce110);
+
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
new file mode 100644
index 0000000..aeb4a86
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_I2C_AUX_DCN10_H__
+#define __DAL_I2C_AUX_DCN10_H__
+
+struct i2caux *dal_i2caux_dcn10_create(
+ struct dc_context *ctx);
+
+#endif /* __DAL_I2C_AUX_DCN10_H__ */
--
2.5.5
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 114/117] drm/amdgpu/display: Add irq support for DCN
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (104 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 113/117] drm/amdgpu/display: Add i2c/aux " Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 115/117] drm/amdgpu/display: Enable DCN in DC Alex Deucher
` (3 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
DCN code for display interrupts.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +++++++++++++++++++++
.../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 ++
2 files changed, 395 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
new file mode 100644
index 0000000..7577e29
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "../dce110/irq_service_dce110.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#include "irq_service_dcn10.h"
+
+#include "ivsrcid/irqsrcs_dcn_1_0.h"
+
+enum dc_irq_source to_dal_irq_source_dcn10(
+ struct irq_service *irq_service,
+ uint32_t src_id,
+ uint32_t ext_id)
+{
+ switch (src_id) {
+ case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK1;
+ case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK2;
+ case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK3;
+ case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK4;
+ case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK5;
+ case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK6;
+ case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP1;
+ case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP2;
+ case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP3;
+ case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP4;
+ case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP5;
+ case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP6;
+
+ case DCN_1_0__SRCID__DC_HPD1_INT:
+ /* generic src_id for all HPD and HPDRX interrupts */
+ switch (ext_id) {
+ case DCN_1_0__CTXID__DC_HPD1_INT:
+ return DC_IRQ_SOURCE_HPD1;
+ case DCN_1_0__CTXID__DC_HPD2_INT:
+ return DC_IRQ_SOURCE_HPD2;
+ case DCN_1_0__CTXID__DC_HPD3_INT:
+ return DC_IRQ_SOURCE_HPD3;
+ case DCN_1_0__CTXID__DC_HPD4_INT:
+ return DC_IRQ_SOURCE_HPD4;
+ case DCN_1_0__CTXID__DC_HPD5_INT:
+ return DC_IRQ_SOURCE_HPD5;
+ case DCN_1_0__CTXID__DC_HPD6_INT:
+ return DC_IRQ_SOURCE_HPD6;
+ case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+ return DC_IRQ_SOURCE_HPD1RX;
+ case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+ return DC_IRQ_SOURCE_HPD2RX;
+ case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+ return DC_IRQ_SOURCE_HPD3RX;
+ case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+ return DC_IRQ_SOURCE_HPD4RX;
+ case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+ return DC_IRQ_SOURCE_HPD5RX;
+ case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+ return DC_IRQ_SOURCE_HPD6RX;
+ default:
+ return DC_IRQ_SOURCE_INVALID;
+ }
+ break;
+
+ default:
+ return DC_IRQ_SOURCE_INVALID;
+ }
+}
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ HPD0_DC_HPD_INT_STATUS,
+ DC_HPD_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ HPD0_DC_HPD_INT_CONTROL,
+ DC_HPD_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+ BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+ .enable_reg = SRI(reg1, block, reg_num),\
+ .enable_mask = \
+ block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+ .enable_value = {\
+ block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+ ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+ },\
+ .ack_reg = SRI(reg2, block, reg_num),\
+ .ack_mask = \
+ block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+ .ack_value = \
+ block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+ IRQ_REG_ENTRY(HPD, reg_num,\
+ DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+ DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+ .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+ .funcs = &hpd_irq_info_funcs\
+ }
+
+#define hpd_rx_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+ IRQ_REG_ENTRY(HPD, reg_num,\
+ DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+ DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+ .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+ .funcs = &hpd_rx_irq_info_funcs\
+ }
+#define pflip_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+ IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+ DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+ DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+ .funcs = &pflip_irq_info_funcs\
+ }
+
+#define vupdate_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+ IRQ_REG_ENTRY(OTG, reg_num,\
+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
+ OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
+ .funcs = &vblank_irq_info_funcs\
+ }
+
+#define vblank_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+ IRQ_REG_ENTRY(OTG, reg_num,\
+ OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+ OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+ .funcs = &vblank_irq_info_funcs\
+ }
+
+#define dummy_irq_entry() \
+ {\
+ .funcs = &dummy_irq_info_funcs\
+ }
+
+#define i2c_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+ [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+ .set = dal_irq_service_dummy_set,
+ .ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
+ [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+ hpd_int_entry(0),
+ hpd_int_entry(1),
+ hpd_int_entry(2),
+ hpd_int_entry(3),
+ hpd_int_entry(4),
+ hpd_int_entry(5),
+ hpd_rx_int_entry(0),
+ hpd_rx_int_entry(1),
+ hpd_rx_int_entry(2),
+ hpd_rx_int_entry(3),
+ hpd_rx_int_entry(4),
+ hpd_rx_int_entry(5),
+ i2c_int_entry(1),
+ i2c_int_entry(2),
+ i2c_int_entry(3),
+ i2c_int_entry(4),
+ i2c_int_entry(5),
+ i2c_int_entry(6),
+ dp_sink_int_entry(1),
+ dp_sink_int_entry(2),
+ dp_sink_int_entry(3),
+ dp_sink_int_entry(4),
+ dp_sink_int_entry(5),
+ dp_sink_int_entry(6),
+ [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+ pflip_int_entry(0),
+ pflip_int_entry(1),
+ pflip_int_entry(2),
+ pflip_int_entry(3),
+ [DC_IRQ_SOURCE_PFLIP4] = dummy_irq_entry(),
+ [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
+ [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+ gpio_pad_int_entry(0),
+ gpio_pad_int_entry(1),
+ gpio_pad_int_entry(2),
+ gpio_pad_int_entry(3),
+ gpio_pad_int_entry(4),
+ gpio_pad_int_entry(5),
+ gpio_pad_int_entry(6),
+ gpio_pad_int_entry(7),
+ gpio_pad_int_entry(8),
+ gpio_pad_int_entry(9),
+ gpio_pad_int_entry(10),
+ gpio_pad_int_entry(11),
+ gpio_pad_int_entry(12),
+ gpio_pad_int_entry(13),
+ gpio_pad_int_entry(14),
+ gpio_pad_int_entry(15),
+ gpio_pad_int_entry(16),
+ gpio_pad_int_entry(17),
+ gpio_pad_int_entry(18),
+ gpio_pad_int_entry(19),
+ gpio_pad_int_entry(20),
+ gpio_pad_int_entry(21),
+ gpio_pad_int_entry(22),
+ gpio_pad_int_entry(23),
+ gpio_pad_int_entry(24),
+ gpio_pad_int_entry(25),
+ gpio_pad_int_entry(26),
+ gpio_pad_int_entry(27),
+ gpio_pad_int_entry(28),
+ gpio_pad_int_entry(29),
+ gpio_pad_int_entry(30),
+ dc_underflow_int_entry(1),
+ dc_underflow_int_entry(2),
+ dc_underflow_int_entry(3),
+ dc_underflow_int_entry(4),
+ dc_underflow_int_entry(5),
+ dc_underflow_int_entry(6),
+ [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+ [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+ vupdate_int_entry(0),
+ vupdate_int_entry(1),
+ vupdate_int_entry(2),
+ vupdate_int_entry(3),
+ vupdate_int_entry(4),
+ vupdate_int_entry(5),
+ vblank_int_entry(0),
+ vblank_int_entry(1),
+ vblank_int_entry(2),
+ vblank_int_entry(3),
+ vblank_int_entry(4),
+ vblank_int_entry(5),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn10 = {
+ .to_dal_irq_source = to_dal_irq_source_dcn10
+};
+
+static bool construct(
+ struct irq_service *irq_service,
+ struct irq_service_init_data *init_data)
+{
+ if (!dal_irq_service_construct(irq_service, init_data))
+ return false;
+
+ irq_service->info = irq_source_info_dcn10;
+ irq_service->funcs = &irq_service_funcs_dcn10;
+
+ return true;
+}
+
+struct irq_service *dal_irq_service_dcn10_create(
+ struct irq_service_init_data *init_data)
+{
+ struct irq_service *irq_service = dm_alloc(sizeof(*irq_service));
+
+ if (!irq_service)
+ return NULL;
+
+ if (construct(irq_service, init_data))
+ return irq_service;
+
+ dm_free(irq_service);
+ return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
new file mode 100644
index 0000000..fd2ca4d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCN10_H__
+#define __DAL_IRQ_SERVICE_DCN10_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn10_create(
+ struct irq_service_init_data *init_data);
+
+#endif
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 115/117] drm/amdgpu/display: Enable DCN in DC
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (105 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 114/117] drm/amdgpu/display: Add irq " Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 116/117] drm/amdgpu: enable dcn1.0 dc support on raven Alex Deucher
` (2 subsequent siblings)
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
From: Harry Wentland <harry.wentland@amd.com>
Enable DCN in DC.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/Kconfig | 7 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 ++++++++++++-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
drivers/gpu/drm/amd/display/dc/Makefile | 5 +
.../amd/display/dc/bios/command_table_helper2.c | 5 +
drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 ++
drivers/gpu/drm/amd/display/dc/dc.h | 18 ++
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 ++++
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +++
.../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 ++
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 ++
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 ++
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 ++
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +++++++++++++++++++++
.../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 ++++++
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +++
drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 ++
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 ++++
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +++++++++
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
.../drm/amd/display/dc/inc/hw/timing_generator.h | 16 ++
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
39 files changed, 1302 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index f652cc3..2b8d77c 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -9,6 +9,13 @@ config DRM_AMD_DC
Will be deprecated when the DC component is upstream.
+config DRM_AMD_DC_DCN1_0
+ bool "DCN 1.0 Raven family"
+ depends on DRM_AMD_DC
+ help
+ Choose this option if you want to have
+ RV family for display engine
+
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bd4bc1c..9813688 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -55,6 +55,16 @@
#include "modules/inc/mod_freesync.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "ivsrcid/irqsrcs_dcn_1_0.h"
+
+#include "raven1/DCN/dcn_1_0_offset.h"
+#include "raven1/DCN/dcn_1_0_sh_mask.h"
+#include "vega10/soc15ip.h"
+
+#include "soc15_common.h"
+#endif
+
static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = {
DRM_PLANE_TYPE_PRIMARY,
DRM_PLANE_TYPE_PRIMARY,
@@ -936,7 +946,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
int i;
unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
- if (adev->asic_type == CHIP_VEGA10)
+ if (adev->asic_type == CHIP_VEGA10 ||
+ adev->asic_type == CHIP_RAVEN)
client_id = AMDGPU_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -1009,6 +1020,92 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
return 0;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+/* Register IRQ sources and initialize IRQ callbacks */
+static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
+{
+ struct dc *dc = adev->dm.dc;
+ struct common_irq_params *c_irq_params;
+ struct dc_interrupt_params int_params = {0};
+ int r;
+ int i;
+
+ int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
+ int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
+
+ /* Actions of amdgpu_irq_add_id():
+ * 1. Register a set() function with base driver.
+ * Base driver will call set() function to enable/disable an
+ * interrupt in DC hardware.
+ * 2. Register amdgpu_dm_irq_handler().
+ * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
+ * coming from DC hardware.
+ * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
+ * for acknowledging and handling.
+ * */
+
+ /* Use VSTARTUP interrupt */
+ for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
+ i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
+ i++) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
+
+ if (r) {
+ DRM_ERROR("Failed to add crtc irq id!\n");
+ return r;
+ }
+
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, i, 0);
+
+ c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
+
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, &int_params,
+ dm_crtc_high_irq, c_irq_params);
+ }
+
+ /* Use GRPH_PFLIP interrupt */
+ for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
+ i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
+ i++) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
+ if (r) {
+ DRM_ERROR("Failed to add page flip irq id!\n");
+ return r;
+ }
+
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, i, 0);
+
+ c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
+
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
+
+ amdgpu_dm_irq_register_interrupt(adev, &int_params,
+ dm_pflip_high_irq, c_irq_params);
+
+ }
+
+ /* HPD */
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
+ &adev->hpd_irq);
+ if (r) {
+ DRM_ERROR("Failed to add hpd irq id!\n");
+ return r;
+ }
+
+ register_hpd_handlers(adev);
+
+ return 0;
+}
+#endif
+
static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
{
int r;
@@ -1178,6 +1275,14 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail_free_encoder;
}
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case CHIP_RAVEN:
+ if (dcn10_register_irq_handlers(dm->adev)) {
+ DRM_ERROR("DM: Failed to initialize IRQ\n");
+ goto fail_free_encoder;
+ }
+ break;
+#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
goto fail_free_encoder;
@@ -1445,6 +1550,32 @@ void dce_v12_0_set_vga_render_state(struct amdgpu_device *adev,
}
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+void dcn_v1_0_set_vga_render_state(struct amdgpu_device *adev,
+ bool render)
+{
+ u32 tmp;
+
+ /* Lockout access through VGA aperture*/
+ tmp = RREG32(SOC15_REG_OFFSET(DCE, 0, mmVGA_HDP_CONTROL));
+ if (render)
+ tmp = tmp & 0xFFFFFFEF;
+ else
+ tmp |= 0x10;
+
+ WREG32(SOC15_REG_OFFSET(DCE, 0, mmVGA_HDP_CONTROL), tmp);
+
+ /* disable VGA render */
+ tmp = RREG32(SOC15_REG_OFFSET(DCE, 0, mmVGA_RENDER_CONTROL));
+ if (render)
+ tmp |= 0x10000;
+ else
+ tmp = tmp & 0xFFFCFFFF;
+
+ WREG32(SOC15_REG_OFFSET(DCE, 0, mmVGA_HDP_CONTROL), tmp);
+}
+#endif
+
#ifdef CONFIG_DRM_AMDGPU_CIK
static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = {
.set_vga_render_state = dce_v8_0_set_vga_render_state,
@@ -1538,6 +1669,30 @@ static const struct amdgpu_display_funcs dm_dce_v12_0_display_funcs = {
};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+static const struct amdgpu_display_funcs dm_dcn_v1_0_display_funcs = {
+ .set_vga_render_state = dcn_v1_0_set_vga_render_state,
+ .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
+ .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
+ .vblank_wait = NULL,
+ .backlight_set_level =
+ dm_set_backlight_level,/* called unconditionally */
+ .backlight_get_level =
+ dm_get_backlight_level,/* called unconditionally */
+ .hpd_sense = NULL,/* called unconditionally */
+ .hpd_set_polarity = NULL, /* called unconditionally */
+ .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
+ .page_flip = dm_page_flip, /* called unconditionally */
+ .page_flip_get_scanoutpos =
+ dm_crtc_get_scanoutpos,/* called unconditionally */
+ .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
+ .add_connector = NULL, /* VBIOS parsing. DAL does it. */
+ .stop_mc_access = dce_v12_0_stop_mc_access, /* called unconditionally */
+ .resume_mc_access = dce_v12_0_resume_mc_access, /* called unconditionally */
+ .notify_freesync = amdgpu_notify_freesync,
+
+};
+#endif
#if defined(CONFIG_DEBUG_KERNEL_DC)
@@ -1639,6 +1794,16 @@ static int dm_early_init(void *handle)
if (adev->mode_info.funcs == NULL)
adev->mode_info.funcs = &dm_dce_v12_0_display_funcs;
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case CHIP_RAVEN:
+ adev->mode_info.num_crtc = 4;
+ adev->mode_info.num_hpd = 4;
+ adev->mode_info.num_dig = 4;
+ adev->mode_info.plane_type = dm_surfaces_type_default;
+ if (adev->mode_info.funcs == NULL)
+ adev->mode_info.funcs = &dm_dcn_v1_0_display_funcs;
+ break;
+#endif
default:
DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 473f991..332595b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -563,7 +563,8 @@ static void fill_plane_attributes_from_fb(
surface->tiling_info.gfx8.pipe_config =
AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
- if (adev->asic_type == CHIP_VEGA10) {
+ if (adev->asic_type == CHIP_VEGA10 ||
+ adev->asic_type == CHIP_RAVEN) {
/* Fill GFX9 params */
surface->tiling_info.gfx9.num_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes;
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 1a79762..4f83e30 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -4,7 +4,12 @@
DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
+ifdef CONFIG_DRM_AMD_DC_DCN1_0
+DC_LIBS += dcn10 dml
+endif
+
DC_LIBS += dce120
+
DC_LIBS += dce112
DC_LIBS += dce110
DC_LIBS += dce100
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 1cc3df1..84b1f51 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -53,6 +53,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCE_VERSION_11_2:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+ *h = dal_cmd_tbl_helper_dce112_get_table2();
+ return true;
+#endif
case DCE_VERSION_12_0:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 63a0edb..a095472 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -3,8 +3,16 @@
# It calculates Bandwidth and Watermarks values for HW programming
#
+CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4
+
BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
+ifdef CONFIG_DRM_AMD_DC_DCN1_0
+BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
+endif
+
AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
AMD_DISPLAY_FILES += $(AMD_DAL_BW_CALCS)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 2de86f8..ae8b221 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -39,6 +39,9 @@
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn10/dcn10_resource.h"
+#endif
#include "dce120/dce120_resource.h"
enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
@@ -69,6 +72,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
case FAMILY_AI:
dc_version = DCE_VERSION_12_0;
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case FAMILY_RV:
+ dc_version = DCN_VERSION_1_0;
+ break;
+#endif
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
@@ -105,6 +113,13 @@ struct resource_pool *dc_create_resource_pool(
res_pool = dce120_create_resource_pool(
num_virtual_links, dc);
break;
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+ res_pool = dcn10_create_resource_pool(
+ num_virtual_links, dc);
+ break;
+#endif
default:
break;
}
@@ -1188,6 +1203,10 @@ static int acquire_first_free_pipe(
pipe_ctx->dis_clk = pool->display_clock;
pipe_ctx->pipe_idx = i;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ pipe_ctx->mpc_idx = -1;
+#endif
+
pipe_ctx->stream = stream;
return i;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 87675f0..d74bbdc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -94,7 +94,13 @@ struct dc_surface;
struct validate_context;
struct dc_cap_funcs {
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ bool (*get_dcc_compression_cap)(const struct dc *dc,
+ const struct dc_dcc_surface_param *input,
+ struct dc_surface_dcc_cap *output);
+#else
int i;
+#endif
};
struct dc_stream_funcs {
@@ -164,6 +170,18 @@ struct dc_debug {
bool disable_stutter;
bool disable_dcc;
bool disable_dfs_bypass;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ bool disable_dpp_power_gate;
+ bool disable_hubp_power_gate;
+ bool disable_pplib_wm_range;
+ bool use_dml_wm;
+ bool use_max_voltage;
+ int sr_exit_time_ns;
+ int sr_enter_plus_exit_time_ns;
+ int urgent_latency_ns;
+ int percent_of_ideal_drambw;
+ int dram_clock_change_latency_ns;
+#endif
bool disable_pplib_clock_request;
bool disable_clock_gate;
bool disable_dmcu;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index 56087b3..e0abd2d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -54,6 +54,22 @@
SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
SR(BIOS_SCRATCH_2)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define ABM_DCN10_REG_LIST(id)\
+ ABM_COMMON_REG_LIST_DCE_BASE(), \
+ SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+ SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+ SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+ SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+ SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+ SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+ SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+ SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+ SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+ SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+ NBIO_SR(BIOS_SCRATCH_2)
+#endif
+
#define ABM_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -105,6 +121,39 @@
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_VMAX_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
+ ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
+ ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
+ BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
+ BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
+ ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
+ BL1_PWM_USER_LEVEL, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+ ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
+ ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
+ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
+#endif
+
#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index bd4524e..142b3a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -586,6 +586,9 @@ static uint32_t dce110_get_pix_clk_dividers(
break;
case DCE_VERSION_11_2:
case DCE_VERSION_12_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+#endif
dce112_get_pix_clk_dividers_helper(clk_src,
pll_settings, pix_clk_params);
break;
@@ -815,6 +818,31 @@ static bool dce110_program_pix_clk(
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
struct bp_pixel_clock_parameters bp_pc_params = {0};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
+ unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+ unsigned dp_dto_ref_kHz = 600000;
+ /* DPREF clock from FPGA TODO: Does FPGA have this value? */
+ unsigned clock_kHz = pll_settings->actual_pix_clk;
+
+ /* For faster simulation, if mode pixe clock less than 290MHz,
+ * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock
+ * is greater than 500Mhz, need real pixel clock
+ * clock_kHz = 290000;
+ */
+ /* TODO: un-hardcode when we can set display clock properly*/
+ /*clock_kHz = pix_clk_params->requested_pix_clk;*/
+ clock_kHz = 290000;
+
+ /* Set DTO values: phase = target clock, modulo = reference clock */
+ REG_WRITE(PHASE[inst], clock_kHz);
+ REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
+
+ /* Enable DTO */
+ REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+ return true;
+ }
+#endif
/* First disable SS
* ATOMBIOS will enable by default SS on PLL for DP,
* do not disable it here
@@ -870,6 +898,9 @@ static bool dce110_program_pix_clk(
break;
case DCE_VERSION_11_2:
case DCE_VERSION_12_0:
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+#endif
if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 28984c79..e8bc98b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -55,6 +55,27 @@
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
+ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+ SRII(PHASE, DP_DTO, 0),\
+ SRII(PHASE, DP_DTO, 1),\
+ SRII(PHASE, DP_DTO, 2),\
+ SRII(PHASE, DP_DTO, 3),\
+ SRII(MODULO, DP_DTO, 0),\
+ SRII(MODULO, DP_DTO, 1),\
+ SRII(MODULO, DP_DTO, 2),\
+ SRII(MODULO, DP_DTO, 3),\
+ SRII(PIXEL_RATE_CNTL, OTG, 0), \
+ SRII(PIXEL_RATE_CNTL, OTG, 1), \
+ SRII(PIXEL_RATE_CNTL, OTG, 2), \
+ SRII(PIXEL_RATE_CNTL, OTG, 3)
+
+#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
+ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
+ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
+#endif
+
#define CS_REG_FIELD_LIST(type) \
type PLL_REF_DIV_SRC; \
type DCCG_DEEP_COLOR_CNTL1; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 81cb138..6e56d83 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -29,6 +29,10 @@
#include "fixed32_32.h"
#include "bios_parser_interface.h"
#include "dc.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn_calcs.h"
+#include "core_dc.h"
+#endif
#define TO_DCE_CLOCKS(clocks)\
container_of(clocks, struct dce_disp_clk, base)
@@ -400,6 +404,10 @@ static void dce112_set_clock(
bp->funcs->set_dce_clock(bp, &dce_clk_params);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ dce_psr_wait_loop(clk_dce, requested_clk_khz);
+#endif
+
}
static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
@@ -596,6 +604,13 @@ static bool dce_apply_clock_voltage_request(
}
}
if (send_request) {
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);
+ /*use dcfclk request voltage*/
+ clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
+ clock_voltage_req.clocks_in_khz =
+ dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value);
+#endif
dm_pp_apply_clock_for_voltage_request(
clk->ctx, &clock_voltage_req);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 29ff470..103e905 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -45,6 +45,15 @@
CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define CLK_DCN10_REG_LIST()\
+ SR(DPREFCLK_CNTL), \
+ SR(DENTIST_DISPCLK_CNTL), \
+ SR(MASTER_COMM_DATA_REG1), \
+ SR(MASTER_COMM_CMD_REG), \
+ SR(MASTER_COMM_CNTL_REG)
+#endif
+
#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index da7f86b..c58328c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -252,12 +252,234 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu,
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
+ unsigned int start_offset,
+ const char *src,
+ unsigned int bytes)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+ unsigned int count = 0;
+
+ REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1);
+
+ /* Enable write access to IRAM */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 1,
+ IRAM_WR_ADDR_AUTO_INC, 1);
+
+ REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
+
+ REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
+
+ for (count = 0; count < bytes; count++)
+ REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
+
+ /* Disable write access to IRAM to allow dynamic sleep state */
+ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
+ IRAM_HOST_ACCESS_EN, 0,
+ IRAM_WR_ADDR_AUTO_INC, 0);
+
+ return true;
+}
+
+static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+
+ uint32_t psrStateOffset = 0xf0;
+
+ /* Enable write access to IRAM */
+ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
+
+ REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
+
+ /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
+ REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset);
+
+ /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
+ *psr_state = REG_READ(DMCU_IRAM_RD_DATA);
+
+ /* Disable write access to IRAM after finished using IRAM
+ * in order to allow dynamic sleep state
+ */
+ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
+}
+
+static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+ unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
+ unsigned int dmcu_wait_reg_ready_interval = 100;
+
+ unsigned int retryCount;
+ uint32_t psr_state = 0;
+
+ /* waitDMCUReadyForCmd */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+ dmcu_wait_reg_ready_interval,
+ dmcu_max_retry_on_wait_reg_ready);
+
+ /* setDMCUParam_Cmd */
+ if (enable)
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+ PSR_ENABLE);
+ else
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+ PSR_EXIT);
+
+ /* notifyDMCUMsg */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+
+ /* Below loops 1000 x 500us = 500 ms.
+ * Exit PSR may need to wait 1-2 frames to power up. Timeout after at
+ * least a few frames. Should never hit the max retry assert below.
+ */
+ for (retryCount = 0; retryCount <= 1000; retryCount++) {
+ dcn10_get_dmcu_psr_state(dmcu, &psr_state);
+ if (enable) {
+ if (psr_state != 0)
+ break;
+ } else {
+ if (psr_state == 0)
+ break;
+ }
+ dm_delay_in_microseconds(dmcu->ctx, 500);
+ }
+
+ /* assert if max retry hit */
+ ASSERT(retryCount <= 1000);
+}
+
+static void dcn10_dmcu_setup_psr(struct dmcu *dmcu,
+ struct core_link *link,
+ struct psr_context *psr_context)
+{
+ struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+
+ unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
+ unsigned int dmcu_wait_reg_ready_interval = 100;
+
+ union dce_dmcu_psr_config_data_reg1 masterCmdData1;
+ union dce_dmcu_psr_config_data_reg2 masterCmdData2;
+ union dce_dmcu_psr_config_data_reg3 masterCmdData3;
+
+ link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
+ psr_context->psrExitLinkTrainingRequired);
+
+ /* Enable static screen interrupts for PSR supported display */
+ /* Disable the interrupt coming from other displays. */
+ REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN1_INT_TO_UC_EN, 0,
+ STATIC_SCREEN2_INT_TO_UC_EN, 0,
+ STATIC_SCREEN3_INT_TO_UC_EN, 0,
+ STATIC_SCREEN4_INT_TO_UC_EN, 0);
+
+ switch (psr_context->controllerId) {
+ /* Driver uses case 1 for unconfigured */
+ case 1:
+ REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN1_INT_TO_UC_EN, 1);
+ break;
+ case 2:
+ REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN2_INT_TO_UC_EN, 1);
+ break;
+ case 3:
+ REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN3_INT_TO_UC_EN, 1);
+ break;
+ case 4:
+ REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN4_INT_TO_UC_EN, 1);
+ break;
+ case 5:
+ /* CZ/NL only has 4 CRTC!!
+ * really valid.
+ * There is no interrupt enable mask for these instances.
+ */
+ break;
+ case 6:
+ /* CZ/NL only has 4 CRTC!!
+ * These are here because they are defined in HW regspec,
+ * but not really valid. There is no interrupt enable mask
+ * for these instances.
+ */
+ break;
+ default:
+ REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
+ STATIC_SCREEN1_INT_TO_UC_EN, 1);
+ break;
+ }
+
+ link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
+ psr_context->sdpTransmitLineNumDeadline);
+
+ if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)
+ REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
+
+ /* waitDMCUReadyForCmd */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
+ dmcu_wait_reg_ready_interval,
+ dmcu_max_retry_on_wait_reg_ready);
+
+ /* setDMCUParam_PSRHostConfigData */
+ masterCmdData1.u32All = 0;
+ masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
+ masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
+ masterCmdData1.bits.rfb_update_auto_en =
+ psr_context->rfb_update_auto_en;
+ masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
+ masterCmdData1.bits.dcp_sel = psr_context->controllerId;
+ masterCmdData1.bits.phy_type = psr_context->phyType;
+ masterCmdData1.bits.frame_cap_ind =
+ psr_context->psrFrameCaptureIndicationReq;
+ masterCmdData1.bits.aux_chan = psr_context->channel;
+ masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
+ dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
+ masterCmdData1.u32All);
+
+ masterCmdData2.u32All = 0;
+ masterCmdData2.bits.dig_fe = psr_context->engineId;
+ masterCmdData2.bits.dig_be = psr_context->transmitterId;
+ masterCmdData2.bits.skip_wait_for_pll_lock =
+ psr_context->skipPsrWaitForPllLock;
+ masterCmdData2.bits.frame_delay = psr_context->frame_delay;
+ masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
+ masterCmdData2.bits.num_of_controllers =
+ psr_context->numberOfControllers;
+ dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
+ masterCmdData2.u32All);
+
+ masterCmdData3.u32All = 0;
+ masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
+ dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
+ masterCmdData3.u32All);
+
+ /* setDMCUParam_Cmd */
+ REG_UPDATE(MASTER_COMM_CMD_REG,
+ MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
+
+ /* notifyDMCUMsg */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+}
+
+#endif
+
static const struct dmcu_funcs dce_funcs = {
.load_iram = dce_dmcu_load_iram,
.set_psr_enable = dce_dmcu_set_psr_enable,
.setup_psr = dce_dmcu_setup_psr,
};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+static const struct dmcu_funcs dcn10_funcs = {
+ .load_iram = dcn10_dmcu_load_iram,
+ .set_psr_enable = dcn10_dmcu_set_psr_enable,
+ .setup_psr = dcn10_dmcu_setup_psr,
+};
+#endif
+
static void dce_dmcu_construct(
struct dce_dmcu *dmcu_dce,
struct dc_context *ctx,
@@ -296,6 +518,29 @@ struct dmcu *dce_dmcu_create(
return &dmcu_dce->base;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+struct dmcu *dcn10_dmcu_create(
+ struct dc_context *ctx,
+ const struct dce_dmcu_registers *regs,
+ const struct dce_dmcu_shift *dmcu_shift,
+ const struct dce_dmcu_mask *dmcu_mask)
+{
+ struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce));
+
+ if (dmcu_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_dmcu_construct(
+ dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
+
+ dmcu_dce->base.funcs = &dcn10_funcs;
+
+ return &dmcu_dce->base;
+}
+#endif
+
void dce_dmcu_destroy(struct dmcu **dmcu)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 7dc2538..584682b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -48,6 +48,12 @@
DMCU_COMMON_REG_LIST_DCE_BASE(), \
SR(DCI_MEM_PWR_STATUS)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define DMCU_DCN10_REG_LIST()\
+ DMCU_COMMON_REG_LIST_DCE_BASE(), \
+ SR(DMU_MEM_PWR_CNTL)
+#endif
+
#define DMCU_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -76,6 +82,13 @@
DMCU_SF(DCI_MEM_PWR_STATUS, \
DMCU_IRAM_MEM_PWR_STATE, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
+ DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+ DMCU_SF(DMU_MEM_PWR_CNTL, \
+ DMCU_IRAM_MEM_PWR_STATE, mask_sh)
+#endif
+
#define DMCU_REG_FIELD_LIST(type) \
type DMCU_IRAM_MEM_PWR_STATE; \
type IRAM_HOST_ACCESS_EN; \
@@ -190,6 +203,14 @@ struct dmcu *dce_dmcu_create(
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+struct dmcu *dcn10_dmcu_create(
+ struct dc_context *ctx,
+ const struct dce_dmcu_registers *regs,
+ const struct dce_dmcu_shift *dmcu_shift,
+ const struct dce_dmcu_mask *dmcu_mask);
+#endif
+
void dce_dmcu_destroy(struct dmcu **dmcu);
#endif /* _DCE_ABM_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index c665851..dd13f47 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -121,6 +121,12 @@
HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
HWSEQ_PHYPLL_REG_LIST(CRTC)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define HWSEQ_DCN1_REG_LIST()\
+ HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
+ HWSEQ_PHYPLL_REG_LIST(OTG)
+#endif
+
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
uint32_t DCFEV_CLOCK_CONTROL;
@@ -129,6 +135,9 @@ struct dce_hwseq_registers {
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /* DCE + DCN */
+#endif
uint32_t CRTC_H_BLANK_START_END[6];
uint32_t PIXEL_RATE_CNTL[6];
uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
@@ -192,6 +201,12 @@ struct dce_hwseq_registers {
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
+ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_)
+#endif
+
#define HWSEQ_REG_FIED_LIST(type) \
type DCFE_CLOCK_ENABLE; \
type DCFEV_CLOCK_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 4e0b5d9..8b04996 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -78,6 +78,10 @@
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SR(DCI_MEM_PWR_STATUS)
+#define LE_DCE80_REG_LIST(id)\
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+ LE_COMMON_REG_LIST_BASE(id)
+
#define LE_DCE100_REG_LIST(id)\
LE_COMMON_REG_LIST_BASE(id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
@@ -97,9 +101,15 @@
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
SR(DCI_MEM_PWR_STATUS)
-#define LE_DCE80_REG_LIST(id)\
- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
- LE_COMMON_REG_LIST_BASE(id)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ #define LE_DCN10_REG_LIST(id)\
+ LE_COMMON_REG_LIST_BASE(id), \
+ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
+ SR(DMU_MEM_PWR_CNTL)
+#endif
+
struct dce110_link_enc_aux_registers {
uint32_t AUX_CONTROL;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 9713def..a065e4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -147,6 +147,46 @@ static void dce110_update_generic_info_packet(
AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2));
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (REG(AFMT_VBI_PACKET_CONTROL1)) {
+ switch (packet_index) {
+ case 0:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC0_FRAME_UPDATE, 1);
+ break;
+ case 1:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC1_FRAME_UPDATE, 1);
+ break;
+ case 2:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC2_FRAME_UPDATE, 1);
+ break;
+ case 3:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC3_FRAME_UPDATE, 1);
+ break;
+ case 4:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC4_FRAME_UPDATE, 1);
+ break;
+ case 5:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC5_FRAME_UPDATE, 1);
+ break;
+ case 6:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC6_FRAME_UPDATE, 1);
+ break;
+ case 7:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC7_FRAME_UPDATE, 1);
+ break;
+ default:
+ break;
+ }
+ }
+#endif
}
static void dce110_update_hdmi_info_packet(
@@ -202,6 +242,36 @@ static void dce110_update_hdmi_info_packet(
HDMI_GENERIC1_SEND, send,
HDMI_GENERIC1_LINE, line);
break;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case 4:
+ if (REG(HDMI_GENERIC_PACKET_CONTROL2))
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 5:
+ if (REG(HDMI_GENERIC_PACKET_CONTROL2))
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+ case 6:
+ if (REG(HDMI_GENERIC_PACKET_CONTROL3))
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 7:
+ if (REG(HDMI_GENERIC_PACKET_CONTROL3))
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+#endif
default:
/* invalid HW packet index */
dm_logger_write(
@@ -218,9 +288,24 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space)
{
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ uint32_t h_active_start;
+ uint32_t v_active_start;
+ uint32_t misc0 = 0;
+ uint32_t misc1 = 0;
+ uint32_t h_blank;
+ uint32_t h_back_porch;
+ uint8_t synchronous_clock = 0; /* asynchronous mode */
+ uint8_t colorimetry_bpc;
+#endif
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (REG(DP_DB_CNTL))
+ REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
+#endif
+
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
@@ -249,6 +334,10 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (enc110->se_mask->DP_VID_N_MUL)
+ REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
+#endif
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
@@ -256,6 +345,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (REG(DP_MSA_MISC))
+ misc1 = REG_READ(DP_MSA_MISC);
+#endif
+
/* set color depth */
switch (crtc_timing->display_color_depth) {
@@ -289,6 +383,128 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
DP_DYN_RANGE, 0,
DP_YCBCR_RANGE, 0);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ colorimetry_bpc = 0;
+ break;
+ case COLOR_DEPTH_888:
+ colorimetry_bpc = 1;
+ break;
+ case COLOR_DEPTH_101010:
+ colorimetry_bpc = 2;
+ break;
+ case COLOR_DEPTH_121212:
+ colorimetry_bpc = 3;
+ break;
+ default:
+ colorimetry_bpc = 0;
+ break;
+ }
+
+ misc0 = misc0 | synchronous_clock;
+ misc0 = colorimetry_bpc << 5;
+
+ if (REG(DP_MSA_TIMING_PARAM1)) {
+ switch (output_color_space) {
+ case COLOR_SPACE_SRGB:
+ misc0 = misc0 | 0x0;;
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ break;
+ case COLOR_SPACE_SRGB_LIMITED:
+ misc0 = misc0 | 0x8; /* bit3=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ break;
+ case COLOR_SPACE_YCBCR601:
+ misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/;
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_YCBCR709:
+ misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+ case COLOR_SPACE_2020_YCBCR:
+ case COLOR_SPACE_ADOBERGB:
+ case COLOR_SPACE_UNKNOWN:
+ case COLOR_SPACE_YCBCR601_LIMITED:
+ case COLOR_SPACE_YCBCR709_LIMITED:
+ /* do nothing */
+ break;
+ }
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (REG(DP_MSA_COLORIMETRY))
+ REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
+
+ if (REG(DP_MSA_MISC))
+ REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
+
+ /* dcn new register
+ * dc_crtc_timing is vesa dmt struct. data from edid
+ */
+ if (REG(DP_MSA_TIMING_PARAM1))
+ REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
+ DP_MSA_HTOTAL, crtc_timing->h_total,
+ DP_MSA_VTOTAL, crtc_timing->v_total);
+#endif
+
+ /* calcuate from vesa timing parameters
+ * h_active_start related to leading edge of sync
+ */
+
+ h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
+ crtc_timing->h_addressable - crtc_timing->h_border_right;
+
+ h_back_porch = h_blank - crtc_timing->h_front_porch -
+ crtc_timing->h_sync_width;
+
+ /* start at begining of left border */
+ h_active_start = crtc_timing->h_sync_width + h_back_porch;
+
+
+ v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
+ crtc_timing->v_addressable - crtc_timing->v_border_bottom -
+ crtc_timing->v_front_porch;
+
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /* start at begining of left border */
+ if (REG(DP_MSA_TIMING_PARAM2))
+ REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
+ DP_MSA_HSTART, h_active_start,
+ DP_MSA_VSTART, v_active_start);
+
+ if (REG(DP_MSA_TIMING_PARAM3))
+ REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
+ DP_MSA_HSYNCWIDTH,
+ crtc_timing->h_sync_width,
+ DP_MSA_HSYNCPOLARITY,
+ !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
+ DP_MSA_VSYNCWIDTH,
+ crtc_timing->v_sync_width,
+ DP_MSA_VSYNCPOLARITY,
+ !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
+
+ /* HWDITH include border or overscan */
+ if (REG(DP_MSA_TIMING_PARAM4))
+ REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
+ DP_MSA_HWIDTH, crtc_timing->h_border_left +
+ crtc_timing->h_addressable + crtc_timing->h_border_right,
+ DP_MSA_VHEIGHT, crtc_timing->v_border_top +
+ crtc_timing->v_addressable + crtc_timing->v_border_bottom);
+#endif
+ }
+#endif
}
static void dce110_stream_encoder_set_stream_attribute_helper(
@@ -533,6 +749,19 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (enc110->se_mask->HDMI_DB_DISABLE) {
+ /* for bring up, disable dp double TODO */
+ if (REG(HDMI_DB_CONTROL))
+ REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
+
+ dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
+ dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
+ dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
+ dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
+ dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
+ }
+#endif
}
static void dce110_stream_encoder_stop_hdmi_info_packets(
@@ -558,6 +787,26 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_LINE, 0,
HDMI_GENERIC1_SEND, 0);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /* stop generic packets 2 & 3 on HDMI */
+ if (REG(HDMI_GENERIC_PACKET_CONTROL2))
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
+
+ if (REG(HDMI_GENERIC_PACKET_CONTROL3))
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
+#endif
}
static void dce110_stream_encoder_update_dp_info_packets(
@@ -621,6 +870,21 @@ static void dce110_stream_encoder_stop_dp_info_packets(
DP_SEC_STREAM_ENABLE, 0);
}
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
+ REG_SET_10(DP_SEC_CNTL, 0,
+ DP_SEC_GSP0_ENABLE, 0,
+ DP_SEC_GSP1_ENABLE, 0,
+ DP_SEC_GSP2_ENABLE, 0,
+ DP_SEC_GSP3_ENABLE, 0,
+ DP_SEC_GSP4_ENABLE, 0,
+ DP_SEC_GSP5_ENABLE, 0,
+ DP_SEC_GSP6_ENABLE, 0,
+ DP_SEC_GSP7_ENABLE, 0,
+ DP_SEC_MPG_ENABLE, 0,
+ DP_SEC_STREAM_ENABLE, 0);
+ }
+#endif
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
index 850e12a..0b548cb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
@@ -97,6 +97,23 @@
SE_COMMON_REG_LIST_DCE_BASE(id), \
SRI(AFMT_CNTL, DIG, id)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define SE_DCN_REG_LIST(id)\
+ SE_COMMON_REG_LIST_BASE(id),\
+ SRI(AFMT_CNTL, DIG, id),\
+ SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
+ SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
+ SRI(DP_DB_CNTL, DP, id), \
+ SRI(DP_MSA_MISC, DP, id), \
+ SRI(DP_MSA_COLORIMETRY, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM1, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM2, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM3, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM4, DP, id), \
+ SRI(HDMI_DB_CONTROL, DIG, id)
+#endif
+
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -311,6 +328,48 @@
SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
+ SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
+ SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
+ SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
+#endif
+
struct dce_stream_encoder_shift {
uint8_t AFMT_GENERIC_INDEX;
uint8_t AFMT_GENERIC0_UPDATE;
@@ -625,6 +684,16 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ uint32_t DP_DB_CNTL;
+ uint32_t DP_MSA_MISC;
+ uint32_t DP_MSA_COLORIMETRY;
+ uint32_t DP_MSA_TIMING_PARAM1;
+ uint32_t DP_MSA_TIMING_PARAM2;
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
+#endif
};
struct dce110_stream_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index dc4c164..c89df8a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -947,6 +947,12 @@ static void program_scaler(const struct core_dc *dc,
{
struct tg_color color = {0};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ /* TOFPGA */
+ if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL)
+ return;
+#endif
+
if (dc->public.debug.surface_visual_confirm)
get_surface_visual_confirm_color(pipe_ctx, &color);
else
@@ -1113,6 +1119,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(
program_scaler(dc, pipe_ctx);
/* mst support - use total stream count */
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (pipe_ctx->mi->funcs->allocate_mem_input != NULL)
+#endif
pipe_ctx->mi->funcs->allocate_mem_input(
pipe_ctx->mi,
stream->public.timing.h_total,
@@ -1637,6 +1646,26 @@ enum dc_status dce110_apply_ctx_to_hw(
/*TODO: when pplib works*/
apply_min_clocks(dc, context, &clocks_state, true);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ if (context->fclk_khz
+ > dc->current_context->fclk_khz) {
+ struct dm_pp_clock_for_voltage_req clock;
+
+ clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
+ clock.clocks_in_khz = context->fclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+ dc->current_context->fclk_khz = clock.clocks_in_khz;
+ }
+ if (context->dcfclk_khz
+ > dc->current_context->dcfclk_khz) {
+ struct dm_pp_clock_for_voltage_req clock;
+
+ clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
+ clock.clocks_in_khz = context->dcfclk_khz;
+ dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
+ dc->current_context->dcfclk_khz = clock.clocks_in_khz;
+ }
+#endif
if (context->dispclk_khz
> dc->current_context->dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index cf6ecfc..fb61e33 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -75,6 +75,10 @@
BREAK_TO_DEBUGGER(); \
} while (0)
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include <asm/fpu/api.h>
+#endif
+
#define dm_alloc(size) kzalloc(size, GFP_KERNEL)
#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
#define dm_free(ptr) kfree(ptr)
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 408141c..b283045 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -69,6 +69,7 @@ enum dm_pp_clock_type {
DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
DM_PP_CLOCK_TYPE_MEMORY_CLK,
DM_PP_CLOCK_TYPE_DCFCLK,
+ DM_PP_CLOCK_TYPE_DCEFCLK,
DM_PP_CLOCK_TYPE_SOCCLK,
DM_PP_CLOCK_TYPE_PIXELCLK,
DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 5e831af..70d01a9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -38,6 +38,17 @@ AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
###############################################################################
+# DCN 1x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_DCN1_0
+GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
+
+AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10)
+endif
+
+###############################################################################
# Diagnostics on FPGA
###############################################################################
GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 29ba83d..8a8b619 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -43,8 +43,10 @@
#include "dce80/hw_factory_dce80.h"
#include "dce110/hw_factory_dce110.h"
-
#include "dce120/hw_factory_dce120.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn10/hw_factory_dcn10.h"
+#endif
#include "diagnostics/hw_factory_diag.h"
@@ -77,6 +79,11 @@ bool dal_hw_factory_init(
case DCE_VERSION_12_0:
dal_hw_factory_dce120_init(factory);
return true;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+ dal_hw_factory_dcn10_init(factory);
+ return true;
+#endif
default:
ASSERT_CRITICAL(false);
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 872edda..36c082b 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -43,6 +43,10 @@
#include "dce80/hw_translate_dce80.h"
#include "dce110/hw_translate_dce110.h"
#include "dce120/hw_translate_dce120.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn10/hw_translate_dcn10.h"
+#endif
+
#include "diagnostics/hw_translate_diag.h"
/*
@@ -71,6 +75,11 @@ bool dal_hw_translate_init(
case DCE_VERSION_12_0:
dal_hw_translate_dce120_init(translate);
return true;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+ dal_hw_translate_dcn10_init(translate);
+ return true;
+#endif
default:
BREAK_TO_DEBUGGER();
return false;
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
index a636768..5560340 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
@@ -48,6 +48,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE
AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
###############################################################################
+# DCN 1.0 family
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_DCN1_0
+I2CAUX_DCN1 = i2caux_dcn10.o
+
+AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCN1)
+endif
+
+###############################################################################
# DCE 120 family
###############################################################################
I2CAUX_DCE120 = i2caux_dce120.o
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index 0743265..983645b 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -59,6 +59,10 @@
#include "dce120/i2caux_dce120.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn10/i2caux_dcn10.h"
+#endif
+
#include "diagnostics/i2caux_diag.h"
/*
@@ -84,6 +88,10 @@ struct i2caux *dal_i2caux_create(
return dal_i2caux_dce100_create(ctx);
case DCE_VERSION_12_0:
return dal_i2caux_dce120_create(ctx);
+ #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case DCN_VERSION_1_0:
+ return dal_i2caux_dcn10_create(ctx);
+ #endif
default:
BREAK_TO_DEBUGGER();
return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index f9363f6..392cff2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -30,6 +30,11 @@ struct core_dc {
/* Inputs into BW and WM calculations. */
struct bw_calcs_dceip bw_dceip;
struct bw_calcs_vbios bw_vbios;
+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ struct dcn_soc_bounding_box dcn_soc;
+ struct dcn_ip_params dcn_ip;
+ struct display_mode_lib dml;
+#endif
/* HW functions */
struct hw_sequencer_funcs hwss;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 9e5e0ba..c1273d6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -28,8 +28,11 @@
#include "dc.h"
#include "dce_calcs.h"
+#include "dcn_calcs.h"
#include "ddc_service_types.h"
#include "dc_bios_types.h"
+#include "mem_input.h"
+#include "mpc.h"
struct core_stream;
@@ -254,6 +257,7 @@ struct resource_pool {
struct abm *abm;
struct dmcu *dmcu;
+ struct mpc *mpc;
const struct resource_funcs *funcs;
const struct resource_caps *res_cap;
@@ -287,10 +291,20 @@ struct pipe_ctx {
struct pipe_ctx *top_pipe;
struct pipe_ctx *bottom_pipe;
+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ uint8_t mpc_idx;
+ struct _vcs_dpi_display_dlg_regs_st dlg_regs;
+ struct _vcs_dpi_display_ttu_regs_st ttu_regs;
+ struct _vcs_dpi_display_rq_regs_st rq_regs;
+ struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
+#endif
};
struct resource_context {
struct pipe_ctx pipe_ctx[MAX_PIPES];
+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ struct mpc_tree_cfg mpc_tree[MAX_PIPES];
+#endif
bool is_stream_enc_acquired[MAX_PIPES * 2];
bool is_audio_acquired[MAX_PIPES];
uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
@@ -309,6 +323,18 @@ struct validate_context {
/* Note: these are big structures, do *not* put on stack! */
struct dm_pp_display_configuration pp_display_cfg;
int dispclk_khz;
+#ifdef CONFIG_DRM_AMD_DC_DCN1_0
+ int dppclk_khz;
+ bool dppclk_div;
+ int dcfclk_khz;
+ int dcfclk_deep_sleep_khz;
+ int socclk_khz;
+ int fclk_khz;
+ int dram_ccm_us;
+ int min_active_dram_ccm_us;
+ struct dcn_watermark_set watermarks;
+ struct dcn_bw_internal_vars dcn_bw_vars;
+#endif
};
#endif /* _CORE_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
index 97f26b5..240ab11 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
@@ -37,6 +37,13 @@ struct clocks_value {
bool dispclk_notify_pplib_done;
bool pixelclk_notify_pplib_done;
bool phyclk_notigy_pplib_done;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ int dcfclock_in_khz;
+ int dppclk_in_khz;
+ int mclk_in_khz;
+ int phyclk_in_khz;
+ int common_vdd_level;
+#endif
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
index 2d472d8..0f952e5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
@@ -122,6 +122,7 @@ struct ipp_funcs {
struct input_pixel_processor *ipp,
const struct pwl_params *params);
+ void (*ipp_destroy)(struct input_pixel_processor **ipp);
};
#endif /* __DAL_IPP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 179f5ad..0880ce9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -31,6 +31,30 @@
#include "dce/dce_mem_input.h" /* temporary */
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dml/display_mode_structs.h"
+
+struct cstate_pstate_watermarks_st {
+ uint32_t cstate_exit_ns;
+ uint32_t cstate_enter_plus_exit_ns;
+ uint32_t pstate_change_ns;
+};
+
+struct dcn_watermarks {
+ uint32_t pte_meta_urgent_ns;
+ uint32_t urgent_ns;
+ struct cstate_pstate_watermarks_st cstate_pstate;
+};
+
+struct dcn_watermark_set {
+ struct dcn_watermarks a;
+ struct dcn_watermarks b;
+ struct dcn_watermarks c;
+ struct dcn_watermarks d;
+};
+
+#endif
+
struct stutter_modes {
bool enhanced;
bool quad_dmif_buffer;
@@ -52,6 +76,23 @@ struct mem_input {
};
struct mem_input_funcs {
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ void (*program_watermarks)(
+ struct mem_input *mem_input,
+ struct dcn_watermark_set *watermarks,
+ unsigned int refclk_period_ns);
+
+ void (*mem_input_setup)(
+ struct mem_input *mem_input,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+ struct _vcs_dpi_display_rq_regs_st *rq_regs,
+ struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
+
+ void (*disable_request)(struct mem_input *mem_input);
+
+#endif
+
void (*mem_input_program_display_marks)(
struct mem_input *mem_input,
struct bw_watermarks nbp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
new file mode 100644
index 0000000..2e86ebe
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -0,0 +1,110 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_MPC_H__
+#define __DC_MPC_H__
+
+/* define the maximum number of pipes
+ * MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h
+ */
+enum {
+ MAX_NUM_PIPPES = 6
+};
+
+enum blend_mode {
+ DIGI_BYPASS = 0, /* digital bypass */
+ TOP_PASSTHRU, /* top layer pass through */
+ TOP_BLND /* top layer blend */
+};
+
+/* This structure define the mpc tree configuration
+ * num_pipes - number of pipes of the tree
+ * opp_id - instance id of OPP to drive MPC
+ * dpp- array of DPP index
+ * mpcc - array of MPCC index
+ * mode - the most bottom layer MPCC mode control.
+ * All other layers need to be program to 3
+ *
+ * The connection will be:
+ * mpcc[num_pipes-1]->mpcc[num_pipes-2]->...->mpcc[1]->mpcc[0]->OPP[opp_id]
+ * dpp[0]->mpcc[0]
+ * dpp[1]->mpcc[1]
+ * ...
+ * dpp[num_pipes-1]->mpcc[num_pipes-1]
+ * mpcc[0] is the most top layer of MPC tree,
+ * mpcc[num_pipes-1] is the most bottom layer.
+ */
+
+struct mpc_tree_cfg {
+ uint8_t num_pipes;
+ uint8_t opp_id;
+ /* dpp pipes for blend */
+ uint8_t dpp[MAX_NUM_PIPPES];
+ /* mpcc insatnces for blend */
+ uint8_t mpcc[MAX_NUM_PIPPES];
+ enum blend_mode mode;
+};
+
+struct mpcc_blnd_cfg {
+ /* 0- perpixel alpha, 1- perpixel alpha combined with global gain,
+ * 2- global alpha
+ */
+ uint8_t alpha_mode;
+ uint8_t global_gain;
+ uint8_t global_alpha;
+ bool overlap_only;
+ bool pre_multiplied_alpha;
+};
+
+struct mpcc_sm_cfg {
+ bool enable;
+ /* 0-single plane, 2-row subsampling, 4-column subsampling,
+ * 6-checkboard subsampling
+ */
+ uint8_t sm_mode;
+ bool frame_alt; /* 0- disable, 1- enable */
+ bool field_alt; /* 0- disable, 1- enable */
+ /* 0-no force, 2-force frame polarity from top,
+ * 3-force frame polarity from bottom
+ */
+ uint8_t force_next_frame_porlarity;
+ /* 0-no force, 2-force field polarity from top,
+ * 3-force field polarity from bottom
+ */
+ uint8_t force_next_field_polarity;
+};
+
+struct mpcc_vupdate_lock_cfg {
+ bool cfg_lock;
+ bool adr_lock;
+ bool adr_cfg_lock;
+ bool cur0_lock;
+ bool cur1_lock;
+};
+
+struct mpc {
+ struct dc_context *ctx;
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 92c99c3..64d4325 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -27,6 +27,7 @@
#define __DAL_OPP_H__
#include "hw_shared.h"
+#include "dc_hw_types.h"
#include "transform.h"
struct fixed31_32;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 00cdaaae..9f130af 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -91,10 +91,22 @@ enum crtc_state {
CRTC_STATE_VBLANK = 0,
CRTC_STATE_VACTIVE
};
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+struct _dlg_otg_param {
+ int vstartup_start;
+ int vupdate_offset;
+ int vupdate_width;
+ int vready_offset;
+ enum signal_type signal;
+};
+#endif
struct timing_generator {
const struct timing_generator_funcs *funcs;
struct dc_bios *bp;
struct dc_context *ctx;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ struct _dlg_otg_param dlg_otg_param;
+#endif
int inst;
};
@@ -155,6 +167,10 @@ struct timing_generator_funcs {
bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ void (*program_global_sync)(struct timing_generator *tg);
+ void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
+#endif
};
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 222f36e..c7e93f7 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -36,3 +36,13 @@ AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
+###############################################################################
+# DCN 1x
+###############################################################################
+ifdef CONFIG_DRM_AMD_DC_DCN1_0
+IRQ_DCN1 = irq_service_dcn10.o
+
+AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
index 5255c14..0a1fae4 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -35,6 +35,11 @@
#include "dce120/irq_service_dce120.h"
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#include "dcn10/irq_service_dcn10.h"
+#endif
+
#include "reg_helper.h"
#include "irq_service.h"
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 6dab058..3d2ed5c 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -109,6 +109,19 @@
#define ASIC_REV_IS_STONEY(rev) \
((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+/* DCN1_0 */
+#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
+#define RAVEN_A0 0x01
+#define RAVEN_UNKNOWN 0xFF
+
+#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+#define FAMILY_RV 142 /* DCN 1*/
+#endif
+
/*
* ASIC chip ID
*/
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 0cefde1..50a2a3e 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -39,7 +39,10 @@ enum dce_version {
DCE_VERSION_11_0,
DCE_VERSION_11_2,
DCE_VERSION_12_0,
- DCE_VERSION_MAX,
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ DCN_VERSION_1_0,
+#endif
+ DCN_VERSION_MAX
};
#endif /* __DAL_TYPES_H__ */
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 116/117] drm/amdgpu: enable dcn1.0 dc support on raven
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (106 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 115/117] drm/amdgpu/display: Enable DCN in DC Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 18:47 ` [PATCH 117/117] drm/amdgpu: add RAVEN pci id Alex Deucher
2017-05-10 19:28 ` [PATCH 000/117] Raven Support Christian König
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Hawking Zhang
From: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9b64864..cfc650c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1962,6 +1962,10 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VEGA10:
return amdgpu_dc != 0;
#endif
+#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_DCN1_0)
+ case CHIP_RAVEN:
+ return amdgpu_dc != 0;
+#endif
default:
return false;
}
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH 117/117] drm/amdgpu: add RAVEN pci id
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (107 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 116/117] drm/amdgpu: enable dcn1.0 dc support on raven Alex Deucher
@ 2017-05-10 18:47 ` Alex Deucher
2017-05-10 19:28 ` [PATCH 000/117] Raven Support Christian König
109 siblings, 0 replies; 114+ messages in thread
From: Alex Deucher @ 2017-05-10 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Chunming Zhou
From: Chunming Zhou <David1.Zhou@amd.com>
Add the RAVEN pci id.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 2211cd8..82796eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -465,6 +465,9 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
+ /* Raven */
+ {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
+
{0, 0, 0}
};
--
2.5.5
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH 000/117] Raven Support
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (108 preceding siblings ...)
2017-05-10 18:47 ` [PATCH 117/117] drm/amdgpu: add RAVEN pci id Alex Deucher
@ 2017-05-10 19:28 ` Christian König
[not found] ` <9c4b2cc4-3632-6131-4d2a-f08a088a6081-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
109 siblings, 1 reply; 114+ messages in thread
From: Christian König @ 2017-05-10 19:28 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Am 10.05.2017 um 20:45 schrieb Alex Deucher:
> This patch set adds support for the new "Raven" APU.
>
> The first 12 patches add support for the new ACP
> audio hardware on Raven. Patches 11 and 12 are not
> meant for upstream, they are for early hardware testing.
> The rest add GPU support. Patches 17-24 are register
> headers (which are relatively large), so I'm not sending
> them out.
>
> You can view the whole patch set here:
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
Patches #1-#13 are Acked-by: Christian König <christian.koenig@amd.com>.
Patches #14-#16 are Reviewed-by: Christian König <christian.koenig@amd.com>.
Patches #17-#25 are somehow missing on the mailing lists at the moment.
Going to take a look at the rest tomorrow.
Christian.
>
> Alex Deucher (12):
> drm/amdgpu: add gpu_info firmware (v3)
> drm/amdgpu: parse the gpu_info firmware (v4)
> drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
> drm/amdgpu: add register headers for DCN 1.0
> drm/amdgpu: add register headers for GC 9.1
> drm/amdgpu: add register headers for MMHUB 9.1
> drm/amdgpu: add register headers for MP 10.0
> drm/amdgpu: add register headers for NBIO 7.0
> drm/amdgpu: add register headers for SDMA 4.1
> drm/amdgpu: add register headers for THM 10.0
> drm/amdgpu: add register headers for VCN 1.0
> drm/amdgpu/raven: power up/down VCN via the SMU (v2)
>
> Andrey Grodzovsky (1):
> drm/amd: Add DCN ivsrcids (v2)
>
> Chunming Zhou (17):
> drm/amdgpu: add RAVEN family id definition
> drm/amdgpu: add Raven ip blocks
> drm/amdgpu/soc15: add Raven golden setting
> drm/amdgpu: add Raven chip id case for ucode
> drm/amdgpu: add module firmware for raven
> drm/amdgpu: add gc9.1 golden setting (v2)
> drm/amdgpu/gfx9: add chip name for raven when initializing microcode
> drm/amdgpu/gfx9: add raven gfx config
> drm/amdgpu: add raven case for gmc9 golden setting
> drm/amdgpu/gmc9: set mc vm fb offset for raven
> drm/amdgpu/gmc9: change fb offset sequence so that used wider
> drm/amdgpu: add Raven sdma golden setting and chip id case
> drm/amdgpu: add nbio7 support
> drm/amdgpu: apply nbio7 for Raven (v3)
> drm/amd/powerplay/rv: power up/down sdma via the SMU
> drm/amdgpu/powerplay/raven: add smu block and enable powerplay
> drm/amdgpu: add RAVEN pci id
>
> Harry Wentland (7):
> drm/amdgpu/display: Add calcs code for DCN
> drm/amdgpu/display: Add core dc support for DCN
> drm/amdgpu/display: Add dml support for DCN
> drm/amdgpu/display: Add gpio support for DCN
> drm/amdgpu/display: Add i2c/aux support for DCN
> drm/amdgpu/display: Add irq support for DCN
> drm/amdgpu/display: Enable DCN in DC
>
> Hawking Zhang (13):
> drm/amd/amdgpu: fill in raven case in soc15 early init
> drm/amdgpu/gfx9: extend rlc fw setup
> drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
> drm/amdgpu: correct gfx9 csb size
> drm/amdgpu/gfx9: add rlc bo init/fini
> drm/amdgpu/gfx9: rlc save&restore list programming
> drm/amdgpu: init gfx power gating on raven
> drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
> drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
> drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
> drm/amdgpu/gfx9: allow updating gfx cgpg state
> drm/amdgpu/gfx9: allow updating gfx mgpg state
> drm/amdgpu: enable dcn1.0 dc support on raven
>
> Huang Rui (17):
> drm/amdgpu/soc15: add clock gating functions for raven
> drm/amdgpu: enable soc15 clock gating flags for raven
> drm/amdgpu: add gfx clock gating for raven
> drm/amdgpu: add raven clock gating and light sleep for mmhub
> drm/amdgpu: enable MC MGCG and LS for raven
> drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
> drm/amdgpu: enable sdma v4 MGCG and LS for raven
> drm/amdgpu: init sdma power gating for raven
> drm/amdgpu/sdma4: add dynamic power gating for raven
> drm/amdgpu: enable sdma power gating for raven
> drm/amdgpu: add nbio MGCG for raven
> drm/amdgpu: add psp v10 function callback for raven
> drm/amdgpu: add psp v10 ip block
> drm/amdgpu: register the psp v10 function pointers at psp sw_init
> drm/amdgpu/soc15: add psp ip block
> drm/amdgpu/vcn: add sw clock gating
> drm/amdgpu: enable sw clock gating for vcn
>
> Leo Liu (32):
> drm/amdgpu: add initial vcn support and decode tests
> drm/amdgpu: add encode tests for vcn
> drm/amdgpu: add vcn ip block functions (v2)
> drm/amdgpu: add vcn decode ring support
> drm/amdgpu: add vcn decode ring type and functions
> drm/amdgpu: add vcn irq functions
> drm/amdgpu: add vcn ip block and type
> drm/amdgpu: move amdgpu_vcn structure to vcn header
> drm/amdgpu: re-group the functions in amdgpu_vcn.c
> drm/amdgpu: move vcn ring test to amdgpu_vcn.c
> drm/amdgpu: expose vcn RB command
> drm/amdgpu: add a ring func for vcn start command
> drm/amdgpu: implement vcn start RB command
> drm/amdgpu: implement insert end ring function for vcn decode
> drm/amdgpu/vcn: implement ib tests with new message buffer interface
> uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
> uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
> drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
> drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
> drm/amdgpu: Disable uvd and vce free handles for raven
> drm/amdgpu: implement new vcn cache window programming
> drm/amdgpu: add vcn ip block to soc15
> drm/amdgpu: change vcn dec rb command specific for decode
> drm/amdgpu: add vcn enc rings
> drm/amdgpu: add vcn enc ring type and functions
> drm/amdgpu: add vcn enc irq support
> drm/amdgpu: enable vcn encode ring tests
> drm/amdgpu: add vcn enc ib test
> drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
> drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
> drm/amdgpu: add vcn firmware header offset
> drm/amdgpu: update vcn decode create msg
>
> Maruthi Srinivas Bayyavarapu (12):
> ASoC: AMD: add ACP 3.x IP register header
> ASoC: AMD: add ACP3.0 PCI driver
> ASoC: AMD: create ACP3x PCM platform device
> ASoC: AMD: add ACP3x PCM platform driver
> ASoC: AMD: handle ACP3x i2s watermark interrupt
> ASoC: AMD: add ACP3x PCM driver DMA ops
> ASoC: AMD: add ACP3x i2s ops
> ASoC: AMD: add ACP3x TDM mode support
> ASoC: AMD: Add ACP3x runtime pm ops
> ASoC: AMD: Add ACP3x system resume pm op
> ASoC: AMD: enable ACP3x drivers build
> ASoC: AMD: create/add dummy codec and machine devices/drivers
>
> Rex Zhu (5):
> drm/amdgpu/powerplay: add header file for smu10. (v2)
> drm/amdgpu: add raven related define in pptable.h.
> drm/amd/powerplay: add ppt_v3 define
> drm/amd/powerplay: add raven support in smumgr. (v2)
> drm/amd/powerplay: add raven support in hwmgr. (v2)
>
> Vijendar Mukunda (1):
> soc/amd/raven: Disabling TDM mode flag
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 111 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 654 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 77 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 793 +-
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 25 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +-
> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +
> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 +
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 128 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 103 +-
> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1190 +
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +-
> drivers/gpu/drm/amd/display/Kconfig | 7 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 +-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
> drivers/gpu/drm/amd/display/dc/Makefile | 5 +
> .../amd/display/dc/bios/command_table_helper2.c | 5 +
> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 +
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 +
> drivers/gpu/drm/amd/display/dc/dc.h | 18 +
> drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 +
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 +
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 +
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +
> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 +
> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 +
> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
> .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +
> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 +
> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +
> drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 +
> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
> .../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +
> .../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +
> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +
> drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
> drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
> drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +
> .../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
> .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 +
> .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
> .../drm/amd/display/dc/dml/display_mode_structs.h | 429 +
> .../drm/amd/display/dc/dml/display_mode_support.c | 2326 +
> .../drm/amd/display/dc/dml/display_mode_support.h | 199 +
> .../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +
> .../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
> .../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +
> .../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 +
> .../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +
> .../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
> .../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +
> .../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
> .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 +
> .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 +
> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 +
> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +
> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 +
> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +
> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 +
> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
> drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
> drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 +
> drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 +
> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
> drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 +
> drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +
> drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
> .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 +
> drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
> .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +
> .../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 +
> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
> drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
> drivers/gpu/drm/amd/include/amd_shared.h | 4 +-
> .../include/asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ++
> .../include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 14087 +++
> .../include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 54316 ++++++++
> .../include/asic_reg/raven1/GC/gc_9_1_default.h | 4005 +
> .../amd/include/asic_reg/raven1/GC/gc_9_1_offset.h | 7491 ++
> .../include/asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 +++++
> .../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 +
> .../asic_reg/raven1/MMHUB/mmhub_9_1_offset.h | 1999 +
> .../asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h | 9790 ++
> .../include/asic_reg/raven1/MP/mp_10_0_default.h | 182 +
> .../include/asic_reg/raven1/MP/mp_10_0_offset.h | 336 +
> .../include/asic_reg/raven1/MP/mp_10_0_sh_mask.h | 886 +
> .../asic_reg/raven1/NBIO/nbio_7_0_default.h | 14865 +++
> .../include/asic_reg/raven1/NBIO/nbio_7_0_offset.h | 4640 +
> .../asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h | 118945 ++++++++++++++++++
> .../asic_reg/raven1/SDMA0/sdma0_4_1_default.h | 242 +
> .../asic_reg/raven1/SDMA0/sdma0_4_1_offset.h | 459 +
> .../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 +
> .../include/asic_reg/raven1/THM/thm_10_0_default.h | 141 +
> .../include/asic_reg/raven1/THM/thm_10_0_offset.h | 257 +
> .../include/asic_reg/raven1/THM/thm_10_0_sh_mask.h | 885 +
> .../include/asic_reg/raven1/VCN/vcn_1_0_default.h | 202 +
> .../include/asic_reg/raven1/VCN/vcn_1_0_offset.h | 376 +
> .../include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h | 1308 +
> .../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 +
> drivers/gpu/drm/amd/include/pptable.h | 57 +-
> drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
> .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +
> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
> drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +
> drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +
> .../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +
> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 399 +
> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 +
> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
> include/uapi/drm/amdgpu_drm.h | 5 +-
> sound/soc/amd/Kconfig | 4 +
> sound/soc/amd/Makefile | 1 +
> sound/soc/amd/raven/Makefile | 8 +
> sound/soc/amd/raven/acp3x-dummy5102.c | 136 +
> sound/soc/amd/raven/acp3x-pcm-dma.c | 805 +
> sound/soc/amd/raven/acp3x.h | 34 +
> sound/soc/amd/raven/chip_offset_byte.h | 655 +
> sound/soc/amd/raven/dummy-w5102.c | 102 +
> sound/soc/amd/raven/pci-acp3x.c | 189 +
> 175 files changed, 314946 insertions(+), 121 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
> create mode 100644 sound/soc/amd/raven/Makefile
> create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
> create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
> create mode 100644 sound/soc/amd/raven/acp3x.h
> create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
> create mode 100644 sound/soc/amd/raven/dummy-w5102.c
> create mode 100644 sound/soc/amd/raven/pci-acp3x.c
>
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^ permalink raw reply [flat|nested] 114+ messages in thread
* RE: [PATCH 000/117] Raven Support
[not found] ` <9c4b2cc4-3632-6131-4d2a-f08a088a6081-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-05-10 19:30 ` Deucher, Alexander
[not found] ` <BN6PR12MB16526517361BBE472EE0A710F7EC0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 114+ messages in thread
From: Deucher, Alexander @ 2017-05-10 19:30 UTC (permalink / raw)
To: 'Christian König',
Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: Christian König [mailto:deathsimple@vodafone.de]
> Sent: Wednesday, May 10, 2017 3:29 PM
> To: Alex Deucher; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH 000/117] Raven Support
>
> Am 10.05.2017 um 20:45 schrieb Alex Deucher:
> > This patch set adds support for the new "Raven" APU.
> >
> > The first 12 patches add support for the new ACP
> > audio hardware on Raven. Patches 11 and 12 are not
> > meant for upstream, they are for early hardware testing.
> > The rest add GPU support. Patches 17-24 are register
> > headers (which are relatively large), so I'm not sending
> > them out.
> >
> > You can view the whole patch set here:
> > https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
>
> Patches #1-#13 are Acked-by: Christian König <christian.koenig@amd.com>.
>
> Patches #14-#16 are Reviewed-by: Christian König
> <christian.koenig@amd.com>.
>
> Patches #17-#25 are somehow missing on the mailing lists at the moment.
17-24 are just register headers. I didn’t send them out because they are too big.
Alex
>
> Going to take a look at the rest tomorrow.
>
> Christian.
>
> >
> > Alex Deucher (12):
> > drm/amdgpu: add gpu_info firmware (v3)
> > drm/amdgpu: parse the gpu_info firmware (v4)
> > drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
> > drm/amdgpu: add register headers for DCN 1.0
> > drm/amdgpu: add register headers for GC 9.1
> > drm/amdgpu: add register headers for MMHUB 9.1
> > drm/amdgpu: add register headers for MP 10.0
> > drm/amdgpu: add register headers for NBIO 7.0
> > drm/amdgpu: add register headers for SDMA 4.1
> > drm/amdgpu: add register headers for THM 10.0
> > drm/amdgpu: add register headers for VCN 1.0
> > drm/amdgpu/raven: power up/down VCN via the SMU (v2)
> >
> > Andrey Grodzovsky (1):
> > drm/amd: Add DCN ivsrcids (v2)
> >
> > Chunming Zhou (17):
> > drm/amdgpu: add RAVEN family id definition
> > drm/amdgpu: add Raven ip blocks
> > drm/amdgpu/soc15: add Raven golden setting
> > drm/amdgpu: add Raven chip id case for ucode
> > drm/amdgpu: add module firmware for raven
> > drm/amdgpu: add gc9.1 golden setting (v2)
> > drm/amdgpu/gfx9: add chip name for raven when initializing microcode
> > drm/amdgpu/gfx9: add raven gfx config
> > drm/amdgpu: add raven case for gmc9 golden setting
> > drm/amdgpu/gmc9: set mc vm fb offset for raven
> > drm/amdgpu/gmc9: change fb offset sequence so that used wider
> > drm/amdgpu: add Raven sdma golden setting and chip id case
> > drm/amdgpu: add nbio7 support
> > drm/amdgpu: apply nbio7 for Raven (v3)
> > drm/amd/powerplay/rv: power up/down sdma via the SMU
> > drm/amdgpu/powerplay/raven: add smu block and enable powerplay
> > drm/amdgpu: add RAVEN pci id
> >
> > Harry Wentland (7):
> > drm/amdgpu/display: Add calcs code for DCN
> > drm/amdgpu/display: Add core dc support for DCN
> > drm/amdgpu/display: Add dml support for DCN
> > drm/amdgpu/display: Add gpio support for DCN
> > drm/amdgpu/display: Add i2c/aux support for DCN
> > drm/amdgpu/display: Add irq support for DCN
> > drm/amdgpu/display: Enable DCN in DC
> >
> > Hawking Zhang (13):
> > drm/amd/amdgpu: fill in raven case in soc15 early init
> > drm/amdgpu/gfx9: extend rlc fw setup
> > drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
> > drm/amdgpu: correct gfx9 csb size
> > drm/amdgpu/gfx9: add rlc bo init/fini
> > drm/amdgpu/gfx9: rlc save&restore list programming
> > drm/amdgpu: init gfx power gating on raven
> > drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
> > drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
> > drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
> > drm/amdgpu/gfx9: allow updating gfx cgpg state
> > drm/amdgpu/gfx9: allow updating gfx mgpg state
> > drm/amdgpu: enable dcn1.0 dc support on raven
> >
> > Huang Rui (17):
> > drm/amdgpu/soc15: add clock gating functions for raven
> > drm/amdgpu: enable soc15 clock gating flags for raven
> > drm/amdgpu: add gfx clock gating for raven
> > drm/amdgpu: add raven clock gating and light sleep for mmhub
> > drm/amdgpu: enable MC MGCG and LS for raven
> > drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
> > drm/amdgpu: enable sdma v4 MGCG and LS for raven
> > drm/amdgpu: init sdma power gating for raven
> > drm/amdgpu/sdma4: add dynamic power gating for raven
> > drm/amdgpu: enable sdma power gating for raven
> > drm/amdgpu: add nbio MGCG for raven
> > drm/amdgpu: add psp v10 function callback for raven
> > drm/amdgpu: add psp v10 ip block
> > drm/amdgpu: register the psp v10 function pointers at psp sw_init
> > drm/amdgpu/soc15: add psp ip block
> > drm/amdgpu/vcn: add sw clock gating
> > drm/amdgpu: enable sw clock gating for vcn
> >
> > Leo Liu (32):
> > drm/amdgpu: add initial vcn support and decode tests
> > drm/amdgpu: add encode tests for vcn
> > drm/amdgpu: add vcn ip block functions (v2)
> > drm/amdgpu: add vcn decode ring support
> > drm/amdgpu: add vcn decode ring type and functions
> > drm/amdgpu: add vcn irq functions
> > drm/amdgpu: add vcn ip block and type
> > drm/amdgpu: move amdgpu_vcn structure to vcn header
> > drm/amdgpu: re-group the functions in amdgpu_vcn.c
> > drm/amdgpu: move vcn ring test to amdgpu_vcn.c
> > drm/amdgpu: expose vcn RB command
> > drm/amdgpu: add a ring func for vcn start command
> > drm/amdgpu: implement vcn start RB command
> > drm/amdgpu: implement insert end ring function for vcn decode
> > drm/amdgpu/vcn: implement ib tests with new message buffer interface
> > uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
> > uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
> > drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
> > drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
> > drm/amdgpu: Disable uvd and vce free handles for raven
> > drm/amdgpu: implement new vcn cache window programming
> > drm/amdgpu: add vcn ip block to soc15
> > drm/amdgpu: change vcn dec rb command specific for decode
> > drm/amdgpu: add vcn enc rings
> > drm/amdgpu: add vcn enc ring type and functions
> > drm/amdgpu: add vcn enc irq support
> > drm/amdgpu: enable vcn encode ring tests
> > drm/amdgpu: add vcn enc ib test
> > drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
> > drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
> > drm/amdgpu: add vcn firmware header offset
> > drm/amdgpu: update vcn decode create msg
> >
> > Maruthi Srinivas Bayyavarapu (12):
> > ASoC: AMD: add ACP 3.x IP register header
> > ASoC: AMD: add ACP3.0 PCI driver
> > ASoC: AMD: create ACP3x PCM platform device
> > ASoC: AMD: add ACP3x PCM platform driver
> > ASoC: AMD: handle ACP3x i2s watermark interrupt
> > ASoC: AMD: add ACP3x PCM driver DMA ops
> > ASoC: AMD: add ACP3x i2s ops
> > ASoC: AMD: add ACP3x TDM mode support
> > ASoC: AMD: Add ACP3x runtime pm ops
> > ASoC: AMD: Add ACP3x system resume pm op
> > ASoC: AMD: enable ACP3x drivers build
> > ASoC: AMD: create/add dummy codec and machine devices/drivers
> >
> > Rex Zhu (5):
> > drm/amdgpu/powerplay: add header file for smu10. (v2)
> > drm/amdgpu: add raven related define in pptable.h.
> > drm/amd/powerplay: add ppt_v3 define
> > drm/amd/powerplay: add raven support in smumgr. (v2)
> > drm/amd/powerplay: add raven support in hwmgr. (v2)
> >
> > Vijendar Mukunda (1):
> > soc/amd/raven: Disabling TDM mode flag
> >
> > drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 111 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 654 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 77 +
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 793 +-
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +
> > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
> > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 25 +-
> > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +-
> > drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +
> > drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 +
> > drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +
> > drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 128 +-
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 103 +-
> > drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1190 +
> > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +
> > drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +-
> > drivers/gpu/drm/amd/display/Kconfig | 7 +
> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 +-
> > .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
> > drivers/gpu/drm/amd/display/dc/Makefile | 5 +
> > .../amd/display/dc/bios/command_table_helper2.c | 5 +
> > drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
> > .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 +
> > .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
> > .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
> > .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
> > drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 +
> > drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 +
> > drivers/gpu/drm/amd/display/dc/dc.h | 18 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 +
> > .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +
> > .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 +
> > drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 +
> > .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
> > .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +
> > .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 +
> > .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +
> > drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
> > .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 +
> > .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +
> > drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
> > .../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +
> > .../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +
> > .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +
> > drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
> > drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
> > drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
> > drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +
> > .../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
> > .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 +
> > .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
> > .../drm/amd/display/dc/dml/display_mode_structs.h | 429 +
> > .../drm/amd/display/dc/dml/display_mode_support.c | 2326 +
> > .../drm/amd/display/dc/dml/display_mode_support.h | 199 +
> > .../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +
> > .../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
> > .../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +
> > .../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 +
> > .../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +
> > .../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
> > .../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +
> > .../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
> > .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 +
> > .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
> > .../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
> > .../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
> > drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
> > .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 +
> > .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 +
> > .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +
> > .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 +
> > drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
> > drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
> > drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
> > .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +
> > .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 +
> > drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
> > drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
> > drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 +
> > drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 +
> > .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
> > drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
> > drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 +
> > drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +
> > drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
> > .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 +
> > drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
> > .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +
> > .../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 +
> > drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
> > drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
> > drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
> > drivers/gpu/drm/amd/include/amd_shared.h | 4 +-
> > .../include/asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ++
> > .../include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 14087 +++
> > .../include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 54316 ++++++++
> > .../include/asic_reg/raven1/GC/gc_9_1_default.h | 4005 +
> > .../amd/include/asic_reg/raven1/GC/gc_9_1_offset.h | 7491 ++
> > .../include/asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 +++++
> > .../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 +
> > .../asic_reg/raven1/MMHUB/mmhub_9_1_offset.h | 1999 +
> > .../asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h | 9790 ++
> > .../include/asic_reg/raven1/MP/mp_10_0_default.h | 182 +
> > .../include/asic_reg/raven1/MP/mp_10_0_offset.h | 336 +
> > .../include/asic_reg/raven1/MP/mp_10_0_sh_mask.h | 886 +
> > .../asic_reg/raven1/NBIO/nbio_7_0_default.h | 14865 +++
> > .../include/asic_reg/raven1/NBIO/nbio_7_0_offset.h | 4640 +
> > .../asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h | 118945
> ++++++++++++++++++
> > .../asic_reg/raven1/SDMA0/sdma0_4_1_default.h | 242 +
> > .../asic_reg/raven1/SDMA0/sdma0_4_1_offset.h | 459 +
> > .../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 +
> > .../include/asic_reg/raven1/THM/thm_10_0_default.h | 141 +
> > .../include/asic_reg/raven1/THM/thm_10_0_offset.h | 257 +
> > .../include/asic_reg/raven1/THM/thm_10_0_sh_mask.h | 885 +
> > .../include/asic_reg/raven1/VCN/vcn_1_0_default.h | 202 +
> > .../include/asic_reg/raven1/VCN/vcn_1_0_offset.h | 376 +
> > .../include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h | 1308 +
> > .../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 +
> > drivers/gpu/drm/amd/include/pptable.h | 57 +-
> > drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
> > drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
> > drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
> > .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
> > drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +
> > drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +
> > drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +
> > drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
> > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
> > drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +
> > drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +
> > .../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +
> > drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
> > drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
> > drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 399 +
> > drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 +
> > drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
> > include/uapi/drm/amdgpu_drm.h | 5 +-
> > sound/soc/amd/Kconfig | 4 +
> > sound/soc/amd/Makefile | 1 +
> > sound/soc/amd/raven/Makefile | 8 +
> > sound/soc/amd/raven/acp3x-dummy5102.c | 136 +
> > sound/soc/amd/raven/acp3x-pcm-dma.c | 805 +
> > sound/soc/amd/raven/acp3x.h | 34 +
> > sound/soc/amd/raven/chip_offset_byte.h | 655 +
> > sound/soc/amd/raven/dummy-w5102.c | 102 +
> > sound/soc/amd/raven/pci-acp3x.c | 189 +
> > 175 files changed, 314946 insertions(+), 121 deletions(-)
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
> > create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
> > create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
> > create mode 100644
> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_defa
> ult.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offs
> et.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_
> mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default
> .h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.
> h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_ma
> sk.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
> > create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
> > create mode 100644
> drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
> > create mode 100644
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> > create mode 100644
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> > create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
> > create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> > create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
> > create mode 100644
> drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
> > create mode 100644
> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> > create mode 100644
> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
> > create mode 100644 sound/soc/amd/raven/Makefile
> > create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
> > create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
> > create mode 100644 sound/soc/amd/raven/acp3x.h
> > create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
> > create mode 100644 sound/soc/amd/raven/dummy-w5102.c
> > create mode 100644 sound/soc/amd/raven/pci-acp3x.c
> >
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH 000/117] Raven Support
[not found] ` <BN6PR12MB16526517361BBE472EE0A710F7EC0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-05-11 18:08 ` Christian König
[not found] ` <aad7efe0-e909-a2b8-b7ee-8abb90534e5b-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 114+ messages in thread
From: Christian König @ 2017-05-11 18:08 UTC (permalink / raw)
To: Deucher, Alexander, Alex Deucher,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 10.05.2017 um 21:30 schrieb Deucher, Alexander:
>> -----Original Message-----
>> From: Christian König [mailto:deathsimple@vodafone.de]
>> Sent: Wednesday, May 10, 2017 3:29 PM
>> To: Alex Deucher; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subject: Re: [PATCH 000/117] Raven Support
>>
>> Am 10.05.2017 um 20:45 schrieb Alex Deucher:
>>> This patch set adds support for the new "Raven" APU.
>>>
>>> The first 12 patches add support for the new ACP
>>> audio hardware on Raven. Patches 11 and 12 are not
>>> meant for upstream, they are for early hardware testing.
>>> The rest add GPU support. Patches 17-24 are register
>>> headers (which are relatively large), so I'm not sending
>>> them out.
>>>
>>> You can view the whole patch set here:
>>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
>> Patches #1-#13 are Acked-by: Christian König <christian.koenig@amd.com>.
>>
>> Patches #14-#16 are Reviewed-by: Christian König
>> <christian.koenig@amd.com>.
>>
>> Patches #17-#25 are somehow missing on the mailing lists at the moment.
> 17-24 are just register headers. I didn’t send them out because they are too big.
Ok, that makes sense. Only had time to skimmed over the set.
Found a few ends which still need some work. For example has anybody
tested multi level page tables on Raven yet?
But that not blocking so feel free to add an Acked-by: Christian König
<christian.koenig@amd.com>.
Christian.
>
> Alex
>
>> Going to take a look at the rest tomorrow.
>>
>> Christian.
>>
>>> Alex Deucher (12):
>>> drm/amdgpu: add gpu_info firmware (v3)
>>> drm/amdgpu: parse the gpu_info firmware (v4)
>>> drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
>>> drm/amdgpu: add register headers for DCN 1.0
>>> drm/amdgpu: add register headers for GC 9.1
>>> drm/amdgpu: add register headers for MMHUB 9.1
>>> drm/amdgpu: add register headers for MP 10.0
>>> drm/amdgpu: add register headers for NBIO 7.0
>>> drm/amdgpu: add register headers for SDMA 4.1
>>> drm/amdgpu: add register headers for THM 10.0
>>> drm/amdgpu: add register headers for VCN 1.0
>>> drm/amdgpu/raven: power up/down VCN via the SMU (v2)
>>>
>>> Andrey Grodzovsky (1):
>>> drm/amd: Add DCN ivsrcids (v2)
>>>
>>> Chunming Zhou (17):
>>> drm/amdgpu: add RAVEN family id definition
>>> drm/amdgpu: add Raven ip blocks
>>> drm/amdgpu/soc15: add Raven golden setting
>>> drm/amdgpu: add Raven chip id case for ucode
>>> drm/amdgpu: add module firmware for raven
>>> drm/amdgpu: add gc9.1 golden setting (v2)
>>> drm/amdgpu/gfx9: add chip name for raven when initializing microcode
>>> drm/amdgpu/gfx9: add raven gfx config
>>> drm/amdgpu: add raven case for gmc9 golden setting
>>> drm/amdgpu/gmc9: set mc vm fb offset for raven
>>> drm/amdgpu/gmc9: change fb offset sequence so that used wider
>>> drm/amdgpu: add Raven sdma golden setting and chip id case
>>> drm/amdgpu: add nbio7 support
>>> drm/amdgpu: apply nbio7 for Raven (v3)
>>> drm/amd/powerplay/rv: power up/down sdma via the SMU
>>> drm/amdgpu/powerplay/raven: add smu block and enable powerplay
>>> drm/amdgpu: add RAVEN pci id
>>>
>>> Harry Wentland (7):
>>> drm/amdgpu/display: Add calcs code for DCN
>>> drm/amdgpu/display: Add core dc support for DCN
>>> drm/amdgpu/display: Add dml support for DCN
>>> drm/amdgpu/display: Add gpio support for DCN
>>> drm/amdgpu/display: Add i2c/aux support for DCN
>>> drm/amdgpu/display: Add irq support for DCN
>>> drm/amdgpu/display: Enable DCN in DC
>>>
>>> Hawking Zhang (13):
>>> drm/amd/amdgpu: fill in raven case in soc15 early init
>>> drm/amdgpu/gfx9: extend rlc fw setup
>>> drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
>>> drm/amdgpu: correct gfx9 csb size
>>> drm/amdgpu/gfx9: add rlc bo init/fini
>>> drm/amdgpu/gfx9: rlc save&restore list programming
>>> drm/amdgpu: init gfx power gating on raven
>>> drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
>>> drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
>>> drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
>>> drm/amdgpu/gfx9: allow updating gfx cgpg state
>>> drm/amdgpu/gfx9: allow updating gfx mgpg state
>>> drm/amdgpu: enable dcn1.0 dc support on raven
>>>
>>> Huang Rui (17):
>>> drm/amdgpu/soc15: add clock gating functions for raven
>>> drm/amdgpu: enable soc15 clock gating flags for raven
>>> drm/amdgpu: add gfx clock gating for raven
>>> drm/amdgpu: add raven clock gating and light sleep for mmhub
>>> drm/amdgpu: enable MC MGCG and LS for raven
>>> drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
>>> drm/amdgpu: enable sdma v4 MGCG and LS for raven
>>> drm/amdgpu: init sdma power gating for raven
>>> drm/amdgpu/sdma4: add dynamic power gating for raven
>>> drm/amdgpu: enable sdma power gating for raven
>>> drm/amdgpu: add nbio MGCG for raven
>>> drm/amdgpu: add psp v10 function callback for raven
>>> drm/amdgpu: add psp v10 ip block
>>> drm/amdgpu: register the psp v10 function pointers at psp sw_init
>>> drm/amdgpu/soc15: add psp ip block
>>> drm/amdgpu/vcn: add sw clock gating
>>> drm/amdgpu: enable sw clock gating for vcn
>>>
>>> Leo Liu (32):
>>> drm/amdgpu: add initial vcn support and decode tests
>>> drm/amdgpu: add encode tests for vcn
>>> drm/amdgpu: add vcn ip block functions (v2)
>>> drm/amdgpu: add vcn decode ring support
>>> drm/amdgpu: add vcn decode ring type and functions
>>> drm/amdgpu: add vcn irq functions
>>> drm/amdgpu: add vcn ip block and type
>>> drm/amdgpu: move amdgpu_vcn structure to vcn header
>>> drm/amdgpu: re-group the functions in amdgpu_vcn.c
>>> drm/amdgpu: move vcn ring test to amdgpu_vcn.c
>>> drm/amdgpu: expose vcn RB command
>>> drm/amdgpu: add a ring func for vcn start command
>>> drm/amdgpu: implement vcn start RB command
>>> drm/amdgpu: implement insert end ring function for vcn decode
>>> drm/amdgpu/vcn: implement ib tests with new message buffer interface
>>> uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
>>> uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
>>> drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
>>> drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
>>> drm/amdgpu: Disable uvd and vce free handles for raven
>>> drm/amdgpu: implement new vcn cache window programming
>>> drm/amdgpu: add vcn ip block to soc15
>>> drm/amdgpu: change vcn dec rb command specific for decode
>>> drm/amdgpu: add vcn enc rings
>>> drm/amdgpu: add vcn enc ring type and functions
>>> drm/amdgpu: add vcn enc irq support
>>> drm/amdgpu: enable vcn encode ring tests
>>> drm/amdgpu: add vcn enc ib test
>>> drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
>>> drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
>>> drm/amdgpu: add vcn firmware header offset
>>> drm/amdgpu: update vcn decode create msg
>>>
>>> Maruthi Srinivas Bayyavarapu (12):
>>> ASoC: AMD: add ACP 3.x IP register header
>>> ASoC: AMD: add ACP3.0 PCI driver
>>> ASoC: AMD: create ACP3x PCM platform device
>>> ASoC: AMD: add ACP3x PCM platform driver
>>> ASoC: AMD: handle ACP3x i2s watermark interrupt
>>> ASoC: AMD: add ACP3x PCM driver DMA ops
>>> ASoC: AMD: add ACP3x i2s ops
>>> ASoC: AMD: add ACP3x TDM mode support
>>> ASoC: AMD: Add ACP3x runtime pm ops
>>> ASoC: AMD: Add ACP3x system resume pm op
>>> ASoC: AMD: enable ACP3x drivers build
>>> ASoC: AMD: create/add dummy codec and machine devices/drivers
>>>
>>> Rex Zhu (5):
>>> drm/amdgpu/powerplay: add header file for smu10. (v2)
>>> drm/amdgpu: add raven related define in pptable.h.
>>> drm/amd/powerplay: add ppt_v3 define
>>> drm/amd/powerplay: add raven support in smumgr. (v2)
>>> drm/amd/powerplay: add raven support in hwmgr. (v2)
>>>
>>> Vijendar Mukunda (1):
>>> soc/amd/raven: Disabling TDM mode flag
>>>
>>> drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 111 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 654 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 77 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 793 +-
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 25 +-
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +-
>>> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +
>>> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 +
>>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +
>>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +
>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 128 +-
>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 103 +-
>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
>>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1190 +
>>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +
>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +-
>>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 +-
>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
>>> drivers/gpu/drm/amd/display/dc/Makefile | 5 +
>>> .../amd/display/dc/bios/command_table_helper2.c | 5 +
>>> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 +
>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 +
>>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 +
>>> drivers/gpu/drm/amd/display/dc/dc.h | 18 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 +
>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +
>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 +
>>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
>>> .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +
>>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 +
>>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
>>> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 +
>>> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
>>> .../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +
>>> .../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +
>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +
>>> drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
>>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
>>> drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
>>> drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +
>>> .../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
>>> .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 +
>>> .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
>>> .../drm/amd/display/dc/dml/display_mode_structs.h | 429 +
>>> .../drm/amd/display/dc/dml/display_mode_support.c | 2326 +
>>> .../drm/amd/display/dc/dml/display_mode_support.h | 199 +
>>> .../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +
>>> .../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
>>> .../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +
>>> .../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 +
>>> .../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +
>>> .../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
>>> .../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +
>>> .../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
>>> .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 +
>>> .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
>>> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
>>> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
>>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>>> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 +
>>> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 +
>>> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +
>>> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
>>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
>>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>>> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +
>>> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 +
>>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>>> drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
>>> drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 +
>>> drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 +
>>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
>>> drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
>>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 +
>>> drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +
>>> drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
>>> .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 +
>>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
>>> .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +
>>> .../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
>>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
>>> drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
>>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +-
>>> .../include/asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ++
>>> .../include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 14087 +++
>>> .../include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 54316 ++++++++
>>> .../include/asic_reg/raven1/GC/gc_9_1_default.h | 4005 +
>>> .../amd/include/asic_reg/raven1/GC/gc_9_1_offset.h | 7491 ++
>>> .../include/asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 +++++
>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 +
>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_offset.h | 1999 +
>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h | 9790 ++
>>> .../include/asic_reg/raven1/MP/mp_10_0_default.h | 182 +
>>> .../include/asic_reg/raven1/MP/mp_10_0_offset.h | 336 +
>>> .../include/asic_reg/raven1/MP/mp_10_0_sh_mask.h | 886 +
>>> .../asic_reg/raven1/NBIO/nbio_7_0_default.h | 14865 +++
>>> .../include/asic_reg/raven1/NBIO/nbio_7_0_offset.h | 4640 +
>>> .../asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h | 118945
>> ++++++++++++++++++
>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_default.h | 242 +
>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_offset.h | 459 +
>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 +
>>> .../include/asic_reg/raven1/THM/thm_10_0_default.h | 141 +
>>> .../include/asic_reg/raven1/THM/thm_10_0_offset.h | 257 +
>>> .../include/asic_reg/raven1/THM/thm_10_0_sh_mask.h | 885 +
>>> .../include/asic_reg/raven1/VCN/vcn_1_0_default.h | 202 +
>>> .../include/asic_reg/raven1/VCN/vcn_1_0_offset.h | 376 +
>>> .../include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h | 1308 +
>>> .../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 +
>>> drivers/gpu/drm/amd/include/pptable.h | 57 +-
>>> drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
>>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>>> .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +
>>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
>>> drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +
>>> drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +
>>> .../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +
>>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
>>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 399 +
>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 +
>>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>>> include/uapi/drm/amdgpu_drm.h | 5 +-
>>> sound/soc/amd/Kconfig | 4 +
>>> sound/soc/amd/Makefile | 1 +
>>> sound/soc/amd/raven/Makefile | 8 +
>>> sound/soc/amd/raven/acp3x-dummy5102.c | 136 +
>>> sound/soc/amd/raven/acp3x-pcm-dma.c | 805 +
>>> sound/soc/amd/raven/acp3x.h | 34 +
>>> sound/soc/amd/raven/chip_offset_byte.h | 655 +
>>> sound/soc/amd/raven/dummy-w5102.c | 102 +
>>> sound/soc/amd/raven/pci-acp3x.c | 189 +
>>> 175 files changed, 314946 insertions(+), 121 deletions(-)
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
>>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_defa
>> ult.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offs
>> et.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_
>> mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default
>> .h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.
>> h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_ma
>> sk.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
>>> create mode 100644
>> drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
>>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
>>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
>>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
>>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
>>> create mode 100644 sound/soc/amd/raven/Makefile
>>> create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
>>> create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
>>> create mode 100644 sound/soc/amd/raven/acp3x.h
>>> create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
>>> create mode 100644 sound/soc/amd/raven/dummy-w5102.c
>>> create mode 100644 sound/soc/amd/raven/pci-acp3x.c
>>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH 000/117] Raven Support
[not found] ` <aad7efe0-e909-a2b8-b7ee-8abb90534e5b-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-05-12 2:50 ` zhoucm1
0 siblings, 0 replies; 114+ messages in thread
From: zhoucm1 @ 2017-05-12 2:50 UTC (permalink / raw)
To: Christian König, Deucher, Alexander, Alex Deucher,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 2017年05月12日 02:08, Christian König wrote:
> Am 10.05.2017 um 21:30 schrieb Deucher, Alexander:
>>> -----Original Message-----
>>> From: Christian König [mailto:deathsimple@vodafone.de]
>>> Sent: Wednesday, May 10, 2017 3:29 PM
>>> To: Alex Deucher; amd-gfx@lists.freedesktop.org
>>> Cc: Deucher, Alexander
>>> Subject: Re: [PATCH 000/117] Raven Support
>>>
>>> Am 10.05.2017 um 20:45 schrieb Alex Deucher:
>>>> This patch set adds support for the new "Raven" APU.
>>>>
>>>> The first 12 patches add support for the new ACP
>>>> audio hardware on Raven. Patches 11 and 12 are not
>>>> meant for upstream, they are for early hardware testing.
>>>> The rest add GPU support. Patches 17-24 are register
>>>> headers (which are relatively large), so I'm not sending
>>>> them out.
>>>>
>>>> You can view the whole patch set here:
>>>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=raven
>>> Patches #1-#13 are Acked-by: Christian König
>>> <christian.koenig@amd.com>.
>>>
>>> Patches #14-#16 are Reviewed-by: Christian König
>>> <christian.koenig@amd.com>.
>>>
>>> Patches #17-#25 are somehow missing on the mailing lists at the moment.
>> 17-24 are just register headers. I didn’t send them out because they
>> are too big.
>
> Ok, that makes sense. Only had time to skimmed over the set.
>
> Found a few ends which still need some work. For example has anybody
> tested multi level page tables on Raven yet?
I've used it for a long time and not found issues, we just need set that
the levels to 3 after Alex pushes these patches.
Regards,
David Zhou
>
> But that not blocking so feel free to add an Acked-by: Christian König
> <christian.koenig@amd.com>.
>
> Christian.
>
>>
>> Alex
>>
>>> Going to take a look at the rest tomorrow.
>>>
>>> Christian.
>>>
>>>> Alex Deucher (12):
>>>> drm/amdgpu: add gpu_info firmware (v3)
>>>> drm/amdgpu: parse the gpu_info firmware (v4)
>>>> drm/amdgpu/gfx9: drop duplicate gfx info init (v3)
>>>> drm/amdgpu: add register headers for DCN 1.0
>>>> drm/amdgpu: add register headers for GC 9.1
>>>> drm/amdgpu: add register headers for MMHUB 9.1
>>>> drm/amdgpu: add register headers for MP 10.0
>>>> drm/amdgpu: add register headers for NBIO 7.0
>>>> drm/amdgpu: add register headers for SDMA 4.1
>>>> drm/amdgpu: add register headers for THM 10.0
>>>> drm/amdgpu: add register headers for VCN 1.0
>>>> drm/amdgpu/raven: power up/down VCN via the SMU (v2)
>>>>
>>>> Andrey Grodzovsky (1):
>>>> drm/amd: Add DCN ivsrcids (v2)
>>>>
>>>> Chunming Zhou (17):
>>>> drm/amdgpu: add RAVEN family id definition
>>>> drm/amdgpu: add Raven ip blocks
>>>> drm/amdgpu/soc15: add Raven golden setting
>>>> drm/amdgpu: add Raven chip id case for ucode
>>>> drm/amdgpu: add module firmware for raven
>>>> drm/amdgpu: add gc9.1 golden setting (v2)
>>>> drm/amdgpu/gfx9: add chip name for raven when initializing
>>>> microcode
>>>> drm/amdgpu/gfx9: add raven gfx config
>>>> drm/amdgpu: add raven case for gmc9 golden setting
>>>> drm/amdgpu/gmc9: set mc vm fb offset for raven
>>>> drm/amdgpu/gmc9: change fb offset sequence so that used wider
>>>> drm/amdgpu: add Raven sdma golden setting and chip id case
>>>> drm/amdgpu: add nbio7 support
>>>> drm/amdgpu: apply nbio7 for Raven (v3)
>>>> drm/amd/powerplay/rv: power up/down sdma via the SMU
>>>> drm/amdgpu/powerplay/raven: add smu block and enable powerplay
>>>> drm/amdgpu: add RAVEN pci id
>>>>
>>>> Harry Wentland (7):
>>>> drm/amdgpu/display: Add calcs code for DCN
>>>> drm/amdgpu/display: Add core dc support for DCN
>>>> drm/amdgpu/display: Add dml support for DCN
>>>> drm/amdgpu/display: Add gpio support for DCN
>>>> drm/amdgpu/display: Add i2c/aux support for DCN
>>>> drm/amdgpu/display: Add irq support for DCN
>>>> drm/amdgpu/display: Enable DCN in DC
>>>>
>>>> Hawking Zhang (13):
>>>> drm/amd/amdgpu: fill in raven case in soc15 early init
>>>> drm/amdgpu/gfx9: extend rlc fw setup
>>>> drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG
>>>> drm/amdgpu: correct gfx9 csb size
>>>> drm/amdgpu/gfx9: add rlc bo init/fini
>>>> drm/amdgpu/gfx9: rlc save&restore list programming
>>>> drm/amdgpu: init gfx power gating on raven
>>>> drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu
>>>> handshake
>>>> drm/amdgpu/gfx9: add enable/disable funcs for cp power gating
>>>> drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state
>>>> drm/amdgpu/gfx9: allow updating gfx cgpg state
>>>> drm/amdgpu/gfx9: allow updating gfx mgpg state
>>>> drm/amdgpu: enable dcn1.0 dc support on raven
>>>>
>>>> Huang Rui (17):
>>>> drm/amdgpu/soc15: add clock gating functions for raven
>>>> drm/amdgpu: enable soc15 clock gating flags for raven
>>>> drm/amdgpu: add gfx clock gating for raven
>>>> drm/amdgpu: add raven clock gating and light sleep for mmhub
>>>> drm/amdgpu: enable MC MGCG and LS for raven
>>>> drm/amdgpu: reuse sdma v4 MGCG and LS function for raven
>>>> drm/amdgpu: enable sdma v4 MGCG and LS for raven
>>>> drm/amdgpu: init sdma power gating for raven
>>>> drm/amdgpu/sdma4: add dynamic power gating for raven
>>>> drm/amdgpu: enable sdma power gating for raven
>>>> drm/amdgpu: add nbio MGCG for raven
>>>> drm/amdgpu: add psp v10 function callback for raven
>>>> drm/amdgpu: add psp v10 ip block
>>>> drm/amdgpu: register the psp v10 function pointers at psp sw_init
>>>> drm/amdgpu/soc15: add psp ip block
>>>> drm/amdgpu/vcn: add sw clock gating
>>>> drm/amdgpu: enable sw clock gating for vcn
>>>>
>>>> Leo Liu (32):
>>>> drm/amdgpu: add initial vcn support and decode tests
>>>> drm/amdgpu: add encode tests for vcn
>>>> drm/amdgpu: add vcn ip block functions (v2)
>>>> drm/amdgpu: add vcn decode ring support
>>>> drm/amdgpu: add vcn decode ring type and functions
>>>> drm/amdgpu: add vcn irq functions
>>>> drm/amdgpu: add vcn ip block and type
>>>> drm/amdgpu: move amdgpu_vcn structure to vcn header
>>>> drm/amdgpu: re-group the functions in amdgpu_vcn.c
>>>> drm/amdgpu: move vcn ring test to amdgpu_vcn.c
>>>> drm/amdgpu: expose vcn RB command
>>>> drm/amdgpu: add a ring func for vcn start command
>>>> drm/amdgpu: implement vcn start RB command
>>>> drm/amdgpu: implement insert end ring function for vcn decode
>>>> drm/amdgpu/vcn: implement ib tests with new message buffer
>>>> interface
>>>> uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS
>>>> uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS
>>>> drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query
>>>> drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC
>>>> drm/amdgpu: Disable uvd and vce free handles for raven
>>>> drm/amdgpu: implement new vcn cache window programming
>>>> drm/amdgpu: add vcn ip block to soc15
>>>> drm/amdgpu: change vcn dec rb command specific for decode
>>>> drm/amdgpu: add vcn enc rings
>>>> drm/amdgpu: add vcn enc ring type and functions
>>>> drm/amdgpu: add vcn enc irq support
>>>> drm/amdgpu: enable vcn encode ring tests
>>>> drm/amdgpu: add vcn enc ib test
>>>> drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query
>>>> drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC
>>>> drm/amdgpu: add vcn firmware header offset
>>>> drm/amdgpu: update vcn decode create msg
>>>>
>>>> Maruthi Srinivas Bayyavarapu (12):
>>>> ASoC: AMD: add ACP 3.x IP register header
>>>> ASoC: AMD: add ACP3.0 PCI driver
>>>> ASoC: AMD: create ACP3x PCM platform device
>>>> ASoC: AMD: add ACP3x PCM platform driver
>>>> ASoC: AMD: handle ACP3x i2s watermark interrupt
>>>> ASoC: AMD: add ACP3x PCM driver DMA ops
>>>> ASoC: AMD: add ACP3x i2s ops
>>>> ASoC: AMD: add ACP3x TDM mode support
>>>> ASoC: AMD: Add ACP3x runtime pm ops
>>>> ASoC: AMD: Add ACP3x system resume pm op
>>>> ASoC: AMD: enable ACP3x drivers build
>>>> ASoC: AMD: create/add dummy codec and machine devices/drivers
>>>>
>>>> Rex Zhu (5):
>>>> drm/amdgpu/powerplay: add header file for smu10. (v2)
>>>> drm/amdgpu: add raven related define in pptable.h.
>>>> drm/amd/powerplay: add ppt_v3 define
>>>> drm/amd/powerplay: add raven support in smumgr. (v2)
>>>> drm/amd/powerplay: add raven support in hwmgr. (v2)
>>>>
>>>> Vijendar Mukunda (1):
>>>> soc/amd/raven: Disabling TDM mode flag
>>>>
>>>> drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 12 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 111 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 3 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 23 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 1 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 30 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 25 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 654 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 77 +
>>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 793 +-
>>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 5 +
>>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 2 +-
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 25 +-
>>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 50 +-
>>>> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 220 +
>>>> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h | 49 +
>>>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 309 +
>>>> drivers/gpu/drm/amd/amdgpu/psp_v10_0.h | 41 +
>>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 128 +-
>>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 103 +-
>>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 1 +
>>>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1190 +
>>>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h | 29 +
>>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +-
>>>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 167 +-
>>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +-
>>>> drivers/gpu/drm/amd/display/dc/Makefile | 5 +
>>>> .../amd/display/dc/bios/command_table_helper2.c | 5 +
>>>> drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 +
>>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 3629 +
>>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h | 37 +
>>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.c | 104 +
>>>> .../gpu/drm/amd/display/dc/calcs/dcn_calc_math.h | 40 +
>>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 1366 +
>>>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 +
>>>> drivers/gpu/drm/amd/display/dc/dc.h | 18 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 +
>>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +
>>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 +
>>>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +-
>>>> .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +
>>>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 +
>>>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 10 +
>>>> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1866 +
>>>> .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 38 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 883 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 549 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 1102 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 553 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 376 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 135 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 801 +
>>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 622 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1475 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 47 +
>>>> .../amd/display/dc/dcn10/dcn10_timing_generator.c | 1202 +
>>>> .../amd/display/dc/dcn10/dcn10_timing_generator.h | 335 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 1057 +
>>>> .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 416 +
>>>> drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +
>>>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 +
>>>> drivers/gpu/drm/amd/display/dc/dml/Makefile | 22 +
>>>> drivers/gpu/drm/amd/display/dc/dml/dc_features.h | 557 +
>>>> .../drm/amd/display/dc/dml/display_mode_enums.h | 111 +
>>>> .../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 147 +
>>>> .../gpu/drm/amd/display/dc/dml/display_mode_lib.h | 52 +
>>>> .../drm/amd/display/dc/dml/display_mode_structs.h | 429 +
>>>> .../drm/amd/display/dc/dml/display_mode_support.c | 2326 +
>>>> .../drm/amd/display/dc/dml/display_mode_support.h | 199 +
>>>> .../drm/amd/display/dc/dml/display_pipe_clocks.c | 367 +
>>>> .../drm/amd/display/dc/dml/display_pipe_clocks.h | 41 +
>>>> .../drm/amd/display/dc/dml/display_rq_dlg_calc.c | 2254 +
>>>> .../drm/amd/display/dc/dml/display_rq_dlg_calc.h | 139 +
>>>> .../amd/display/dc/dml/display_rq_dlg_helpers.c | 320 +
>>>> .../amd/display/dc/dml/display_rq_dlg_helpers.h | 66 +
>>>> .../gpu/drm/amd/display/dc/dml/display_watermark.c | 1281 +
>>>> .../gpu/drm/amd/display/dc/dml/display_watermark.h | 98 +
>>>> .../gpu/drm/amd/display/dc/dml/dml_common_defs.c | 148 +
>>>> .../gpu/drm/amd/display/dc/dml/dml_common_defs.h | 51 +
>>>> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.c | 73 +
>>>> .../gpu/drm/amd/display/dc/dml/soc_bounding_box.h | 36 +
>>>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>>>> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 192 +
>>>> .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.h | 32 +
>>>> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 408 +
>>>> .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +-
>>>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +
>>>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>>>> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 125 +
>>>> .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h | 32 +
>>>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>>>> drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 +
>>>> drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 +
>>>> drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 629 +
>>>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 +
>>>> drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 +
>>>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 +
>>>> drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +
>>>> drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 +
>>>> .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 +
>>>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
>>>> .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 361 +
>>>> .../amd/display/dc/irq/dcn10/irq_service_dcn10.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 +
>>>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 +
>>>> drivers/gpu/drm/amd/display/include/dal_types.h | 5 +-
>>>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +-
>>>> .../include/asic_reg/raven1/DCN/dcn_1_0_default.h | 7988 ++
>>>> .../include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 14087 +++
>>>> .../include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 54316 ++++++++
>>>> .../include/asic_reg/raven1/GC/gc_9_1_default.h | 4005 +
>>>> .../amd/include/asic_reg/raven1/GC/gc_9_1_offset.h | 7491 ++
>>>> .../include/asic_reg/raven1/GC/gc_9_1_sh_mask.h | 31191 +++++
>>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_default.h | 1028 +
>>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_offset.h | 1999 +
>>>> .../asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h | 9790 ++
>>>> .../include/asic_reg/raven1/MP/mp_10_0_default.h | 182 +
>>>> .../include/asic_reg/raven1/MP/mp_10_0_offset.h | 336 +
>>>> .../include/asic_reg/raven1/MP/mp_10_0_sh_mask.h | 886 +
>>>> .../asic_reg/raven1/NBIO/nbio_7_0_default.h | 14865 +++
>>>> .../include/asic_reg/raven1/NBIO/nbio_7_0_offset.h | 4640 +
>>>> .../asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h | 118945
>>> ++++++++++++++++++
>>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_default.h | 242 +
>>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_offset.h | 459 +
>>>> .../asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h | 1658 +
>>>> .../include/asic_reg/raven1/THM/thm_10_0_default.h | 141 +
>>>> .../include/asic_reg/raven1/THM/thm_10_0_offset.h | 257 +
>>>> .../include/asic_reg/raven1/THM/thm_10_0_sh_mask.h | 885 +
>>>> .../include/asic_reg/raven1/VCN/vcn_1_0_default.h | 202 +
>>>> .../include/asic_reg/raven1/VCN/vcn_1_0_offset.h | 376 +
>>>> .../include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h | 1308 +
>>>> .../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 +
>>>> drivers/gpu/drm/amd/include/pptable.h | 57 +-
>>>> drivers/gpu/drm/amd/powerplay/eventmgr/eventmgr.c | 4 +-
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/processpptables.c | 4 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 974 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 295 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | 43 +
>>>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 3 +-
>>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 7 +-
>>>> drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 76 +
>>>> drivers/gpu/drm/amd/powerplay/inc/smu10.h | 188 +
>>>> .../gpu/drm/amd/powerplay/inc/smu10_driver_if.h | 116 +
>>>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 1 +
>>>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 399 +
>>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h | 62 +
>>>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>>>> include/uapi/drm/amdgpu_drm.h | 5 +-
>>>> sound/soc/amd/Kconfig | 4 +
>>>> sound/soc/amd/Makefile | 1 +
>>>> sound/soc/amd/raven/Makefile | 8 +
>>>> sound/soc/amd/raven/acp3x-dummy5102.c | 136 +
>>>> sound/soc/amd/raven/acp3x-pcm-dma.c | 805 +
>>>> sound/soc/amd/raven/acp3x.h | 34 +
>>>> sound/soc/amd/raven/chip_offset_byte.h | 655 +
>>>> sound/soc/amd/raven/dummy-w5102.c | 102 +
>>>> sound/soc/amd/raven/pci-acp3x.c | 189 +
>>>> 175 files changed, 314946 insertions(+), 121 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/Makefile
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/Makefile
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dc_features.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_watermark.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/display_watermark.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_defa
>>> ult.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offs
>>> et.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_
>>> mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default
>>> .h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.
>>> h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_ma
>>> sk.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu10.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/inc/smu10_driver_if.h
>>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
>>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
>>>> create mode 100644 sound/soc/amd/raven/Makefile
>>>> create mode 100644 sound/soc/amd/raven/acp3x-dummy5102.c
>>>> create mode 100644 sound/soc/amd/raven/acp3x-pcm-dma.c
>>>> create mode 100644 sound/soc/amd/raven/acp3x.h
>>>> create mode 100644 sound/soc/amd/raven/chip_offset_byte.h
>>>> create mode 100644 sound/soc/amd/raven/dummy-w5102.c
>>>> create mode 100644 sound/soc/amd/raven/pci-acp3x.c
>>>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 114+ messages in thread
end of thread, other threads:[~2017-05-12 2:50 UTC | newest]
Thread overview: 114+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-10 18:45 [PATCH 000/117] Raven Support Alex Deucher
[not found] ` <1494442068-8202-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2017-05-10 18:46 ` [PATCH 001/117] ASoC: AMD: add ACP 3.x IP register header Alex Deucher
2017-05-10 18:46 ` [PATCH 002/117] ASoC: AMD: add ACP3.0 PCI driver Alex Deucher
2017-05-10 18:46 ` [PATCH 003/117] ASoC: AMD: create ACP3x PCM platform device Alex Deucher
2017-05-10 18:46 ` [PATCH 004/117] ASoC: AMD: add ACP3x PCM platform driver Alex Deucher
2017-05-10 18:46 ` [PATCH 005/117] ASoC: AMD: handle ACP3x i2s watermark interrupt Alex Deucher
2017-05-10 18:46 ` [PATCH 006/117] ASoC: AMD: add ACP3x PCM driver DMA ops Alex Deucher
2017-05-10 18:46 ` [PATCH 007/117] ASoC: AMD: add ACP3x i2s ops Alex Deucher
2017-05-10 18:46 ` [PATCH 008/117] ASoC: AMD: add ACP3x TDM mode support Alex Deucher
2017-05-10 18:46 ` [PATCH 009/117] ASoC: AMD: Add ACP3x runtime pm ops Alex Deucher
2017-05-10 18:46 ` [PATCH 010/117] ASoC: AMD: Add ACP3x system resume pm op Alex Deucher
2017-05-10 18:46 ` [PATCH 011/117] ASoC: AMD: enable ACP3x drivers build Alex Deucher
2017-05-10 18:46 ` [PATCH 012/117] ASoC: AMD: create/add dummy codec and machine devices/drivers Alex Deucher
2017-05-10 18:46 ` [PATCH 013/117] soc/amd/raven: Disabling TDM mode flag Alex Deucher
2017-05-10 18:46 ` [PATCH 014/117] drm/amdgpu: add gpu_info firmware (v3) Alex Deucher
2017-05-10 18:46 ` [PATCH 015/117] drm/amdgpu: parse the gpu_info firmware (v4) Alex Deucher
2017-05-10 18:46 ` [PATCH 016/117] drm/amdgpu/gfx9: drop duplicate gfx info init (v3) Alex Deucher
2017-05-10 18:46 ` [PATCH 025/117] drm/amdgpu: add RAVEN family id definition Alex Deucher
2017-05-10 18:46 ` [PATCH 026/117] drm/amdgpu: add Raven ip blocks Alex Deucher
2017-05-10 18:46 ` [PATCH 027/117] drm/amdgpu/soc15: add Raven golden setting Alex Deucher
2017-05-10 18:46 ` [PATCH 028/117] drm/amd/amdgpu: fill in raven case in soc15 early init Alex Deucher
2017-05-10 18:46 ` [PATCH 029/117] drm/amdgpu/soc15: add clock gating functions for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 030/117] drm/amdgpu: enable soc15 clock gating flags " Alex Deucher
2017-05-10 18:46 ` [PATCH 031/117] drm/amdgpu: add Raven chip id case for ucode Alex Deucher
2017-05-10 18:46 ` [PATCH 032/117] drm/amdgpu: add module firmware for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 033/117] drm/amdgpu: add gc9.1 golden setting (v2) Alex Deucher
2017-05-10 18:46 ` [PATCH 034/117] drm/amdgpu/gfx9: add chip name for raven when initializing microcode Alex Deucher
2017-05-10 18:46 ` [PATCH 035/117] drm/amdgpu/gfx9: add raven gfx config Alex Deucher
2017-05-10 18:46 ` [PATCH 036/117] drm/amdgpu: add gfx clock gating for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 037/117] drm/amdgpu/gfx9: extend rlc fw setup Alex Deucher
2017-05-10 18:46 ` [PATCH 038/117] drm/amdgpu/gfx9: enable cp interrupt for CGCG/CGLS/MGCG Alex Deucher
2017-05-10 18:46 ` [PATCH 039/117] drm/amdgpu: correct gfx9 csb size Alex Deucher
2017-05-10 18:46 ` [PATCH 040/117] drm/amdgpu/gfx9: add rlc bo init/fini Alex Deucher
2017-05-10 18:46 ` [PATCH 041/117] drm/amdgpu/gfx9: rlc save&restore list programming Alex Deucher
2017-05-10 18:46 ` [PATCH 042/117] drm/amdgpu: init gfx power gating on raven Alex Deucher
2017-05-10 18:46 ` [PATCH 043/117] drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake Alex Deucher
2017-05-10 18:46 ` [PATCH 044/117] drm/amdgpu/gfx9: add enable/disable funcs for cp power gating Alex Deucher
2017-05-10 18:46 ` [PATCH 045/117] drm/amdgpu/gfx9: allow updating sck slowdown and cp pg state Alex Deucher
2017-05-10 18:46 ` [PATCH 046/117] drm/amdgpu/gfx9: allow updating gfx cgpg state Alex Deucher
2017-05-10 18:46 ` [PATCH 047/117] drm/amdgpu/gfx9: allow updating gfx mgpg state Alex Deucher
2017-05-10 18:46 ` [PATCH 048/117] drm/amdgpu: add raven case for gmc9 golden setting Alex Deucher
2017-05-10 18:46 ` [PATCH 049/117] drm/amdgpu/gmc9: set mc vm fb offset for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 050/117] drm/amdgpu/gmc9: change fb offset sequence so that used wider Alex Deucher
2017-05-10 18:46 ` [PATCH 051/117] drm/amdgpu: add raven clock gating and light sleep for mmhub Alex Deucher
2017-05-10 18:46 ` [PATCH 052/117] drm/amdgpu: enable MC MGCG and LS for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 053/117] drm/amdgpu: add Raven sdma golden setting and chip id case Alex Deucher
2017-05-10 18:46 ` [PATCH 054/117] drm/amdgpu: reuse sdma v4 MGCG and LS function for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 055/117] drm/amdgpu: enable sdma v4 MGCG and LS " Alex Deucher
2017-05-10 18:46 ` [PATCH 056/117] drm/amdgpu: init sdma power gating " Alex Deucher
2017-05-10 18:46 ` [PATCH 057/117] drm/amdgpu/sdma4: add dynamic " Alex Deucher
2017-05-10 18:46 ` [PATCH 058/117] drm/amdgpu: enable sdma " Alex Deucher
2017-05-10 18:46 ` [PATCH 059/117] drm/amdgpu: add nbio7 support Alex Deucher
2017-05-10 18:46 ` [PATCH 060/117] drm/amdgpu: apply nbio7 for Raven (v3) Alex Deucher
2017-05-10 18:46 ` [PATCH 061/117] drm/amdgpu: add nbio MGCG for raven Alex Deucher
2017-05-10 18:46 ` [PATCH 062/117] drm/amdgpu: add psp v10 function callback " Alex Deucher
2017-05-10 18:46 ` [PATCH 063/117] drm/amdgpu: add psp v10 ip block Alex Deucher
2017-05-10 18:46 ` [PATCH 064/117] drm/amdgpu: register the psp v10 function pointers at psp sw_init Alex Deucher
2017-05-10 18:46 ` [PATCH 065/117] drm/amdgpu/soc15: add psp ip block Alex Deucher
2017-05-10 18:46 ` [PATCH 066/117] drm/amdgpu: add initial vcn support and decode tests Alex Deucher
2017-05-10 18:46 ` [PATCH 067/117] drm/amdgpu: add encode tests for vcn Alex Deucher
2017-05-10 18:46 ` [PATCH 068/117] drm/amdgpu: add vcn ip block functions (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 069/117] drm/amdgpu: add vcn decode ring support Alex Deucher
2017-05-10 18:47 ` [PATCH 070/117] drm/amdgpu: add vcn decode ring type and functions Alex Deucher
2017-05-10 18:47 ` [PATCH 071/117] drm/amdgpu: add vcn irq functions Alex Deucher
2017-05-10 18:47 ` [PATCH 072/117] drm/amdgpu: add vcn ip block and type Alex Deucher
2017-05-10 18:47 ` [PATCH 073/117] drm/amdgpu: move amdgpu_vcn structure to vcn header Alex Deucher
2017-05-10 18:47 ` [PATCH 074/117] drm/amdgpu: re-group the functions in amdgpu_vcn.c Alex Deucher
2017-05-10 18:47 ` [PATCH 075/117] drm/amdgpu: move vcn ring test to amdgpu_vcn.c Alex Deucher
2017-05-10 18:47 ` [PATCH 076/117] drm/amdgpu: expose vcn RB command Alex Deucher
2017-05-10 18:47 ` [PATCH 077/117] drm/amdgpu: add a ring func for vcn start command Alex Deucher
2017-05-10 18:47 ` [PATCH 078/117] drm/amdgpu: implement vcn start RB command Alex Deucher
2017-05-10 18:47 ` [PATCH 079/117] drm/amdgpu: implement insert end ring function for vcn decode Alex Deucher
2017-05-10 18:47 ` [PATCH 080/117] drm/amdgpu/vcn: implement ib tests with new message buffer interface Alex Deucher
2017-05-10 18:47 ` [PATCH 081/117] uapi/drm: add AMDGPU_HW_IP_VCN_DEC for decode CS Alex Deucher
2017-05-10 18:47 ` [PATCH 082/117] uapi/drm: add AMDGPU_HW_IP_VCN_ENC for encode CS Alex Deucher
2017-05-10 18:47 ` [PATCH 083/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_DEC to info query Alex Deucher
2017-05-10 18:47 ` [PATCH 084/117] drm/amdgpu: get cs support of AMDGPU_HW_IP_VCN_DEC Alex Deucher
2017-05-10 18:47 ` [PATCH 085/117] drm/amdgpu: Disable uvd and vce free handles for raven Alex Deucher
2017-05-10 18:47 ` [PATCH 086/117] drm/amdgpu: implement new vcn cache window programming Alex Deucher
2017-05-10 18:47 ` [PATCH 087/117] drm/amdgpu: add vcn ip block to soc15 Alex Deucher
2017-05-10 18:47 ` [PATCH 088/117] drm/amdgpu: change vcn dec rb command specific for decode Alex Deucher
2017-05-10 18:47 ` [PATCH 089/117] drm/amdgpu: add vcn enc rings Alex Deucher
2017-05-10 18:47 ` [PATCH 090/117] drm/amdgpu: add vcn enc ring type and functions Alex Deucher
2017-05-10 18:47 ` [PATCH 091/117] drm/amdgpu: add vcn enc irq support Alex Deucher
2017-05-10 18:47 ` [PATCH 092/117] drm/amdgpu: enable vcn encode ring tests Alex Deucher
2017-05-10 18:47 ` [PATCH 093/117] drm/amdgpu: add vcn enc ib test Alex Deucher
2017-05-10 18:47 ` [PATCH 094/117] drm/amdgpu: add AMDGPU_HW_IP_VCN_ENC to info query Alex Deucher
2017-05-10 18:47 ` [PATCH 095/117] drm/amdgpu: get cs support for AMDGPU_HW_IP_VCN_ENC Alex Deucher
2017-05-10 18:47 ` [PATCH 096/117] drm/amdgpu: add vcn firmware header offset Alex Deucher
2017-05-10 18:47 ` [PATCH 097/117] drm/amdgpu: update vcn decode create msg Alex Deucher
2017-05-10 18:47 ` [PATCH 098/117] drm/amdgpu/vcn: add sw clock gating Alex Deucher
2017-05-10 18:47 ` [PATCH 099/117] drm/amdgpu: enable sw clock gating for vcn Alex Deucher
2017-05-10 18:47 ` [PATCH 100/117] drm/amdgpu/powerplay: add header file for smu10. (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 101/117] drm/amdgpu: add raven related define in pptable.h Alex Deucher
2017-05-10 18:47 ` [PATCH 102/117] drm/amd/powerplay: add ppt_v3 define Alex Deucher
2017-05-10 18:47 ` [PATCH 103/117] drm/amd/powerplay: add raven support in smumgr. (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 104/117] drm/amd/powerplay: add raven support in hwmgr. (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 105/117] drm/amd/powerplay/rv: power up/down sdma via the SMU Alex Deucher
2017-05-10 18:47 ` [PATCH 106/117] drm/amdgpu/raven: power up/down VCN via the SMU (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 107/117] drm/amdgpu/powerplay/raven: add smu block and enable powerplay Alex Deucher
2017-05-10 18:47 ` [PATCH 108/117] drm/amd: Add DCN ivsrcids (v2) Alex Deucher
2017-05-10 18:47 ` [PATCH 109/117] drm/amdgpu/display: Add calcs code for DCN Alex Deucher
2017-05-10 18:47 ` [PATCH 110/117] drm/amdgpu/display: Add core dc support " Alex Deucher
2017-05-10 18:47 ` [PATCH 111/117] drm/amdgpu/display: Add dml " Alex Deucher
2017-05-10 18:47 ` [PATCH 112/117] drm/amdgpu/display: Add gpio " Alex Deucher
2017-05-10 18:47 ` [PATCH 113/117] drm/amdgpu/display: Add i2c/aux " Alex Deucher
2017-05-10 18:47 ` [PATCH 114/117] drm/amdgpu/display: Add irq " Alex Deucher
2017-05-10 18:47 ` [PATCH 115/117] drm/amdgpu/display: Enable DCN in DC Alex Deucher
2017-05-10 18:47 ` [PATCH 116/117] drm/amdgpu: enable dcn1.0 dc support on raven Alex Deucher
2017-05-10 18:47 ` [PATCH 117/117] drm/amdgpu: add RAVEN pci id Alex Deucher
2017-05-10 19:28 ` [PATCH 000/117] Raven Support Christian König
[not found] ` <9c4b2cc4-3632-6131-4d2a-f08a088a6081-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-05-10 19:30 ` Deucher, Alexander
[not found] ` <BN6PR12MB16526517361BBE472EE0A710F7EC0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-05-11 18:08 ` Christian König
[not found] ` <aad7efe0-e909-a2b8-b7ee-8abb90534e5b-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-05-12 2:50 ` zhoucm1
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