* [PATCH v2 0/6] Samsung clock providers: convert to the new clk_hw API
[not found] <CGME20170424064228eucas1p26228b4b334cc22ad22e77c8dd2e7dcdd@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
[not found] ` <CGME20170424064228eucas1p2543d7f206ac18476891e500991611733@eucas1p2.samsung.com>
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Dear All,
Clock providers should use the new struct clk_hw based API, so convert
all Samsung clock providers and their helper functions to the new approach.
Patches are based on top of linux-next from 20170420.
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Changle log:
v2:
- moved some changes to separate patches as requested by Krzysztof Kozlowski
v1:
- initial version
Marek Szyprowski (6):
clk: samsung: Remove dead code
clk: samsung: Add local variable to match it purpose
clk: samsung: Convert common drivers to the new clk_hw API
clk: samsung: exynos-audss: Convert to the new clk_hw API
clk: samsung: exynos-clkout: Convert to the new clk_hw API
clk: samsung: s5pv210-audss: Convert to the new clk_hw API
drivers/clk/samsung/clk-cpu.c | 15 +++---
drivers/clk/samsung/clk-exynos-audss.c | 55 ++++++++++----------
drivers/clk/samsung/clk-exynos-clkout.c | 18 +++----
drivers/clk/samsung/clk-pll.c | 14 ++---
drivers/clk/samsung/clk-pll.h | 4 --
drivers/clk/samsung/clk-s3c2410-dclk.c | 75 ++++++++++++++-------------
drivers/clk/samsung/clk-s5pv210-audss.c | 50 +++++++++---------
drivers/clk/samsung/clk.c | 91 +++++++++++++++------------------
drivers/clk/samsung/clk.h | 9 ++--
9 files changed, 159 insertions(+), 172 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 1/6] clk: samsung: Remove dead code
[not found] ` <CGME20170424064228eucas1p2543d7f206ac18476891e500991611733@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
2017-04-24 6:49 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
samsung_clk_register_pll2550x() function is not used anymore, so remove its
declaration.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-pll.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a1ca0233cb4b..61eb8abbfd9c 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -103,8 +103,4 @@ struct samsung_pll_rate_table {
unsigned int vsel;
};
-extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
- const char *pname, const void __iomem *reg_base,
- const unsigned long offset);
-
#endif /* __SAMSUNG_CLK_PLL_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 2/6] clk: samsung: Add local variable to match it purpose
[not found] ` <CGME20170424064229eucas1p2367a90a36b5bcb99f48a24e72b29a629@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
2017-04-24 6:53 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-cpu.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 8bf7e805fd34..6e1c6007e721 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -410,6 +410,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
{
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
+ struct clk *parent_clk;
struct clk *clk;
int ret = 0;
@@ -440,15 +441,15 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
goto free_cpuclk;
}
- clk = __clk_lookup(parent);
- if (!clk) {
+ parent_clk = __clk_lookup(parent);
+ if (!parent_clk) {
pr_err("%s: could not lookup parent clock %s\n",
__func__, parent);
ret = -EINVAL;
goto free_cpuclk;
}
- ret = clk_notifier_register(clk, &cpuclk->clk_nb);
+ ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 3/6] clk: samsung: Convert common drivers to the new clk_hw API
[not found] ` <CGME20170424064229eucas1p2f2feb95623d6c4ac8db01ff519a53fa9@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
2017-04-24 6:55 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Samsung clock providers and their helper functions to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-cpu.c | 8 ++-
drivers/clk/samsung/clk-pll.c | 14 +++---
drivers/clk/samsung/clk-s3c2410-dclk.c | 75 ++++++++++++++--------------
drivers/clk/samsung/clk.c | 91 +++++++++++++++-------------------
drivers/clk/samsung/clk.h | 9 ++--
5 files changed, 92 insertions(+), 105 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 6e1c6007e721..fbf0154b81a5 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -411,7 +411,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
struct clk *parent_clk;
- struct clk *clk;
int ret = 0;
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
@@ -464,14 +463,13 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
goto unregister_clk_nb;
}
- clk = clk_register(NULL, &cpuclk->hw);
- if (IS_ERR(clk)) {
+ ret = clk_hw_register(NULL, &cpuclk->hw);
+ if (ret) {
pr_err("%s: could not register cpuclk %s\n", __func__, name);
- ret = PTR_ERR(clk);
goto free_cpuclk_data;
}
- samsung_clk_add_lookup(ctx, clk, lookup_id);
+ samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
return 0;
free_cpuclk_data:
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 52290894857a..db680575a9bd 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1244,7 +1244,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
void __iomem *base)
{
struct samsung_clk_pll *pll;
- struct clk *clk;
struct clk_init_data init;
int ret, len;
@@ -1376,20 +1375,21 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
pll->lock_reg = base + pll_clk->lock_offset;
pll->con_reg = base + pll_clk->con_offset;
- clk = clk_register(NULL, &pll->hw);
- if (IS_ERR(clk)) {
- pr_err("%s: failed to register pll clock %s : %ld\n",
- __func__, pll_clk->name, PTR_ERR(clk));
+ ret = clk_hw_register(NULL, &pll->hw);
+ if (ret) {
+ pr_err("%s: failed to register pll clock %s : %d\n",
+ __func__, pll_clk->name, ret);
kfree(pll);
return;
}
- samsung_clk_add_lookup(ctx, clk, pll_clk->id);
+ samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
if (!pll_clk->alias)
return;
- ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
+ ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
+ pll_clk->dev_name);
if (ret)
pr_err("%s: failed to register lookup for %s : %d",
__func__, pll_clk->name, ret);
diff --git a/drivers/clk/samsung/clk-s3c2410-dclk.c b/drivers/clk/samsung/clk-s3c2410-dclk.c
index ae9a595c72d0..077df3e539a7 100644
--- a/drivers/clk/samsung/clk-s3c2410-dclk.c
+++ b/drivers/clk/samsung/clk-s3c2410-dclk.c
@@ -90,13 +90,13 @@ static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
.determine_rate = __clk_mux_determine_rate,
};
-static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
- const char **parent_names, u8 num_parents,
+static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
+ const char *name, const char **parent_names, u8 num_parents,
u8 shift, u32 mask)
{
struct s3c24xx_clkout *clkout;
- struct clk *clk;
struct clk_init_data init;
+ int ret;
/* allocate the clkout */
clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
@@ -113,9 +113,11 @@ static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
clkout->mask = mask;
clkout->hw.init = &init;
- clk = clk_register(dev, &clkout->hw);
+ ret = clk_hw_register(dev, &clkout->hw);
+ if (ret)
+ return ERR_PTR(ret);
- return clk;
+ return &clkout->hw;
}
/*
@@ -125,11 +127,12 @@ static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
struct s3c24xx_dclk {
struct device *dev;
void __iomem *base;
- struct clk_onecell_data clk_data;
struct notifier_block dclk0_div_change_nb;
struct notifier_block dclk1_div_change_nb;
spinlock_t dclk_lock;
unsigned long reg_save;
+ /* clk_data must be the last entry in the structure */
+ struct clk_hw_onecell_data clk_data;
};
#define to_s3c24xx_dclk0(x) \
@@ -240,28 +243,23 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
{
struct s3c24xx_dclk *s3c24xx_dclk;
struct resource *mem;
- struct clk **clk_table;
struct s3c24xx_dclk_drv_data *dclk_variant;
+ struct clk_hw **clk_table;
int ret, i;
- s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk),
- GFP_KERNEL);
+ s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk) +
+ sizeof(*s3c24xx_dclk->clk_data.hws) * DCLK_MAX_CLKS,
+ GFP_KERNEL);
if (!s3c24xx_dclk)
return -ENOMEM;
+ clk_table = s3c24xx_dclk->clk_data.hws;
+
s3c24xx_dclk->dev = &pdev->dev;
+ s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
platform_set_drvdata(pdev, s3c24xx_dclk);
spin_lock_init(&s3c24xx_dclk->dclk_lock);
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * DCLK_MAX_CLKS,
- GFP_KERNEL);
- if (!clk_table)
- return -ENOMEM;
-
- s3c24xx_dclk->clk_data.clks = clk_table;
- s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS;
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(s3c24xx_dclk->base))
@@ -271,29 +269,29 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
platform_get_device_id(pdev)->driver_data;
- clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0",
+ clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
dclk_variant->mux_parent_names,
dclk_variant->mux_num_parents, 0,
s3c24xx_dclk->base, 1, 1, 0,
&s3c24xx_dclk->dclk_lock);
- clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1",
+ clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
dclk_variant->mux_parent_names,
dclk_variant->mux_num_parents, 0,
s3c24xx_dclk->base, 17, 1, 0,
&s3c24xx_dclk->dclk_lock);
- clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0",
+ clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
"mux_dclk0", 0, s3c24xx_dclk->base,
4, 4, 0, &s3c24xx_dclk->dclk_lock);
- clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1",
+ clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
"mux_dclk1", 0, s3c24xx_dclk->base,
20, 4, 0, &s3c24xx_dclk->dclk_lock);
- clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0",
+ clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
"div_dclk0", CLK_SET_RATE_PARENT,
s3c24xx_dclk->base, 0, 0,
&s3c24xx_dclk->dclk_lock);
- clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1",
+ clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
"div_dclk1", CLK_SET_RATE_PARENT,
s3c24xx_dclk->base, 16, 0,
&s3c24xx_dclk->dclk_lock);
@@ -312,15 +310,16 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
goto err_clk_register;
}
- ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
+ ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
if (!ret)
- ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
+ ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
+ NULL);
if (!ret)
- ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
- "clkout0", NULL);
+ ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
+ "clkout0", NULL);
if (!ret)
- ret = clk_register_clkdev(clk_table[MUX_CLKOUT1],
- "clkout1", NULL);
+ ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
+ "clkout1", NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
goto err_clk_register;
@@ -332,12 +331,12 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
s3c24xx_dclk1_div_notify;
- ret = clk_notifier_register(clk_table[DIV_DCLK0],
+ ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
&s3c24xx_dclk->dclk0_div_change_nb);
if (ret)
goto err_clk_register;
- ret = clk_notifier_register(clk_table[DIV_DCLK1],
+ ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
&s3c24xx_dclk->dclk1_div_change_nb);
if (ret)
goto err_dclk_notify;
@@ -345,12 +344,12 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
return 0;
err_dclk_notify:
- clk_notifier_unregister(clk_table[DIV_DCLK0],
+ clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
&s3c24xx_dclk->dclk0_div_change_nb);
err_clk_register:
for (i = 0; i < DCLK_MAX_CLKS; i++)
if (clk_table[i] && !IS_ERR(clk_table[i]))
- clk_unregister(clk_table[i]);
+ clk_hw_unregister(clk_table[i]);
return ret;
}
@@ -358,16 +357,16 @@ static int s3c24xx_dclk_probe(struct platform_device *pdev)
static int s3c24xx_dclk_remove(struct platform_device *pdev)
{
struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
- struct clk **clk_table = s3c24xx_dclk->clk_data.clks;
+ struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
int i;
- clk_notifier_unregister(clk_table[DIV_DCLK1],
+ clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
&s3c24xx_dclk->dclk1_div_change_nb);
- clk_notifier_unregister(clk_table[DIV_DCLK0],
+ clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
&s3c24xx_dclk->dclk0_div_change_nb);
for (i = 0; i < DCLK_MAX_CLKS; i++)
- clk_unregister(clk_table[i]);
+ clk_hw_unregister(clk_table[i]);
return 0;
}
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index b7d87d6db9dc..7ce0fa86c5ff 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -60,23 +60,18 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
void __iomem *base, unsigned long nr_clks)
{
struct samsung_clk_provider *ctx;
- struct clk **clk_table;
int i;
- ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
+ ctx = kzalloc(sizeof(struct samsung_clk_provider) +
+ sizeof(*ctx->clk_data.hws) * nr_clks, GFP_KERNEL);
if (!ctx)
panic("could not allocate clock provider context.\n");
- clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
- if (!clk_table)
- panic("could not allocate clock lookup table\n");
-
for (i = 0; i < nr_clks; ++i)
- clk_table[i] = ERR_PTR(-ENOENT);
+ ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
ctx->reg_base = base;
- ctx->clk_data.clks = clk_table;
- ctx->clk_data.clk_num = nr_clks;
+ ctx->clk_data.num = nr_clks;
spin_lock_init(&ctx->lock);
return ctx;
@@ -86,18 +81,18 @@ void __init samsung_clk_of_add_provider(struct device_node *np,
struct samsung_clk_provider *ctx)
{
if (np) {
- if (of_clk_add_provider(np, of_clk_src_onecell_get,
+ if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
&ctx->clk_data))
panic("could not register clk provider\n");
}
}
/* add a clock instance to the clock lookup table used for dt based lookup */
-void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
- unsigned int id)
+void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
+ struct clk_hw *clk_hw, unsigned int id)
{
- if (ctx->clk_data.clks && id)
- ctx->clk_data.clks[id] = clk;
+ if (id)
+ ctx->clk_data.hws[id] = clk_hw;
}
/* register a list of aliases */
@@ -105,14 +100,9 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
const struct samsung_clock_alias *list,
unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx, ret;
- if (!ctx->clk_data.clks) {
- pr_err("%s: clock table missing\n", __func__);
- return;
- }
-
for (idx = 0; idx < nr_clk; idx++, list++) {
if (!list->id) {
pr_err("%s: clock id missing for index %d\n", __func__,
@@ -120,14 +110,15 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
continue;
}
- clk = ctx->clk_data.clks[list->id];
- if (!clk) {
+ clk_hw = ctx->clk_data.hws[list->id];
+ if (!clk_hw) {
pr_err("%s: failed to find clock %d\n", __func__,
list->id);
continue;
}
- ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+ ret = clk_hw_register_clkdev(clk_hw, list->alias,
+ list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
@@ -139,25 +130,25 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
const struct samsung_fixed_rate_clock *list,
unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
- clk = clk_register_fixed_rate(NULL, list->name,
+ clk_hw = clk_hw_register_fixed_rate(NULL, list->name,
list->parent_name, list->flags, list->fixed_rate);
- if (IS_ERR(clk)) {
+ if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
- samsung_clk_add_lookup(ctx, clk, list->id);
+ samsung_clk_add_lookup(ctx, clk_hw, list->id);
/*
* Unconditionally add a clock lookup for the fixed rate clocks.
* There are not many of these on any of Samsung platforms.
*/
- ret = clk_register_clkdev(clk, list->name, NULL);
+ ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
if (ret)
pr_err("%s: failed to register clock lookup for %s",
__func__, list->name);
@@ -168,19 +159,19 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx;
for (idx = 0; idx < nr_clk; idx++, list++) {
- clk = clk_register_fixed_factor(NULL, list->name,
+ clk_hw = clk_hw_register_fixed_factor(NULL, list->name,
list->parent_name, list->flags, list->mult, list->div);
- if (IS_ERR(clk)) {
+ if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
- samsung_clk_add_lookup(ctx, clk, list->id);
+ samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
@@ -189,25 +180,25 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
const struct samsung_mux_clock *list,
unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
- clk = clk_register_mux(NULL, list->name, list->parent_names,
- list->num_parents, list->flags,
+ clk_hw = clk_hw_register_mux(NULL, list->name,
+ list->parent_names, list->num_parents, list->flags,
ctx->reg_base + list->offset,
list->shift, list->width, list->mux_flags, &ctx->lock);
- if (IS_ERR(clk)) {
+ if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
- samsung_clk_add_lookup(ctx, clk, list->id);
+ samsung_clk_add_lookup(ctx, clk_hw, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
- ret = clk_register_clkdev(clk, list->alias,
+ ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
@@ -221,32 +212,32 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
const struct samsung_div_clock *list,
unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
if (list->table)
- clk = clk_register_divider_table(NULL, list->name,
- list->parent_name, list->flags,
+ clk_hw = clk_hw_register_divider_table(NULL,
+ list->name, list->parent_name, list->flags,
ctx->reg_base + list->offset,
list->shift, list->width, list->div_flags,
list->table, &ctx->lock);
else
- clk = clk_register_divider(NULL, list->name,
+ clk_hw = clk_hw_register_divider(NULL, list->name,
list->parent_name, list->flags,
ctx->reg_base + list->offset, list->shift,
list->width, list->div_flags, &ctx->lock);
- if (IS_ERR(clk)) {
+ if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
- samsung_clk_add_lookup(ctx, clk, list->id);
+ samsung_clk_add_lookup(ctx, clk_hw, list->id);
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
- ret = clk_register_clkdev(clk, list->alias,
+ ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
@@ -260,14 +251,14 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
const struct samsung_gate_clock *list,
unsigned int nr_clk)
{
- struct clk *clk;
+ struct clk_hw *clk_hw;
unsigned int idx, ret;
for (idx = 0; idx < nr_clk; idx++, list++) {
- clk = clk_register_gate(NULL, list->name, list->parent_name,
+ clk_hw = clk_hw_register_gate(NULL, list->name, list->parent_name,
list->flags, ctx->reg_base + list->offset,
list->bit_idx, list->gate_flags, &ctx->lock);
- if (IS_ERR(clk)) {
+ if (IS_ERR(clk_hw)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
@@ -275,14 +266,14 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
/* register a clock lookup only if a clock alias is specified */
if (list->alias) {
- ret = clk_register_clkdev(clk, list->alias,
+ ret = clk_hw_register_clkdev(clk_hw, list->alias,
list->dev_name);
if (ret)
pr_err("%s: failed to register lookup %s\n",
__func__, list->alias);
}
- samsung_clk_add_lookup(ctx, clk, list->id);
+ samsung_clk_add_lookup(ctx, clk_hw, list->id);
}
}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index da3bdebabf1e..b8ca0dd3a38b 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -16,18 +16,17 @@
#include <linux/clk-provider.h>
#include "clk-pll.h"
-struct clk;
-
/**
* struct samsung_clk_provider: information about clock provider
* @reg_base: virtual address for the register base.
- * @clk_data: holds clock related data like clk* and number of clocks.
* @lock: maintains exclusion between callbacks for a given clock-provider.
+ * @clk_data: holds clock related data like clk_hw* and number of clocks.
*/
struct samsung_clk_provider {
void __iomem *reg_base;
- struct clk_onecell_data clk_data;
spinlock_t lock;
+ /* clk_data must be the last entry due to variable lenght 'hws' array */
+ struct clk_hw_onecell_data clk_data;
};
/**
@@ -367,7 +366,7 @@ extern void __init samsung_clk_of_register_fixed_ext(
const struct of_device_id *clk_matches);
extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
- struct clk *clk, unsigned int id);
+ struct clk_hw *clk_hw, unsigned int id);
extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
const struct samsung_clock_alias *list,
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 4/6] clk: samsung: exynos-audss: Convert to the new clk_hw API
[not found] ` <CGME20170424064230eucas1p183fecc2feda35c3fb5fc1af44d130f59@eucas1p1.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
[not found] ` <CGME20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55@eucas1p2.samsung.com>
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/clk/samsung/clk-exynos-audss.c | 55 +++++++++++++++++-----------------
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index cb7df358a27d..e8f89529da07 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -22,9 +22,8 @@
#include <dt-bindings/clock/exynos-audss-clk.h>
static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
+static struct clk_hw_onecell_data *clk_data;
/*
* On Exynos5420 this will be a clock which has to be enabled before any
* access to audss registers. Typically a child of EPLL.
@@ -110,18 +109,18 @@ static void exynos_audss_clk_teardown(void)
int i;
for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_mux(clk_table[i]);
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_mux(clk_data->hws[i]);
}
for (; i < EXYNOS_SRP_CLK; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_divider(clk_table[i]);
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_divider(clk_data->hws[i]);
}
- for (; i < clk_data.clk_num; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_gate(clk_table[i]);
+ for (; i < clk_data->num; i++) {
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_gate(clk_data->hws[i]);
}
}
@@ -133,6 +132,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct exynos_audss_clk_drvdata *variant;
+ struct clk_hw **clk_table;
struct resource *res;
int i, ret = 0;
@@ -149,14 +149,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
epll = ERR_PTR(-ENODEV);
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_data = devm_kzalloc(&pdev->dev,
+ sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table)
+ if (!clk_data)
return -ENOMEM;
- clk_data.clks = clk_table;
- clk_data.clk_num = variant->num_clks;
+ clk_data->num = variant->num_clks;
+ clk_table = clk_data->hws;
pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
pll_in = devm_clk_get(&pdev->dev, "pll_in");
@@ -176,7 +177,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
}
}
}
- clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
@@ -187,53 +188,53 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
mout_i2s_p[1] = __clk_get_name(cdclk);
if (!IS_ERR(sclk_audio))
mout_i2s_p[2] = __clk_get_name(sclk_audio);
- clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+ clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
- clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+ clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
0, &lock);
- clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
"dout_aud_bus", "dout_srp", 0,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
- clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+ clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
&lock);
- clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+ clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
- clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+ clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus",
"dout_aud_bus", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
- clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+ clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s",
"dout_i2s", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
- clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+ clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus",
"sclk_pcm", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
if (!IS_ERR(sclk_pcm_in))
sclk_pcm_p = __clk_get_name(sclk_pcm_in);
- clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+ clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm",
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
if (variant->has_adma_clk) {
- clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 9, 0, &lock);
}
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
@@ -241,7 +242,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
}
}
- ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
&clk_data);
if (ret) {
dev_err(&pdev->dev, "failed to add clock provider\n");
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 5/6] clk: samsung: exynos-clkout: Convert to the new clk_hw API
[not found] ` <CGME20170424064231eucas1p2edd27880b5adc7c884e00db54c100cc2@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
0 siblings, 0 replies; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Exynos CLKOUT clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/clk/samsung/clk-exynos-clkout.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index 6c6afb87b4ce..a21aea062bae 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -29,10 +29,9 @@ struct exynos_clkout {
struct clk_gate gate;
struct clk_mux mux;
spinlock_t slock;
- struct clk_onecell_data data;
- struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
void __iomem *reg;
u32 pmu_debug_save;
+ struct clk_hw_onecell_data data;
};
static struct exynos_clkout *clkout;
@@ -62,7 +61,9 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
int ret;
int i;
- clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
+ clkout = kzalloc(sizeof(*clkout) +
+ sizeof(*clkout->data.hws) * EXYNOS_CLKOUT_NR_CLKS,
+ GFP_KERNEL);
if (!clkout)
return;
@@ -100,17 +101,16 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
clkout->mux.lock = &clkout->slock;
- clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
+ clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
parent_names, parent_count, &clkout->mux.hw,
&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
&clk_gate_ops, CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT);
- if (IS_ERR(clkout->clk_table[0]))
+ if (IS_ERR(clkout->data.hws[0]))
goto err_unmap;
- clkout->data.clks = clkout->clk_table;
- clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
- ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
+ clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data);
if (ret)
goto err_clk_unreg;
@@ -119,7 +119,7 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
return;
err_clk_unreg:
- clk_unregister(clkout->clk_table[0]);
+ clk_hw_unregister(clkout->data.hws[0]);
err_unmap:
iounmap(clkout->reg);
clks_put:
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 6/6] clk: samsung: s5pv210-audss: Convert to the new clk_hw API
[not found] ` <CGME20170424064231eucas1p2dc993650881054dfea9aadb6abb0eb38@eucas1p2.samsung.com>
@ 2017-04-24 6:42 ` Marek Szyprowski
2017-04-24 6:56 ` Krzysztof Kozlowski
[not found] ` <CGME20170515065110eucas1p1b558e1c1ce24852219aa7d98e3b57dff@eucas1p1.samsung.com>
0 siblings, 2 replies; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 6:42 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-s5pv210-audss.c | 50 +++++++++++++++++----------------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c
index c66ed2d1450e..e12f5b81834f 100644
--- a/drivers/clk/samsung/clk-s5pv210-audss.c
+++ b/drivers/clk/samsung/clk-s5pv210-audss.c
@@ -24,9 +24,8 @@
#include <dt-bindings/clock/s5pv210-audss.h>
static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
+static struct clk_hw_onecell_data *clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
@@ -71,6 +70,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
const char *mout_audss_p[2];
const char *mout_i2s_p[3];
const char *hclk_p;
+ struct clk_hw **clk_table;
struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -80,14 +80,16 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * AUDSS_MAX_CLKS,
+ clk_data = devm_kzalloc(&pdev->dev,
+ sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table)
+
+ if (!clk_data)
return -ENOMEM;
- clk_data.clks = clk_table;
- clk_data.clk_num = AUDSS_MAX_CLKS;
+ clk_data->num = AUDSS_MAX_CLKS;
+ clk_table = clk_data->hws;
hclk = devm_clk_get(&pdev->dev, "hclk");
if (IS_ERR(hclk)) {
@@ -116,7 +118,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
else
mout_audss_p[0] = "xxti";
mout_audss_p[1] = __clk_get_name(pll_in);
- clk_table[CLK_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
@@ -127,44 +129,44 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
else
mout_i2s_p[1] = "iiscdclk0";
mout_i2s_p[2] = __clk_get_name(sclk_audio);
- clk_table[CLK_MOUT_I2S_A] = clk_register_mux(NULL, "mout_i2s_audss",
+ clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
- clk_table[CLK_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
"dout_aud_bus", "mout_audss", 0,
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
- clk_table[CLK_DOUT_I2S_A] = clk_register_divider(NULL, "dout_i2s_audss",
- "mout_i2s_audss", 0, reg_base + ASS_CLK_DIV,
- 4, 4, 0, &lock);
+ clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
+ "dout_i2s_audss", "mout_i2s_audss", 0,
+ reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
- clk_table[CLK_I2S] = clk_register_gate(NULL, "i2s_audss",
+ clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
"dout_i2s_audss", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 6, 0, &lock);
hclk_p = __clk_get_name(hclk);
- clk_table[CLK_HCLK_I2S] = clk_register_gate(NULL, "hclk_i2s_audss",
+ clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
- clk_table[CLK_HCLK_UART] = clk_register_gate(NULL, "hclk_uart_audss",
+ clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
- clk_table[CLK_HCLK_HWA] = clk_register_gate(NULL, "hclk_hwa_audss",
+ clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
- clk_table[CLK_HCLK_DMA] = clk_register_gate(NULL, "hclk_dma_audss",
+ clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
- clk_table[CLK_HCLK_BUF] = clk_register_gate(NULL, "hclk_buf_audss",
+ clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 1, 0, &lock);
- clk_table[CLK_HCLK_RP] = clk_register_gate(NULL, "hclk_rp_audss",
+ clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
@@ -172,7 +174,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
}
}
- ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
&clk_data);
if (ret) {
dev_err(&pdev->dev, "failed to add clock provider\n");
@@ -186,9 +188,9 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
return 0;
unregister:
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (!IS_ERR(clk_table[i]))
- clk_unregister(clk_table[i]);
+ clk_hw_unregister(clk_table[i]);
}
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/6] clk: samsung: Remove dead code
2017-04-24 6:42 ` [PATCH v2 1/6] clk: samsung: Remove dead code Marek Szyprowski
@ 2017-04-24 6:49 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2017-04-24 6:49 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Bartlomiej Zolnierkiewicz
On Mon, Apr 24, 2017 at 8:42 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> samsung_clk_register_pll2550x() function is not used anymore, so remove its
> declaration.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-pll.h | 4 ----
> 1 file changed, 4 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/6] clk: samsung: Add local variable to match it purpose
2017-04-24 6:42 ` [PATCH v2 2/6] clk: samsung: Add local variable to match it purpose Marek Szyprowski
@ 2017-04-24 6:53 ` Krzysztof Kozlowski
[not found] ` <CGME20170424075423eucas1p239eaef08b93dade23292c175b838d9a5@eucas1p2.samsung.com>
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2017-04-24 6:53 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Bartlomiej Zolnierkiewicz
On Mon, Apr 24, 2017 at 8:42 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Add new variable to avoid using clk pointer for different purposes across
> the exynos_register_cpu_clock() function. This will help in future rewrite
> for the new clk_hw API.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-cpu.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
> index 8bf7e805fd34..6e1c6007e721 100644
> --- a/drivers/clk/samsung/clk-cpu.c
> +++ b/drivers/clk/samsung/clk-cpu.c
> @@ -410,6 +410,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
> {
> struct exynos_cpuclk *cpuclk;
> struct clk_init_data init;
> + struct clk *parent_clk;
> struct clk *clk;
> int ret = 0;
>
> @@ -440,15 +441,15 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
> goto free_cpuclk;
> }
>
> - clk = __clk_lookup(parent);
> - if (!clk) {
> + parent_clk = __clk_lookup(parent);
> + if (!parent_clk) {
> pr_err("%s: could not lookup parent clock %s\n",
> __func__, parent);
> ret = -EINVAL;
> goto free_cpuclk;
> }
>
> - ret = clk_notifier_register(clk, &cpuclk->clk_nb);
> + ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
> if (ret) {
> pr_err("%s: failed to register clock notifier for %s\n",
> __func__, name);
You can also remove one clk_lookup and just use "parent_clk" in error path:
478 unregister_clk_nb:
479 clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb);
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 3/6] clk: samsung: Convert common drivers to the new clk_hw API
2017-04-24 6:42 ` [PATCH v2 3/6] clk: samsung: Convert common drivers to the new clk_hw API Marek Szyprowski
@ 2017-04-24 6:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2017-04-24 6:55 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Bartlomiej Zolnierkiewicz
On Mon, Apr 24, 2017 at 8:42 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Clock providers should use the new struct clk_hw based API, so convert
> Samsung clock providers and their helper functions to the new approach.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-cpu.c | 8 ++-
> drivers/clk/samsung/clk-pll.c | 14 +++---
> drivers/clk/samsung/clk-s3c2410-dclk.c | 75 ++++++++++++++--------------
> drivers/clk/samsung/clk.c | 91 +++++++++++++++-------------------
> drivers/clk/samsung/clk.h | 9 ++--
> 5 files changed, 92 insertions(+), 105 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 6/6] clk: samsung: s5pv210-audss: Convert to the new clk_hw API
2017-04-24 6:42 ` [PATCH v2 6/6] clk: samsung: s5pv210-audss: " Marek Szyprowski
@ 2017-04-24 6:56 ` Krzysztof Kozlowski
[not found] ` <CGME20170515065110eucas1p1b558e1c1ce24852219aa7d98e3b57dff@eucas1p1.samsung.com>
1 sibling, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2017-04-24 6:56 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Bartlomiej Zolnierkiewicz
On Mon, Apr 24, 2017 at 8:42 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Clock providers should use the new struct clk_hw based API, so convert
> Samsung S5PV210 Audio Subsystem clock provider to the new approach.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-s5pv210-audss.c | 50 +++++++++++++++++----------------
> 1 file changed, 26 insertions(+), 24 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2.1 2/6] clk: samsung: Add local variable to match it purpose
[not found] ` <CGME20170424075423eucas1p239eaef08b93dade23292c175b838d9a5@eucas1p2.samsung.com>
@ 2017-04-24 7:54 ` Marek Szyprowski
2017-04-24 7:56 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-04-24 7:54 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/clk/samsung/clk-cpu.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 8bf7e805fd34..c6dd83dce09d 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -410,6 +410,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
{
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
+ struct clk *parent_clk;
struct clk *clk;
int ret = 0;
@@ -440,15 +441,15 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
goto free_cpuclk;
}
- clk = __clk_lookup(parent);
- if (!clk) {
+ parent_clk = __clk_lookup(parent);
+ if (!parent_clk) {
pr_err("%s: could not lookup parent clock %s\n",
__func__, parent);
ret = -EINVAL;
goto free_cpuclk;
}
- ret = clk_notifier_register(clk, &cpuclk->clk_nb);
+ ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
@@ -476,7 +477,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
free_cpuclk_data:
kfree(cpuclk->cfg);
unregister_clk_nb:
- clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb);
+ clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);
free_cpuclk:
kfree(cpuclk);
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2.1 2/6] clk: samsung: Add local variable to match it purpose
2017-04-24 7:54 ` [PATCH v2.1 " Marek Szyprowski
@ 2017-04-24 7:56 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2017-04-24 7:56 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Bartlomiej Zolnierkiewicz
On Mon, Apr 24, 2017 at 9:54 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Add new variable to avoid using clk pointer for different purposes across
> the exynos_register_cpu_clock() function. This will help in future rewrite
> for the new clk_hw API.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-cpu.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/6] Samsung clock providers: convert to the new clk_hw API
2017-04-24 6:42 ` [PATCH v2 0/6] Samsung clock providers: convert to the new clk_hw API Marek Szyprowski
` (5 preceding siblings ...)
[not found] ` <CGME20170424064231eucas1p2dc993650881054dfea9aadb6abb0eb38@eucas1p2.samsung.com>
@ 2017-04-25 10:31 ` Sylwester Nawrocki
6 siblings, 0 replies; 18+ messages in thread
From: Sylwester Nawrocki @ 2017-04-25 10:31 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-clk, linux-samsung-soc, Stephen Boyd, Michael Turquette,
Chanwoo Choi, Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz
On 04/24/2017 08:42 AM, Marek Szyprowski wrote:
> Marek Szyprowski (6):
> clk: samsung: Remove dead code
> clk: samsung: Add local variable to match it purpose
> clk: samsung: Convert common drivers to the new clk_hw API
> clk: samsung: exynos-audss: Convert to the new clk_hw API
> clk: samsung: exynos-clkout: Convert to the new clk_hw API
> clk: samsung: s5pv210-audss: Convert to the new clk_hw API
Whole series applied, thanks.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 4/6] clk: samsung: exynos-audss: Convert to the new clk_hw API
[not found] ` <CGME20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55@eucas1p2.samsung.com>
@ 2017-05-15 6:50 ` Marek Szyprowski
2017-06-09 1:33 ` Chanwoo Choi
0 siblings, 1 reply; 18+ messages in thread
From: Marek Szyprowski @ 2017-05-15 6:50 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Sylwester, if possible, please replace v2 with this fixed version in your tree,
as it has not been merged yet to clk-next nor to linux-next.
Changelog
v3:
- fixed clock data parameter passed to of_clk_add_hw_provider() - after conversion
clk_data is a pointer, so passing it as &clk_data is wrong and causes serious issues
---
drivers/clk/samsung/clk-exynos-audss.c | 57 +++++++++++++++++-----------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index cb7df358a27d..85edeb738853 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -22,9 +22,8 @@
#include <dt-bindings/clock/exynos-audss-clk.h>
static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
+static struct clk_hw_onecell_data *clk_data;
/*
* On Exynos5420 this will be a clock which has to be enabled before any
* access to audss registers. Typically a child of EPLL.
@@ -110,18 +109,18 @@ static void exynos_audss_clk_teardown(void)
int i;
for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_mux(clk_table[i]);
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_mux(clk_data->hws[i]);
}
for (; i < EXYNOS_SRP_CLK; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_divider(clk_table[i]);
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_divider(clk_data->hws[i]);
}
- for (; i < clk_data.clk_num; i++) {
- if (!IS_ERR(clk_table[i]))
- clk_unregister_gate(clk_table[i]);
+ for (; i < clk_data->num; i++) {
+ if (!IS_ERR(clk_data->hws[i]))
+ clk_hw_unregister_gate(clk_data->hws[i]);
}
}
@@ -133,6 +132,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
const struct exynos_audss_clk_drvdata *variant;
+ struct clk_hw **clk_table;
struct resource *res;
int i, ret = 0;
@@ -149,14 +149,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
epll = ERR_PTR(-ENODEV);
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_data = devm_kzalloc(&pdev->dev,
+ sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table)
+ if (!clk_data)
return -ENOMEM;
- clk_data.clks = clk_table;
- clk_data.clk_num = variant->num_clks;
+ clk_data->num = variant->num_clks;
+ clk_table = clk_data->hws;
pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
pll_in = devm_clk_get(&pdev->dev, "pll_in");
@@ -176,7 +177,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
}
}
}
- clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
@@ -187,53 +188,53 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
mout_i2s_p[1] = __clk_get_name(cdclk);
if (!IS_ERR(sclk_audio))
mout_i2s_p[2] = __clk_get_name(sclk_audio);
- clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+ clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
- clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+ clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
0, &lock);
- clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
"dout_aud_bus", "dout_srp", 0,
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
- clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+ clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
&lock);
- clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+ clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
- clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+ clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus",
"dout_aud_bus", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
- clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+ clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s",
"dout_i2s", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
- clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+ clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus",
"sclk_pcm", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
if (!IS_ERR(sclk_pcm_in))
sclk_pcm_p = __clk_get_name(sclk_pcm_in);
- clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+ clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm",
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
if (variant->has_adma_clk) {
- clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma",
"dout_srp", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 9, 0, &lock);
}
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
@@ -241,8 +242,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
}
}
- ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
- &clk_data);
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+ clk_data);
if (ret) {
dev_err(&pdev->dev, "failed to add clock provider\n");
goto unregister;
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 6/6] clk: samsung: s5pv210-audss: Convert to the new clk_hw API
[not found] ` <CGME20170515065110eucas1p1b558e1c1ce24852219aa7d98e3b57dff@eucas1p1.samsung.com>
@ 2017-05-15 6:51 ` Marek Szyprowski
0 siblings, 0 replies; 18+ messages in thread
From: Marek Szyprowski @ 2017-05-15 6:51 UTC (permalink / raw)
To: linux-clk, linux-samsung-soc
Cc: Marek Szyprowski, Stephen Boyd, Michael Turquette,
Sylwester Nawrocki, Chanwoo Choi, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Sylwester, if possible, please replace v2 with this fixed version in your tree,
as it has not been merged yet to clk-next nor to linux-next.
Changelog
v3:
- fixed clock data parameter passed to of_clk_add_hw_provider() - after conversion
clk_data is a pointer, so passing it as &clk_data is wrong and causes serious issues
---
drivers/clk/samsung/clk-s5pv210-audss.c | 52 +++++++++++++++++----------------
1 file changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c
index c66ed2d1450e..b9641414ddc6 100644
--- a/drivers/clk/samsung/clk-s5pv210-audss.c
+++ b/drivers/clk/samsung/clk-s5pv210-audss.c
@@ -24,9 +24,8 @@
#include <dt-bindings/clock/s5pv210-audss.h>
static DEFINE_SPINLOCK(lock);
-static struct clk **clk_table;
static void __iomem *reg_base;
-static struct clk_onecell_data clk_data;
+static struct clk_hw_onecell_data *clk_data;
#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
@@ -71,6 +70,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
const char *mout_audss_p[2];
const char *mout_i2s_p[3];
const char *hclk_p;
+ struct clk_hw **clk_table;
struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -80,14 +80,16 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
return PTR_ERR(reg_base);
}
- clk_table = devm_kzalloc(&pdev->dev,
- sizeof(struct clk *) * AUDSS_MAX_CLKS,
+ clk_data = devm_kzalloc(&pdev->dev,
+ sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table)
+
+ if (!clk_data)
return -ENOMEM;
- clk_data.clks = clk_table;
- clk_data.clk_num = AUDSS_MAX_CLKS;
+ clk_data->num = AUDSS_MAX_CLKS;
+ clk_table = clk_data->hws;
hclk = devm_clk_get(&pdev->dev, "hclk");
if (IS_ERR(hclk)) {
@@ -116,7 +118,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
else
mout_audss_p[0] = "xxti";
mout_audss_p[1] = __clk_get_name(pll_in);
- clk_table[CLK_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+ clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
@@ -127,44 +129,44 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
else
mout_i2s_p[1] = "iiscdclk0";
mout_i2s_p[2] = __clk_get_name(sclk_audio);
- clk_table[CLK_MOUT_I2S_A] = clk_register_mux(NULL, "mout_i2s_audss",
+ clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
- clk_table[CLK_DOUT_AUD_BUS] = clk_register_divider(NULL,
+ clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
"dout_aud_bus", "mout_audss", 0,
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
- clk_table[CLK_DOUT_I2S_A] = clk_register_divider(NULL, "dout_i2s_audss",
- "mout_i2s_audss", 0, reg_base + ASS_CLK_DIV,
- 4, 4, 0, &lock);
+ clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
+ "dout_i2s_audss", "mout_i2s_audss", 0,
+ reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
- clk_table[CLK_I2S] = clk_register_gate(NULL, "i2s_audss",
+ clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
"dout_i2s_audss", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 6, 0, &lock);
hclk_p = __clk_get_name(hclk);
- clk_table[CLK_HCLK_I2S] = clk_register_gate(NULL, "hclk_i2s_audss",
+ clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
- clk_table[CLK_HCLK_UART] = clk_register_gate(NULL, "hclk_uart_audss",
+ clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 4, 0, &lock);
- clk_table[CLK_HCLK_HWA] = clk_register_gate(NULL, "hclk_hwa_audss",
+ clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 3, 0, &lock);
- clk_table[CLK_HCLK_DMA] = clk_register_gate(NULL, "hclk_dma_audss",
+ clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 2, 0, &lock);
- clk_table[CLK_HCLK_BUF] = clk_register_gate(NULL, "hclk_buf_audss",
+ clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 1, 0, &lock);
- clk_table[CLK_HCLK_RP] = clk_register_gate(NULL, "hclk_rp_audss",
+ clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
hclk_p, CLK_IGNORE_UNUSED,
reg_base + ASS_CLK_GATE, 0, 0, &lock);
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
ret = PTR_ERR(clk_table[i]);
@@ -172,8 +174,8 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
}
}
- ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
- &clk_data);
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+ clk_data);
if (ret) {
dev_err(&pdev->dev, "failed to add clock provider\n");
goto unregister;
@@ -186,9 +188,9 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev)
return 0;
unregister:
- for (i = 0; i < clk_data.clk_num; i++) {
+ for (i = 0; i < clk_data->num; i++) {
if (!IS_ERR(clk_table[i]))
- clk_unregister(clk_table[i]);
+ clk_hw_unregister(clk_table[i]);
}
return ret;
--
1.9.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 4/6] clk: samsung: exynos-audss: Convert to the new clk_hw API
2017-05-15 6:50 ` [PATCH v3 " Marek Szyprowski
@ 2017-06-09 1:33 ` Chanwoo Choi
2017-06-09 10:25 ` Sylwester Nawrocki
0 siblings, 1 reply; 18+ messages in thread
From: Chanwoo Choi @ 2017-06-09 1:33 UTC (permalink / raw)
To: Marek Szyprowski, linux-clk, linux-samsung-soc
Cc: Stephen Boyd, Michael Turquette, Sylwester Nawrocki,
Krzysztof Kozlowski, Bartlomiej Zolnierkiewicz
Dear Marek,
I tested this patch[1] which was applied on Sylwester's git repo.
[1] https://git.linuxtv.org/snawrocki/samsung.git/commit/?h=for-v4.13/clk/next&id=6622c52f47372186c17548ca7398c229c45e6215
When I tested it on XU3, I can't get the kernel booting.
[Following log]
U-Boot 2016.03-gc2deb3a51-TIZEN.org (Oct 28 2016 - 18:00:23 +0000) for ODROID-XU3
CPU: Exynos5422 @ 800 MHz
Model: Odroid XU3 based on EXYNOS5422
Board: Odroid XU3 based on EXYNOS5422
Type: xu3
DRAM: 2 GiB
MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 1
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
reading exynos5422-odroidxu3.dtb
56532 bytes read in 16 ms (3.4 MiB/s)
reading uInitrd
** Unable to read file uInitrd **
reading zImage
7676176 bytes read in 208 ms (35.2 MiB/s)
Kernel image @ 0x40007fc0 [ 0x000000 - 0x752110 ]
## Flattened Device Tree blob at 40800000
Booting using the fdt blob at 0x40800000
Loading Device Tree to 4ffef000, end 4ffffcd3 ... OK
Starting kernel ...
On 2017년 05월 15일 15:50, Marek Szyprowski wrote:
> Clock providers should use the new struct clk_hw based API, so convert
> Exynos Audio Subsystem clock provider to the new approach.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> Sylwester, if possible, please replace v2 with this fixed version in your tree,
> as it has not been merged yet to clk-next nor to linux-next.
>
> Changelog
> v3:
> - fixed clock data parameter passed to of_clk_add_hw_provider() - after conversion
> clk_data is a pointer, so passing it as &clk_data is wrong and causes serious issues
>
> ---
> drivers/clk/samsung/clk-exynos-audss.c | 57 +++++++++++++++++-----------------
> 1 file changed, 29 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> index cb7df358a27d..85edeb738853 100644
> --- a/drivers/clk/samsung/clk-exynos-audss.c
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -22,9 +22,8 @@
> #include <dt-bindings/clock/exynos-audss-clk.h>
>
> static DEFINE_SPINLOCK(lock);
> -static struct clk **clk_table;
> static void __iomem *reg_base;
> -static struct clk_onecell_data clk_data;
> +static struct clk_hw_onecell_data *clk_data;
> /*
> * On Exynos5420 this will be a clock which has to be enabled before any
> * access to audss registers. Typically a child of EPLL.
> @@ -110,18 +109,18 @@ static void exynos_audss_clk_teardown(void)
> int i;
>
> for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
> - if (!IS_ERR(clk_table[i]))
> - clk_unregister_mux(clk_table[i]);
> + if (!IS_ERR(clk_data->hws[i]))
> + clk_hw_unregister_mux(clk_data->hws[i]);
> }
>
> for (; i < EXYNOS_SRP_CLK; i++) {
> - if (!IS_ERR(clk_table[i]))
> - clk_unregister_divider(clk_table[i]);
> + if (!IS_ERR(clk_data->hws[i]))
> + clk_hw_unregister_divider(clk_data->hws[i]);
> }
>
> - for (; i < clk_data.clk_num; i++) {
> - if (!IS_ERR(clk_table[i]))
> - clk_unregister_gate(clk_table[i]);
> + for (; i < clk_data->num; i++) {
> + if (!IS_ERR(clk_data->hws[i]))
> + clk_hw_unregister_gate(clk_data->hws[i]);
> }
> }
>
> @@ -133,6 +132,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
> const char *sclk_pcm_p = "sclk_pcm0";
> struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
> const struct exynos_audss_clk_drvdata *variant;
> + struct clk_hw **clk_table;
> struct resource *res;
> int i, ret = 0;
>
> @@ -149,14 +149,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
>
> epll = ERR_PTR(-ENODEV);
>
> - clk_table = devm_kzalloc(&pdev->dev,
> - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> + clk_data = devm_kzalloc(&pdev->dev,
> + sizeof(*clk_data) +
> + sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS,
> GFP_KERNEL);
> - if (!clk_table)
> + if (!clk_data)
> return -ENOMEM;
>
> - clk_data.clks = clk_table;
> - clk_data.clk_num = variant->num_clks;
> + clk_data->num = variant->num_clks;
> + clk_table = clk_data->hws;
>
> pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
> pll_in = devm_clk_get(&pdev->dev, "pll_in");
> @@ -176,7 +177,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
> }
> }
> }
> - clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
> + clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
> mout_audss_p, ARRAY_SIZE(mout_audss_p),
> CLK_SET_RATE_NO_REPARENT,
> reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
> @@ -187,53 +188,53 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
> mout_i2s_p[1] = __clk_get_name(cdclk);
> if (!IS_ERR(sclk_audio))
> mout_i2s_p[2] = __clk_get_name(sclk_audio);
> - clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
> + clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s",
> mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
> CLK_SET_RATE_NO_REPARENT,
> reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
>
> - clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
> + clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp",
> "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
> 0, &lock);
>
> - clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
> + clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
> "dout_aud_bus", "dout_srp", 0,
> reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
>
> - clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
> + clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",
> "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
> &lock);
>
> - clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
> + clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk",
> "dout_srp", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 0, 0, &lock);
>
> - clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
> + clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus",
> "dout_aud_bus", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 2, 0, &lock);
>
> - clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
> + clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s",
> "dout_i2s", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 3, 0, &lock);
>
> - clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
> + clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus",
> "sclk_pcm", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 4, 0, &lock);
>
> sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
> if (!IS_ERR(sclk_pcm_in))
> sclk_pcm_p = __clk_get_name(sclk_pcm_in);
> - clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> + clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm",
> sclk_pcm_p, CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 5, 0, &lock);
>
> if (variant->has_adma_clk) {
> - clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
> + clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma",
> "dout_srp", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 9, 0, &lock);
> }
>
> - for (i = 0; i < clk_data.clk_num; i++) {
> + for (i = 0; i < clk_data->num; i++) {
> if (IS_ERR(clk_table[i])) {
> dev_err(&pdev->dev, "failed to register clock %d\n", i);
> ret = PTR_ERR(clk_table[i]);
> @@ -241,8 +242,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
> }
> }
>
> - ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
> - &clk_data);
> + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
> + clk_data);
> if (ret) {
> dev_err(&pdev->dev, "failed to add clock provider\n");
> goto unregister;
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 4/6] clk: samsung: exynos-audss: Convert to the new clk_hw API
2017-06-09 1:33 ` Chanwoo Choi
@ 2017-06-09 10:25 ` Sylwester Nawrocki
0 siblings, 0 replies; 18+ messages in thread
From: Sylwester Nawrocki @ 2017-06-09 10:25 UTC (permalink / raw)
To: Chanwoo Choi
Cc: Marek Szyprowski, linux-clk, linux-samsung-soc, Stephen Boyd,
Michael Turquette, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Hi Chanwoo,
On 06/09/2017 03:33 AM, Chanwoo Choi wrote:
> I tested this patch[1] which was applied on Sylwester's git repo.
> [1]https://git.linuxtv.org/snawrocki/samsung.git/commit/?h=for-v4.13/clk/next&id=6622c52f47372186c17548ca7398c229c45e6215
>
> When I tested it on XU3, I can't get the kernel booting.
Thanks for checking this, it seems I didn't appply v3 patches from Marek.
I corrected this now and tested on Odroid-XU3. The right patches should
be now in the for-v4.13/clk/next branch.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2017-06-09 10:25 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20170424064228eucas1p26228b4b334cc22ad22e77c8dd2e7dcdd@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 0/6] Samsung clock providers: convert to the new clk_hw API Marek Szyprowski
[not found] ` <CGME20170424064228eucas1p2543d7f206ac18476891e500991611733@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 1/6] clk: samsung: Remove dead code Marek Szyprowski
2017-04-24 6:49 ` Krzysztof Kozlowski
[not found] ` <CGME20170424064229eucas1p2367a90a36b5bcb99f48a24e72b29a629@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 2/6] clk: samsung: Add local variable to match it purpose Marek Szyprowski
2017-04-24 6:53 ` Krzysztof Kozlowski
[not found] ` <CGME20170424075423eucas1p239eaef08b93dade23292c175b838d9a5@eucas1p2.samsung.com>
2017-04-24 7:54 ` [PATCH v2.1 " Marek Szyprowski
2017-04-24 7:56 ` Krzysztof Kozlowski
[not found] ` <CGME20170424064229eucas1p2f2feb95623d6c4ac8db01ff519a53fa9@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 3/6] clk: samsung: Convert common drivers to the new clk_hw API Marek Szyprowski
2017-04-24 6:55 ` Krzysztof Kozlowski
[not found] ` <CGME20170424064230eucas1p183fecc2feda35c3fb5fc1af44d130f59@eucas1p1.samsung.com>
2017-04-24 6:42 ` [PATCH v2 4/6] clk: samsung: exynos-audss: Convert " Marek Szyprowski
[not found] ` <CGME20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55@eucas1p2.samsung.com>
2017-05-15 6:50 ` [PATCH v3 " Marek Szyprowski
2017-06-09 1:33 ` Chanwoo Choi
2017-06-09 10:25 ` Sylwester Nawrocki
[not found] ` <CGME20170424064231eucas1p2edd27880b5adc7c884e00db54c100cc2@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 5/6] clk: samsung: exynos-clkout: " Marek Szyprowski
[not found] ` <CGME20170424064231eucas1p2dc993650881054dfea9aadb6abb0eb38@eucas1p2.samsung.com>
2017-04-24 6:42 ` [PATCH v2 6/6] clk: samsung: s5pv210-audss: " Marek Szyprowski
2017-04-24 6:56 ` Krzysztof Kozlowski
[not found] ` <CGME20170515065110eucas1p1b558e1c1ce24852219aa7d98e3b57dff@eucas1p1.samsung.com>
2017-05-15 6:51 ` [PATCH v3 " Marek Szyprowski
2017-04-25 10:31 ` [PATCH v2 0/6] Samsung clock providers: convert " Sylwester Nawrocki
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