* [PATCH 00/22] hisi_sas: hip08 support
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd, John Garry
This patchset adds support for the HiSilicon SAS controller
in the hip08 chipset.
The key difference compared to earlier chipsets is that the
controller is an integrated PCI endpoint in hip08.
As such, the controller is a pci device (not a platform device,
like v2 hw in hip07).
The driver is refactored so it can support both platform and
pci device-based controllers.
File hisi_sas_pci_init.c is introduced for pci device probing
and initialization. Common functionality is still in
hisi_sas_main.c, along with platform device probing and
initialization.
New hw layer file hisi_sas_v3_hw.c is added for hip08
controller support. HW revisions v2 and v3 are very similar,
but it was decided to keep support in separate files for now.
As for the patches, (ignoring #1 and #2) the first few
reorganise some functions from v2 hw.c into main.c, as they
are required for v3 hw. Then support is added for pci
device-based controller in subsequent patches.
And then hip08 support is added in the final patches.
John Garry (4):
scsi: hisi_sas: add pci_dev in hisi_hba struct
scsi: hisi_sas: add the initialisation for pci-based controller
scsi: hisi_sas: add bare v3 hw driver
scsi: hisi_sas: retrieve SAS address for pci-based controller
Xiang Chen (18):
scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort()
scsi: hisi_sas: optimise the usage of hisi_hba.lock
scsi: hisi_sas: relocate get_ata_protocol()
scsi: hisi_sas: relocate sata_done_v2_hw()
scsi: hisi_sas: relocate get_ncq_tag_v2_hw()
scsi: hisi_sas: add v3 hw init
scsi: hisi_sas: add v3 hw PHY init
scsi: hisi_sas: add phy up/down/bcast and channel ISR
scsi: hisi_sas: add v3 cq interrupt handler
scsi: hisi_sas: add v3 code to send SSP frame
scsi: hisi_sas: add v3 code to send SMP frame
scsi: hisi_sas: add v3 code to send ATA frame
scsi: hisi_sas: add v3 code for itct setup and free
scsi: hisi_sas: add v3 code to send internal abort command
scsi: hisi_sas: add get_wideport_bitmap_v3_hw()
scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
scsi: hisi_sas: add v3 code to fill some more hw function pointers
scsi: hisi_sas: modify internal abort dev flow for v3 hw
drivers/scsi/hisi_sas/Kconfig | 10 +-
drivers/scsi/hisi_sas/Makefile | 2 +
drivers/scsi/hisi_sas/hisi_sas.h | 42 +-
drivers/scsi/hisi_sas/hisi_sas_main.c | 280 +++-
drivers/scsi/hisi_sas/hisi_sas_pci_init.c | 286 ++++
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 51 +-
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 175 +--
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2090 +++++++++++++++++++++++++++++
8 files changed, 2714 insertions(+), 222 deletions(-)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_pci_init.c
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
--
1.9.1
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 01/22] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort()
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
We need to check for timeout before task status, or the task will be
mistook as completed internal abort command.
Also add protection for sas_task.task_state_flags in
hisi_sas_tmf_timedout().
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index d622db5..98535aa 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task)
static void hisi_sas_tmf_timedout(unsigned long data)
{
struct sas_task *task = (struct sas_task *)data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE))
+ task->task_state_flags |= SAS_TASK_STATE_ABORTED;
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
- task->task_state_flags |= SAS_TASK_STATE_ABORTED;
complete(&task->slow_task->completion);
}
@@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task)
wait_for_completion(&task->slow_task->completion);
res = TMF_RESP_FUNC_FAILED;
+ /* Internal abort timed out */
+ if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
+ struct hisi_sas_slot *slot = task->lldd_task;
+
+ if (slot)
+ slot->task = NULL;
+ dev_err(dev, "internal task abort: timeout.\n");
+ }
+ }
+
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == TMF_RESP_FUNC_COMPLETE) {
res = TMF_RESP_FUNC_COMPLETE;
@@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task)
goto exit;
}
- /* Internal abort timed out */
- if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
- if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
- dev_err(dev, "internal task abort: timeout.\n");
- }
- }
-
exit:
dev_dbg(dev, "internal task abort: task to dev %016llx task=%p "
"resp: 0x%x sts 0x%x\n",
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 01/22] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort()
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
We need to check for timeout before task status, or the task will be
mistook as completed internal abort command.
Also add protection for sas_task.task_state_flags in
hisi_sas_tmf_timedout().
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index d622db5..98535aa 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task)
static void hisi_sas_tmf_timedout(unsigned long data)
{
struct sas_task *task = (struct sas_task *)data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE))
+ task->task_state_flags |= SAS_TASK_STATE_ABORTED;
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
- task->task_state_flags |= SAS_TASK_STATE_ABORTED;
complete(&task->slow_task->completion);
}
@@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task)
wait_for_completion(&task->slow_task->completion);
res = TMF_RESP_FUNC_FAILED;
+ /* Internal abort timed out */
+ if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
+ if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
+ struct hisi_sas_slot *slot = task->lldd_task;
+
+ if (slot)
+ slot->task = NULL;
+ dev_err(dev, "internal task abort: timeout.\n");
+ }
+ }
+
if (task->task_status.resp == SAS_TASK_COMPLETE &&
task->task_status.stat == TMF_RESP_FUNC_COMPLETE) {
res = TMF_RESP_FUNC_COMPLETE;
@@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task)
goto exit;
}
- /* Internal abort timed out */
- if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
- if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
- dev_err(dev, "internal task abort: timeout.\n");
- }
- }
-
exit:
dev_dbg(dev, "internal task abort: task to dev %016llx task=%p "
"resp: 0x%x sts 0x%x\n",
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 02/22] scsi: hisi_sas: optimise the usage of hisi_hba.lock
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Currently hisi_hba.lock is locked to deliver and receive a
command to/from any hw queue. This causes much
contention at high data-rates.
To boost performance, lock on a per queue basis for
sending and receiving commands to/from hw.
Certain critical regions still need to be locked in the delivery
and completion stages with hisi_hba.lock.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 8 ++---
drivers/scsi/hisi_sas/hisi_sas_main.c | 59 ++++++++++++++++++++++------------
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 23 +++++--------
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 30 ++++++++---------
4 files changed, 64 insertions(+), 56 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 4e28f32..88f06be 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -102,8 +102,10 @@ struct hisi_sas_cq {
struct hisi_sas_dq {
struct hisi_hba *hisi_hba;
+ spinlock_t lock;
int wr_point;
int id;
+ struct hisi_sas_slot *slot_prep;
};
struct hisi_sas_device {
@@ -154,9 +156,8 @@ struct hisi_sas_hw {
struct domain_device *device);
struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no);
- int (*get_free_slot)(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s);
- void (*start_delivery)(struct hisi_hba *hisi_hba);
+ int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq);
+ void (*start_delivery)(struct hisi_sas_dq *dq);
int (*prep_ssp)(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot, int is_tmf,
struct hisi_sas_tmf_task *tmf);
@@ -217,7 +218,6 @@ struct hisi_hba {
struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
int queue_count;
- struct hisi_sas_slot *slot_prep;
struct dma_pool *sge_page_pool;
struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 98535aa..c986618 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -179,10 +179,11 @@ static void hisi_sas_slot_abort(struct work_struct *work)
task->task_done(task);
}
-static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
- int is_tmf, struct hisi_sas_tmf_task *tmf,
- int *pass)
+static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq
+ *dq, int is_tmf, struct hisi_sas_tmf_task *tmf,
+ int *pass)
{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_sas_port *port;
@@ -240,18 +241,24 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
} else
n_elem = task->num_scatter;
+ spin_lock_irqsave(&hisi_hba->lock, flags);
if (hisi_hba->hw->slot_index_alloc)
rc = hisi_hba->hw->slot_index_alloc(hisi_hba, &slot_idx,
device);
else
rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
- if (rc)
+ if (rc) {
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
goto err_out;
- rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id,
- &dlvry_queue, &dlvry_queue_slot);
+ }
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+ rc = hisi_hba->hw->get_free_slot(hisi_hba, dq);
if (rc)
goto err_out_tag;
+ dlvry_queue = dq->id;
+ dlvry_queue_slot = dq->wr_point;
slot = &hisi_hba->slot_info[slot_idx];
memset(slot, 0, sizeof(struct hisi_sas_slot));
@@ -316,7 +323,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
task->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock_irqrestore(&task->task_state_lock, flags);
- hisi_hba->slot_prep = slot;
+ dq->slot_prep = slot;
atomic64_inc(&sas_dev->running_req);
++(*pass);
@@ -354,19 +361,23 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,
unsigned long flags;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
struct device *dev = &hisi_hba->pdev->dev;
+ struct domain_device *device = task->dev;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ int queue_id = sas_dev->device_id % hisi_hba->queue_count;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id];
if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)))
return -EINVAL;
/* protect task_prep and start_delivery sequence */
- spin_lock_irqsave(&hisi_hba->lock, flags);
- rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass);
+ spin_lock_irqsave(&dq->lock, flags);
+ rc = hisi_sas_task_prep(task, dq, is_tmf, tmf, &pass);
if (rc)
dev_err(dev, "task exec: failed[%d]!\n", rc);
if (likely(pass))
- hisi_hba->hw->start_delivery(hisi_hba);
- spin_unlock_irqrestore(&hisi_hba->lock, flags);
+ hisi_hba->hw->start_delivery(dq);
+ spin_unlock_irqrestore(&dq->lock, flags);
return rc;
}
@@ -1142,6 +1153,8 @@ static int hisi_sas_query_task(struct sas_task *task)
struct hisi_sas_cmd_hdr *cmd_hdr_base;
int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
unsigned long flags;
+ int queue_id = sas_dev->device_id % hisi_hba->queue_count;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id];
if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)))
return -EINVAL;
@@ -1152,14 +1165,22 @@ static int hisi_sas_query_task(struct sas_task *task)
port = to_hisi_sas_port(sas_port);
/* simply get a slot and send abort command */
+ spin_lock_irqsave(&hisi_hba->lock, flags);
rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
- if (rc)
+ if (rc) {
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
goto err_out;
- rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id,
- &dlvry_queue, &dlvry_queue_slot);
+ }
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+ spin_lock_irqsave(&dq->lock, flags);
+ rc = hisi_hba->hw->get_free_slot(hisi_hba, dq);
if (rc)
goto err_out_tag;
+ dlvry_queue = dq->id;
+ dlvry_queue_slot = dq->wr_point;
+
slot = &hisi_hba->slot_info[slot_idx];
memset(slot, 0, sizeof(struct hisi_sas_slot));
@@ -1186,18 +1207,20 @@ static int hisi_sas_query_task(struct sas_task *task)
task->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock_irqrestore(&task->task_state_lock, flags);
- hisi_hba->slot_prep = slot;
+ dq->slot_prep = slot;
atomic64_inc(&sas_dev->running_req);
/* send abort command to our chip */
- hisi_hba->hw->start_delivery(hisi_hba);
+ hisi_hba->hw->start_delivery(dq);
+ spin_unlock_irqrestore(&dq->lock, flags);
return 0;
err_out_tag:
hisi_sas_slot_index_free(hisi_hba, slot_idx);
err_out:
+ spin_unlock_irqrestore(&dq->lock, flags);
dev_err(dev, "internal abort task prep: failed[%d]!\n", rc);
return rc;
@@ -1221,7 +1244,6 @@ static int hisi_sas_query_task(struct sas_task *task)
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct device *dev = &hisi_hba->pdev->dev;
int res;
- unsigned long flags;
if (!hisi_hba->hw->prep_abort)
return -EOPNOTSUPP;
@@ -1238,11 +1260,8 @@ static int hisi_sas_query_task(struct sas_task *task)
task->slow_task->timer.expires = jiffies + msecs_to_jiffies(110);
add_timer(&task->slow_task->timer);
- /* Lock as we are alloc'ing a slot, which cannot be interrupted */
- spin_lock_irqsave(&hisi_hba->lock, flags);
res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id,
task, abort_flag, tag);
- spin_unlock_irqrestore(&hisi_hba->lock, flags);
if (res) {
del_timer(&task->slow_task->timer);
dev_err(dev, "internal task abort: executing internal task failed: %d\n",
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index fc1c1b2..7d7d2a7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -900,22 +900,17 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
return bitmap;
}
-/**
- * This function allocates across all queues to load balance.
- * Slots are allocated from queues in a round-robin fashion.
- *
+/*
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
*/
-static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s)
+static int
+get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
struct device *dev = &hisi_hba->pdev->dev;
- struct hisi_sas_dq *dq;
+ int queue = dq->id;
u32 r, w;
- int queue = dev_id % hisi_hba->queue_count;
- dq = &hisi_hba->dq[queue];
w = dq->wr_point;
r = hisi_sas_read32_relaxed(hisi_hba,
DLVRY_Q_0_RD_PTR + (queue * 0x14));
@@ -924,16 +919,14 @@ static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id,
return -EAGAIN;
}
- *q = queue;
- *s = w;
return 0;
}
-static void start_delivery_v1_hw(struct hisi_hba *hisi_hba)
+static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
{
- int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
- int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
- struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index e241921..193cc43 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -1454,22 +1454,17 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
return bitmap;
}
-/**
- * This function allocates across all queues to load balance.
- * Slots are allocated from queues in a round-robin fashion.
- *
+/*
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
*/
-static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s)
+static int
+get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
struct device *dev = &hisi_hba->pdev->dev;
- struct hisi_sas_dq *dq;
+ int queue = dq->id;
u32 r, w;
- int queue = dev_id % hisi_hba->queue_count;
- dq = &hisi_hba->dq[queue];
w = dq->wr_point;
r = hisi_sas_read32_relaxed(hisi_hba,
DLVRY_Q_0_RD_PTR + (queue * 0x14));
@@ -1479,16 +1474,14 @@ static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id,
return -EAGAIN;
}
- *q = queue;
- *s = w;
return 0;
}
-static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
+static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
{
- int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
- int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
- struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
@@ -2344,7 +2337,9 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
spin_lock_irqsave(&task->task_state_lock, flags);
task->task_state_flags |= SAS_TASK_STATE_DONE;
spin_unlock_irqrestore(&task->task_state_lock, flags);
+ spin_lock_irqsave(&hisi_hba->lock, flags);
hisi_sas_slot_task_free(hisi_hba, task, slot);
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
sts = ts->stat;
if (task->task_done)
@@ -3162,13 +3157,14 @@ static void cq_tasklet_v2_hw(unsigned long val)
struct hisi_sas_complete_v2_hdr *complete_queue;
u32 rd_point = cq->rd_point, wr_point, dev_id;
int queue = cq->id;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
if (unlikely(hisi_hba->reject_stp_links_msk))
phys_try_accept_stp_links_v2_hw(hisi_hba);
complete_queue = hisi_hba->complete_hdr[queue];
- spin_lock(&hisi_hba->lock);
+ spin_lock(&dq->lock);
wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
(0x14 * queue));
@@ -3218,7 +3214,7 @@ static void cq_tasklet_v2_hw(unsigned long val)
/* update rd_point */
cq->rd_point = rd_point;
hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
- spin_unlock(&hisi_hba->lock);
+ spin_unlock(&dq->lock);
}
static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 02/22] scsi: hisi_sas: optimise the usage of hisi_hba.lock
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Currently hisi_hba.lock is locked to deliver and receive a
command to/from any hw queue. This causes much
contention at high data-rates.
To boost performance, lock on a per queue basis for
sending and receiving commands to/from hw.
Certain critical regions still need to be locked in the delivery
and completion stages with hisi_hba.lock.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 8 ++---
drivers/scsi/hisi_sas/hisi_sas_main.c | 59 ++++++++++++++++++++++------------
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 23 +++++--------
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 30 ++++++++---------
4 files changed, 64 insertions(+), 56 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 4e28f32..88f06be 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -102,8 +102,10 @@ struct hisi_sas_cq {
struct hisi_sas_dq {
struct hisi_hba *hisi_hba;
+ spinlock_t lock;
int wr_point;
int id;
+ struct hisi_sas_slot *slot_prep;
};
struct hisi_sas_device {
@@ -154,9 +156,8 @@ struct hisi_sas_hw {
struct domain_device *device);
struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
void (*sl_notify)(struct hisi_hba *hisi_hba, int phy_no);
- int (*get_free_slot)(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s);
- void (*start_delivery)(struct hisi_hba *hisi_hba);
+ int (*get_free_slot)(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq);
+ void (*start_delivery)(struct hisi_sas_dq *dq);
int (*prep_ssp)(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot, int is_tmf,
struct hisi_sas_tmf_task *tmf);
@@ -217,7 +218,6 @@ struct hisi_hba {
struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
int queue_count;
- struct hisi_sas_slot *slot_prep;
struct dma_pool *sge_page_pool;
struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 98535aa..c986618 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -179,10 +179,11 @@ static void hisi_sas_slot_abort(struct work_struct *work)
task->task_done(task);
}
-static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
- int is_tmf, struct hisi_sas_tmf_task *tmf,
- int *pass)
+static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq
+ *dq, int is_tmf, struct hisi_sas_tmf_task *tmf,
+ int *pass)
{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_sas_port *port;
@@ -240,18 +241,24 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
} else
n_elem = task->num_scatter;
+ spin_lock_irqsave(&hisi_hba->lock, flags);
if (hisi_hba->hw->slot_index_alloc)
rc = hisi_hba->hw->slot_index_alloc(hisi_hba, &slot_idx,
device);
else
rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
- if (rc)
+ if (rc) {
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
goto err_out;
- rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id,
- &dlvry_queue, &dlvry_queue_slot);
+ }
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+ rc = hisi_hba->hw->get_free_slot(hisi_hba, dq);
if (rc)
goto err_out_tag;
+ dlvry_queue = dq->id;
+ dlvry_queue_slot = dq->wr_point;
slot = &hisi_hba->slot_info[slot_idx];
memset(slot, 0, sizeof(struct hisi_sas_slot));
@@ -316,7 +323,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_hba *hisi_hba,
task->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock_irqrestore(&task->task_state_lock, flags);
- hisi_hba->slot_prep = slot;
+ dq->slot_prep = slot;
atomic64_inc(&sas_dev->running_req);
++(*pass);
@@ -354,19 +361,23 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,
unsigned long flags;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
struct device *dev = &hisi_hba->pdev->dev;
+ struct domain_device *device = task->dev;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ int queue_id = sas_dev->device_id % hisi_hba->queue_count;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id];
if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)))
return -EINVAL;
/* protect task_prep and start_delivery sequence */
- spin_lock_irqsave(&hisi_hba->lock, flags);
- rc = hisi_sas_task_prep(task, hisi_hba, is_tmf, tmf, &pass);
+ spin_lock_irqsave(&dq->lock, flags);
+ rc = hisi_sas_task_prep(task, dq, is_tmf, tmf, &pass);
if (rc)
dev_err(dev, "task exec: failed[%d]!\n", rc);
if (likely(pass))
- hisi_hba->hw->start_delivery(hisi_hba);
- spin_unlock_irqrestore(&hisi_hba->lock, flags);
+ hisi_hba->hw->start_delivery(dq);
+ spin_unlock_irqrestore(&dq->lock, flags);
return rc;
}
@@ -1142,6 +1153,8 @@ static int hisi_sas_query_task(struct sas_task *task)
struct hisi_sas_cmd_hdr *cmd_hdr_base;
int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
unsigned long flags;
+ int queue_id = sas_dev->device_id % hisi_hba->queue_count;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue_id];
if (unlikely(test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)))
return -EINVAL;
@@ -1152,14 +1165,22 @@ static int hisi_sas_query_task(struct sas_task *task)
port = to_hisi_sas_port(sas_port);
/* simply get a slot and send abort command */
+ spin_lock_irqsave(&hisi_hba->lock, flags);
rc = hisi_sas_slot_index_alloc(hisi_hba, &slot_idx);
- if (rc)
+ if (rc) {
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
goto err_out;
- rc = hisi_hba->hw->get_free_slot(hisi_hba, sas_dev->device_id,
- &dlvry_queue, &dlvry_queue_slot);
+ }
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+
+ spin_lock_irqsave(&dq->lock, flags);
+ rc = hisi_hba->hw->get_free_slot(hisi_hba, dq);
if (rc)
goto err_out_tag;
+ dlvry_queue = dq->id;
+ dlvry_queue_slot = dq->wr_point;
+
slot = &hisi_hba->slot_info[slot_idx];
memset(slot, 0, sizeof(struct hisi_sas_slot));
@@ -1186,18 +1207,20 @@ static int hisi_sas_query_task(struct sas_task *task)
task->task_state_flags |= SAS_TASK_AT_INITIATOR;
spin_unlock_irqrestore(&task->task_state_lock, flags);
- hisi_hba->slot_prep = slot;
+ dq->slot_prep = slot;
atomic64_inc(&sas_dev->running_req);
/* send abort command to our chip */
- hisi_hba->hw->start_delivery(hisi_hba);
+ hisi_hba->hw->start_delivery(dq);
+ spin_unlock_irqrestore(&dq->lock, flags);
return 0;
err_out_tag:
hisi_sas_slot_index_free(hisi_hba, slot_idx);
err_out:
+ spin_unlock_irqrestore(&dq->lock, flags);
dev_err(dev, "internal abort task prep: failed[%d]!\n", rc);
return rc;
@@ -1221,7 +1244,6 @@ static int hisi_sas_query_task(struct sas_task *task)
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct device *dev = &hisi_hba->pdev->dev;
int res;
- unsigned long flags;
if (!hisi_hba->hw->prep_abort)
return -EOPNOTSUPP;
@@ -1238,11 +1260,8 @@ static int hisi_sas_query_task(struct sas_task *task)
task->slow_task->timer.expires = jiffies + msecs_to_jiffies(110);
add_timer(&task->slow_task->timer);
- /* Lock as we are alloc'ing a slot, which cannot be interrupted */
- spin_lock_irqsave(&hisi_hba->lock, flags);
res = hisi_sas_internal_abort_task_exec(hisi_hba, sas_dev->device_id,
task, abort_flag, tag);
- spin_unlock_irqrestore(&hisi_hba->lock, flags);
if (res) {
del_timer(&task->slow_task->timer);
dev_err(dev, "internal task abort: executing internal task failed: %d\n",
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index fc1c1b2..7d7d2a7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -900,22 +900,17 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
return bitmap;
}
-/**
- * This function allocates across all queues to load balance.
- * Slots are allocated from queues in a round-robin fashion.
- *
+/*
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
*/
-static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s)
+static int
+get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
struct device *dev = &hisi_hba->pdev->dev;
- struct hisi_sas_dq *dq;
+ int queue = dq->id;
u32 r, w;
- int queue = dev_id % hisi_hba->queue_count;
- dq = &hisi_hba->dq[queue];
w = dq->wr_point;
r = hisi_sas_read32_relaxed(hisi_hba,
DLVRY_Q_0_RD_PTR + (queue * 0x14));
@@ -924,16 +919,14 @@ static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id,
return -EAGAIN;
}
- *q = queue;
- *s = w;
return 0;
}
-static void start_delivery_v1_hw(struct hisi_hba *hisi_hba)
+static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
{
- int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
- int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
- struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index e241921..193cc43 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -1454,22 +1454,17 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
return bitmap;
}
-/**
- * This function allocates across all queues to load balance.
- * Slots are allocated from queues in a round-robin fashion.
- *
+/*
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
*/
-static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id,
- int *q, int *s)
+static int
+get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
struct device *dev = &hisi_hba->pdev->dev;
- struct hisi_sas_dq *dq;
+ int queue = dq->id;
u32 r, w;
- int queue = dev_id % hisi_hba->queue_count;
- dq = &hisi_hba->dq[queue];
w = dq->wr_point;
r = hisi_sas_read32_relaxed(hisi_hba,
DLVRY_Q_0_RD_PTR + (queue * 0x14));
@@ -1479,16 +1474,14 @@ static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id,
return -EAGAIN;
}
- *q = queue;
- *s = w;
return 0;
}
-static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
+static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
{
- int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
- int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
- struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue];
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
@@ -2344,7 +2337,9 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
spin_lock_irqsave(&task->task_state_lock, flags);
task->task_state_flags |= SAS_TASK_STATE_DONE;
spin_unlock_irqrestore(&task->task_state_lock, flags);
+ spin_lock_irqsave(&hisi_hba->lock, flags);
hisi_sas_slot_task_free(hisi_hba, task, slot);
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
sts = ts->stat;
if (task->task_done)
@@ -3162,13 +3157,14 @@ static void cq_tasklet_v2_hw(unsigned long val)
struct hisi_sas_complete_v2_hdr *complete_queue;
u32 rd_point = cq->rd_point, wr_point, dev_id;
int queue = cq->id;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
if (unlikely(hisi_hba->reject_stp_links_msk))
phys_try_accept_stp_links_v2_hw(hisi_hba);
complete_queue = hisi_hba->complete_hdr[queue];
- spin_lock(&hisi_hba->lock);
+ spin_lock(&dq->lock);
wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
(0x14 * queue));
@@ -3218,7 +3214,7 @@ static void cq_tasklet_v2_hw(unsigned long val)
/* update rd_point */
cq->rd_point = rd_point;
hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
- spin_unlock(&hisi_hba->lock);
+ spin_unlock(&dq->lock);
}
static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 03/22] scsi: hisi_sas: relocate get_ata_protocol()
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ata_protocol() to a common location, as future
hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 65 +++++++++++++++++++++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 67 +---------------------------------
3 files changed, 68 insertions(+), 65 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 88f06be..02ec10b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -355,6 +355,7 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index c986618..437eefe 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -15,6 +15,12 @@
#define DEV_IS_GONE(dev) \
((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
+#define SATA_PROTOCOL_NONDATA 0x1
+#define SATA_PROTOCOL_PIO 0x2
+#define SATA_PROTOCOL_DMA 0x4
+#define SATA_PROTOCOL_FPDMA 0x8
+#define SATA_PROTOCOL_ATAPI 0x10
+
static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device,
u8 *lun, struct hisi_sas_tmf_task *tmf);
static int
@@ -23,6 +29,65 @@ static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device,
int abort_flag, int tag);
static int hisi_sas_softreset_ata_disk(struct domain_device *device);
+u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
+{
+ switch (cmd) {
+ case ATA_CMD_FPDMA_WRITE:
+ case ATA_CMD_FPDMA_READ:
+ case ATA_CMD_FPDMA_RECV:
+ case ATA_CMD_FPDMA_SEND:
+ case ATA_CMD_NCQ_NON_DATA:
+ return SATA_PROTOCOL_FPDMA;
+
+ case ATA_CMD_DOWNLOAD_MICRO:
+ case ATA_CMD_ID_ATA:
+ case ATA_CMD_PMP_READ:
+ case ATA_CMD_READ_LOG_EXT:
+ case ATA_CMD_PIO_READ:
+ case ATA_CMD_PIO_READ_EXT:
+ case ATA_CMD_PMP_WRITE:
+ case ATA_CMD_WRITE_LOG_EXT:
+ case ATA_CMD_PIO_WRITE:
+ case ATA_CMD_PIO_WRITE_EXT:
+ return SATA_PROTOCOL_PIO;
+
+ case ATA_CMD_DSM:
+ case ATA_CMD_DOWNLOAD_MICRO_DMA:
+ case ATA_CMD_PMP_READ_DMA:
+ case ATA_CMD_PMP_WRITE_DMA:
+ case ATA_CMD_READ:
+ case ATA_CMD_READ_EXT:
+ case ATA_CMD_READ_LOG_DMA_EXT:
+ case ATA_CMD_READ_STREAM_DMA_EXT:
+ case ATA_CMD_TRUSTED_RCV_DMA:
+ case ATA_CMD_TRUSTED_SND_DMA:
+ case ATA_CMD_WRITE:
+ case ATA_CMD_WRITE_EXT:
+ case ATA_CMD_WRITE_FUA_EXT:
+ case ATA_CMD_WRITE_QUEUED:
+ case ATA_CMD_WRITE_LOG_DMA_EXT:
+ case ATA_CMD_WRITE_STREAM_DMA_EXT:
+ return SATA_PROTOCOL_DMA;
+
+ case ATA_CMD_CHK_POWER:
+ case ATA_CMD_DEV_RESET:
+ case ATA_CMD_EDD:
+ case ATA_CMD_FLUSH:
+ case ATA_CMD_FLUSH_EXT:
+ case ATA_CMD_VERIFY:
+ case ATA_CMD_VERIFY_EXT:
+ case ATA_CMD_SET_FEATURES:
+ case ATA_CMD_STANDBY:
+ case ATA_CMD_STANDBYNOW1:
+ return SATA_PROTOCOL_NONDATA;
+ default:
+ if (direction == DMA_NONE)
+ return SATA_PROTOCOL_NONDATA;
+ return SATA_PROTOCOL_PIO;
+ }
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 193cc43..397f01e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -554,12 +554,6 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
-#define SATA_PROTOCOL_NONDATA 0x1
-#define SATA_PROTOCOL_PIO 0x2
-#define SATA_PROTOCOL_DMA 0x4
-#define SATA_PROTOCOL_FPDMA 0x8
-#define SATA_PROTOCOL_ATAPI 0x10
-
#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
err_phase == 0x4 || err_phase == 0x8 ||\
err_phase == 0x6 || err_phase == 0xa)
@@ -2348,64 +2342,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static u8 get_ata_protocol(u8 cmd, int direction)
-{
- switch (cmd) {
- case ATA_CMD_FPDMA_WRITE:
- case ATA_CMD_FPDMA_READ:
- case ATA_CMD_FPDMA_RECV:
- case ATA_CMD_FPDMA_SEND:
- case ATA_CMD_NCQ_NON_DATA:
- return SATA_PROTOCOL_FPDMA;
-
- case ATA_CMD_DOWNLOAD_MICRO:
- case ATA_CMD_ID_ATA:
- case ATA_CMD_PMP_READ:
- case ATA_CMD_READ_LOG_EXT:
- case ATA_CMD_PIO_READ:
- case ATA_CMD_PIO_READ_EXT:
- case ATA_CMD_PMP_WRITE:
- case ATA_CMD_WRITE_LOG_EXT:
- case ATA_CMD_PIO_WRITE:
- case ATA_CMD_PIO_WRITE_EXT:
- return SATA_PROTOCOL_PIO;
-
- case ATA_CMD_DSM:
- case ATA_CMD_DOWNLOAD_MICRO_DMA:
- case ATA_CMD_PMP_READ_DMA:
- case ATA_CMD_PMP_WRITE_DMA:
- case ATA_CMD_READ:
- case ATA_CMD_READ_EXT:
- case ATA_CMD_READ_LOG_DMA_EXT:
- case ATA_CMD_READ_STREAM_DMA_EXT:
- case ATA_CMD_TRUSTED_RCV_DMA:
- case ATA_CMD_TRUSTED_SND_DMA:
- case ATA_CMD_WRITE:
- case ATA_CMD_WRITE_EXT:
- case ATA_CMD_WRITE_FUA_EXT:
- case ATA_CMD_WRITE_QUEUED:
- case ATA_CMD_WRITE_LOG_DMA_EXT:
- case ATA_CMD_WRITE_STREAM_DMA_EXT:
- return SATA_PROTOCOL_DMA;
-
- case ATA_CMD_CHK_POWER:
- case ATA_CMD_DEV_RESET:
- case ATA_CMD_EDD:
- case ATA_CMD_FLUSH:
- case ATA_CMD_FLUSH_EXT:
- case ATA_CMD_VERIFY:
- case ATA_CMD_VERIFY_EXT:
- case ATA_CMD_SET_FEATURES:
- case ATA_CMD_STANDBY:
- case ATA_CMD_STANDBYNOW1:
- return SATA_PROTOCOL_NONDATA;
- default:
- if (direction == DMA_NONE)
- return SATA_PROTOCOL_NONDATA;
- return SATA_PROTOCOL_PIO;
- }
-}
-
static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
{
struct ata_queued_cmd *qc = task->uldd_task;
@@ -2460,7 +2396,8 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
(task->ata_task.fis.control & ATA_SRST))
dw1 |= 1 << CMD_HDR_RESET_OFF;
- dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
+ dw1 |= (hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command, task->data_dir))
<< CMD_HDR_FRAME_TYPE_OFF;
dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
hdr->dw1 = cpu_to_le32(dw1);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 03/22] scsi: hisi_sas: relocate get_ata_protocol()
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ata_protocol() to a common location, as future
hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 65 +++++++++++++++++++++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 67 +---------------------------------
3 files changed, 68 insertions(+), 65 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 88f06be..02ec10b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -355,6 +355,7 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index c986618..437eefe 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -15,6 +15,12 @@
#define DEV_IS_GONE(dev) \
((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
+#define SATA_PROTOCOL_NONDATA 0x1
+#define SATA_PROTOCOL_PIO 0x2
+#define SATA_PROTOCOL_DMA 0x4
+#define SATA_PROTOCOL_FPDMA 0x8
+#define SATA_PROTOCOL_ATAPI 0x10
+
static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device,
u8 *lun, struct hisi_sas_tmf_task *tmf);
static int
@@ -23,6 +29,65 @@ static int hisi_sas_debug_issue_ssp_tmf(struct domain_device *device,
int abort_flag, int tag);
static int hisi_sas_softreset_ata_disk(struct domain_device *device);
+u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
+{
+ switch (cmd) {
+ case ATA_CMD_FPDMA_WRITE:
+ case ATA_CMD_FPDMA_READ:
+ case ATA_CMD_FPDMA_RECV:
+ case ATA_CMD_FPDMA_SEND:
+ case ATA_CMD_NCQ_NON_DATA:
+ return SATA_PROTOCOL_FPDMA;
+
+ case ATA_CMD_DOWNLOAD_MICRO:
+ case ATA_CMD_ID_ATA:
+ case ATA_CMD_PMP_READ:
+ case ATA_CMD_READ_LOG_EXT:
+ case ATA_CMD_PIO_READ:
+ case ATA_CMD_PIO_READ_EXT:
+ case ATA_CMD_PMP_WRITE:
+ case ATA_CMD_WRITE_LOG_EXT:
+ case ATA_CMD_PIO_WRITE:
+ case ATA_CMD_PIO_WRITE_EXT:
+ return SATA_PROTOCOL_PIO;
+
+ case ATA_CMD_DSM:
+ case ATA_CMD_DOWNLOAD_MICRO_DMA:
+ case ATA_CMD_PMP_READ_DMA:
+ case ATA_CMD_PMP_WRITE_DMA:
+ case ATA_CMD_READ:
+ case ATA_CMD_READ_EXT:
+ case ATA_CMD_READ_LOG_DMA_EXT:
+ case ATA_CMD_READ_STREAM_DMA_EXT:
+ case ATA_CMD_TRUSTED_RCV_DMA:
+ case ATA_CMD_TRUSTED_SND_DMA:
+ case ATA_CMD_WRITE:
+ case ATA_CMD_WRITE_EXT:
+ case ATA_CMD_WRITE_FUA_EXT:
+ case ATA_CMD_WRITE_QUEUED:
+ case ATA_CMD_WRITE_LOG_DMA_EXT:
+ case ATA_CMD_WRITE_STREAM_DMA_EXT:
+ return SATA_PROTOCOL_DMA;
+
+ case ATA_CMD_CHK_POWER:
+ case ATA_CMD_DEV_RESET:
+ case ATA_CMD_EDD:
+ case ATA_CMD_FLUSH:
+ case ATA_CMD_FLUSH_EXT:
+ case ATA_CMD_VERIFY:
+ case ATA_CMD_VERIFY_EXT:
+ case ATA_CMD_SET_FEATURES:
+ case ATA_CMD_STANDBY:
+ case ATA_CMD_STANDBYNOW1:
+ return SATA_PROTOCOL_NONDATA;
+ default:
+ if (direction == DMA_NONE)
+ return SATA_PROTOCOL_NONDATA;
+ return SATA_PROTOCOL_PIO;
+ }
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 193cc43..397f01e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -554,12 +554,6 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
-#define SATA_PROTOCOL_NONDATA 0x1
-#define SATA_PROTOCOL_PIO 0x2
-#define SATA_PROTOCOL_DMA 0x4
-#define SATA_PROTOCOL_FPDMA 0x8
-#define SATA_PROTOCOL_ATAPI 0x10
-
#define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
err_phase == 0x4 || err_phase == 0x8 ||\
err_phase == 0x6 || err_phase == 0xa)
@@ -2348,64 +2342,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static u8 get_ata_protocol(u8 cmd, int direction)
-{
- switch (cmd) {
- case ATA_CMD_FPDMA_WRITE:
- case ATA_CMD_FPDMA_READ:
- case ATA_CMD_FPDMA_RECV:
- case ATA_CMD_FPDMA_SEND:
- case ATA_CMD_NCQ_NON_DATA:
- return SATA_PROTOCOL_FPDMA;
-
- case ATA_CMD_DOWNLOAD_MICRO:
- case ATA_CMD_ID_ATA:
- case ATA_CMD_PMP_READ:
- case ATA_CMD_READ_LOG_EXT:
- case ATA_CMD_PIO_READ:
- case ATA_CMD_PIO_READ_EXT:
- case ATA_CMD_PMP_WRITE:
- case ATA_CMD_WRITE_LOG_EXT:
- case ATA_CMD_PIO_WRITE:
- case ATA_CMD_PIO_WRITE_EXT:
- return SATA_PROTOCOL_PIO;
-
- case ATA_CMD_DSM:
- case ATA_CMD_DOWNLOAD_MICRO_DMA:
- case ATA_CMD_PMP_READ_DMA:
- case ATA_CMD_PMP_WRITE_DMA:
- case ATA_CMD_READ:
- case ATA_CMD_READ_EXT:
- case ATA_CMD_READ_LOG_DMA_EXT:
- case ATA_CMD_READ_STREAM_DMA_EXT:
- case ATA_CMD_TRUSTED_RCV_DMA:
- case ATA_CMD_TRUSTED_SND_DMA:
- case ATA_CMD_WRITE:
- case ATA_CMD_WRITE_EXT:
- case ATA_CMD_WRITE_FUA_EXT:
- case ATA_CMD_WRITE_QUEUED:
- case ATA_CMD_WRITE_LOG_DMA_EXT:
- case ATA_CMD_WRITE_STREAM_DMA_EXT:
- return SATA_PROTOCOL_DMA;
-
- case ATA_CMD_CHK_POWER:
- case ATA_CMD_DEV_RESET:
- case ATA_CMD_EDD:
- case ATA_CMD_FLUSH:
- case ATA_CMD_FLUSH_EXT:
- case ATA_CMD_VERIFY:
- case ATA_CMD_VERIFY_EXT:
- case ATA_CMD_SET_FEATURES:
- case ATA_CMD_STANDBY:
- case ATA_CMD_STANDBYNOW1:
- return SATA_PROTOCOL_NONDATA;
- default:
- if (direction == DMA_NONE)
- return SATA_PROTOCOL_NONDATA;
- return SATA_PROTOCOL_PIO;
- }
-}
-
static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
{
struct ata_queued_cmd *qc = task->uldd_task;
@@ -2460,7 +2396,8 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
(task->ata_task.fis.control & ATA_SRST))
dw1 |= 1 << CMD_HDR_RESET_OFF;
- dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
+ dw1 |= (hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command, task->data_dir))
<< CMD_HDR_FRAME_TYPE_OFF;
dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
hdr->dw1 = cpu_to_le32(dw1);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 04/22] scsi: hisi_sas: relocate sata_done_v2_hw()
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ata_protocol() to a common location, as future hw
versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 18 ++----------------
3 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 02ec10b..d0c0844 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -357,6 +357,8 @@ struct hisi_sas_command_table_ssp {
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
+extern void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 437eefe..335f3ba4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -88,6 +88,21 @@ u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
}
EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
+ struct dev_to_host_fis *d2h = slot->status_buffer +
+ sizeof(struct hisi_sas_err_record);
+
+ resp->frame_len = sizeof(struct dev_to_host_fis);
+ memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
+
+ ts->buf_valid_size = sizeof(*resp);
+}
+EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 397f01e..51140dc 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -1679,20 +1679,6 @@ static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
return 0;
}
-static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
- struct hisi_sas_slot *slot)
-{
- struct task_status_struct *ts = &task->task_status;
- struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
- struct dev_to_host_fis *d2h = slot->status_buffer +
- sizeof(struct hisi_sas_err_record);
-
- resp->frame_len = sizeof(struct dev_to_host_fis);
- memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
-
- ts->buf_valid_size = sizeof(*resp);
-}
-
#define TRANS_TX_ERR 0
#define TRANS_RX_ERR 1
#define DMA_TX_ERR 2
@@ -2185,7 +2171,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
break;
}
}
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
}
break;
default:
@@ -2313,7 +2299,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
{
ts->stat = SAM_STAT_GOOD;
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
break;
}
default:
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 04/22] scsi: hisi_sas: relocate sata_done_v2_hw()
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ata_protocol() to a common location, as future hw
versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 18 ++----------------
3 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 02ec10b..d0c0844 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -357,6 +357,8 @@ struct hisi_sas_command_table_ssp {
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
+extern void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 437eefe..335f3ba4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -88,6 +88,21 @@ u8 hisi_sas_get_ata_protocol(u8 cmd, int direction)
}
EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
+void hisi_sas_sata_done(struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
+ struct dev_to_host_fis *d2h = slot->status_buffer +
+ sizeof(struct hisi_sas_err_record);
+
+ resp->frame_len = sizeof(struct dev_to_host_fis);
+ memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
+
+ ts->buf_valid_size = sizeof(*resp);
+}
+EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 397f01e..51140dc 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -1679,20 +1679,6 @@ static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
return 0;
}
-static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
- struct hisi_sas_slot *slot)
-{
- struct task_status_struct *ts = &task->task_status;
- struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
- struct dev_to_host_fis *d2h = slot->status_buffer +
- sizeof(struct hisi_sas_err_record);
-
- resp->frame_len = sizeof(struct dev_to_host_fis);
- memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
-
- ts->buf_valid_size = sizeof(*resp);
-}
-
#define TRANS_TX_ERR 0
#define TRANS_RX_ERR 1
#define DMA_TX_ERR 2
@@ -2185,7 +2171,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
break;
}
}
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
}
break;
default:
@@ -2313,7 +2299,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
{
ts->stat = SAM_STAT_GOOD;
- sata_done_v2_hw(hisi_hba, task, slot);
+ hisi_sas_sata_done(task, slot);
break;
}
default:
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 05/22] scsi: hisi_sas: relocate get_ncq_tag_v2_hw()
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ncq_tag_v2_hw() to a common location, as
future hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 16 +---------------
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index d0c0844..210daec 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -359,6 +359,7 @@ struct hisi_sas_command_table_ssp {
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
+extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 335f3ba4..12fece3 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -103,6 +103,21 @@ void hisi_sas_sata_done(struct sas_task *task,
}
EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 51140dc..e64047c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -2328,20 +2328,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
-{
- struct ata_queued_cmd *qc = task->uldd_task;
-
- if (qc) {
- if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
- qc->tf.command == ATA_CMD_FPDMA_READ) {
- *tag = qc->tag;
- return 1;
- }
- }
- return 0;
-}
-
static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot)
{
@@ -2389,7 +2375,7 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
hdr->dw1 = cpu_to_le32(dw1);
/* dw2 */
- if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
+ if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 05/22] scsi: hisi_sas: relocate get_ncq_tag_v2_hw()
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Relocate get_ncq_tag_v2_hw() to a common location, as
future hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 16 +---------------
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index d0c0844..210daec 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -359,6 +359,7 @@ struct hisi_sas_command_table_ssp {
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
+extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 335f3ba4..12fece3 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -103,6 +103,21 @@ void hisi_sas_sata_done(struct sas_task *task,
}
EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
+int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index 51140dc..e64047c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -2328,20 +2328,6 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
return sts;
}
-static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
-{
- struct ata_queued_cmd *qc = task->uldd_task;
-
- if (qc) {
- if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
- qc->tf.command == ATA_CMD_FPDMA_READ) {
- *tag = qc->tag;
- return 1;
- }
- }
- return 0;
-}
-
static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_slot *slot)
{
@@ -2389,7 +2375,7 @@ static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
hdr->dw1 = cpu_to_le32(dw1);
/* dw2 */
- if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
+ if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 06/22] scsi: hisi_sas: add pci_dev in hisi_hba struct
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Since hip08 SAS controller is based on pci device, add hisi_hba.pci_dev
for hip08 (will be v3), and also rename hisi_hba.pdev to .platform_dev
for clarity.
In addition, for common code which wants to reference the controller
device struct, add hisi_hba.dev, and change the common code to use
it.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 6 ++++-
drivers/scsi/hisi_sas/hisi_sas_main.c | 36 ++++++++++++++--------------
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 +++++++++++-----------
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 44 +++++++++++++++++-----------------
4 files changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 210daec..18044b7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -18,6 +18,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
@@ -189,7 +190,10 @@ struct hisi_hba {
/* This must be the first element, used by SHOST_TO_SAS_HA */
struct sas_ha_struct *p;
- struct platform_device *pdev;
+ struct platform_device *platform_dev;
+ struct pci_dev *pci_dev;
+ struct device *dev;
+
void __iomem *regs;
struct regmap *ctrl;
u32 ctrl_reset_reg;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 12fece3..d20a2f2 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -174,7 +174,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
{
if (task) {
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -251,7 +251,7 @@ static void hisi_sas_slot_abort(struct work_struct *work)
struct scsi_cmnd *cmnd = task->uldd_task;
struct hisi_sas_tmf_task tmf_task;
struct scsi_lun lun;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int tag = abort_slot->idx;
unsigned long flags;
@@ -285,7 +285,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq
struct hisi_sas_slot *slot;
struct hisi_sas_cmd_hdr *cmd_hdr_base;
struct asd_sas_port *sas_port = device->port;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
unsigned long flags;
@@ -455,7 +455,7 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,
u32 pass = 0;
unsigned long flags;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
int queue_id = sas_dev->device_id % hisi_hba->queue_count;
@@ -547,7 +547,7 @@ static int hisi_sas_dev_found(struct domain_device *device)
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
struct domain_device *parent_dev = device->parent;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
if (hisi_hba->hw->alloc_dev)
sas_dev = hisi_hba->hw->alloc_dev(device);
@@ -732,7 +732,7 @@ static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 dev_id = sas_dev->device_id;
dev_info(dev, "found dev[%lld:%x] is gone\n",
@@ -815,7 +815,7 @@ static int hisi_sas_exec_internal_tmf_task(struct domain_device *device,
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct sas_task *task;
int res, retry;
@@ -932,7 +932,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device *device)
struct ata_link *link;
int rc = TMF_RESP_FUNC_FAILED;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int s = sizeof(struct host_to_dev_fis);
unsigned long flags;
@@ -990,7 +990,7 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba)
return -1;
if (!test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) {
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct sas_ha_struct *sas_ha = &hisi_hba->sha;
unsigned long flags;
@@ -1023,7 +1023,7 @@ static int hisi_sas_abort_task(struct sas_task *task)
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc = TMF_RESP_FUNC_FAILED;
unsigned long flags;
@@ -1152,7 +1152,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
unsigned long flags;
int rc = TMF_RESP_FUNC_FAILED;
@@ -1241,7 +1241,7 @@ static int hisi_sas_query_task(struct sas_task *task)
{
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port;
struct hisi_sas_slot *slot;
struct asd_sas_port *sas_port = device->port;
@@ -1337,7 +1337,7 @@ static int hisi_sas_query_task(struct sas_task *task)
{
struct sas_task *task;
struct hisi_sas_device *sas_dev = device->lldd_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int res;
if (!hisi_hba->hw->prep_abort)
@@ -1547,8 +1547,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
{
- struct platform_device *pdev = hisi_hba->pdev;
- struct device *dev = &pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
spin_lock_init(&hisi_hba->lock);
@@ -1668,7 +1667,7 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
static void hisi_sas_free(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
for (i = 0; i < hisi_hba->queue_count; i++) {
@@ -1749,7 +1748,8 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
hisi_hba->hw = hw;
- hisi_hba->pdev = pdev;
+ hisi_hba->platform_dev = pdev;
+ hisi_hba->dev = dev;
hisi_hba->shost = shost;
SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
@@ -1866,7 +1866,7 @@ int hisi_sas_probe(struct platform_device *pdev,
shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
sha->sas_ha_name = DRV_NAME;
- sha->dev = &hisi_hba->pdev->dev;
+ sha->dev = hisi_hba->dev;
sha->lldd_module = THIS_MODULE;
sha->sas_addr = &hisi_hba->sas_addr[0];
sha->num_phys = hisi_hba->n_phy;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 7d7d2a7..afa87d4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -505,7 +505,7 @@ static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
struct domain_device *device = sas_dev->sas_device;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 qw0, device_id = sas_dev->device_id;
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
struct asd_sas_port *sas_port = device->port;
@@ -571,7 +571,7 @@ static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
int i;
unsigned long end_time;
u32 val;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
for (i = 0; i < hisi_hba->n_phy; i++) {
u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
@@ -756,7 +756,7 @@ static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc;
rc = reset_hw_v1_hw(hisi_hba);
@@ -907,7 +907,7 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
static int
get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int queue = dq->id;
u32 r, w;
@@ -939,7 +939,7 @@ static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
struct scatterlist *scatter,
int n_elem)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct scatterlist *sg;
int i;
@@ -976,7 +976,7 @@ static int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
struct sas_task *task = slot->task;
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
struct domain_device *device = task->dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port = slot->port;
struct scatterlist *sg_req, *sg_resp;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -1148,7 +1148,7 @@ static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
{
struct task_status_struct *ts = &task->task_status;
struct hisi_sas_err_record_v1 *err_record = slot->status_buffer;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
switch (task->task_proto) {
case SAS_PROTOCOL_SSP:
@@ -1274,7 +1274,7 @@ static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
{
struct sas_task *task = slot->task;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct task_status_struct *ts;
struct domain_device *device;
enum exec_status sts;
@@ -1423,7 +1423,7 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
{
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
int i, phy_no = sas_phy->id;
u32 irq_value, context, port_id, link_rate;
@@ -1504,7 +1504,7 @@ static irqreturn_t int_bcast_v1_hw(int irq, void *p)
struct hisi_hba *hisi_hba = phy->hisi_hba;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
struct sas_ha_struct *sha = &hisi_hba->sha;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int phy_no = sas_phy->id;
u32 irq_value;
irqreturn_t res = IRQ_HANDLED;
@@ -1531,7 +1531,7 @@ static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
{
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
u32 irq_value, irq_mask_old;
int phy_no = sas_phy->id;
@@ -1634,7 +1634,7 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
@@ -1693,7 +1693,7 @@ static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
@@ -1731,7 +1731,7 @@ static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
struct device *dev = &pdev->dev;
int i, j, irq, rc, idx;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index e64047c..e4cd86a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -653,7 +653,7 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
{
unsigned int index;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
void *bitmap = hisi_hba->sata_dev_bitmap;
index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
@@ -750,7 +750,7 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
struct domain_device *device = sas_dev->sas_device;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 qw0, device_id = sas_dev->device_id;
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
struct domain_device *parent_dev = device->parent;
@@ -803,7 +803,7 @@ static void free_device_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
u64 dev_id = sas_dev->device_id;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
int i;
@@ -847,7 +847,7 @@ static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
int i, reset_val;
u32 val;
unsigned long end_time;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
/* The mask needs to be set depending on the number of phys */
if (hisi_hba->n_phy == 9)
@@ -983,7 +983,7 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i;
/* Global registers init */
@@ -1164,7 +1164,7 @@ static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc;
rc = reset_hw_v2_hw(hisi_hba);
@@ -1213,7 +1213,7 @@ static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
int i, max_loop = 1000;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 status, axi_status, dfx_val, dfx_tx_val;
for (i = 0; i < max_loop; i++) {
@@ -1239,7 +1239,7 @@ static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
int i, max_loop = 1000;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 status, tx_dfx0;
for (i = 0; i < max_loop; i++) {
@@ -1277,7 +1277,7 @@ static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
u32 cfg, axi_val, dfx0_val, txid_auto;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
/* Close axi bus. */
axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
@@ -1455,7 +1455,7 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
static int
get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int queue = dq->id;
u32 r, w;
@@ -1488,7 +1488,7 @@ static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
struct scatterlist *scatter,
int n_elem)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct scatterlist *sg;
int i;
@@ -1525,7 +1525,7 @@ static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
struct sas_task *task = slot->task;
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
struct domain_device *device = task->dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port = slot->port;
struct scatterlist *sg_req, *sg_resp;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -2184,7 +2184,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
{
struct sas_task *task = slot->task;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct task_status_struct *ts;
struct domain_device *device;
enum exec_status sts;
@@ -2482,7 +2482,7 @@ static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
u32 port_id, link_rate, hard_phy_linkrate;
struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
struct asd_sas_phy *sas_phy = &phy->sas_phy;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
@@ -2669,7 +2669,7 @@ static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 ent_msk, ent_tmp, irq_msk;
int phy_no = 0;
@@ -2729,7 +2729,7 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
static void
one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 reg_val;
if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
@@ -2818,7 +2818,7 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
u32 irq_value)
{
u32 reg_val;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
@@ -2968,7 +2968,7 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
{
struct hisi_hba *hisi_hba = p;
u32 irq_value, irq_msk, err_value;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
@@ -3144,7 +3144,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_initial_fis *initial_fis;
struct dev_to_host_fis *fis;
u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
@@ -3246,7 +3246,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
*/
static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
struct device *dev = &pdev->dev;
int i, irq, rc, irq_map[128];
@@ -3360,7 +3360,7 @@ static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
int i;
for (i = 0; i < hisi_hba->queue_count; i++)
@@ -3382,7 +3382,7 @@ static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 old_state, state;
int rc, cnt;
int phy_no;
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 06/22] scsi: hisi_sas: add pci_dev in hisi_hba struct
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Since hip08 SAS controller is based on pci device, add hisi_hba.pci_dev
for hip08 (will be v3), and also rename hisi_hba.pdev to .platform_dev
for clarity.
In addition, for common code which wants to reference the controller
device struct, add hisi_hba.dev, and change the common code to use
it.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 6 ++++-
drivers/scsi/hisi_sas/hisi_sas_main.c | 36 ++++++++++++++--------------
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 28 +++++++++++-----------
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 44 +++++++++++++++++-----------------
4 files changed, 59 insertions(+), 55 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 210daec..18044b7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -18,6 +18,7 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
@@ -189,7 +190,10 @@ struct hisi_hba {
/* This must be the first element, used by SHOST_TO_SAS_HA */
struct sas_ha_struct *p;
- struct platform_device *pdev;
+ struct platform_device *platform_dev;
+ struct pci_dev *pci_dev;
+ struct device *dev;
+
void __iomem *regs;
struct regmap *ctrl;
u32 ctrl_reset_reg;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 12fece3..d20a2f2 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -174,7 +174,7 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
{
if (task) {
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -251,7 +251,7 @@ static void hisi_sas_slot_abort(struct work_struct *work)
struct scsi_cmnd *cmnd = task->uldd_task;
struct hisi_sas_tmf_task tmf_task;
struct scsi_lun lun;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int tag = abort_slot->idx;
unsigned long flags;
@@ -285,7 +285,7 @@ static int hisi_sas_task_prep(struct sas_task *task, struct hisi_sas_dq
struct hisi_sas_slot *slot;
struct hisi_sas_cmd_hdr *cmd_hdr_base;
struct asd_sas_port *sas_port = device->port;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int dlvry_queue_slot, dlvry_queue, n_elem = 0, rc, slot_idx;
unsigned long flags;
@@ -455,7 +455,7 @@ static int hisi_sas_task_exec(struct sas_task *task, gfp_t gfp_flags,
u32 pass = 0;
unsigned long flags;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
int queue_id = sas_dev->device_id % hisi_hba->queue_count;
@@ -547,7 +547,7 @@ static int hisi_sas_dev_found(struct domain_device *device)
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
struct domain_device *parent_dev = device->parent;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
if (hisi_hba->hw->alloc_dev)
sas_dev = hisi_hba->hw->alloc_dev(device);
@@ -732,7 +732,7 @@ static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 dev_id = sas_dev->device_id;
dev_info(dev, "found dev[%lld:%x] is gone\n",
@@ -815,7 +815,7 @@ static int hisi_sas_exec_internal_tmf_task(struct domain_device *device,
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct sas_task *task;
int res, retry;
@@ -932,7 +932,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device *device)
struct ata_link *link;
int rc = TMF_RESP_FUNC_FAILED;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int s = sizeof(struct host_to_dev_fis);
unsigned long flags;
@@ -990,7 +990,7 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba)
return -1;
if (!test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) {
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct sas_ha_struct *sas_ha = &hisi_hba->sha;
unsigned long flags;
@@ -1023,7 +1023,7 @@ static int hisi_sas_abort_task(struct sas_task *task)
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(task->dev);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc = TMF_RESP_FUNC_FAILED;
unsigned long flags;
@@ -1152,7 +1152,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
unsigned long flags;
int rc = TMF_RESP_FUNC_FAILED;
@@ -1241,7 +1241,7 @@ static int hisi_sas_query_task(struct sas_task *task)
{
struct domain_device *device = task->dev;
struct hisi_sas_device *sas_dev = device->lldd_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port;
struct hisi_sas_slot *slot;
struct asd_sas_port *sas_port = device->port;
@@ -1337,7 +1337,7 @@ static int hisi_sas_query_task(struct sas_task *task)
{
struct sas_task *task;
struct hisi_sas_device *sas_dev = device->lldd_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int res;
if (!hisi_hba->hw->prep_abort)
@@ -1547,8 +1547,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
{
- struct platform_device *pdev = hisi_hba->pdev;
- struct device *dev = &pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
spin_lock_init(&hisi_hba->lock);
@@ -1668,7 +1667,7 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
static void hisi_sas_free(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
for (i = 0; i < hisi_hba->queue_count; i++) {
@@ -1749,7 +1748,8 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
hisi_hba->hw = hw;
- hisi_hba->pdev = pdev;
+ hisi_hba->platform_dev = pdev;
+ hisi_hba->dev = dev;
hisi_hba->shost = shost;
SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
@@ -1866,7 +1866,7 @@ int hisi_sas_probe(struct platform_device *pdev,
shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
sha->sas_ha_name = DRV_NAME;
- sha->dev = &hisi_hba->pdev->dev;
+ sha->dev = hisi_hba->dev;
sha->lldd_module = THIS_MODULE;
sha->sas_addr = &hisi_hba->sas_addr[0];
sha->num_phys = hisi_hba->n_phy;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index 7d7d2a7..afa87d4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -505,7 +505,7 @@ static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
struct domain_device *device = sas_dev->sas_device;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 qw0, device_id = sas_dev->device_id;
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
struct asd_sas_port *sas_port = device->port;
@@ -571,7 +571,7 @@ static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
int i;
unsigned long end_time;
u32 val;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
for (i = 0; i < hisi_hba->n_phy; i++) {
u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
@@ -756,7 +756,7 @@ static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc;
rc = reset_hw_v1_hw(hisi_hba);
@@ -907,7 +907,7 @@ static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
static int
get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int queue = dq->id;
u32 r, w;
@@ -939,7 +939,7 @@ static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
struct scatterlist *scatter,
int n_elem)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct scatterlist *sg;
int i;
@@ -976,7 +976,7 @@ static int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
struct sas_task *task = slot->task;
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
struct domain_device *device = task->dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port = slot->port;
struct scatterlist *sg_req, *sg_resp;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -1148,7 +1148,7 @@ static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
{
struct task_status_struct *ts = &task->task_status;
struct hisi_sas_err_record_v1 *err_record = slot->status_buffer;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
switch (task->task_proto) {
case SAS_PROTOCOL_SSP:
@@ -1274,7 +1274,7 @@ static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
{
struct sas_task *task = slot->task;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct task_status_struct *ts;
struct domain_device *device;
enum exec_status sts;
@@ -1423,7 +1423,7 @@ static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
{
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
int i, phy_no = sas_phy->id;
u32 irq_value, context, port_id, link_rate;
@@ -1504,7 +1504,7 @@ static irqreturn_t int_bcast_v1_hw(int irq, void *p)
struct hisi_hba *hisi_hba = phy->hisi_hba;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
struct sas_ha_struct *sha = &hisi_hba->sha;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int phy_no = sas_phy->id;
u32 irq_value;
irqreturn_t res = IRQ_HANDLED;
@@ -1531,7 +1531,7 @@ static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
{
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
u32 irq_value, irq_mask_old;
int phy_no = sas_phy->id;
@@ -1634,7 +1634,7 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
@@ -1693,7 +1693,7 @@ static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
@@ -1731,7 +1731,7 @@ static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
struct device *dev = &pdev->dev;
int i, j, irq, rc, idx;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
index e64047c..e4cd86a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
@@ -653,7 +653,7 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
{
unsigned int index;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
void *bitmap = hisi_hba->sata_dev_bitmap;
index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
@@ -750,7 +750,7 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
struct domain_device *device = sas_dev->sas_device;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u64 qw0, device_id = sas_dev->device_id;
struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
struct domain_device *parent_dev = device->parent;
@@ -803,7 +803,7 @@ static void free_device_v2_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev)
{
u64 dev_id = sas_dev->device_id;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
int i;
@@ -847,7 +847,7 @@ static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
int i, reset_val;
u32 val;
unsigned long end_time;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
/* The mask needs to be set depending on the number of phys */
if (hisi_hba->n_phy == 9)
@@ -983,7 +983,7 @@ static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int i;
/* Global registers init */
@@ -1164,7 +1164,7 @@ static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int rc;
rc = reset_hw_v2_hw(hisi_hba);
@@ -1213,7 +1213,7 @@ static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
int i, max_loop = 1000;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 status, axi_status, dfx_val, dfx_tx_val;
for (i = 0; i < max_loop; i++) {
@@ -1239,7 +1239,7 @@ static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
int i, max_loop = 1000;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 status, tx_dfx0;
for (i = 0; i < max_loop; i++) {
@@ -1277,7 +1277,7 @@ static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
{
u32 cfg, axi_val, dfx0_val, txid_auto;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
/* Close axi bus. */
axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
@@ -1455,7 +1455,7 @@ static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
static int
get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
int queue = dq->id;
u32 r, w;
@@ -1488,7 +1488,7 @@ static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
struct scatterlist *scatter,
int n_elem)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct scatterlist *sg;
int i;
@@ -1525,7 +1525,7 @@ static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
struct sas_task *task = slot->task;
struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
struct domain_device *device = task->dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_port *port = slot->port;
struct scatterlist *sg_req, *sg_resp;
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -2184,7 +2184,7 @@ static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
{
struct sas_task *task = slot->task;
struct hisi_sas_device *sas_dev;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct task_status_struct *ts;
struct domain_device *device;
enum exec_status sts;
@@ -2482,7 +2482,7 @@ static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
u32 port_id, link_rate, hard_phy_linkrate;
struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
struct asd_sas_phy *sas_phy = &phy->sas_phy;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
@@ -2669,7 +2669,7 @@ static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
{
struct hisi_hba *hisi_hba = p;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 ent_msk, ent_tmp, irq_msk;
int phy_no = 0;
@@ -2729,7 +2729,7 @@ static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
static void
one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 reg_val;
if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
@@ -2818,7 +2818,7 @@ static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
u32 irq_value)
{
u32 reg_val;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
@@ -2968,7 +2968,7 @@ static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
{
struct hisi_hba *hisi_hba = p;
u32 irq_value, irq_msk, err_value;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
@@ -3144,7 +3144,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
struct hisi_sas_phy *phy = p;
struct hisi_hba *hisi_hba = phy->hisi_hba;
struct asd_sas_phy *sas_phy = &phy->sas_phy;
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
struct hisi_sas_initial_fis *initial_fis;
struct dev_to_host_fis *fis;
u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
@@ -3246,7 +3246,7 @@ static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
*/
static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
struct device *dev = &pdev->dev;
int i, irq, rc, irq_map[128];
@@ -3360,7 +3360,7 @@ static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
{
- struct platform_device *pdev = hisi_hba->pdev;
+ struct platform_device *pdev = hisi_hba->platform_dev;
int i;
for (i = 0; i < hisi_hba->queue_count; i++)
@@ -3382,7 +3382,7 @@ static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
{
- struct device *dev = &hisi_hba->pdev->dev;
+ struct device *dev = hisi_hba->dev;
u32 old_state, state;
int rc, cnt;
int phy_no;
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 07/22] scsi: hisi_sas: add the initialisation for pci-based controller
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Add the code to initialise controller which is based on pci device
in hisi_sas_pci_init.c
The main functionality added is for probing and initialisation of
the controller based on pci device.
The core controller routines are still in hisi_sas_main.c; some
common initialisation functions and structures are also exported from
hisi_sas_main.c for pci init.
For platform device-based controller, controller properties - like
phy count - were read from the firmware. For pci-based controller this
information is hard-coded in the driver, in new struct hisi_sas_pci_hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/Kconfig | 10 +-
drivers/scsi/hisi_sas/Makefile | 1 +
drivers/scsi/hisi_sas/hisi_sas.h | 19 ++++
drivers/scsi/hisi_sas/hisi_sas_main.c | 18 ++-
drivers/scsi/hisi_sas/hisi_sas_pci_init.c | 182 ++++++++++++++++++++++++++++++
5 files changed, 223 insertions(+), 7 deletions(-)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_pci_init.c
diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
index 374a329..d42f29a 100644
--- a/drivers/scsi/hisi_sas/Kconfig
+++ b/drivers/scsi/hisi_sas/Kconfig
@@ -6,4 +6,12 @@ config SCSI_HISI_SAS
select BLK_DEV_INTEGRITY
depends on ATA
help
- This driver supports HiSilicon's SAS HBA
+ This driver supports HiSilicon's SAS HBA, including support based
+ on platform device
+
+config SCSI_HISI_SAS_PCI
+ tristate "HiSilicon SAS on PCI bus"
+ depends on SCSI_HISI_SAS
+ depends on PCI
+ help
+ This driver supports HiSilicon's SAS HBA based on PCI device
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index c6d3a1b..3a036a8 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_main.o
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_v1_hw.o hisi_sas_v2_hw.o
+obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_pci_init.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 18044b7..9bc9550 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -186,6 +186,12 @@ struct hisi_sas_hw {
int complete_hdr_size;
};
+struct hisi_sas_pci_hw {
+ int n_phy;
+ int queue_count;
+ const struct hisi_sas_hw *hw;
+};
+
struct hisi_hba {
/* This must be the first element, used by SHOST_TO_SAS_HA */
struct sas_ha_struct *p;
@@ -359,6 +365,19 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern struct scsi_transport_template *hisi_sas_stt;
+extern struct scsi_host_template *hisi_sas_sht;
+
+extern void hisi_sas_init_add(struct hisi_hba *hisi_hba);
+extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
+extern void hisi_sas_free(struct hisi_hba *hisi_hba);
+
+#if IS_ENABLED(CONFIG_SCSI_HISI_SAS_PCI)
+extern int hisi_sas_pci_probe(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw);
+extern void hisi_sas_pci_remove(struct pci_dev *pdev);
+#endif
+
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index d20a2f2..33bd3c45 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -1476,9 +1476,10 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state,
}
EXPORT_SYMBOL_GPL(hisi_sas_rescan_topology);
-static struct scsi_transport_template *hisi_sas_stt;
+struct scsi_transport_template *hisi_sas_stt;
+EXPORT_SYMBOL_GPL(hisi_sas_stt);
-static struct scsi_host_template hisi_sas_sht = {
+static struct scsi_host_template _hisi_sas_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
.queuecommand = sas_queuecommand,
@@ -1498,6 +1499,8 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state,
.target_destroy = sas_target_destroy,
.ioctl = sas_ioctl,
};
+struct scsi_host_template *hisi_sas_sht = &_hisi_sas_sht;
+EXPORT_SYMBOL_GPL(hisi_sas_sht);
static struct sas_domain_function_template hisi_sas_transport_ops = {
.lldd_dev_found = hisi_sas_dev_found,
@@ -1545,7 +1548,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
}
EXPORT_SYMBOL_GPL(hisi_sas_init_mem);
-static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
+int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1664,8 +1667,9 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
err_out:
return -ENOMEM;
}
+EXPORT_SYMBOL_GPL(hisi_sas_alloc);
-static void hisi_sas_free(struct hisi_hba *hisi_hba)
+void hisi_sas_free(struct hisi_hba *hisi_hba)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1720,6 +1724,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
if (hisi_hba->wq)
destroy_workqueue(hisi_hba->wq);
}
+EXPORT_SYMBOL_GPL(hisi_sas_free);
static void hisi_sas_rst_work_handler(struct work_struct *work)
{
@@ -1739,7 +1744,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct clk *refclk;
- shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
+ shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
if (!shost) {
dev_err(dev, "scsi host alloc failed\n");
return NULL;
@@ -1814,7 +1819,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
return NULL;
}
-static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
+void hisi_sas_init_add(struct hisi_hba *hisi_hba)
{
int i;
@@ -1823,6 +1828,7 @@ static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
hisi_hba->sas_addr,
SAS_ADDR_SIZE);
}
+EXPORT_SYMBOL_GPL(hisi_sas_init_add);
int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *hw)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
new file mode 100644
index 0000000..e00b482
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2017 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+#define DRV_NAME "hisi_sas_pci"
+
+static struct Scsi_Host *
+hisi_sas_shost_alloc_pci(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw)
+{
+ struct Scsi_Host *shost;
+ struct hisi_hba *hisi_hba;
+ struct device *dev = &pdev->dev;
+
+ shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
+ if (!shost)
+ goto err_out;
+ hisi_hba = shost_priv(shost);
+
+ hisi_hba->hw = hw->hw;
+ hisi_hba->queue_count = hw->queue_count;
+ hisi_hba->n_phy = hw->n_phy;
+ hisi_hba->pci_dev = pdev;
+ hisi_hba->dev = dev;
+ hisi_hba->shost = shost;
+ SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
+
+ init_timer(&hisi_hba->timer);
+
+ if (hisi_sas_alloc(hisi_hba, shost)) {
+ hisi_sas_free(hisi_hba);
+ goto err_out;
+ }
+
+ return shost;
+err_out:
+ dev_err(dev, "shost alloc failed\n");
+ return NULL;
+}
+
+int hisi_sas_pci_probe(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw)
+{
+ struct Scsi_Host *shost;
+ struct hisi_hba *hisi_hba;
+ struct device *dev = &pdev->dev;
+ struct asd_sas_phy **arr_phy;
+ struct asd_sas_port **arr_port;
+ struct sas_ha_struct *sha;
+ int rc, phy_nr, port_nr, i;
+
+ rc = pci_enable_device(pdev);
+ if (rc)
+ goto err_out;
+
+ pci_set_master(pdev);
+
+ rc = pci_request_regions(pdev, DRV_NAME);
+ if (rc)
+ goto err_out_disable_device;
+
+ if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
+ (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
+ if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
+ (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
+ dev_err(dev, "No usable DMA addressing method\n");
+ rc = -EIO;
+ goto err_out_regions;
+ }
+ }
+
+ shost = hisi_sas_shost_alloc_pci(pdev, hw);
+ if (!shost) {
+ rc = -ENOMEM;
+ goto err_out_regions;
+ }
+
+ sha = SHOST_TO_SAS_HA(shost);
+ hisi_hba = shost_priv(shost);
+ dev_set_drvdata(dev, sha);
+
+ hisi_hba->regs = pcim_iomap(pdev, 5, 0);
+ if (!hisi_hba->regs) {
+ dev_err(dev, "cannot map register.\n");
+ rc = -ENOMEM;
+ goto err_out_ha;
+ }
+
+ phy_nr = port_nr = hisi_hba->n_phy;
+
+ arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
+ arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
+ if (!arr_phy || !arr_port) {
+ rc = -ENOMEM;
+ goto err_out_ha;
+ }
+
+ sha->sas_phy = arr_phy;
+ sha->sas_port = arr_port;
+ sha->core.shost = shost;
+ sha->lldd_ha = hisi_hba;
+
+ shost->transportt = hisi_sas_stt;
+ shost->max_id = HISI_SAS_MAX_DEVICES;
+ shost->max_lun = ~0;
+ shost->max_channel = 1;
+ shost->max_cmd_len = 16;
+ shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
+ shost->can_queue = hisi_hba->hw->max_command_entries;
+ shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
+
+ sha->sas_ha_name = DRV_NAME;
+ sha->dev = dev;
+ sha->lldd_module = THIS_MODULE;
+ sha->sas_addr = &hisi_hba->sas_addr[0];
+ sha->num_phys = hisi_hba->n_phy;
+ sha->core.shost = hisi_hba->shost;
+
+ for (i = 0; i < hisi_hba->n_phy; i++) {
+ sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
+ sha->sas_port[i] = &hisi_hba->port[i].sas_port;
+ }
+
+ hisi_sas_init_add(hisi_hba);
+
+ rc = scsi_add_host(shost, dev);
+ if (rc)
+ goto err_out_ha;
+
+ rc = sas_register_ha(sha);
+ if (rc)
+ goto err_out_register_ha;
+
+ rc = hisi_hba->hw->hw_init(hisi_hba);
+ if (rc)
+ goto err_out_register_ha;
+
+ scsi_scan_host(shost);
+
+ return 0;
+
+err_out_register_ha:
+ scsi_remove_host(shost);
+err_out_ha:
+ kfree(shost);
+err_out_regions:
+ pci_release_regions(pdev);
+err_out_disable_device:
+ pci_disable_device(pdev);
+err_out:
+ return rc;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_pci_probe);
+
+void hisi_sas_pci_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct sas_ha_struct *sha = dev_get_drvdata(dev);
+ struct hisi_hba *hisi_hba = sha->lldd_ha;
+
+ scsi_remove_host(sha->core.shost);
+ sas_unregister_ha(sha);
+ sas_remove_host(sha->core.shost);
+
+ hisi_sas_free(hisi_hba);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+EXPORT_SYMBOL_GPL(hisi_sas_pci_remove);
+
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
+MODULE_DESCRIPTION("HISILICON SAS pci controller driver");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 07/22] scsi: hisi_sas: add the initialisation for pci-based controller
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Add the code to initialise controller which is based on pci device
in hisi_sas_pci_init.c
The main functionality added is for probing and initialisation of
the controller based on pci device.
The core controller routines are still in hisi_sas_main.c; some
common initialisation functions and structures are also exported from
hisi_sas_main.c for pci init.
For platform device-based controller, controller properties - like
phy count - were read from the firmware. For pci-based controller this
information is hard-coded in the driver, in new struct hisi_sas_pci_hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/Kconfig | 10 +-
drivers/scsi/hisi_sas/Makefile | 1 +
drivers/scsi/hisi_sas/hisi_sas.h | 19 ++++
drivers/scsi/hisi_sas/hisi_sas_main.c | 18 ++-
drivers/scsi/hisi_sas/hisi_sas_pci_init.c | 182 ++++++++++++++++++++++++++++++
5 files changed, 223 insertions(+), 7 deletions(-)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_pci_init.c
diff --git a/drivers/scsi/hisi_sas/Kconfig b/drivers/scsi/hisi_sas/Kconfig
index 374a329..d42f29a 100644
--- a/drivers/scsi/hisi_sas/Kconfig
+++ b/drivers/scsi/hisi_sas/Kconfig
@@ -6,4 +6,12 @@ config SCSI_HISI_SAS
select BLK_DEV_INTEGRITY
depends on ATA
help
- This driver supports HiSilicon's SAS HBA
+ This driver supports HiSilicon's SAS HBA, including support based
+ on platform device
+
+config SCSI_HISI_SAS_PCI
+ tristate "HiSilicon SAS on PCI bus"
+ depends on SCSI_HISI_SAS
+ depends on PCI
+ help
+ This driver supports HiSilicon's SAS HBA based on PCI device
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index c6d3a1b..3a036a8 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_main.o
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_v1_hw.o hisi_sas_v2_hw.o
+obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_pci_init.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 18044b7..9bc9550 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -186,6 +186,12 @@ struct hisi_sas_hw {
int complete_hdr_size;
};
+struct hisi_sas_pci_hw {
+ int n_phy;
+ int queue_count;
+ const struct hisi_sas_hw *hw;
+};
+
struct hisi_hba {
/* This must be the first element, used by SHOST_TO_SAS_HA */
struct sas_ha_struct *p;
@@ -359,6 +365,19 @@ struct hisi_sas_command_table_ssp {
struct hisi_sas_command_table_stp stp;
};
+extern struct scsi_transport_template *hisi_sas_stt;
+extern struct scsi_host_template *hisi_sas_sht;
+
+extern void hisi_sas_init_add(struct hisi_hba *hisi_hba);
+extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
+extern void hisi_sas_free(struct hisi_hba *hisi_hba);
+
+#if IS_ENABLED(CONFIG_SCSI_HISI_SAS_PCI)
+extern int hisi_sas_pci_probe(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw);
+extern void hisi_sas_pci_remove(struct pci_dev *pdev);
+#endif
+
extern u8 hisi_sas_get_ata_protocol(u8 cmd, int direction);
extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
extern void hisi_sas_sata_done(struct sas_task *task,
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index d20a2f2..33bd3c45 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -1476,9 +1476,10 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state,
}
EXPORT_SYMBOL_GPL(hisi_sas_rescan_topology);
-static struct scsi_transport_template *hisi_sas_stt;
+struct scsi_transport_template *hisi_sas_stt;
+EXPORT_SYMBOL_GPL(hisi_sas_stt);
-static struct scsi_host_template hisi_sas_sht = {
+static struct scsi_host_template _hisi_sas_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
.queuecommand = sas_queuecommand,
@@ -1498,6 +1499,8 @@ void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 old_state,
.target_destroy = sas_target_destroy,
.ioctl = sas_ioctl,
};
+struct scsi_host_template *hisi_sas_sht = &_hisi_sas_sht;
+EXPORT_SYMBOL_GPL(hisi_sas_sht);
static struct sas_domain_function_template hisi_sas_transport_ops = {
.lldd_dev_found = hisi_sas_dev_found,
@@ -1545,7 +1548,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
}
EXPORT_SYMBOL_GPL(hisi_sas_init_mem);
-static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
+int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1664,8 +1667,9 @@ static int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost)
err_out:
return -ENOMEM;
}
+EXPORT_SYMBOL_GPL(hisi_sas_alloc);
-static void hisi_sas_free(struct hisi_hba *hisi_hba)
+void hisi_sas_free(struct hisi_hba *hisi_hba)
{
struct device *dev = hisi_hba->dev;
int i, s, max_command_entries = hisi_hba->hw->max_command_entries;
@@ -1720,6 +1724,7 @@ static void hisi_sas_free(struct hisi_hba *hisi_hba)
if (hisi_hba->wq)
destroy_workqueue(hisi_hba->wq);
}
+EXPORT_SYMBOL_GPL(hisi_sas_free);
static void hisi_sas_rst_work_handler(struct work_struct *work)
{
@@ -1739,7 +1744,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct clk *refclk;
- shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
+ shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
if (!shost) {
dev_err(dev, "scsi host alloc failed\n");
return NULL;
@@ -1814,7 +1819,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
return NULL;
}
-static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
+void hisi_sas_init_add(struct hisi_hba *hisi_hba)
{
int i;
@@ -1823,6 +1828,7 @@ static void hisi_sas_init_add(struct hisi_hba *hisi_hba)
hisi_hba->sas_addr,
SAS_ADDR_SIZE);
}
+EXPORT_SYMBOL_GPL(hisi_sas_init_add);
int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *hw)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
new file mode 100644
index 0000000..e00b482
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2017 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+#define DRV_NAME "hisi_sas_pci"
+
+static struct Scsi_Host *
+hisi_sas_shost_alloc_pci(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw)
+{
+ struct Scsi_Host *shost;
+ struct hisi_hba *hisi_hba;
+ struct device *dev = &pdev->dev;
+
+ shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
+ if (!shost)
+ goto err_out;
+ hisi_hba = shost_priv(shost);
+
+ hisi_hba->hw = hw->hw;
+ hisi_hba->queue_count = hw->queue_count;
+ hisi_hba->n_phy = hw->n_phy;
+ hisi_hba->pci_dev = pdev;
+ hisi_hba->dev = dev;
+ hisi_hba->shost = shost;
+ SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
+
+ init_timer(&hisi_hba->timer);
+
+ if (hisi_sas_alloc(hisi_hba, shost)) {
+ hisi_sas_free(hisi_hba);
+ goto err_out;
+ }
+
+ return shost;
+err_out:
+ dev_err(dev, "shost alloc failed\n");
+ return NULL;
+}
+
+int hisi_sas_pci_probe(struct pci_dev *pdev,
+ const struct hisi_sas_pci_hw *hw)
+{
+ struct Scsi_Host *shost;
+ struct hisi_hba *hisi_hba;
+ struct device *dev = &pdev->dev;
+ struct asd_sas_phy **arr_phy;
+ struct asd_sas_port **arr_port;
+ struct sas_ha_struct *sha;
+ int rc, phy_nr, port_nr, i;
+
+ rc = pci_enable_device(pdev);
+ if (rc)
+ goto err_out;
+
+ pci_set_master(pdev);
+
+ rc = pci_request_regions(pdev, DRV_NAME);
+ if (rc)
+ goto err_out_disable_device;
+
+ if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
+ (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
+ if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
+ (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
+ dev_err(dev, "No usable DMA addressing method\n");
+ rc = -EIO;
+ goto err_out_regions;
+ }
+ }
+
+ shost = hisi_sas_shost_alloc_pci(pdev, hw);
+ if (!shost) {
+ rc = -ENOMEM;
+ goto err_out_regions;
+ }
+
+ sha = SHOST_TO_SAS_HA(shost);
+ hisi_hba = shost_priv(shost);
+ dev_set_drvdata(dev, sha);
+
+ hisi_hba->regs = pcim_iomap(pdev, 5, 0);
+ if (!hisi_hba->regs) {
+ dev_err(dev, "cannot map register.\n");
+ rc = -ENOMEM;
+ goto err_out_ha;
+ }
+
+ phy_nr = port_nr = hisi_hba->n_phy;
+
+ arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
+ arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
+ if (!arr_phy || !arr_port) {
+ rc = -ENOMEM;
+ goto err_out_ha;
+ }
+
+ sha->sas_phy = arr_phy;
+ sha->sas_port = arr_port;
+ sha->core.shost = shost;
+ sha->lldd_ha = hisi_hba;
+
+ shost->transportt = hisi_sas_stt;
+ shost->max_id = HISI_SAS_MAX_DEVICES;
+ shost->max_lun = ~0;
+ shost->max_channel = 1;
+ shost->max_cmd_len = 16;
+ shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
+ shost->can_queue = hisi_hba->hw->max_command_entries;
+ shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
+
+ sha->sas_ha_name = DRV_NAME;
+ sha->dev = dev;
+ sha->lldd_module = THIS_MODULE;
+ sha->sas_addr = &hisi_hba->sas_addr[0];
+ sha->num_phys = hisi_hba->n_phy;
+ sha->core.shost = hisi_hba->shost;
+
+ for (i = 0; i < hisi_hba->n_phy; i++) {
+ sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
+ sha->sas_port[i] = &hisi_hba->port[i].sas_port;
+ }
+
+ hisi_sas_init_add(hisi_hba);
+
+ rc = scsi_add_host(shost, dev);
+ if (rc)
+ goto err_out_ha;
+
+ rc = sas_register_ha(sha);
+ if (rc)
+ goto err_out_register_ha;
+
+ rc = hisi_hba->hw->hw_init(hisi_hba);
+ if (rc)
+ goto err_out_register_ha;
+
+ scsi_scan_host(shost);
+
+ return 0;
+
+err_out_register_ha:
+ scsi_remove_host(shost);
+err_out_ha:
+ kfree(shost);
+err_out_regions:
+ pci_release_regions(pdev);
+err_out_disable_device:
+ pci_disable_device(pdev);
+err_out:
+ return rc;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_pci_probe);
+
+void hisi_sas_pci_remove(struct pci_dev *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct sas_ha_struct *sha = dev_get_drvdata(dev);
+ struct hisi_hba *hisi_hba = sha->lldd_ha;
+
+ scsi_remove_host(sha->core.shost);
+ sas_unregister_ha(sha);
+ sas_remove_host(sha->core.shost);
+
+ hisi_sas_free(hisi_hba);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+EXPORT_SYMBOL_GPL(hisi_sas_pci_remove);
+
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
+MODULE_DESCRIPTION("HISILICON SAS pci controller driver");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 07/22] scsi: hisi_sas: add the initialisation for pci-based controller
2017-05-17 10:49 ` John Garry
(?)
@ 2017-05-17 12:33 ` Arnd Bergmann
2017-05-17 13:03 ` John Garry
-1 siblings, 1 reply; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 12:33 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
> Add the code to initialise controller which is based on pci device
> in hisi_sas_pci_init.c
>
> The main functionality added is for probing and initialisation of
> the controller based on pci device.
>
> The core controller routines are still in hisi_sas_main.c; some
> common initialisation functions and structures are also exported from
> hisi_sas_main.c for pci init.
>
> For platform device-based controller, controller properties - like
> phy count - were read from the firmware. For pci-based controller this
> information is hard-coded in the driver, in new struct hisi_sas_pci_hw.
>
Do you plan to add further PCI based front-ends besides the v3 driver
in the future? If not, you can save one level of indirection here and merge
pci_init.c into the v3 implementation.
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 07/22] scsi: hisi_sas: add the initialisation for pci-based controller
2017-05-17 12:33 ` Arnd Bergmann
@ 2017-05-17 13:03 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 13:03 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:33, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > Add the code to initialise controller which is based on pci device
>> > in hisi_sas_pci_init.c
>> >
>> > The main functionality added is for probing and initialisation of
>> > the controller based on pci device.
>> >
>> > The core controller routines are still in hisi_sas_main.c; some
>> > common initialisation functions and structures are also exported from
>> > hisi_sas_main.c for pci init.
>> >
>> > For platform device-based controller, controller properties - like
>> > phy count - were read from the firmware. For pci-based controller this
>> > information is hard-coded in the driver, in new struct hisi_sas_pci_hw.
>> >
> Do you plan to add further PCI based front-ends besides the v3 driver
> in the future? If not, you can save one level of indirection here and merge
> pci_init.c into the v3 implementation.
>
> Arnd
Hi Arnd,
I think for now, any hw revisions will be very closely based on v3. And,
for future revisions, the driver has been well abstracted so we can
still support any updated features in another version of hisi_sas_hw in
v3 driver.
I actually kept v3 driver and pci_init.c separate as initially I thought
we could merge v2 and v3 driver eventually. But with different
functionality, register format, interrupts, I am not 100% confident. Now
my only concern is that layout differences between v1/2 and v3 driver,
but this is not critical. Anyway, I think we can merge them for now.
Cheers,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 07/22] scsi: hisi_sas: add the initialisation for pci-based controller
@ 2017-05-17 13:03 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 13:03 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:33, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > Add the code to initialise controller which is based on pci device
>> > in hisi_sas_pci_init.c
>> >
>> > The main functionality added is for probing and initialisation of
>> > the controller based on pci device.
>> >
>> > The core controller routines are still in hisi_sas_main.c; some
>> > common initialisation functions and structures are also exported from
>> > hisi_sas_main.c for pci init.
>> >
>> > For platform device-based controller, controller properties - like
>> > phy count - were read from the firmware. For pci-based controller this
>> > information is hard-coded in the driver, in new struct hisi_sas_pci_hw.
>> >
> Do you plan to add further PCI based front-ends besides the v3 driver
> in the future? If not, you can save one level of indirection here and merge
> pci_init.c into the v3 implementation.
>
> Arnd
Hi Arnd,
I think for now, any hw revisions will be very closely based on v3. And,
for future revisions, the driver has been well abstracted so we can
still support any updated features in another version of hisi_sas_hw in
v3 driver.
I actually kept v3 driver and pci_init.c separate as initially I thought
we could merge v2 and v3 driver eventually. But with different
functionality, register format, interrupts, I am not 100% confident. Now
my only concern is that layout differences between v1/2 and v3 driver,
but this is not critical. Anyway, I think we can merge them for now.
Cheers,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 08/22] scsi: hisi_sas: add bare v3 hw driver
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Add new file hisi_sas_v3_hw.c for hip08 support.
The controller design is quite similar to v2 hw in hip07.
However key differences include:
-All v2 hw bugs are fixed (hopefully), so workarounds are not
required
-support for device deregistration
-some interrupt modifications
-configurable max device support
Not yet supported:
- controller reset
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/Makefile | 1 +
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 57 ++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index 3a036a8..54774a4 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_main.o
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_v1_hw.o hisi_sas_v2_hw.o
obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_pci_init.o
+obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_v3_hw.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
new file mode 100644
index 0000000..80707f6
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+#define DRV_NAME "hisi_sas_v3_hw"
+
+static const struct hisi_sas_hw hisi_sas_v3_hw = {
+};
+
+enum {
+ /* instances of the controller */
+ hip08,
+};
+
+static const struct hisi_sas_pci_hw hisi_sas_pci_hw_info[] = {
+ [hip08] = {8, 16, &hisi_sas_v3_hw},
+};
+
+static const struct pci_device_id sas_v3_pci_table[] = {
+ { PCI_VDEVICE(HUAWEI, 0xa230), hip08},
+ {}
+};
+
+static int
+hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ const struct hisi_sas_pci_hw *hw;
+
+ hw = &hisi_sas_pci_hw_info[ent->driver_data];
+ return hisi_sas_pci_probe(pdev, hw);
+}
+
+static void hisi_sas_v3_remove(struct pci_dev *pdev)
+{
+ hisi_sas_pci_remove(pdev);
+}
+
+static struct pci_driver sas_v3_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = sas_v3_pci_table,
+ .probe = hisi_sas_v3_probe,
+ .remove = hisi_sas_v3_remove,
+};
+
+module_pci_driver(sas_v3_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
+MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 08/22] scsi: hisi_sas: add bare v3 hw driver
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
John Garry, Xiang Chen
Add new file hisi_sas_v3_hw.c for hip08 support.
The controller design is quite similar to v2 hw in hip07.
However key differences include:
-All v2 hw bugs are fixed (hopefully), so workarounds are not
required
-support for device deregistration
-some interrupt modifications
-configurable max device support
Not yet supported:
- controller reset
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/Makefile | 1 +
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 57 ++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
diff --git a/drivers/scsi/hisi_sas/Makefile b/drivers/scsi/hisi_sas/Makefile
index 3a036a8..54774a4 100644
--- a/drivers/scsi/hisi_sas/Makefile
+++ b/drivers/scsi/hisi_sas/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_main.o
obj-$(CONFIG_SCSI_HISI_SAS) += hisi_sas_v1_hw.o hisi_sas_v2_hw.o
obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_pci_init.o
+obj-$(CONFIG_SCSI_HISI_SAS_PCI) += hisi_sas_v3_hw.o
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
new file mode 100644
index 0000000..80707f6
--- /dev/null
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include "hisi_sas.h"
+#define DRV_NAME "hisi_sas_v3_hw"
+
+static const struct hisi_sas_hw hisi_sas_v3_hw = {
+};
+
+enum {
+ /* instances of the controller */
+ hip08,
+};
+
+static const struct hisi_sas_pci_hw hisi_sas_pci_hw_info[] = {
+ [hip08] = {8, 16, &hisi_sas_v3_hw},
+};
+
+static const struct pci_device_id sas_v3_pci_table[] = {
+ { PCI_VDEVICE(HUAWEI, 0xa230), hip08},
+ {}
+};
+
+static int
+hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ const struct hisi_sas_pci_hw *hw;
+
+ hw = &hisi_sas_pci_hw_info[ent->driver_data];
+ return hisi_sas_pci_probe(pdev, hw);
+}
+
+static void hisi_sas_v3_remove(struct pci_dev *pdev)
+{
+ hisi_sas_pci_remove(pdev);
+}
+
+static struct pci_driver sas_v3_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = sas_v3_pci_table,
+ .probe = hisi_sas_v3_probe,
+ .remove = hisi_sas_v3_remove,
+};
+
+module_pci_driver(sas_v3_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
+MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd, John Garry
For a pci-based controller, retrieve the SAS address from the
ACPI tables.
The retrieval is based on the ACPI device node name. Sample is
as follows:
Scope(_SB)
{
Device(SAS0) {
Name(_HID, "HISI0163")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 00, 00, 0x00}},
}
})
}
}
If the ACPI node or node property is not available, then we fall
back on a default address.
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 +
drivers/scsi/hisi_sas/hisi_sas_pci_init.c | 104 ++++++++++++++++++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 +-
3 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 9bc9550..9fd874d 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -190,6 +190,7 @@ struct hisi_sas_pci_hw {
int n_phy;
int queue_count;
const struct hisi_sas_hw *hw;
+ const char *fw_name;
};
struct hisi_hba {
@@ -250,6 +251,7 @@ struct hisi_hba {
struct hisi_sas_slot *slot_info;
unsigned long flags;
const struct hisi_sas_hw *hw; /* Low level hw interface */
+ const char *fw_name;
unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
struct work_struct rst_work;
};
diff --git a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
index e00b482..6d92893 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
@@ -11,6 +11,107 @@
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_pci"
+
+static const u8 default_sas_addr[SAS_ADDR_SIZE] = {
+ 0x50, 0x01, 0x88, 0x20, 0x16, 0x0, 0x0, 0x0};
+static void hisi_sas_pci_set_sas_addr(struct hisi_hba *hisi_hba);
+
+static void
+hisi_sas_pci_set_default_sas_addr(struct hisi_hba *hisi_hba)
+{
+ dev_warn(hisi_hba->dev, "using default SAS ADDR\n");
+ memcpy(hisi_hba->sas_addr, default_sas_addr, SAS_ADDR_SIZE);
+}
+
+#if defined(CONFIG_ACPI)
+static int
+acpi_get_sas_address(struct device *dev, struct acpi_device *adev,
+ u8 *dst)
+{
+ u8 addr[SAS_ADDR_SIZE];
+ int rc;
+
+ rc = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
+ "sas-addr", addr, SAS_ADDR_SIZE);
+ if (rc) {
+ dev_warn(dev, "could not read sas-addr (%d)\n", rc);
+ return rc;
+ }
+
+ dev_info(dev, "SAS address set to: %pM\n", addr);
+
+ memcpy(dst, addr, SAS_ADDR_SIZE);
+
+ return 0;
+}
+
+static acpi_status
+hisi_sas_acpi_match_id(acpi_handle handle, u32 lvl,
+ void *context, void **ret_val)
+{
+ struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
+ struct hisi_hba *hisi_hba = context;
+ struct device *dev = hisi_hba->dev;
+ struct acpi_device *adev;
+ int rc;
+
+ if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
+ dev_warn(dev, "Invalid link device\n");
+ return AE_OK;
+ }
+
+ if (strncmp(string.pointer, hisi_hba->fw_name, 4))
+ return AE_OK;
+
+ rc = acpi_bus_get_device(handle, &adev);
+
+ if (rc == 0)
+ rc = acpi_get_sas_address(dev, adev, hisi_hba->sas_addr);
+ else
+ dev_warn(dev, "could not get acpi bus device (%d)\n", rc);
+
+ if (rc == 0)
+ *(acpi_handle *)ret_val = handle;
+
+ kfree(string.pointer);
+ return AE_CTRL_TERMINATE;
+}
+
+static acpi_status
+hisi_sas_acpi_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ acpi_status status1;
+ acpi_handle *acpi_handle = NULL;
+
+ status1 = acpi_get_devices(NULL, hisi_sas_acpi_match_id,
+ hisi_hba, (void **)&acpi_handle);
+
+ if (status1 != AE_OK)
+ return status1;
+
+ if (!acpi_handle)
+ return AE_ERROR;
+
+ return AE_OK;
+}
+#else
+static acpi_status
+hisi_sas_acpi_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ return AE_ERROR;
+}
+#endif
+
+static void hisi_sas_pci_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ acpi_status status = AE_ERROR;
+ if (!acpi_disabled)
+ status = hisi_sas_acpi_set_sas_addr(hisi_hba);
+ if (status == AE_OK)
+ return;
+ hisi_sas_pci_set_default_sas_addr(hisi_hba);
+}
+
static struct Scsi_Host *
hisi_sas_shost_alloc_pci(struct pci_dev *pdev,
const struct hisi_sas_pci_hw *hw)
@@ -32,6 +133,9 @@
hisi_hba->shost = shost;
SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
+ hisi_hba->fw_name = hw->fw_name;
+ hisi_sas_pci_set_sas_addr(hisi_hba);
+
init_timer(&hisi_hba->timer);
if (hisi_sas_alloc(hisi_hba, shost)) {
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 80707f6..68b9b0e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -20,7 +20,7 @@ enum {
};
static const struct hisi_sas_pci_hw hisi_sas_pci_hw_info[] = {
- [hip08] = {8, 16, &hisi_sas_v3_hw},
+ [hip08] = {8, 16, &hisi_sas_v3_hw, "SAS0"},
};
static const struct pci_device_id sas_v3_pci_table[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd, John Garry
For a pci-based controller, retrieve the SAS address from the
ACPI tables.
The retrieval is based on the ACPI device node name. Sample is
as follows:
Scope(_SB)
{
Device(SAS0) {
Name(_HID, "HISI0163")
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 00, 00, 0x00}},
}
})
}
}
If the ACPI node or node property is not available, then we fall
back on a default address.
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 +
drivers/scsi/hisi_sas/hisi_sas_pci_init.c | 104 ++++++++++++++++++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 +-
3 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 9bc9550..9fd874d 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -190,6 +190,7 @@ struct hisi_sas_pci_hw {
int n_phy;
int queue_count;
const struct hisi_sas_hw *hw;
+ const char *fw_name;
};
struct hisi_hba {
@@ -250,6 +251,7 @@ struct hisi_hba {
struct hisi_sas_slot *slot_info;
unsigned long flags;
const struct hisi_sas_hw *hw; /* Low level hw interface */
+ const char *fw_name;
unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
struct work_struct rst_work;
};
diff --git a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
index e00b482..6d92893 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_pci_init.c
@@ -11,6 +11,107 @@
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_pci"
+
+static const u8 default_sas_addr[SAS_ADDR_SIZE] = {
+ 0x50, 0x01, 0x88, 0x20, 0x16, 0x0, 0x0, 0x0};
+static void hisi_sas_pci_set_sas_addr(struct hisi_hba *hisi_hba);
+
+static void
+hisi_sas_pci_set_default_sas_addr(struct hisi_hba *hisi_hba)
+{
+ dev_warn(hisi_hba->dev, "using default SAS ADDR\n");
+ memcpy(hisi_hba->sas_addr, default_sas_addr, SAS_ADDR_SIZE);
+}
+
+#if defined(CONFIG_ACPI)
+static int
+acpi_get_sas_address(struct device *dev, struct acpi_device *adev,
+ u8 *dst)
+{
+ u8 addr[SAS_ADDR_SIZE];
+ int rc;
+
+ rc = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
+ "sas-addr", addr, SAS_ADDR_SIZE);
+ if (rc) {
+ dev_warn(dev, "could not read sas-addr (%d)\n", rc);
+ return rc;
+ }
+
+ dev_info(dev, "SAS address set to: %pM\n", addr);
+
+ memcpy(dst, addr, SAS_ADDR_SIZE);
+
+ return 0;
+}
+
+static acpi_status
+hisi_sas_acpi_match_id(acpi_handle handle, u32 lvl,
+ void *context, void **ret_val)
+{
+ struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
+ struct hisi_hba *hisi_hba = context;
+ struct device *dev = hisi_hba->dev;
+ struct acpi_device *adev;
+ int rc;
+
+ if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
+ dev_warn(dev, "Invalid link device\n");
+ return AE_OK;
+ }
+
+ if (strncmp(string.pointer, hisi_hba->fw_name, 4))
+ return AE_OK;
+
+ rc = acpi_bus_get_device(handle, &adev);
+
+ if (rc == 0)
+ rc = acpi_get_sas_address(dev, adev, hisi_hba->sas_addr);
+ else
+ dev_warn(dev, "could not get acpi bus device (%d)\n", rc);
+
+ if (rc == 0)
+ *(acpi_handle *)ret_val = handle;
+
+ kfree(string.pointer);
+ return AE_CTRL_TERMINATE;
+}
+
+static acpi_status
+hisi_sas_acpi_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ acpi_status status1;
+ acpi_handle *acpi_handle = NULL;
+
+ status1 = acpi_get_devices(NULL, hisi_sas_acpi_match_id,
+ hisi_hba, (void **)&acpi_handle);
+
+ if (status1 != AE_OK)
+ return status1;
+
+ if (!acpi_handle)
+ return AE_ERROR;
+
+ return AE_OK;
+}
+#else
+static acpi_status
+hisi_sas_acpi_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ return AE_ERROR;
+}
+#endif
+
+static void hisi_sas_pci_set_sas_addr(struct hisi_hba *hisi_hba)
+{
+ acpi_status status = AE_ERROR;
+ if (!acpi_disabled)
+ status = hisi_sas_acpi_set_sas_addr(hisi_hba);
+ if (status == AE_OK)
+ return;
+ hisi_sas_pci_set_default_sas_addr(hisi_hba);
+}
+
static struct Scsi_Host *
hisi_sas_shost_alloc_pci(struct pci_dev *pdev,
const struct hisi_sas_pci_hw *hw)
@@ -32,6 +133,9 @@
hisi_hba->shost = shost;
SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
+ hisi_hba->fw_name = hw->fw_name;
+ hisi_sas_pci_set_sas_addr(hisi_hba);
+
init_timer(&hisi_hba->timer);
if (hisi_sas_alloc(hisi_hba, shost)) {
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 80707f6..68b9b0e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -20,7 +20,7 @@ enum {
};
static const struct hisi_sas_pci_hw hisi_sas_pci_hw_info[] = {
- [hip08] = {8, 16, &hisi_sas_v3_hw},
+ [hip08] = {8, 16, &hisi_sas_v3_hw, "SAS0"},
};
static const struct pci_device_id sas_v3_pci_table[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 10:49 ` John Garry
(?)
@ 2017-05-17 12:37 ` Arnd Bergmann
2017-05-17 13:37 ` John Garry
-1 siblings, 1 reply; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 12:37 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
> For a pci-based controller, retrieve the SAS address from the
> ACPI tables.
>
> The retrieval is based on the ACPI device node name. Sample is
> as follows:
> Scope(_SB)
> {
> Device(SAS0) {
> Name(_HID, "HISI0163")
> Name (_DSD, Package () {
> ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
> Package () {
> Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 00, 00, 0x00}},
> }
> })
> }
> }
>
> If the ACPI node or node property is not available, then we fall
> back on a default address.
>
> Signed-off-by: John Garry <john.garry@huawei.com>
Since this uses the _DSD information that was introduced for compatibility
between device tree and ACPI based data, why not write the code so that
it can work for both?
Ideally this should just look up the property for pci_dev->fwnode, but I'm
not entirely sure if this works the same way on ACPI and DT today.
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 12:37 ` Arnd Bergmann
@ 2017-05-17 13:37 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 13:37 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On 17/05/2017 13:37, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > For a pci-based controller, retrieve the SAS address from the
>> > ACPI tables.
>> >
>> > The retrieval is based on the ACPI device node name. Sample is
>> > as follows:
>> > Scope(_SB)
>> > {
>> > Device(SAS0) {
>> > Name(_HID, "HISI0163")
>> > Name (_DSD, Package () {
>> > ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>> > Package () {
>> > Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 00, 00, 0x00}},
>> > }
>> > })
>> > }
>> > }
>> >
>> > If the ACPI node or node property is not available, then we fall
>> > back on a default address.
>> >
>> > Signed-off-by: John Garry <john.garry@huawei.com>
> Since this uses the _DSD information that was introduced for compatibility
> between device tree and ACPI based data, why not write the code so that
> it can work for both?
>
> Ideally this should just look up the property for pci_dev->fwnode, but I'm
> not entirely sure if this works the same way on ACPI and DT today.
>
Hi Arnd,
There is no relation at all between the pci device and the ACPI DSDT,
apart from the fact that the device node name is known by the driver,
that being "SAS0". I am not 100% comfortable with this, as we are
introducing some sort of device indexing in the driver.
Please note that Cavium did something similar on their thunderx network
driver:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/cavium/thunder/thunder_bgx.c?h=v4.12-rc1#n1162
As for your suggestion, in theory it could be ok to have a
pci_dev->fwnode, and this would work for Unified Device Properties
Interface (if that is indeed what you mean). But how to create/match
this fwnode?
Thanks,
John
> Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
@ 2017-05-17 13:37 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 13:37 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On 17/05/2017 13:37, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > For a pci-based controller, retrieve the SAS address from the
>> > ACPI tables.
>> >
>> > The retrieval is based on the ACPI device node name. Sample is
>> > as follows:
>> > Scope(_SB)
>> > {
>> > Device(SAS0) {
>> > Name(_HID, "HISI0163")
>> > Name (_DSD, Package () {
>> > ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>> > Package () {
>> > Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 00, 00, 0x00}},
>> > }
>> > })
>> > }
>> > }
>> >
>> > If the ACPI node or node property is not available, then we fall
>> > back on a default address.
>> >
>> > Signed-off-by: John Garry <john.garry@huawei.com>
> Since this uses the _DSD information that was introduced for compatibility
> between device tree and ACPI based data, why not write the code so that
> it can work for both?
>
> Ideally this should just look up the property for pci_dev->fwnode, but I'm
> not entirely sure if this works the same way on ACPI and DT today.
>
Hi Arnd,
There is no relation at all between the pci device and the ACPI DSDT,
apart from the fact that the device node name is known by the driver,
that being "SAS0". I am not 100% comfortable with this, as we are
introducing some sort of device indexing in the driver.
Please note that Cavium did something similar on their thunderx network
driver:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/cavium/thunder/thunder_bgx.c?h=v4.12-rc1#n1162
As for your suggestion, in theory it could be ok to have a
pci_dev->fwnode, and this would work for Unified Device Properties
Interface (if that is indeed what you mean). But how to create/match
this fwnode?
Thanks,
John
> Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 13:37 ` John Garry
(?)
@ 2017-05-17 14:13 ` Arnd Bergmann
2017-05-17 16:45 ` John Garry
-1 siblings, 1 reply; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 14:13 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On Wed, May 17, 2017 at 3:37 PM, John Garry <john.garry@huawei.com> wrote:
> On 17/05/2017 13:37, Arnd Bergmann wrote:
>> Since this uses the _DSD information that was introduced for compatibility
>> between device tree and ACPI based data, why not write the code so that
>> it can work for both?
>>
>> Ideally this should just look up the property for pci_dev->fwnode, but I'm
>> not entirely sure if this works the same way on ACPI and DT today.
>>
>
> Hi Arnd,
>
> There is no relation at all between the pci device and the ACPI DSDT, apart
> from the fact that the device node name is known by the driver, that being
> "SAS0". I am not 100% comfortable with this, as we are introducing some sort
> of device indexing in the driver.
>
> Please note that Cavium did something similar on their thunderx network
> driver:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/cavium/thunder/thunder_bgx.c?h=v4.12-rc1#n1162
>
> As for your suggestion, in theory it could be ok to have a pci_dev->fwnode,
> and this would work for Unified Device Properties Interface (if that is
> indeed what you mean). But how to create/match this fwnode?
pci_scan_device sets the dev->of_node field for DT based probing, we
could add a trivial patch to set the fwnode field as well if that isn't
already done elsewhere.
>From what I can tell, the ACPI code sets up a 'companion' device for
any PCI device that is listed in the ACPI tables, at least it refers to
that later on, but I could not figure out where it actually gets set.
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 14:13 ` Arnd Bergmann
@ 2017-05-17 16:45 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 16:45 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On 17/05/2017 15:13, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 3:37 PM, John Garry <john.garry@huawei.com> wrote:
>> On 17/05/2017 13:37, Arnd Bergmann wrote:
>
>>> Since this uses the _DSD information that was introduced for compatibility
>>> between device tree and ACPI based data, why not write the code so that
>>> it can work for both?
>>>
>>> Ideally this should just look up the property for pci_dev->fwnode, but I'm
>>> not entirely sure if this works the same way on ACPI and DT today.
>>>
>>
>> Hi Arnd,
>>
>> There is no relation at all between the pci device and the ACPI DSDT, apart
>> from the fact that the device node name is known by the driver, that being
>> "SAS0". I am not 100% comfortable with this, as we are introducing some sort
>> of device indexing in the driver.
>>
>> Please note that Cavium did something similar on their thunderx network
>> driver:
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/cavium/thunder/thunder_bgx.c?h=v4.12-rc1#n1162
>>
>> As for your suggestion, in theory it could be ok to have a pci_dev->fwnode,
>> and this would work for Unified Device Properties Interface (if that is
>> indeed what you mean). But how to create/match this fwnode?
>
> pci_scan_device sets the dev->of_node field for DT based probing, we
> could add a trivial patch to set the fwnode field as well if that isn't
> already done elsewhere.
>
>>From what I can tell, the ACPI code sets up a 'companion' device for
> any PCI device that is listed in the ACPI tables, at least it refers to
> that later on, but I could not figure out where it actually gets set.
>
Hi Arnd,
Currently there is no pci device listed in the ACPI tables.
What I am doing is declaring a fake device in the root of the System bus
tree of the ACPI tables, and in the kernel driver finding it by matching
the name. It is not the ACPI companion for the pci device.
So I think that we can define the pci device under the pci bus in the
ACPI tables, and define the ADR and DSD. Then we would have an ACPI
companion for the device, and from that get the SAS address.
An alternative to this ACPI device method is for UEFI to write the SAS
address to a defined free location in device's pci config space, which
the driver can read.
Much appreciated,
John
> Arnd
>
> .
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
@ 2017-05-17 16:45 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 16:45 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On 17/05/2017 15:13, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 3:37 PM, John Garry <john.garry@huawei.com> wrote:
>> On 17/05/2017 13:37, Arnd Bergmann wrote:
>
>>> Since this uses the _DSD information that was introduced for compatibility
>>> between device tree and ACPI based data, why not write the code so that
>>> it can work for both?
>>>
>>> Ideally this should just look up the property for pci_dev->fwnode, but I'm
>>> not entirely sure if this works the same way on ACPI and DT today.
>>>
>>
>> Hi Arnd,
>>
>> There is no relation at all between the pci device and the ACPI DSDT, apart
>> from the fact that the device node name is known by the driver, that being
>> "SAS0". I am not 100% comfortable with this, as we are introducing some sort
>> of device indexing in the driver.
>>
>> Please note that Cavium did something similar on their thunderx network
>> driver:
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/cavium/thunder/thunder_bgx.c?h=v4.12-rc1#n1162
>>
>> As for your suggestion, in theory it could be ok to have a pci_dev->fwnode,
>> and this would work for Unified Device Properties Interface (if that is
>> indeed what you mean). But how to create/match this fwnode?
>
> pci_scan_device sets the dev->of_node field for DT based probing, we
> could add a trivial patch to set the fwnode field as well if that isn't
> already done elsewhere.
>
>>From what I can tell, the ACPI code sets up a 'companion' device for
> any PCI device that is listed in the ACPI tables, at least it refers to
> that later on, but I could not figure out where it actually gets set.
>
Hi Arnd,
Currently there is no pci device listed in the ACPI tables.
What I am doing is declaring a fake device in the root of the System bus
tree of the ACPI tables, and in the kernel driver finding it by matching
the name. It is not the ACPI companion for the pci device.
So I think that we can define the pci device under the pci bus in the
ACPI tables, and define the ADR and DSD. Then we would have an ACPI
companion for the device, and from that get the SAS address.
An alternative to this ACPI device method is for UEFI to write the SAS
address to a defined free location in device's pci config space, which
the driver can read.
Much appreciated,
John
> Arnd
>
> .
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 16:45 ` John Garry
(?)
@ 2017-05-17 19:23 ` Arnd Bergmann
2017-05-18 9:09 ` John Garry
-1 siblings, 1 reply; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 19:23 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On Wed, May 17, 2017 at 6:45 PM, John Garry <john.garry@huawei.com> wrote:
> On 17/05/2017 15:13, Arnd Bergmann wrote:
>> On Wed, May 17, 2017 at 3:37 PM, John Garry <john.garry@huawei.com> wrote:
>>> On 17/05/2017 13:37, Arnd Bergmann wrote:
>>> As for your suggestion, in theory it could be ok to have a
>>> pci_dev->fwnode,
>>> and this would work for Unified Device Properties Interface (if that is
>>> indeed what you mean). But how to create/match this fwnode?
>>
>>
>> pci_scan_device sets the dev->of_node field for DT based probing, we
>> could add a trivial patch to set the fwnode field as well if that isn't
>> already done elsewhere.
>>
>>> From what I can tell, the ACPI code sets up a 'companion' device for
>>
>> any PCI device that is listed in the ACPI tables, at least it refers to
>> that later on, but I could not figure out where it actually gets set.
>>
>
> Hi Arnd,
>
> Currently there is no pci device listed in the ACPI tables.
>
> What I am doing is declaring a fake device in the root of the System bus
> tree of the ACPI tables, and in the kernel driver finding it by matching the
> name. It is not the ACPI companion for the pci device.
>
> So I think that we can define the pci device under the pci bus in the ACPI
> tables, and define the ADR and DSD. Then we would have an ACPI companion for
> the device, and from that get the SAS address.
Yes, that would be much better, and allow us to use the device properties
interface directly. An additional advantage is that the property definition
can be exactly the same as for the v1/v2 platform_device properties
for anything that might be needed across all versions. sas-addr already
fits in there, and there might be additional properties you need in the
future.
> An alternative to this ACPI device method is for UEFI to write the SAS
> address to a defined free location in device's pci config space, which the
> driver can read.
That sounds ok as well, it would be nice to not rely on firmware data here,
but I'd have to see how the implementation ends up: IIRC you should
not just put the data at a fixed location in the config space but instead use
the 'extended capabilities' infrastructure to find the data.
PCI_EXT_CAP_ID_VNDR might be the right one here, but I don't
know enough about this, so please consult with someone who does
(or the PCIe specification).
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
2017-05-17 19:23 ` Arnd Bergmann
@ 2017-05-18 9:09 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-18 9:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
>> Hi Arnd,
>>
>> Currently there is no pci device listed in the ACPI tables.
>>
>> What I am doing is declaring a fake device in the root of the System bus
>> tree of the ACPI tables, and in the kernel driver finding it by matching the
>> name. It is not the ACPI companion for the pci device.
>>
>> So I think that we can define the pci device under the pci bus in the ACPI
>> tables, and define the ADR and DSD. Then we would have an ACPI companion for
>> the device, and from that get the SAS address.
>
> Yes, that would be much better, and allow us to use the device properties
> interface directly. An additional advantage is that the property definition
> can be exactly the same as for the v1/v2 platform_device properties
> for anything that might be needed across all versions. sas-addr already
> fits in there, and there might be additional properties you need in the
> future.
>
Hi Arnd,
OK, we'll try this.
As for other properties, phy and queue count are common to all versions.
However, I need to consider more if I should add these - maybe it is ok.
The reason we did not hardcode these for v1/v2 was that these were
variable for controllers inter and intra SoC.
hip08 only has 1 controller, and I have been told that each controller
will have a unique pci device id that for future SoCs, so it's viable to
hardcode.
>> An alternative to this ACPI device method is for UEFI to write the SAS
>> address to a defined free location in device's pci config space, which the
>> driver can read.
>
> That sounds ok as well, it would be nice to not rely on firmware data here,
> but I'd have to see how the implementation ends up: IIRC you should
> not just put the data at a fixed location in the config space but instead use
> the 'extended capabilities' infrastructure to find the data.
> PCI_EXT_CAP_ID_VNDR might be the right one here, but I don't
> know enough about this, so please consult with someone who does
> (or the PCIe specification).
>
Right, we'll keep ACPI table description as plan A.
> Arnd
>
Much appreciated,
John
> .
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 09/22] scsi: hisi_sas: retrieve SAS address for pci-based controller
@ 2017-05-18 9:09 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-18 9:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
>> Hi Arnd,
>>
>> Currently there is no pci device listed in the ACPI tables.
>>
>> What I am doing is declaring a fake device in the root of the System bus
>> tree of the ACPI tables, and in the kernel driver finding it by matching the
>> name. It is not the ACPI companion for the pci device.
>>
>> So I think that we can define the pci device under the pci bus in the ACPI
>> tables, and define the ADR and DSD. Then we would have an ACPI companion for
>> the device, and from that get the SAS address.
>
> Yes, that would be much better, and allow us to use the device properties
> interface directly. An additional advantage is that the property definition
> can be exactly the same as for the v1/v2 platform_device properties
> for anything that might be needed across all versions. sas-addr already
> fits in there, and there might be additional properties you need in the
> future.
>
Hi Arnd,
OK, we'll try this.
As for other properties, phy and queue count are common to all versions.
However, I need to consider more if I should add these - maybe it is ok.
The reason we did not hardcode these for v1/v2 was that these were
variable for controllers inter and intra SoC.
hip08 only has 1 controller, and I have been told that each controller
will have a unique pci device id that for future SoCs, so it's viable to
hardcode.
>> An alternative to this ACPI device method is for UEFI to write the SAS
>> address to a defined free location in device's pci config space, which the
>> driver can read.
>
> That sounds ok as well, it would be nice to not rely on firmware data here,
> but I'd have to see how the implementation ends up: IIRC you should
> not just put the data at a fixed location in the config space but instead use
> the 'extended capabilities' infrastructure to find the data.
> PCI_EXT_CAP_ID_VNDR might be the right one here, but I don't
> know enough about this, so please consult with someone who does
> (or the PCIe specification).
>
Right, we'll keep ACPI table description as plan A.
> Arnd
>
Much appreciated,
John
> .
>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 10/22] scsi: hisi_sas: add v3 hw init
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to initialise v3 hardware.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 275 +++++++++++++++++++++++++++++++++
1 file changed, 275 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 68b9b0e..f2ea8c8 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -11,7 +11,282 @@
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_v3_hw"
+/* global registers need init*/
+#define DLVRY_QUEUE_ENABLE 0x0
+#define IOST_BASE_ADDR_LO 0x8
+#define IOST_BASE_ADDR_HI 0xc
+#define ITCT_BASE_ADDR_LO 0x10
+#define ITCT_BASE_ADDR_HI 0x14
+#define IO_BROKEN_MSG_ADDR_LO 0x18
+#define IO_BROKEN_MSG_ADDR_HI 0x1c
+#define AXI_AHB_CLK_CFG 0x3c
+#define AXI_USER1 0x48
+#define AXI_USER2 0x4c
+#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
+#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
+#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
+#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
+#define CFG_MAX_TAG 0x68
+#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
+#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
+#define HGC_GET_ITV_TIME 0x90
+#define DEVICE_MSG_WORK_MODE 0x94
+#define OPENA_WT_CONTI_TIME 0x9c
+#define I_T_NEXUS_LOSS_TIME 0xa0
+#define MAX_CON_TIME_LIMIT_TIME 0xa4
+#define BUS_INACTIVE_LIMIT_TIME 0xa8
+#define REJECT_TO_OPEN_LIMIT_TIME 0xac
+#define CFG_AGING_TIME 0xbc
+#define HGC_DFX_CFG2 0xc0
+#define CFG_ABT_SET_QUERY_IPTT 0xd4
+#define CFG_SET_ABORTED_IPTT_OFF 0
+#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
+#define CFG_1US_TIMER_TRSH 0xcc
+#define INT_COAL_EN 0x19c
+#define OQ_INT_COAL_TIME 0x1a0
+#define OQ_INT_COAL_CNT 0x1a4
+#define ENT_INT_COAL_TIME 0x1a8
+#define ENT_INT_COAL_CNT 0x1ac
+#define OQ_INT_SRC 0x1b0
+#define OQ_INT_SRC_MSK 0x1b4
+#define ENT_INT_SRC1 0x1b8
+#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
+#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
+#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
+#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
+#define ENT_INT_SRC2 0x1bc
+#define ENT_INT_SRC3 0x1c0
+#define ENT_INT_SRC3_WP_DEPTH_OFF 8
+#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
+#define ENT_INT_SRC3_RP_DEPTH_OFF 10
+#define ENT_INT_SRC3_AXI_OFF 11
+#define ENT_INT_SRC3_FIFO_OFF 12
+#define ENT_INT_SRC3_LM_OFF 14
+#define ENT_INT_SRC3_ITC_INT_OFF 15
+#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
+#define ENT_INT_SRC3_ABT_OFF 16
+#define ENT_INT_SRC_MSK1 0x1c4
+#define ENT_INT_SRC_MSK2 0x1c8
+#define ENT_INT_SRC_MSK3 0x1cc
+#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
+#define CHNL_ENT_INT_MSK 0x1d4
+#define HGC_COM_INT_MSK 0x1d8
+#define SAS_ECC_INTR 0x1e8
+#define SAS_ECC_INTR_MSK 0x1ec
+#define HGC_ERR_STAT_EN 0x238
+#define DLVRY_Q_0_BASE_ADDR_LO 0x260
+#define DLVRY_Q_0_BASE_ADDR_HI 0x264
+#define DLVRY_Q_0_DEPTH 0x268
+#define DLVRY_Q_0_WR_PTR 0x26c
+#define DLVRY_Q_0_RD_PTR 0x270
+#define HYPER_STREAM_ID_EN_CFG 0xc80
+#define OQ0_INT_SRC_MSK 0xc90
+#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
+#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
+#define COMPL_Q_0_DEPTH 0x4e8
+#define COMPL_Q_0_WR_PTR 0x4ec
+#define COMPL_Q_0_RD_PTR 0x4f0
+#define AWQOS_AWCACHE_CFG 0xc84
+#define ARQOS_ARCACHE_CFG 0xc88
+
+/* phy registers requiring init */
+#define PORT_BASE (0x2000)
+#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
+#define PHY_CTRL (PORT_BASE + 0x14)
+#define PHY_CTRL_RESET_OFF 0
+#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
+#define SL_CFG (PORT_BASE + 0x84)
+#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
+#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
+#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
+#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
+#define CHL_INT0 (PORT_BASE + 0x1b4)
+#define CHL_INT0_HOTPLUG_TOUT_OFF 0
+#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
+#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
+#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
+#define CHL_INT0_SL_PHY_ENABLE_OFF 2
+#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
+#define CHL_INT0_NOT_RDY_OFF 4
+#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
+#define CHL_INT0_PHY_RDY_OFF 5
+#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
+#define CHL_INT1 (PORT_BASE + 0x1b8)
+#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
+#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
+#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
+#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
+#define CHL_INT2 (PORT_BASE + 0x1bc)
+#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
+#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
+#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
+#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
+#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
+#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
+#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
+#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
+#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
+#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+struct hisi_sas_complete_v3_hdr {
+ __le32 dw0;
+ __le32 dw1;
+ __le32 act;
+ __le32 dw3;
+};
+
+#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
+
+static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ writel(val, regs);
+}
+
+static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
+ u32 off, u32 val)
+{
+ void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+ writel(val, regs);
+}
+
+static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
+{
+ int i;
+
+ /* Global registers init */
+ hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
+ (u32)((1ULL << hisi_hba->queue_count) - 1));
+ hisi_sas_write32(hisi_hba, AXI_USER1, 0x0);
+ hisi_sas_write32(hisi_hba, AXI_USER2, 0x40000060);
+ hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
+ hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
+ hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
+ hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
+ hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
+ hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
+ for (i = 0; i < hisi_hba->queue_count; i++)
+ hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
+
+ hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
+ hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
+ hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff07fff);
+
+ for (i = 0; i < hisi_hba->n_phy; i++) {
+ hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
+ hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x83f801fc);
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
+ 0xa0064);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
+ 0xa0064);
+ }
+ for (i = 0; i < hisi_hba->queue_count; i++) {
+ /* Delivery queue */
+ hisi_sas_write32(hisi_hba,
+ DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
+ upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
+ lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
+ HISI_SAS_QUEUE_SLOTS);
+
+ /* Completion queue */
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
+ upper_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
+ lower_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
+ HISI_SAS_QUEUE_SLOTS);
+ }
+
+ /* itct */
+ hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
+ lower_32_bits(hisi_hba->itct_dma));
+
+ hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
+ upper_32_bits(hisi_hba->itct_dma));
+
+ /* iost */
+ hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
+ lower_32_bits(hisi_hba->iost_dma));
+
+ hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
+ upper_32_bits(hisi_hba->iost_dma));
+
+ /* breakpoint */
+ hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
+ lower_32_bits(hisi_hba->breakpoint_dma));
+
+ hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
+ upper_32_bits(hisi_hba->breakpoint_dma));
+
+ /* SATA broken msg */
+ hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
+ lower_32_bits(hisi_hba->sata_breakpoint_dma));
+
+ hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
+ upper_32_bits(hisi_hba->sata_breakpoint_dma));
+
+ /* SATA initial fis */
+ hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
+ lower_32_bits(hisi_hba->initial_fis_dma));
+
+ hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
+ upper_32_bits(hisi_hba->initial_fis_dma));
+}
+
+static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ init_reg_v3_hw(hisi_hba);
+
+ return 0;
+}
+
+static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
+{
+ int rc;
+
+ rc = hw_init_v3_hw(hisi_hba);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
+ .hw_init = hisi_sas_v3_init,
+ .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
+ .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 10/22] scsi: hisi_sas: add v3 hw init
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to initialise v3 hardware.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 275 +++++++++++++++++++++++++++++++++
1 file changed, 275 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 68b9b0e..f2ea8c8 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -11,7 +11,282 @@
#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_v3_hw"
+/* global registers need init*/
+#define DLVRY_QUEUE_ENABLE 0x0
+#define IOST_BASE_ADDR_LO 0x8
+#define IOST_BASE_ADDR_HI 0xc
+#define ITCT_BASE_ADDR_LO 0x10
+#define ITCT_BASE_ADDR_HI 0x14
+#define IO_BROKEN_MSG_ADDR_LO 0x18
+#define IO_BROKEN_MSG_ADDR_HI 0x1c
+#define AXI_AHB_CLK_CFG 0x3c
+#define AXI_USER1 0x48
+#define AXI_USER2 0x4c
+#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
+#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
+#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
+#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
+#define CFG_MAX_TAG 0x68
+#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
+#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
+#define HGC_GET_ITV_TIME 0x90
+#define DEVICE_MSG_WORK_MODE 0x94
+#define OPENA_WT_CONTI_TIME 0x9c
+#define I_T_NEXUS_LOSS_TIME 0xa0
+#define MAX_CON_TIME_LIMIT_TIME 0xa4
+#define BUS_INACTIVE_LIMIT_TIME 0xa8
+#define REJECT_TO_OPEN_LIMIT_TIME 0xac
+#define CFG_AGING_TIME 0xbc
+#define HGC_DFX_CFG2 0xc0
+#define CFG_ABT_SET_QUERY_IPTT 0xd4
+#define CFG_SET_ABORTED_IPTT_OFF 0
+#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
+#define CFG_1US_TIMER_TRSH 0xcc
+#define INT_COAL_EN 0x19c
+#define OQ_INT_COAL_TIME 0x1a0
+#define OQ_INT_COAL_CNT 0x1a4
+#define ENT_INT_COAL_TIME 0x1a8
+#define ENT_INT_COAL_CNT 0x1ac
+#define OQ_INT_SRC 0x1b0
+#define OQ_INT_SRC_MSK 0x1b4
+#define ENT_INT_SRC1 0x1b8
+#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
+#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
+#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
+#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
+#define ENT_INT_SRC2 0x1bc
+#define ENT_INT_SRC3 0x1c0
+#define ENT_INT_SRC3_WP_DEPTH_OFF 8
+#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
+#define ENT_INT_SRC3_RP_DEPTH_OFF 10
+#define ENT_INT_SRC3_AXI_OFF 11
+#define ENT_INT_SRC3_FIFO_OFF 12
+#define ENT_INT_SRC3_LM_OFF 14
+#define ENT_INT_SRC3_ITC_INT_OFF 15
+#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
+#define ENT_INT_SRC3_ABT_OFF 16
+#define ENT_INT_SRC_MSK1 0x1c4
+#define ENT_INT_SRC_MSK2 0x1c8
+#define ENT_INT_SRC_MSK3 0x1cc
+#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
+#define CHNL_ENT_INT_MSK 0x1d4
+#define HGC_COM_INT_MSK 0x1d8
+#define SAS_ECC_INTR 0x1e8
+#define SAS_ECC_INTR_MSK 0x1ec
+#define HGC_ERR_STAT_EN 0x238
+#define DLVRY_Q_0_BASE_ADDR_LO 0x260
+#define DLVRY_Q_0_BASE_ADDR_HI 0x264
+#define DLVRY_Q_0_DEPTH 0x268
+#define DLVRY_Q_0_WR_PTR 0x26c
+#define DLVRY_Q_0_RD_PTR 0x270
+#define HYPER_STREAM_ID_EN_CFG 0xc80
+#define OQ0_INT_SRC_MSK 0xc90
+#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
+#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
+#define COMPL_Q_0_DEPTH 0x4e8
+#define COMPL_Q_0_WR_PTR 0x4ec
+#define COMPL_Q_0_RD_PTR 0x4f0
+#define AWQOS_AWCACHE_CFG 0xc84
+#define ARQOS_ARCACHE_CFG 0xc88
+
+/* phy registers requiring init */
+#define PORT_BASE (0x2000)
+#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
+#define PHY_CTRL (PORT_BASE + 0x14)
+#define PHY_CTRL_RESET_OFF 0
+#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
+#define SL_CFG (PORT_BASE + 0x84)
+#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
+#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
+#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
+#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
+#define CHL_INT0 (PORT_BASE + 0x1b4)
+#define CHL_INT0_HOTPLUG_TOUT_OFF 0
+#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
+#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
+#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
+#define CHL_INT0_SL_PHY_ENABLE_OFF 2
+#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
+#define CHL_INT0_NOT_RDY_OFF 4
+#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
+#define CHL_INT0_PHY_RDY_OFF 5
+#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
+#define CHL_INT1 (PORT_BASE + 0x1b8)
+#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
+#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
+#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
+#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
+#define CHL_INT2 (PORT_BASE + 0x1bc)
+#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
+#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
+#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
+#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
+#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
+#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
+#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
+#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
+#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
+#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+struct hisi_sas_complete_v3_hdr {
+ __le32 dw0;
+ __le32 dw1;
+ __le32 act;
+ __le32 dw3;
+};
+
+#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
+
+static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ writel(val, regs);
+}
+
+static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
+ u32 off, u32 val)
+{
+ void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+ writel(val, regs);
+}
+
+static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
+{
+ int i;
+
+ /* Global registers init */
+ hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
+ (u32)((1ULL << hisi_hba->queue_count) - 1));
+ hisi_sas_write32(hisi_hba, AXI_USER1, 0x0);
+ hisi_sas_write32(hisi_hba, AXI_USER2, 0x40000060);
+ hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
+ hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
+ hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
+ hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
+ hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
+ hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
+ hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
+ for (i = 0; i < hisi_hba->queue_count; i++)
+ hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
+
+ hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
+ hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
+ hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff07fff);
+
+ for (i = 0; i < hisi_hba->n_phy; i++) {
+ hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
+ hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
+ hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x83f801fc);
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
+ hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
+ 0xa0064);
+ hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
+ 0xa0064);
+ }
+ for (i = 0; i < hisi_hba->queue_count; i++) {
+ /* Delivery queue */
+ hisi_sas_write32(hisi_hba,
+ DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
+ upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
+ lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
+ HISI_SAS_QUEUE_SLOTS);
+
+ /* Completion queue */
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
+ upper_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
+ lower_32_bits(hisi_hba->complete_hdr_dma[i]));
+
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
+ HISI_SAS_QUEUE_SLOTS);
+ }
+
+ /* itct */
+ hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
+ lower_32_bits(hisi_hba->itct_dma));
+
+ hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
+ upper_32_bits(hisi_hba->itct_dma));
+
+ /* iost */
+ hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
+ lower_32_bits(hisi_hba->iost_dma));
+
+ hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
+ upper_32_bits(hisi_hba->iost_dma));
+
+ /* breakpoint */
+ hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
+ lower_32_bits(hisi_hba->breakpoint_dma));
+
+ hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
+ upper_32_bits(hisi_hba->breakpoint_dma));
+
+ /* SATA broken msg */
+ hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
+ lower_32_bits(hisi_hba->sata_breakpoint_dma));
+
+ hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
+ upper_32_bits(hisi_hba->sata_breakpoint_dma));
+
+ /* SATA initial fis */
+ hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
+ lower_32_bits(hisi_hba->initial_fis_dma));
+
+ hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
+ upper_32_bits(hisi_hba->initial_fis_dma));
+}
+
+static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ init_reg_v3_hw(hisi_hba);
+
+ return 0;
+}
+
+static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
+{
+ int rc;
+
+ rc = hw_init_v3_hw(hisi_hba);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
+ .hw_init = hisi_sas_v3_init,
+ .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
+ .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 11/22] scsi: hisi_sas: add v3 hw PHY init
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to configure PHYs for v3 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 126 +++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index f2ea8c8..ea18582 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -19,6 +19,10 @@
#define ITCT_BASE_ADDR_HI 0x14
#define IO_BROKEN_MSG_ADDR_LO 0x18
#define IO_BROKEN_MSG_ADDR_HI 0x1c
+#define PHY_CONTEXT 0x20
+#define PHY_STATE 0x24
+#define PHY_PORT_NUM_MA 0x28
+#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG 0x3c
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
@@ -42,6 +46,7 @@
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_1US_TIMER_TRSH 0xcc
+#define CHNL_INT_STATUS 0x148
#define INT_COAL_EN 0x19c
#define OQ_INT_COAL_TIME 0x1a0
#define OQ_INT_COAL_CNT 0x1a4
@@ -68,9 +73,11 @@
#define ENT_INT_SRC_MSK1 0x1c4
#define ENT_INT_SRC_MSK2 0x1c8
#define ENT_INT_SRC_MSK3 0x1cc
+#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
#define CHNL_ENT_INT_MSK 0x1d4
#define HGC_COM_INT_MSK 0x1d8
+#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR 0x1e8
#define SAS_ECC_INTR_MSK 0x1ec
#define HGC_ERR_STAT_EN 0x238
@@ -91,11 +98,33 @@
/* phy registers requiring init */
#define PORT_BASE (0x2000)
+#define PHY_CFG (PORT_BASE + 0x0)
+#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
+#define PHY_CFG_ENA_OFF 0
+#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
+#define PHY_CFG_DC_OPT_OFF 2
+#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
#define PHY_CTRL (PORT_BASE + 0x14)
#define PHY_CTRL_RESET_OFF 0
#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
#define SL_CFG (PORT_BASE + 0x84)
+#define SL_CONTROL (PORT_BASE + 0x94)
+#define SL_CONTROL_NOTIFY_EN_OFF 0
+#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
+#define SL_CTA_OFF 17
+#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
+#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
+#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
+#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
+#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
+#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
+#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
+#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
+#define TXID_AUTO (PORT_BASE + 0xb8)
+#define CT3_OFF 1
+#define CT3_MSK (0x1 << CT3_OFF)
+#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
@@ -135,6 +164,13 @@ struct hisi_sas_complete_v3_hdr {
};
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
+#define HISI_SAS_MSI_COUNT_V3_HW 32
+
+enum {
+ HISI_SAS_PHY_PHY_UPDOWN,
+ HISI_SAS_PHY_CHNL_INT,
+ HISI_SAS_PHY_INT_NR
+};
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
@@ -151,6 +187,14 @@ static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
writel(val, regs);
}
+static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
+ int phy_no, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+ return readl(regs);
+}
+
static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -265,6 +309,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
upper_32_bits(hisi_hba->initial_fis_dma));
}
+static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_DC_OPT_MSK;
+ cfg |= 1 << PHY_CFG_DC_OPT_OFF;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct sas_identify_frame identify_frame;
+ u32 *identify_buffer;
+
+ memset(&identify_frame, 0, sizeof(identify_frame));
+ identify_frame.dev_type = SAS_END_DEVICE;
+ identify_frame.frame_type = 0;
+ identify_frame._un1 = 1;
+ identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
+ identify_frame.target_bits = SAS_PROTOCOL_NONE;
+ memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
+ memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
+ identify_frame.phy_id = phy_no;
+ identify_buffer = (u32 *)(&identify_frame);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
+ __swab32(identify_buffer[0]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
+ __swab32(identify_buffer[1]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
+ __swab32(identify_buffer[2]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
+ __swab32(identify_buffer[3]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
+ __swab32(identify_buffer[4]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
+ __swab32(identify_buffer[5]));
+}
+
static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
{
init_reg_v3_hw(hisi_hba);
@@ -272,6 +355,47 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
return 0;
}
+static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg |= PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ config_id_frame_v3_hw(hisi_hba, phy_no);
+ config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
+ enable_phy_v3_hw(hisi_hba, phy_no);
+}
+
+static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
+{
+ int i;
+
+ for (i = 0; i < hisi_hba->n_phy; i++)
+ start_phy_v3_hw(hisi_hba, i);
+}
+
+static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ start_phys_v3_hw(hisi_hba);
+}
+
+static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 sl_control;
+
+ sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+ msleep(1);
+ sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+}
+
static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
{
int rc;
@@ -286,7 +410,9 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
+ .sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .phys_init = phys_init_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 11/22] scsi: hisi_sas: add v3 hw PHY init
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to configure PHYs for v3 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 126 +++++++++++++++++++++++++++++++++
1 file changed, 126 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index f2ea8c8..ea18582 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -19,6 +19,10 @@
#define ITCT_BASE_ADDR_HI 0x14
#define IO_BROKEN_MSG_ADDR_LO 0x18
#define IO_BROKEN_MSG_ADDR_HI 0x1c
+#define PHY_CONTEXT 0x20
+#define PHY_STATE 0x24
+#define PHY_PORT_NUM_MA 0x28
+#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG 0x3c
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
@@ -42,6 +46,7 @@
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_1US_TIMER_TRSH 0xcc
+#define CHNL_INT_STATUS 0x148
#define INT_COAL_EN 0x19c
#define OQ_INT_COAL_TIME 0x1a0
#define OQ_INT_COAL_CNT 0x1a4
@@ -68,9 +73,11 @@
#define ENT_INT_SRC_MSK1 0x1c4
#define ENT_INT_SRC_MSK2 0x1c8
#define ENT_INT_SRC_MSK3 0x1cc
+#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
#define CHNL_ENT_INT_MSK 0x1d4
#define HGC_COM_INT_MSK 0x1d8
+#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR 0x1e8
#define SAS_ECC_INTR_MSK 0x1ec
#define HGC_ERR_STAT_EN 0x238
@@ -91,11 +98,33 @@
/* phy registers requiring init */
#define PORT_BASE (0x2000)
+#define PHY_CFG (PORT_BASE + 0x0)
+#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
+#define PHY_CFG_ENA_OFF 0
+#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
+#define PHY_CFG_DC_OPT_OFF 2
+#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
#define PHY_CTRL (PORT_BASE + 0x14)
#define PHY_CTRL_RESET_OFF 0
#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
#define SL_CFG (PORT_BASE + 0x84)
+#define SL_CONTROL (PORT_BASE + 0x94)
+#define SL_CONTROL_NOTIFY_EN_OFF 0
+#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
+#define SL_CTA_OFF 17
+#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
+#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
+#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
+#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
+#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
+#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
+#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
+#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
+#define TXID_AUTO (PORT_BASE + 0xb8)
+#define CT3_OFF 1
+#define CT3_MSK (0x1 << CT3_OFF)
+#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
@@ -135,6 +164,13 @@ struct hisi_sas_complete_v3_hdr {
};
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
+#define HISI_SAS_MSI_COUNT_V3_HW 32
+
+enum {
+ HISI_SAS_PHY_PHY_UPDOWN,
+ HISI_SAS_PHY_CHNL_INT,
+ HISI_SAS_PHY_INT_NR
+};
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
@@ -151,6 +187,14 @@ static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
writel(val, regs);
}
+static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
+ int phy_no, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
+
+ return readl(regs);
+}
+
static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -265,6 +309,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
upper_32_bits(hisi_hba->initial_fis_dma));
}
+static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_DC_OPT_MSK;
+ cfg |= 1 << PHY_CFG_DC_OPT_OFF;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct sas_identify_frame identify_frame;
+ u32 *identify_buffer;
+
+ memset(&identify_frame, 0, sizeof(identify_frame));
+ identify_frame.dev_type = SAS_END_DEVICE;
+ identify_frame.frame_type = 0;
+ identify_frame._un1 = 1;
+ identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
+ identify_frame.target_bits = SAS_PROTOCOL_NONE;
+ memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
+ memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
+ identify_frame.phy_id = phy_no;
+ identify_buffer = (u32 *)(&identify_frame);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
+ __swab32(identify_buffer[0]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
+ __swab32(identify_buffer[1]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
+ __swab32(identify_buffer[2]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
+ __swab32(identify_buffer[3]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
+ __swab32(identify_buffer[4]));
+ hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
+ __swab32(identify_buffer[5]));
+}
+
static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
{
init_reg_v3_hw(hisi_hba);
@@ -272,6 +355,47 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
return 0;
}
+static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg |= PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
+static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ config_id_frame_v3_hw(hisi_hba, phy_no);
+ config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
+ enable_phy_v3_hw(hisi_hba, phy_no);
+}
+
+static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
+{
+ int i;
+
+ for (i = 0; i < hisi_hba->n_phy; i++)
+ start_phy_v3_hw(hisi_hba, i);
+}
+
+static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ start_phys_v3_hw(hisi_hba);
+}
+
+static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 sl_control;
+
+ sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+ msleep(1);
+ sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
+}
+
static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
{
int rc;
@@ -286,7 +410,9 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
+ .sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .phys_init = phys_init_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 12/22] scsi: hisi_sas: add phy up/down/bcast and channel ISR
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to initialise interrupts and add some interrupt handlers.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 281 +++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index ea18582..f7872c5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -172,6 +172,13 @@ enum {
HISI_SAS_PHY_INT_NR
};
+static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -396,6 +403,276 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ int i, res = 0;
+ u32 context, port_id, link_rate, hard_phy_linkrate;
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ struct asd_sas_phy *sas_phy = &phy->sas_phy;
+ struct device *dev = hisi_hba->dev;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
+
+ port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+ port_id = (port_id >> (4 * phy_no)) & 0xf;
+ link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
+ link_rate = (link_rate >> (phy_no * 4)) & 0xf;
+
+ if (port_id == 0xf) {
+ dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
+ res = IRQ_NONE;
+ goto end;
+ }
+ sas_phy->linkrate = link_rate;
+ hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
+ HARD_PHY_LINKRATE);
+ phy->maximum_linkrate = hard_phy_linkrate & 0xf;
+ phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
+ phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
+
+ /* Check for SATA dev */
+ context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
+ if (context & (1 << phy_no)) {
+ struct hisi_sas_initial_fis *initial_fis;
+ struct dev_to_host_fis *fis;
+ u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ initial_fis = &hisi_hba->initial_fis[phy_no];
+ fis = &initial_fis->fis;
+ sas_phy->oob_mode = SATA_OOB_MODE;
+ attached_sas_addr[0] = 0x50;
+ attached_sas_addr[7] = phy_no;
+ memcpy(sas_phy->attached_sas_addr,
+ attached_sas_addr,
+ SAS_ADDR_SIZE);
+ memcpy(sas_phy->frame_rcvd, fis,
+ sizeof(struct dev_to_host_fis));
+ phy->phy_type |= PORT_TYPE_SATA;
+ phy->identify.device_type = SAS_SATA_DEV;
+ phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
+ phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
+ } else {
+ u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
+ struct sas_identify_frame *id =
+ (struct sas_identify_frame *)frame_rcvd;
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ for (i = 0; i < 6; i++) {
+ u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
+ RX_IDAF_DWORD0 + (i * 4));
+ frame_rcvd[i] = __swab32(idaf);
+ }
+ sas_phy->oob_mode = SAS_OOB_MODE;
+ memcpy(sas_phy->attached_sas_addr,
+ &id->sas_addr,
+ SAS_ADDR_SIZE);
+ phy->phy_type |= PORT_TYPE_SAS;
+ phy->identify.device_type = id->dev_type;
+ phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
+ if (phy->identify.device_type == SAS_END_DEVICE)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SSP;
+ else if (phy->identify.device_type != SAS_PHY_UNUSED)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SMP;
+ }
+
+ phy->port_id = port_id;
+ phy->phy_attached = 1;
+ queue_work(hisi_hba->wq, &phy->phyup_ws);
+
+end:
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
+ CHL_INT0_SL_PHY_ENABLE_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
+
+ return res;
+}
+
+static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ int res = 0;
+ u32 phy_state, sl_ctrl, txid_auto;
+ struct device *dev = hisi_hba->dev;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
+
+ phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
+ dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
+ hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
+
+ sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
+ sl_ctrl&(~SL_CTA_MSK));
+
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | CT3_MSK);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
+
+ return res;
+}
+
+static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ struct asd_sas_phy *sas_phy = &phy->sas_phy;
+ struct sas_ha_struct *sas_ha = &hisi_hba->sha;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
+ sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
+ CHL_INT0_SL_RX_BCST_ACK_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
+}
+
+static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ u32 irq_msk;
+ int phy_no = 0;
+ irqreturn_t res = IRQ_NONE;
+
+ irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
+ & 0x11111111;
+ while (irq_msk) {
+ if (irq_msk & 1) {
+ u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT0);
+ u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
+ int rdy = phy_state & (1 << phy_no);
+
+ if (rdy) {
+ if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
+ /* phy up */
+ if (phy_up_v3_hw(phy_no, hisi_hba)
+ == IRQ_HANDLED)
+ res = IRQ_HANDLED;
+ if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
+ /* phy bcast */
+ phy_bcast_v3_hw(phy_no, hisi_hba);
+ } else {
+ if (irq_value & CHL_INT0_NOT_RDY_MSK)
+ /* phy down */
+ if (phy_down_v3_hw(phy_no, hisi_hba)
+ == IRQ_HANDLED)
+ res = IRQ_HANDLED;
+ }
+ }
+ irq_msk >>= 4;
+ phy_no++;
+ }
+
+ return res;
+}
+
+static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ struct device *dev = hisi_hba->dev;
+ u32 ent_msk, ent_tmp, irq_msk;
+ int phy_no = 0;
+
+ ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
+ ent_tmp = ent_msk;
+ ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
+
+ irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
+ & 0xeeeeeeee;
+
+ while (irq_msk) {
+ u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT0);
+ u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT1);
+ u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT2);
+
+ if ((irq_msk & (4 << (phy_no * 4))) &&
+ irq_value1) {
+ if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
+ CHL_INT1_DMAC_TX_ECC_ERR_MSK))
+ panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
+ dev_name(dev), irq_value1);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT1, irq_value1);
+ }
+
+ if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT2, irq_value2);
+
+
+ if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT0, irq_value0
+ & (~CHL_INT0_HOTPLUG_TOUT_MSK)
+ & (~CHL_INT0_SL_PHY_ENABLE_MSK)
+ & (~CHL_INT0_NOT_RDY_MSK));
+ }
+ irq_msk &= ~(0xe << (phy_no * 4));
+ phy_no++;
+ }
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
+
+ return IRQ_HANDLED;
+}
+
+static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
+ int_phy_up_down_bcast_v3_hw,
+ int_chnl_int_v3_hw,
+};
+
+static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ struct device *dev = hisi_hba->dev;
+ struct pci_dev *pdev = hisi_hba->pci_dev;
+ int vectors, i, irq, rc;
+ int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
+ int msi_vectors[HISI_SAS_MSI_COUNT_V3_HW];
+
+ if (pdev->msi_enabled)
+ pci_disable_msi(pdev);
+
+ vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
+ max_msi, PCI_IRQ_MSI);
+ if (vectors < max_msi) {
+ dev_err(dev, "could not allocate all msi (%d)\n", vectors);
+ return -ENOENT;
+ }
+
+ for (i = 0; i < vectors; i++)
+ msi_vectors[i] = pdev->irq + i;
+
+ for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
+ int idx = i;
+
+ irq = msi_vectors[idx + 1]; /* Phy up/down/bcast is irq1 */
+ if (!irq) {
+ dev_err(dev, "irq init: failed to map PHY interrupt %d\n",
+ idx);
+ return -ENOENT;
+ }
+
+ rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
+ DRV_NAME " phy", hisi_hba);
+ if (rc) {
+ dev_err(dev, "irq init: could not request "
+ "phy interrupt %d, rc=%d\n",
+ irq, rc);
+ return -ENOENT;
+ }
+ }
+
+ return 0;
+}
+
static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
{
int rc;
@@ -404,6 +681,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
if (rc)
return rc;
+ rc = interrupt_init_v3_hw(hisi_hba);
+ if (rc)
+ return rc;
+
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 12/22] scsi: hisi_sas: add phy up/down/bcast and channel ISR
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to initialise interrupts and add some interrupt handlers.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 281 +++++++++++++++++++++++++++++++++
1 file changed, 281 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index ea18582..f7872c5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -172,6 +172,13 @@ enum {
HISI_SAS_PHY_INT_NR
};
+static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -396,6 +403,276 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ int i, res = 0;
+ u32 context, port_id, link_rate, hard_phy_linkrate;
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ struct asd_sas_phy *sas_phy = &phy->sas_phy;
+ struct device *dev = hisi_hba->dev;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
+
+ port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+ port_id = (port_id >> (4 * phy_no)) & 0xf;
+ link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
+ link_rate = (link_rate >> (phy_no * 4)) & 0xf;
+
+ if (port_id == 0xf) {
+ dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
+ res = IRQ_NONE;
+ goto end;
+ }
+ sas_phy->linkrate = link_rate;
+ hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
+ HARD_PHY_LINKRATE);
+ phy->maximum_linkrate = hard_phy_linkrate & 0xf;
+ phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
+ phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
+
+ /* Check for SATA dev */
+ context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
+ if (context & (1 << phy_no)) {
+ struct hisi_sas_initial_fis *initial_fis;
+ struct dev_to_host_fis *fis;
+ u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ initial_fis = &hisi_hba->initial_fis[phy_no];
+ fis = &initial_fis->fis;
+ sas_phy->oob_mode = SATA_OOB_MODE;
+ attached_sas_addr[0] = 0x50;
+ attached_sas_addr[7] = phy_no;
+ memcpy(sas_phy->attached_sas_addr,
+ attached_sas_addr,
+ SAS_ADDR_SIZE);
+ memcpy(sas_phy->frame_rcvd, fis,
+ sizeof(struct dev_to_host_fis));
+ phy->phy_type |= PORT_TYPE_SATA;
+ phy->identify.device_type = SAS_SATA_DEV;
+ phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
+ phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
+ } else {
+ u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
+ struct sas_identify_frame *id =
+ (struct sas_identify_frame *)frame_rcvd;
+
+ dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
+ for (i = 0; i < 6; i++) {
+ u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
+ RX_IDAF_DWORD0 + (i * 4));
+ frame_rcvd[i] = __swab32(idaf);
+ }
+ sas_phy->oob_mode = SAS_OOB_MODE;
+ memcpy(sas_phy->attached_sas_addr,
+ &id->sas_addr,
+ SAS_ADDR_SIZE);
+ phy->phy_type |= PORT_TYPE_SAS;
+ phy->identify.device_type = id->dev_type;
+ phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
+ if (phy->identify.device_type == SAS_END_DEVICE)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SSP;
+ else if (phy->identify.device_type != SAS_PHY_UNUSED)
+ phy->identify.target_port_protocols =
+ SAS_PROTOCOL_SMP;
+ }
+
+ phy->port_id = port_id;
+ phy->phy_attached = 1;
+ queue_work(hisi_hba->wq, &phy->phyup_ws);
+
+end:
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
+ CHL_INT0_SL_PHY_ENABLE_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
+
+ return res;
+}
+
+static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ int res = 0;
+ u32 phy_state, sl_ctrl, txid_auto;
+ struct device *dev = hisi_hba->dev;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
+
+ phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
+ dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
+ hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
+
+ sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
+ sl_ctrl&(~SL_CTA_MSK));
+
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | CT3_MSK);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
+
+ return res;
+}
+
+static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ struct asd_sas_phy *sas_phy = &phy->sas_phy;
+ struct sas_ha_struct *sas_ha = &hisi_hba->sha;
+
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
+ sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
+ hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
+ CHL_INT0_SL_RX_BCST_ACK_MSK);
+ hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
+}
+
+static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ u32 irq_msk;
+ int phy_no = 0;
+ irqreturn_t res = IRQ_NONE;
+
+ irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
+ & 0x11111111;
+ while (irq_msk) {
+ if (irq_msk & 1) {
+ u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT0);
+ u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
+ int rdy = phy_state & (1 << phy_no);
+
+ if (rdy) {
+ if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
+ /* phy up */
+ if (phy_up_v3_hw(phy_no, hisi_hba)
+ == IRQ_HANDLED)
+ res = IRQ_HANDLED;
+ if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
+ /* phy bcast */
+ phy_bcast_v3_hw(phy_no, hisi_hba);
+ } else {
+ if (irq_value & CHL_INT0_NOT_RDY_MSK)
+ /* phy down */
+ if (phy_down_v3_hw(phy_no, hisi_hba)
+ == IRQ_HANDLED)
+ res = IRQ_HANDLED;
+ }
+ }
+ irq_msk >>= 4;
+ phy_no++;
+ }
+
+ return res;
+}
+
+static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ struct device *dev = hisi_hba->dev;
+ u32 ent_msk, ent_tmp, irq_msk;
+ int phy_no = 0;
+
+ ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
+ ent_tmp = ent_msk;
+ ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
+
+ irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
+ & 0xeeeeeeee;
+
+ while (irq_msk) {
+ u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT0);
+ u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT1);
+ u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
+ CHL_INT2);
+
+ if ((irq_msk & (4 << (phy_no * 4))) &&
+ irq_value1) {
+ if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
+ CHL_INT1_DMAC_TX_ECC_ERR_MSK))
+ panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
+ dev_name(dev), irq_value1);
+
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT1, irq_value1);
+ }
+
+ if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT2, irq_value2);
+
+
+ if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
+ hisi_sas_phy_write32(hisi_hba, phy_no,
+ CHL_INT0, irq_value0
+ & (~CHL_INT0_HOTPLUG_TOUT_MSK)
+ & (~CHL_INT0_SL_PHY_ENABLE_MSK)
+ & (~CHL_INT0_NOT_RDY_MSK));
+ }
+ irq_msk &= ~(0xe << (phy_no * 4));
+ phy_no++;
+ }
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
+
+ return IRQ_HANDLED;
+}
+
+static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
+ int_phy_up_down_bcast_v3_hw,
+ int_chnl_int_v3_hw,
+};
+
+static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
+{
+ struct device *dev = hisi_hba->dev;
+ struct pci_dev *pdev = hisi_hba->pci_dev;
+ int vectors, i, irq, rc;
+ int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
+ int msi_vectors[HISI_SAS_MSI_COUNT_V3_HW];
+
+ if (pdev->msi_enabled)
+ pci_disable_msi(pdev);
+
+ vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
+ max_msi, PCI_IRQ_MSI);
+ if (vectors < max_msi) {
+ dev_err(dev, "could not allocate all msi (%d)\n", vectors);
+ return -ENOENT;
+ }
+
+ for (i = 0; i < vectors; i++)
+ msi_vectors[i] = pdev->irq + i;
+
+ for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
+ int idx = i;
+
+ irq = msi_vectors[idx + 1]; /* Phy up/down/bcast is irq1 */
+ if (!irq) {
+ dev_err(dev, "irq init: failed to map PHY interrupt %d\n",
+ idx);
+ return -ENOENT;
+ }
+
+ rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
+ DRV_NAME " phy", hisi_hba);
+ if (rc) {
+ dev_err(dev, "irq init: could not request "
+ "phy interrupt %d, rc=%d\n",
+ irq, rc);
+ return -ENOENT;
+ }
+ }
+
+ return 0;
+}
+
static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
{
int rc;
@@ -404,6 +681,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
if (rc)
return rc;
+ rc = interrupt_init_v3_hw(hisi_hba);
+ if (rc)
+ return rc;
+
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 13/22] scsi: hisi_sas: add v3 cq interrupt handler
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add v3 cq interrupt handler.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 32 ++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 332 +++++++++++++++++++++++++++++++++
3 files changed, 365 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 9fd874d..c7d1144 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -385,6 +385,7 @@ extern int hisi_sas_pci_probe(struct pci_dev *pdev,
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
+extern bool hisi_sas_is_rw_cmd(struct sas_task *task);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 33bd3c45..156b66b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -118,6 +118,38 @@ int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag)
}
EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag);
+bool hisi_sas_is_rw_cmd(struct sas_task *task)
+{
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ unsigned char op = task->ssp_task.cmd->cmnd[0];
+
+ if (op == READ_6 || op == WRITE_6 ||
+ op == READ_10 || op == WRITE_10 ||
+ op == READ_12 || op == WRITE_12 ||
+ op == READ_16 || op == WRITE_16)
+ return true;
+ break;
+ }
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ u32 cmd_proto = hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command,
+ task->data_dir);
+ if (cmd_proto != SATA_PROTOCOL_NONDATA)
+ return true;
+ break;
+ }
+ default:
+ break;
+ }
+ return false;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_is_rw_cmd);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index f7872c5..b33781b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -156,6 +156,33 @@
#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+
+/* Completion header */
+/* dw0 */
+#define CMPLT_HDR_CMPLT_OFF 0
+#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
+#define CMPLT_HDR_ERROR_PHASE_OFF 2
+#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
+#define CMPLT_HDR_RSPNS_XFRD_OFF 10
+#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
+#define CMPLT_HDR_ERX_OFF 12
+#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
+#define CMPLT_HDR_ABORT_STAT_OFF 13
+#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
+/* abort_stat */
+#define STAT_IO_NOT_VALID 0x1
+#define STAT_IO_NO_DEVICE 0x2
+#define STAT_IO_COMPLETE 0x3
+#define STAT_IO_ABORTED 0x4
+/* dw1 */
+#define CMPLT_HDR_IPTT_OFF 0
+#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
+#define CMPLT_HDR_DEV_ID_OFF 16
+#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
+/* dw3 */
+#define CMPLT_HDR_IO_IN_TARGET_OFF 17
+#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -163,6 +190,8 @@ struct hisi_sas_complete_v3_hdr {
__le32 dw3;
};
+#define IO_RX_DATA_LEN_UNDERFLOW_OFF 6
+#define IO_RX_DATA_LEN_UNDERFLOW_MSK (1 << IO_RX_DATA_LEN_UNDERFLOW_OFF)
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
#define HISI_SAS_MSI_COUNT_V3_HW 32
@@ -624,6 +653,286 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
return IRQ_HANDLED;
}
+static void slot_err_v3_hw(struct hisi_hba *hisi_hba,
+ struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct hisi_sas_complete_v3_hdr *complete_queue =
+ hisi_hba->complete_hdr[slot->cmplt_queue];
+ struct hisi_sas_complete_v3_hdr *complete_hdr =
+ &complete_queue[slot->cmplt_queue_slot];
+
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_QUEUE_FULL;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ }
+ break;
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_PHY_DOWN;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ hisi_sas_sata_done(task, slot);
+ }
+ break;
+ case SAS_PROTOCOL_SMP:
+ ts->stat = SAM_STAT_CHECK_CONDITION;
+ break;
+ default:
+ break;
+ }
+}
+
+static int
+slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_device *sas_dev;
+ struct device *dev = hisi_hba->dev;
+ struct task_status_struct *ts;
+ struct domain_device *device;
+ enum exec_status sts;
+ u32 *error_info = slot->status_buffer;
+ struct hisi_sas_complete_v3_hdr *complete_queue =
+ hisi_hba->complete_hdr[slot->cmplt_queue];
+ struct hisi_sas_complete_v3_hdr *complete_hdr =
+ &complete_queue[slot->cmplt_queue_slot];
+ int aborted;
+ unsigned long flags;
+
+ if (unlikely(!task || !task->lldd_task || !task->dev))
+ return -EINVAL;
+
+ ts = &task->task_status;
+ device = task->dev;
+ sas_dev = device->lldd_dev;
+
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
+ task->task_state_flags &=
+ ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
+
+ memset(ts, 0, sizeof(*ts));
+ ts->resp = SAS_TASK_COMPLETE;
+ if (unlikely(aborted)) {
+ ts->stat = SAS_ABORTED_TASK;
+ hisi_sas_slot_task_free(hisi_hba, task, slot);
+ return -1;
+ }
+
+ if (unlikely(!sas_dev)) {
+ dev_dbg(dev, "slot complete: port has not device\n");
+ ts->stat = SAS_PHY_DOWN;
+ goto out;
+ }
+
+ /*
+ * Use SAS+TMF status codes
+ */
+ switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
+ >> CMPLT_HDR_ABORT_STAT_OFF) {
+ case STAT_IO_ABORTED:
+ /* this IO has been aborted by abort command */
+ ts->stat = SAS_ABORTED_TASK;
+ goto out;
+ case STAT_IO_COMPLETE:
+ /* internal abort command complete */
+ ts->stat = TMF_RESP_FUNC_SUCC;
+ goto out;
+ case STAT_IO_NO_DEVICE:
+ ts->stat = TMF_RESP_FUNC_COMPLETE;
+ goto out;
+ case STAT_IO_NOT_VALID:
+ /*
+ * abort single IO, the controller can't find the IO
+ */
+ ts->stat = TMF_RESP_FUNC_FAILED;
+ goto out;
+ default:
+ break;
+ }
+
+ if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3 &&
+ (!(error_info[3] &
+ IO_RX_DATA_LEN_UNDERFLOW_MSK) ||
+ hisi_sas_is_rw_cmd(task))) {
+ if ((complete_hdr->dw0 &
+ CMPLT_HDR_ERROR_PHASE_MSK) == 0x1) {
+ /* error happens on parse DQ entry */
+ dev_dbg(dev, "Error happens on parse DQ entry!\n");
+ } else if ((complete_hdr->dw0 &
+ CMPLT_HDR_ERROR_PHASE_MSK) == 0x80) {
+ /* error happens on ITCT or IOST configuration */
+ dev_dbg(dev, "Error happens on ITCT or IOST configuration!\n");
+ } else {
+ /* error info is recorded in memory*/
+ dev_dbg(dev, "Error info: 0x%x, 0x%x, 0x%x, 0x%x\n",
+ error_info[0], error_info[1],
+ error_info[2], error_info[3]);
+ }
+
+ slot_err_v3_hw(hisi_hba, task, slot);
+ if (unlikely(slot->abort))
+ return ts->stat;
+ goto out;
+ }
+
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ struct ssp_response_iu *iu = slot->status_buffer +
+ sizeof(struct hisi_sas_err_record);
+
+ sas_ssp_task_response(dev, task, iu);
+ break;
+ }
+ case SAS_PROTOCOL_SMP:
+ {
+ struct scatterlist *sg_resp = &task->smp_task.smp_resp;
+ void *to;
+
+ ts->stat = SAM_STAT_GOOD;
+ to = kmap_atomic(sg_page(sg_resp));
+
+ dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
+ DMA_FROM_DEVICE);
+ dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
+ DMA_TO_DEVICE);
+ memcpy(to + sg_resp->offset,
+ slot->status_buffer +
+ sizeof(struct hisi_sas_err_record),
+ sg_dma_len(sg_resp));
+ kunmap_atomic(to);
+ break;
+ }
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ ts->stat = SAM_STAT_GOOD;
+ hisi_sas_sata_done(task, slot);
+ break;
+ }
+ default:
+ ts->stat = SAM_STAT_CHECK_CONDITION;
+ break;
+ }
+
+ if (!slot->port->port_attached) {
+ dev_err(dev, "slot complete: port %d has removed\n",
+ slot->port->sas_port.id);
+ ts->stat = SAS_PHY_DOWN;
+ }
+
+out:
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ task->task_state_flags |= SAS_TASK_STATE_DONE;
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
+ spin_lock_irqsave(&hisi_hba->lock, flags);
+ hisi_sas_slot_task_free(hisi_hba, task, slot);
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+ sts = ts->stat;
+
+ if (task->task_done)
+ task->task_done(task);
+
+ return sts;
+}
+
+static void cq_tasklet_v3_hw(unsigned long val)
+{
+ struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
+ struct hisi_hba *hisi_hba = cq->hisi_hba;
+ struct hisi_sas_slot *slot;
+ struct hisi_sas_itct *itct;
+ struct hisi_sas_complete_v3_hdr *complete_queue;
+ u32 rd_point = cq->rd_point, wr_point, dev_id;
+ int queue = cq->id;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
+
+ complete_queue = hisi_hba->complete_hdr[queue];
+
+ spin_lock(&dq->lock);
+ wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
+ (0x14 * queue));
+
+ while (rd_point != wr_point) {
+ struct hisi_sas_complete_v3_hdr *complete_hdr;
+ int iptt;
+
+ complete_hdr = &complete_queue[rd_point];
+
+ /* Check for NCQ completion */
+ if (complete_hdr->act) {
+ u32 act_tmp = complete_hdr->act;
+ int ncq_tag_count = ffs(act_tmp);
+
+ dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
+ CMPLT_HDR_DEV_ID_OFF;
+ itct = &hisi_hba->itct[dev_id];
+
+ /* The NCQ tags are held in the itct header */
+ while (ncq_tag_count) {
+ __le64 *ncq_tag = &itct->qw4_15[0];
+
+ ncq_tag_count -= 1;
+ iptt = (ncq_tag[ncq_tag_count / 5]
+ >> (ncq_tag_count % 5) * 12) & 0xfff;
+
+ slot = &hisi_hba->slot_info[iptt];
+ slot->cmplt_queue_slot = rd_point;
+ slot->cmplt_queue = queue;
+ slot_complete_v3_hw(hisi_hba, slot);
+
+ act_tmp &= ~(1 << ncq_tag_count);
+ ncq_tag_count = ffs(act_tmp);
+ }
+ } else {
+ iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
+ slot = &hisi_hba->slot_info[iptt];
+ slot->cmplt_queue_slot = rd_point;
+ slot->cmplt_queue = queue;
+ slot_complete_v3_hw(hisi_hba, slot);
+ }
+
+ if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
+ rd_point = 0;
+ }
+
+ /* update rd_point */
+ cq->rd_point = rd_point;
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
+ spin_unlock(&dq->lock);
+}
+
+static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
+{
+ struct hisi_sas_cq *cq = p;
+ struct hisi_hba *hisi_hba = cq->hisi_hba;
+ int queue = cq->id;
+
+ hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
+
+ tasklet_schedule(&cq->tasklet);
+
+ return IRQ_HANDLED;
+}
+
static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
int_phy_up_down_bcast_v3_hw,
int_chnl_int_v3_hw,
@@ -670,6 +979,29 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
}
}
+ for (i = 0; i < hisi_hba->queue_count; i++) {
+ int idx = i + 16; /* First cq interrupt is irq16 */
+ struct hisi_sas_cq *cq = &hisi_hba->cq[i];
+ struct tasklet_struct *t = &cq->tasklet;
+
+ irq = msi_vectors[idx];
+ if (!irq) {
+ dev_err(dev,
+ "irq init: could not map cq interrupt %d\n",
+ idx);
+ return -ENOENT;
+ }
+ rc = devm_request_irq(dev, irq, cq_interrupt_v3_hw, 0,
+ DRV_NAME " cq", &hisi_hba->cq[i]);
+ if (rc) {
+ dev_err(dev,
+ "irq init: could not request cq interrupt %d, rc=%d\n",
+ irq, rc);
+ return -ENOENT;
+ }
+ tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
+ }
+
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 13/22] scsi: hisi_sas: add v3 cq interrupt handler
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add v3 cq interrupt handler.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
drivers/scsi/hisi_sas/hisi_sas_main.c | 32 ++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 332 +++++++++++++++++++++++++++++++++
3 files changed, 365 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index 9fd874d..c7d1144 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -385,6 +385,7 @@ extern int hisi_sas_pci_probe(struct pci_dev *pdev,
extern void hisi_sas_sata_done(struct sas_task *task,
struct hisi_sas_slot *slot);
extern int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag);
+extern bool hisi_sas_is_rw_cmd(struct sas_task *task);
extern int hisi_sas_probe(struct platform_device *pdev,
const struct hisi_sas_hw *ops);
extern int hisi_sas_remove(struct platform_device *pdev);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 33bd3c45..156b66b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -118,6 +118,38 @@ int hisi_sas_get_ncq_tag(struct sas_task *task, u32 *tag)
}
EXPORT_SYMBOL_GPL(hisi_sas_get_ncq_tag);
+bool hisi_sas_is_rw_cmd(struct sas_task *task)
+{
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ unsigned char op = task->ssp_task.cmd->cmnd[0];
+
+ if (op == READ_6 || op == WRITE_6 ||
+ op == READ_10 || op == WRITE_10 ||
+ op == READ_12 || op == WRITE_12 ||
+ op == READ_16 || op == WRITE_16)
+ return true;
+ break;
+ }
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ u32 cmd_proto = hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command,
+ task->data_dir);
+ if (cmd_proto != SATA_PROTOCOL_NONDATA)
+ return true;
+ break;
+ }
+ default:
+ break;
+ }
+ return false;
+}
+EXPORT_SYMBOL_GPL(hisi_sas_is_rw_cmd);
+
static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
{
return device->port->ha->lldd_ha;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index f7872c5..b33781b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -156,6 +156,33 @@
#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+
+/* Completion header */
+/* dw0 */
+#define CMPLT_HDR_CMPLT_OFF 0
+#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
+#define CMPLT_HDR_ERROR_PHASE_OFF 2
+#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
+#define CMPLT_HDR_RSPNS_XFRD_OFF 10
+#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
+#define CMPLT_HDR_ERX_OFF 12
+#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
+#define CMPLT_HDR_ABORT_STAT_OFF 13
+#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
+/* abort_stat */
+#define STAT_IO_NOT_VALID 0x1
+#define STAT_IO_NO_DEVICE 0x2
+#define STAT_IO_COMPLETE 0x3
+#define STAT_IO_ABORTED 0x4
+/* dw1 */
+#define CMPLT_HDR_IPTT_OFF 0
+#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
+#define CMPLT_HDR_DEV_ID_OFF 16
+#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
+/* dw3 */
+#define CMPLT_HDR_IO_IN_TARGET_OFF 17
+#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -163,6 +190,8 @@ struct hisi_sas_complete_v3_hdr {
__le32 dw3;
};
+#define IO_RX_DATA_LEN_UNDERFLOW_OFF 6
+#define IO_RX_DATA_LEN_UNDERFLOW_MSK (1 << IO_RX_DATA_LEN_UNDERFLOW_OFF)
#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
#define HISI_SAS_MSI_COUNT_V3_HW 32
@@ -624,6 +653,286 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
return IRQ_HANDLED;
}
+static void slot_err_v3_hw(struct hisi_hba *hisi_hba,
+ struct sas_task *task,
+ struct hisi_sas_slot *slot)
+{
+ struct task_status_struct *ts = &task->task_status;
+ struct hisi_sas_complete_v3_hdr *complete_queue =
+ hisi_hba->complete_hdr[slot->cmplt_queue];
+ struct hisi_sas_complete_v3_hdr *complete_hdr =
+ &complete_queue[slot->cmplt_queue_slot];
+
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_QUEUE_FULL;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ }
+ break;
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+ ts->stat = SAS_PHY_DOWN;
+ slot->abort = 1;
+ } else {
+ ts->stat = SAS_OPEN_REJECT;
+ ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
+ }
+ hisi_sas_sata_done(task, slot);
+ }
+ break;
+ case SAS_PROTOCOL_SMP:
+ ts->stat = SAM_STAT_CHECK_CONDITION;
+ break;
+ default:
+ break;
+ }
+}
+
+static int
+slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_device *sas_dev;
+ struct device *dev = hisi_hba->dev;
+ struct task_status_struct *ts;
+ struct domain_device *device;
+ enum exec_status sts;
+ u32 *error_info = slot->status_buffer;
+ struct hisi_sas_complete_v3_hdr *complete_queue =
+ hisi_hba->complete_hdr[slot->cmplt_queue];
+ struct hisi_sas_complete_v3_hdr *complete_hdr =
+ &complete_queue[slot->cmplt_queue_slot];
+ int aborted;
+ unsigned long flags;
+
+ if (unlikely(!task || !task->lldd_task || !task->dev))
+ return -EINVAL;
+
+ ts = &task->task_status;
+ device = task->dev;
+ sas_dev = device->lldd_dev;
+
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
+ task->task_state_flags &=
+ ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
+
+ memset(ts, 0, sizeof(*ts));
+ ts->resp = SAS_TASK_COMPLETE;
+ if (unlikely(aborted)) {
+ ts->stat = SAS_ABORTED_TASK;
+ hisi_sas_slot_task_free(hisi_hba, task, slot);
+ return -1;
+ }
+
+ if (unlikely(!sas_dev)) {
+ dev_dbg(dev, "slot complete: port has not device\n");
+ ts->stat = SAS_PHY_DOWN;
+ goto out;
+ }
+
+ /*
+ * Use SAS+TMF status codes
+ */
+ switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
+ >> CMPLT_HDR_ABORT_STAT_OFF) {
+ case STAT_IO_ABORTED:
+ /* this IO has been aborted by abort command */
+ ts->stat = SAS_ABORTED_TASK;
+ goto out;
+ case STAT_IO_COMPLETE:
+ /* internal abort command complete */
+ ts->stat = TMF_RESP_FUNC_SUCC;
+ goto out;
+ case STAT_IO_NO_DEVICE:
+ ts->stat = TMF_RESP_FUNC_COMPLETE;
+ goto out;
+ case STAT_IO_NOT_VALID:
+ /*
+ * abort single IO, the controller can't find the IO
+ */
+ ts->stat = TMF_RESP_FUNC_FAILED;
+ goto out;
+ default:
+ break;
+ }
+
+ if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3 &&
+ (!(error_info[3] &
+ IO_RX_DATA_LEN_UNDERFLOW_MSK) ||
+ hisi_sas_is_rw_cmd(task))) {
+ if ((complete_hdr->dw0 &
+ CMPLT_HDR_ERROR_PHASE_MSK) == 0x1) {
+ /* error happens on parse DQ entry */
+ dev_dbg(dev, "Error happens on parse DQ entry!\n");
+ } else if ((complete_hdr->dw0 &
+ CMPLT_HDR_ERROR_PHASE_MSK) == 0x80) {
+ /* error happens on ITCT or IOST configuration */
+ dev_dbg(dev, "Error happens on ITCT or IOST configuration!\n");
+ } else {
+ /* error info is recorded in memory*/
+ dev_dbg(dev, "Error info: 0x%x, 0x%x, 0x%x, 0x%x\n",
+ error_info[0], error_info[1],
+ error_info[2], error_info[3]);
+ }
+
+ slot_err_v3_hw(hisi_hba, task, slot);
+ if (unlikely(slot->abort))
+ return ts->stat;
+ goto out;
+ }
+
+ switch (task->task_proto) {
+ case SAS_PROTOCOL_SSP:
+ {
+ struct ssp_response_iu *iu = slot->status_buffer +
+ sizeof(struct hisi_sas_err_record);
+
+ sas_ssp_task_response(dev, task, iu);
+ break;
+ }
+ case SAS_PROTOCOL_SMP:
+ {
+ struct scatterlist *sg_resp = &task->smp_task.smp_resp;
+ void *to;
+
+ ts->stat = SAM_STAT_GOOD;
+ to = kmap_atomic(sg_page(sg_resp));
+
+ dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
+ DMA_FROM_DEVICE);
+ dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
+ DMA_TO_DEVICE);
+ memcpy(to + sg_resp->offset,
+ slot->status_buffer +
+ sizeof(struct hisi_sas_err_record),
+ sg_dma_len(sg_resp));
+ kunmap_atomic(to);
+ break;
+ }
+ case SAS_PROTOCOL_SATA:
+ case SAS_PROTOCOL_STP:
+ case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
+ {
+ ts->stat = SAM_STAT_GOOD;
+ hisi_sas_sata_done(task, slot);
+ break;
+ }
+ default:
+ ts->stat = SAM_STAT_CHECK_CONDITION;
+ break;
+ }
+
+ if (!slot->port->port_attached) {
+ dev_err(dev, "slot complete: port %d has removed\n",
+ slot->port->sas_port.id);
+ ts->stat = SAS_PHY_DOWN;
+ }
+
+out:
+ spin_lock_irqsave(&task->task_state_lock, flags);
+ task->task_state_flags |= SAS_TASK_STATE_DONE;
+ spin_unlock_irqrestore(&task->task_state_lock, flags);
+ spin_lock_irqsave(&hisi_hba->lock, flags);
+ hisi_sas_slot_task_free(hisi_hba, task, slot);
+ spin_unlock_irqrestore(&hisi_hba->lock, flags);
+ sts = ts->stat;
+
+ if (task->task_done)
+ task->task_done(task);
+
+ return sts;
+}
+
+static void cq_tasklet_v3_hw(unsigned long val)
+{
+ struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
+ struct hisi_hba *hisi_hba = cq->hisi_hba;
+ struct hisi_sas_slot *slot;
+ struct hisi_sas_itct *itct;
+ struct hisi_sas_complete_v3_hdr *complete_queue;
+ u32 rd_point = cq->rd_point, wr_point, dev_id;
+ int queue = cq->id;
+ struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
+
+ complete_queue = hisi_hba->complete_hdr[queue];
+
+ spin_lock(&dq->lock);
+ wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
+ (0x14 * queue));
+
+ while (rd_point != wr_point) {
+ struct hisi_sas_complete_v3_hdr *complete_hdr;
+ int iptt;
+
+ complete_hdr = &complete_queue[rd_point];
+
+ /* Check for NCQ completion */
+ if (complete_hdr->act) {
+ u32 act_tmp = complete_hdr->act;
+ int ncq_tag_count = ffs(act_tmp);
+
+ dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
+ CMPLT_HDR_DEV_ID_OFF;
+ itct = &hisi_hba->itct[dev_id];
+
+ /* The NCQ tags are held in the itct header */
+ while (ncq_tag_count) {
+ __le64 *ncq_tag = &itct->qw4_15[0];
+
+ ncq_tag_count -= 1;
+ iptt = (ncq_tag[ncq_tag_count / 5]
+ >> (ncq_tag_count % 5) * 12) & 0xfff;
+
+ slot = &hisi_hba->slot_info[iptt];
+ slot->cmplt_queue_slot = rd_point;
+ slot->cmplt_queue = queue;
+ slot_complete_v3_hw(hisi_hba, slot);
+
+ act_tmp &= ~(1 << ncq_tag_count);
+ ncq_tag_count = ffs(act_tmp);
+ }
+ } else {
+ iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
+ slot = &hisi_hba->slot_info[iptt];
+ slot->cmplt_queue_slot = rd_point;
+ slot->cmplt_queue = queue;
+ slot_complete_v3_hw(hisi_hba, slot);
+ }
+
+ if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
+ rd_point = 0;
+ }
+
+ /* update rd_point */
+ cq->rd_point = rd_point;
+ hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
+ spin_unlock(&dq->lock);
+}
+
+static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
+{
+ struct hisi_sas_cq *cq = p;
+ struct hisi_hba *hisi_hba = cq->hisi_hba;
+ int queue = cq->id;
+
+ hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
+
+ tasklet_schedule(&cq->tasklet);
+
+ return IRQ_HANDLED;
+}
+
static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
int_phy_up_down_bcast_v3_hw,
int_chnl_int_v3_hw,
@@ -670,6 +979,29 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
}
}
+ for (i = 0; i < hisi_hba->queue_count; i++) {
+ int idx = i + 16; /* First cq interrupt is irq16 */
+ struct hisi_sas_cq *cq = &hisi_hba->cq[i];
+ struct tasklet_struct *t = &cq->tasklet;
+
+ irq = msi_vectors[idx];
+ if (!irq) {
+ dev_err(dev,
+ "irq init: could not map cq interrupt %d\n",
+ idx);
+ return -ENOENT;
+ }
+ rc = devm_request_irq(dev, irq, cq_interrupt_v3_hw, 0,
+ DRV_NAME " cq", &hisi_hba->cq[i]);
+ if (rc) {
+ dev_err(dev,
+ "irq init: could not request cq interrupt %d, rc=%d\n",
+ irq, rc);
+ return -ENOENT;
+ }
+ tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
+ }
+
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 14/22] scsi: hisi_sas: add v3 code to send SSP frame
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare SSP frame and deliver it to hardware.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 209 +++++++++++++++++++++++++++++++++
1 file changed, 209 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index b33781b..77616ff 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -157,6 +157,41 @@
#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+/* HW dma structures */
+/* Delivery queue header */
+/* dw0 */
+#define CMD_HDR_RESP_REPORT_OFF 5
+#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
+#define CMD_HDR_TLR_CTRL_OFF 6
+#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
+#define CMD_HDR_PORT_OFF 18
+#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
+#define CMD_HDR_PRIORITY_OFF 27
+#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
+#define CMD_HDR_CMD_OFF 29
+#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
+/* dw1 */
+#define CMD_HDR_DIR_OFF 5
+#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_VDTL_OFF 10
+#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
+#define CMD_HDR_FRAME_TYPE_OFF 11
+#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
+#define CMD_HDR_DEV_ID_OFF 16
+#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
+/* dw2 */
+#define CMD_HDR_CFL_OFF 0
+#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_MRFL_OFF 15
+#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
+#define CMD_HDR_SG_MOD_OFF 24
+#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw6 */
+#define CMD_HDR_DIF_SGL_LEN_OFF 0
+#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
+#define CMD_HDR_DATA_SGL_LEN_OFF 16
+#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
+
/* Completion header */
/* dw0 */
#define CMPLT_HDR_CMPLT_OFF 0
@@ -201,6 +236,11 @@ enum {
HISI_SAS_PHY_INT_NR
};
+#define DIR_NO_DATA 0
+#define DIR_TO_INI 1
+#define DIR_TO_DEVICE 2
+#define DIR_RESERVED 3
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -208,6 +248,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
return readl(regs);
}
+static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl_relaxed(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -432,6 +479,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+/**
+ * The callpath to this function and upto writing the write
+ * queue pointer should be safe from interruption.
+ */
+static int
+get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
+{
+ struct device *dev = hisi_hba->dev;
+ int queue = dq->id;
+ u32 r, w;
+
+ w = dq->wr_point;
+ r = hisi_sas_read32_relaxed(hisi_hba,
+ DLVRY_Q_0_RD_PTR + (queue * 0x14));
+ if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
+ dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
+ queue, r, w);
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
+{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
+
+ dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
+ dq->wr_point);
+}
+
+static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ struct hisi_sas_cmd_hdr *hdr,
+ struct scatterlist *scatter,
+ int n_elem)
+{
+ struct device *dev = hisi_hba->dev;
+ struct scatterlist *sg;
+ int i;
+
+ if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
+ dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
+ n_elem);
+ return -EINVAL;
+ }
+
+ slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
+ &slot->sge_page_dma);
+ if (!slot->sge_page)
+ return -ENOMEM;
+
+ for_each_sg(scatter, sg, n_elem, i) {
+ struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
+
+ entry->addr = cpu_to_le64(sg_dma_address(sg));
+ entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
+ entry->data_len = cpu_to_le32(sg_dma_len(sg));
+ entry->data_off = 0;
+ }
+
+ hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
+ hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
+
+ return 0;
+}
+
+static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot, int is_tmf,
+ struct hisi_sas_tmf_task *tmf)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct domain_device *device = task->dev;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ struct hisi_sas_port *port = slot->port;
+ struct sas_ssp_task *ssp_task = &task->ssp_task;
+ struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
+ int has_data = 0, rc, priority = is_tmf;
+ u8 *buf_cmd;
+ u32 dw1 = 0, dw2 = 0;
+
+ hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
+ (2 << CMD_HDR_TLR_CTRL_OFF) |
+ (port->id << CMD_HDR_PORT_OFF) |
+ (priority << CMD_HDR_PRIORITY_OFF) |
+ (1 << CMD_HDR_CMD_OFF)); /* ssp */
+
+ dw1 = 1 << CMD_HDR_VDTL_OFF;
+ if (is_tmf) {
+ dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
+ dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
+ } else {
+ dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
+ switch (scsi_cmnd->sc_data_direction) {
+ case DMA_TO_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
+ break;
+ case DMA_FROM_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
+ break;
+ default:
+ dw1 &= ~CMD_HDR_DIR_MSK;
+ }
+ }
+
+ /* map itct entry */
+ dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
+ hdr->dw1 = cpu_to_le32(dw1);
+
+ dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
+ + 3) / 4) << CMD_HDR_CFL_OFF) |
+ ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
+ (2 << CMD_HDR_SG_MOD_OFF);
+ hdr->dw2 = cpu_to_le32(dw2);
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ if (has_data) {
+ rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
+ slot->n_elem);
+ if (rc)
+ return rc;
+ }
+
+ hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+ hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
+ memcpy(buf_cmd, ssp_task->LUN, 8);
+
+ if (!is_tmf) {
+ buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
+ memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
+ } else {
+ buf_cmd[10] = tmf->tmf;
+ switch (tmf->tmf) {
+ case TMF_ABORT_TASK:
+ case TMF_QUERY_TASK:
+ buf_cmd[12] =
+ (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
+ buf_cmd[13] =
+ tmf->tag_of_task_to_be_managed & 0xff;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1020,11 +1224,16 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
return 0;
}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .prep_ssp = prep_ssp_v3_hw,
+ .get_free_slot = get_free_slot_v3_hw,
+ .start_delivery = start_delivery_v3_hw,
+ .slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
};
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 14/22] scsi: hisi_sas: add v3 code to send SSP frame
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare SSP frame and deliver it to hardware.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 209 +++++++++++++++++++++++++++++++++
1 file changed, 209 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index b33781b..77616ff 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -157,6 +157,41 @@
#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
+/* HW dma structures */
+/* Delivery queue header */
+/* dw0 */
+#define CMD_HDR_RESP_REPORT_OFF 5
+#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
+#define CMD_HDR_TLR_CTRL_OFF 6
+#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
+#define CMD_HDR_PORT_OFF 18
+#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
+#define CMD_HDR_PRIORITY_OFF 27
+#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
+#define CMD_HDR_CMD_OFF 29
+#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
+/* dw1 */
+#define CMD_HDR_DIR_OFF 5
+#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_VDTL_OFF 10
+#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
+#define CMD_HDR_FRAME_TYPE_OFF 11
+#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
+#define CMD_HDR_DEV_ID_OFF 16
+#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
+/* dw2 */
+#define CMD_HDR_CFL_OFF 0
+#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_MRFL_OFF 15
+#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
+#define CMD_HDR_SG_MOD_OFF 24
+#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw6 */
+#define CMD_HDR_DIF_SGL_LEN_OFF 0
+#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
+#define CMD_HDR_DATA_SGL_LEN_OFF 16
+#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
+
/* Completion header */
/* dw0 */
#define CMPLT_HDR_CMPLT_OFF 0
@@ -201,6 +236,11 @@ enum {
HISI_SAS_PHY_INT_NR
};
+#define DIR_NO_DATA 0
+#define DIR_TO_INI 1
+#define DIR_TO_DEVICE 2
+#define DIR_RESERVED 3
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -208,6 +248,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
return readl(regs);
}
+static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
+{
+ void __iomem *regs = hisi_hba->regs + off;
+
+ return readl_relaxed(regs);
+}
+
static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -432,6 +479,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+/**
+ * The callpath to this function and upto writing the write
+ * queue pointer should be safe from interruption.
+ */
+static int
+get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
+{
+ struct device *dev = hisi_hba->dev;
+ int queue = dq->id;
+ u32 r, w;
+
+ w = dq->wr_point;
+ r = hisi_sas_read32_relaxed(hisi_hba,
+ DLVRY_Q_0_RD_PTR + (queue * 0x14));
+ if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
+ dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
+ queue, r, w);
+ return -EAGAIN;
+ }
+
+ return 0;
+}
+
+static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
+{
+ struct hisi_hba *hisi_hba = dq->hisi_hba;
+ int dlvry_queue = dq->slot_prep->dlvry_queue;
+ int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
+
+ dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
+ hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
+ dq->wr_point);
+}
+
+static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ struct hisi_sas_cmd_hdr *hdr,
+ struct scatterlist *scatter,
+ int n_elem)
+{
+ struct device *dev = hisi_hba->dev;
+ struct scatterlist *sg;
+ int i;
+
+ if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
+ dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
+ n_elem);
+ return -EINVAL;
+ }
+
+ slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
+ &slot->sge_page_dma);
+ if (!slot->sge_page)
+ return -ENOMEM;
+
+ for_each_sg(scatter, sg, n_elem, i) {
+ struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
+
+ entry->addr = cpu_to_le64(sg_dma_address(sg));
+ entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
+ entry->data_len = cpu_to_le32(sg_dma_len(sg));
+ entry->data_off = 0;
+ }
+
+ hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
+ hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
+
+ return 0;
+}
+
+static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot, int is_tmf,
+ struct hisi_sas_tmf_task *tmf)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct domain_device *device = task->dev;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ struct hisi_sas_port *port = slot->port;
+ struct sas_ssp_task *ssp_task = &task->ssp_task;
+ struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
+ int has_data = 0, rc, priority = is_tmf;
+ u8 *buf_cmd;
+ u32 dw1 = 0, dw2 = 0;
+
+ hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
+ (2 << CMD_HDR_TLR_CTRL_OFF) |
+ (port->id << CMD_HDR_PORT_OFF) |
+ (priority << CMD_HDR_PRIORITY_OFF) |
+ (1 << CMD_HDR_CMD_OFF)); /* ssp */
+
+ dw1 = 1 << CMD_HDR_VDTL_OFF;
+ if (is_tmf) {
+ dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
+ dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
+ } else {
+ dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
+ switch (scsi_cmnd->sc_data_direction) {
+ case DMA_TO_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
+ break;
+ case DMA_FROM_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
+ break;
+ default:
+ dw1 &= ~CMD_HDR_DIR_MSK;
+ }
+ }
+
+ /* map itct entry */
+ dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
+ hdr->dw1 = cpu_to_le32(dw1);
+
+ dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
+ + 3) / 4) << CMD_HDR_CFL_OFF) |
+ ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
+ (2 << CMD_HDR_SG_MOD_OFF);
+ hdr->dw2 = cpu_to_le32(dw2);
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ if (has_data) {
+ rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
+ slot->n_elem);
+ if (rc)
+ return rc;
+ }
+
+ hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+ hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
+ memcpy(buf_cmd, ssp_task->LUN, 8);
+
+ if (!is_tmf) {
+ buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
+ memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
+ } else {
+ buf_cmd[10] = tmf->tmf;
+ switch (tmf->tmf) {
+ case TMF_ABORT_TASK:
+ case TMF_QUERY_TASK:
+ buf_cmd[12] =
+ (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
+ buf_cmd[13] =
+ tmf->tag_of_task_to_be_managed & 0xff;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1020,11 +1224,16 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
return 0;
}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .prep_ssp = prep_ssp_v3_hw,
+ .get_free_slot = get_free_slot_v3_hw,
+ .start_delivery = start_delivery_v3_hw,
+ .slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
};
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 15/22] scsi: hisi_sas: add v3 code to send SMP frame
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare SMP frame.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 77616ff..396bb4c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -186,6 +186,9 @@
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw3 */
+#define CMD_HDR_IPTT_OFF 0
+#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
/* dw6 */
#define CMD_HDR_DIF_SGL_LEN_OFF 0
#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
@@ -636,6 +639,76 @@ static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct domain_device *device = task->dev;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_port *port = slot->port;
+ struct scatterlist *sg_req, *sg_resp;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ dma_addr_t req_dma_addr;
+ unsigned int req_len, resp_len;
+ int elem, rc;
+
+ /*
+ * DMA-map SMP request, response buffers
+ */
+ /* req */
+ sg_req = &task->smp_task.smp_req;
+ elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
+ if (!elem)
+ return -ENOMEM;
+ req_len = sg_dma_len(sg_req);
+ req_dma_addr = sg_dma_address(sg_req);
+
+ /* resp */
+ sg_resp = &task->smp_task.smp_resp;
+ elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
+ if (!elem) {
+ rc = -ENOMEM;
+ goto err_out_req;
+ }
+ resp_len = sg_dma_len(sg_resp);
+ if ((req_len & 0x3) || (resp_len & 0x3)) {
+ rc = -EINVAL;
+ goto err_out_resp;
+ }
+
+ /* create header */
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
+ (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
+ (2 << CMD_HDR_CMD_OFF)); /* smp */
+
+ /* map itct entry */
+ hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
+ (1 << CMD_HDR_FRAME_TYPE_OFF) |
+ (DIR_NO_DATA << CMD_HDR_DIR_OFF));
+
+ /* dw2 */
+ hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
+ (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
+ CMD_HDR_MRFL_OFF));
+
+ hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
+
+ hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ return 0;
+
+err_out_resp:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
+ DMA_FROM_DEVICE);
+err_out_req:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
+ DMA_TO_DEVICE);
+ return rc;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1231,6 +1304,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.prep_ssp = prep_ssp_v3_hw,
+ .prep_smp = prep_smp_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 15/22] scsi: hisi_sas: add v3 code to send SMP frame
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare SMP frame.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 77616ff..396bb4c 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -186,6 +186,9 @@
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
+/* dw3 */
+#define CMD_HDR_IPTT_OFF 0
+#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
/* dw6 */
#define CMD_HDR_DIF_SGL_LEN_OFF 0
#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
@@ -636,6 +639,76 @@ static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct domain_device *device = task->dev;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_port *port = slot->port;
+ struct scatterlist *sg_req, *sg_resp;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ dma_addr_t req_dma_addr;
+ unsigned int req_len, resp_len;
+ int elem, rc;
+
+ /*
+ * DMA-map SMP request, response buffers
+ */
+ /* req */
+ sg_req = &task->smp_task.smp_req;
+ elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
+ if (!elem)
+ return -ENOMEM;
+ req_len = sg_dma_len(sg_req);
+ req_dma_addr = sg_dma_address(sg_req);
+
+ /* resp */
+ sg_resp = &task->smp_task.smp_resp;
+ elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
+ if (!elem) {
+ rc = -ENOMEM;
+ goto err_out_req;
+ }
+ resp_len = sg_dma_len(sg_resp);
+ if ((req_len & 0x3) || (resp_len & 0x3)) {
+ rc = -EINVAL;
+ goto err_out_resp;
+ }
+
+ /* create header */
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
+ (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
+ (2 << CMD_HDR_CMD_OFF)); /* smp */
+
+ /* map itct entry */
+ hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
+ (1 << CMD_HDR_FRAME_TYPE_OFF) |
+ (DIR_NO_DATA << CMD_HDR_DIR_OFF));
+
+ /* dw2 */
+ hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
+ (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
+ CMD_HDR_MRFL_OFF));
+
+ hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
+
+ hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ return 0;
+
+err_out_resp:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
+ DMA_FROM_DEVICE);
+err_out_req:
+ dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
+ DMA_TO_DEVICE);
+ return rc;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1231,6 +1304,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.prep_ssp = prep_ssp_v3_hw,
+ .prep_smp = prep_smp_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 16/22] scsi: hisi_sas: add v3 code to send ATA frame
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare ATA frame for v3 hw
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 106 +++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 396bb4c..976c6e6 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -171,8 +171,11 @@
#define CMD_HDR_CMD_OFF 29
#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
/* dw1 */
+#define CMD_HDR_UNCON_CMD_OFF 3
#define CMD_HDR_DIR_OFF 5
#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_RESET_OFF 7
+#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
#define CMD_HDR_VDTL_OFF 10
#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
#define CMD_HDR_FRAME_TYPE_OFF 11
@@ -182,6 +185,8 @@
/* dw2 */
#define CMD_HDR_CFL_OFF 0
#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_NCQ_TAG_OFF 10
+#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
#define CMD_HDR_MRFL_OFF 15
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
@@ -244,6 +249,11 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
+#define CMD_IS_UNCONSTRAINT(cmd) \
+ ((cmd == ATA_CMD_READ_LOG_EXT) || \
+ (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
+ (cmd == ATA_CMD_DEV_RESET))
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -709,6 +719,101 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
return rc;
}
+static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *device = task->dev;
+ struct domain_device *parent_dev = device->parent;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+ u8 *buf_cmd;
+ int has_data = 0, rc = 0, hdr_tag = 0;
+ u32 dw1 = 0, dw2 = 0;
+
+ hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
+ else
+ hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
+
+ switch (task->data_dir) {
+ case DMA_TO_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
+ break;
+ case DMA_FROM_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
+ break;
+ default:
+ dw1 &= ~CMD_HDR_DIR_MSK;
+ }
+
+ if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
+ (task->ata_task.fis.control & ATA_SRST))
+ dw1 |= 1 << CMD_HDR_RESET_OFF;
+
+ dw1 |= (hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command, task->data_dir))
+ << CMD_HDR_FRAME_TYPE_OFF;
+ dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
+
+ if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
+ dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
+
+ hdr->dw1 = cpu_to_le32(dw1);
+
+ /* dw2 */
+ if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
+ task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
+ dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
+ }
+
+ dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
+ 2 << CMD_HDR_SG_MOD_OFF;
+ hdr->dw2 = cpu_to_le32(dw2);
+
+ /* dw3 */
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ if (has_data) {
+ rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
+ slot->n_elem);
+ if (rc)
+ return rc;
+ }
+
+ hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+ hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ buf_cmd = slot->command_table;
+
+ if (likely(!task->ata_task.device_control_reg_update))
+ task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
+ /* fill in command FIS */
+ memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1305,6 +1410,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
+ .prep_stp = prep_ata_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 16/22] scsi: hisi_sas: add v3 code to send ATA frame
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare ATA frame for v3 hw
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 106 +++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 396bb4c..976c6e6 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -171,8 +171,11 @@
#define CMD_HDR_CMD_OFF 29
#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
/* dw1 */
+#define CMD_HDR_UNCON_CMD_OFF 3
#define CMD_HDR_DIR_OFF 5
#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
+#define CMD_HDR_RESET_OFF 7
+#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
#define CMD_HDR_VDTL_OFF 10
#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
#define CMD_HDR_FRAME_TYPE_OFF 11
@@ -182,6 +185,8 @@
/* dw2 */
#define CMD_HDR_CFL_OFF 0
#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
+#define CMD_HDR_NCQ_TAG_OFF 10
+#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
#define CMD_HDR_MRFL_OFF 15
#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF 24
@@ -244,6 +249,11 @@ enum {
#define DIR_TO_DEVICE 2
#define DIR_RESERVED 3
+#define CMD_IS_UNCONSTRAINT(cmd) \
+ ((cmd == ATA_CMD_READ_LOG_EXT) || \
+ (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
+ (cmd == ATA_CMD_DEV_RESET))
+
static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
void __iomem *regs = hisi_hba->regs + off;
@@ -709,6 +719,101 @@ static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
return rc;
}
+static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
+{
+ struct ata_queued_cmd *qc = task->uldd_task;
+
+ if (qc) {
+ if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
+ qc->tf.command == ATA_CMD_FPDMA_READ) {
+ *tag = qc->tag;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *device = task->dev;
+ struct domain_device *parent_dev = device->parent;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+ u8 *buf_cmd;
+ int has_data = 0, rc = 0, hdr_tag = 0;
+ u32 dw1 = 0, dw2 = 0;
+
+ hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
+ else
+ hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
+
+ switch (task->data_dir) {
+ case DMA_TO_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
+ break;
+ case DMA_FROM_DEVICE:
+ has_data = 1;
+ dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
+ break;
+ default:
+ dw1 &= ~CMD_HDR_DIR_MSK;
+ }
+
+ if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
+ (task->ata_task.fis.control & ATA_SRST))
+ dw1 |= 1 << CMD_HDR_RESET_OFF;
+
+ dw1 |= (hisi_sas_get_ata_protocol(
+ task->ata_task.fis.command, task->data_dir))
+ << CMD_HDR_FRAME_TYPE_OFF;
+ dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
+
+ if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
+ dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
+
+ hdr->dw1 = cpu_to_le32(dw1);
+
+ /* dw2 */
+ if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
+ task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
+ dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
+ }
+
+ dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
+ 2 << CMD_HDR_SG_MOD_OFF;
+ hdr->dw2 = cpu_to_le32(dw2);
+
+ /* dw3 */
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ if (has_data) {
+ rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
+ slot->n_elem);
+ if (rc)
+ return rc;
+ }
+
+ hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
+ hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
+ hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
+
+ buf_cmd = slot->command_table;
+
+ if (likely(!task->ata_task.device_control_reg_update))
+ task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
+ /* fill in command FIS */
+ memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1305,6 +1410,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
+ .prep_stp = prep_ata_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 17/22] scsi: hisi_sas: add v3 code for itct setup and free
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code for itct setup and free for v3 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 115 +++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 976c6e6..cbc2640 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -24,6 +24,11 @@
#define PHY_PORT_NUM_MA 0x28
#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG 0x3c
+#define ITCT_CLR 0x44
+#define ITCT_CLR_EN_OFF 16
+#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
+#define ITCT_DEV_OFF 0
+#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
@@ -226,6 +231,27 @@
#define CMPLT_HDR_IO_IN_TARGET_OFF 17
#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+/* ITCT header */
+/* qw0 */
+#define ITCT_HDR_DEV_TYPE_OFF 0
+#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
+#define ITCT_HDR_VALID_OFF 2
+#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
+#define ITCT_HDR_MCR_OFF 5
+#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
+#define ITCT_HDR_VLN_OFF 9
+#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
+#define ITCT_HDR_SMP_TIMEOUT_OFF 16
+#define ITCT_HDR_AWT_CONTINUE_OFF 25
+#define ITCT_HDR_PORT_ID_OFF 28
+#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
+/* qw2 */
+#define ITCT_HDR_INLT_OFF 0
+#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
+#define ITCT_HDR_RTOLT_OFF 48
+#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
+
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -444,6 +470,93 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
__swab32(identify_buffer[5]));
}
+static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_device *sas_dev)
+{
+ struct domain_device *device = sas_dev->sas_device;
+ struct device *dev = hisi_hba->dev;
+ u64 qw0, device_id = sas_dev->device_id;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
+ struct domain_device *parent_dev = device->parent;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+
+ memset(itct, 0, sizeof(*itct));
+
+ /* qw0 */
+ qw0 = 0;
+ switch (sas_dev->dev_type) {
+ case SAS_END_DEVICE:
+ case SAS_EDGE_EXPANDER_DEVICE:
+ case SAS_FANOUT_EXPANDER_DEVICE:
+ qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ case SAS_SATA_DEV:
+ case SAS_SATA_PENDING:
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
+ else
+ qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ default:
+ dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
+ sas_dev->dev_type);
+ }
+
+ qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
+ (device->linkrate << ITCT_HDR_MCR_OFF) |
+ (1 << ITCT_HDR_VLN_OFF) |
+ (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
+ (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
+ (port->id << ITCT_HDR_PORT_ID_OFF));
+ itct->qw0 = cpu_to_le64(qw0);
+
+ /* qw1 */
+ memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+ itct->sas_addr = __swab64(itct->sas_addr);
+
+ /* qw2 */
+ if (!dev_is_sata(device))
+ itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
+ (0x1ULL << ITCT_HDR_RTOLT_OFF));
+}
+
+static void free_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_device *sas_dev)
+{
+ u64 dev_id = sas_dev->device_id;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
+ u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+
+ /* clear the itct interrupt state */
+ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ ENT_INT_SRC3_ITC_INT_MSK);
+
+ /* clear the itct table*/
+ reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
+ reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
+ hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
+
+ udelay(10);
+ reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
+ dev_dbg(dev, "got clear ITCT done interrupt\n");
+
+ /* invalid the itct state*/
+ memset(itct, 0, sizeof(struct hisi_sas_itct));
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ ENT_INT_SRC3_ITC_INT_MSK);
+ hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
+ hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
+
+ /* clear the itct */
+ hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
+ dev_dbg(dev, "clear ITCT ok\n");
+ }
+}
+
static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
{
init_reg_v3_hw(hisi_hba);
@@ -1405,9 +1518,11 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
+ .setup_itct = setup_itct_v3_hw,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .free_device = free_device_v3_hw,
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
.prep_stp = prep_ata_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 17/22] scsi: hisi_sas: add v3 code for itct setup and free
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code for itct setup and free for v3 hw.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 115 +++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 976c6e6..cbc2640 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -24,6 +24,11 @@
#define PHY_PORT_NUM_MA 0x28
#define PHY_CONN_RATE 0x30
#define AXI_AHB_CLK_CFG 0x3c
+#define ITCT_CLR 0x44
+#define ITCT_CLR_EN_OFF 16
+#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
+#define ITCT_DEV_OFF 0
+#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
#define AXI_USER1 0x48
#define AXI_USER2 0x4c
#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
@@ -226,6 +231,27 @@
#define CMPLT_HDR_IO_IN_TARGET_OFF 17
#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
+/* ITCT header */
+/* qw0 */
+#define ITCT_HDR_DEV_TYPE_OFF 0
+#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
+#define ITCT_HDR_VALID_OFF 2
+#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
+#define ITCT_HDR_MCR_OFF 5
+#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
+#define ITCT_HDR_VLN_OFF 9
+#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
+#define ITCT_HDR_SMP_TIMEOUT_OFF 16
+#define ITCT_HDR_AWT_CONTINUE_OFF 25
+#define ITCT_HDR_PORT_ID_OFF 28
+#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
+/* qw2 */
+#define ITCT_HDR_INLT_OFF 0
+#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
+#define ITCT_HDR_RTOLT_OFF 48
+#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
+
+
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
__le32 dw1;
@@ -444,6 +470,93 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
__swab32(identify_buffer[5]));
}
+static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_device *sas_dev)
+{
+ struct domain_device *device = sas_dev->sas_device;
+ struct device *dev = hisi_hba->dev;
+ u64 qw0, device_id = sas_dev->device_id;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
+ struct domain_device *parent_dev = device->parent;
+ struct asd_sas_port *sas_port = device->port;
+ struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+
+ memset(itct, 0, sizeof(*itct));
+
+ /* qw0 */
+ qw0 = 0;
+ switch (sas_dev->dev_type) {
+ case SAS_END_DEVICE:
+ case SAS_EDGE_EXPANDER_DEVICE:
+ case SAS_FANOUT_EXPANDER_DEVICE:
+ qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ case SAS_SATA_DEV:
+ case SAS_SATA_PENDING:
+ if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
+ qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
+ else
+ qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
+ break;
+ default:
+ dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
+ sas_dev->dev_type);
+ }
+
+ qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
+ (device->linkrate << ITCT_HDR_MCR_OFF) |
+ (1 << ITCT_HDR_VLN_OFF) |
+ (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
+ (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
+ (port->id << ITCT_HDR_PORT_ID_OFF));
+ itct->qw0 = cpu_to_le64(qw0);
+
+ /* qw1 */
+ memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+ itct->sas_addr = __swab64(itct->sas_addr);
+
+ /* qw2 */
+ if (!dev_is_sata(device))
+ itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
+ (0x1ULL << ITCT_HDR_RTOLT_OFF));
+}
+
+static void free_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_device *sas_dev)
+{
+ u64 dev_id = sas_dev->device_id;
+ struct device *dev = hisi_hba->dev;
+ struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
+ u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+
+ /* clear the itct interrupt state */
+ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ ENT_INT_SRC3_ITC_INT_MSK);
+
+ /* clear the itct table*/
+ reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
+ reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
+ hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
+
+ udelay(10);
+ reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
+ dev_dbg(dev, "got clear ITCT done interrupt\n");
+
+ /* invalid the itct state*/
+ memset(itct, 0, sizeof(struct hisi_sas_itct));
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ ENT_INT_SRC3_ITC_INT_MSK);
+ hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
+ hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
+
+ /* clear the itct */
+ hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
+ dev_dbg(dev, "clear ITCT ok\n");
+ }
+}
+
static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
{
init_reg_v3_hw(hisi_hba);
@@ -1405,9 +1518,11 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
+ .setup_itct = setup_itct_v3_hw,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
+ .free_device = free_device_v3_hw,
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
.prep_stp = prep_ata_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 18/22] scsi: hisi_sas: add v3 code to send internal abort command
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare internal abort command.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index cbc2640..9d5047e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -165,6 +165,10 @@
/* HW dma structures */
/* Delivery queue header */
/* dw0 */
+#define CMD_HDR_ABORT_FLAG_OFF 0
+#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
+#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
+#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
#define CMD_HDR_RESP_REPORT_OFF 5
#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
#define CMD_HDR_TLR_CTRL_OFF 6
@@ -204,6 +208,11 @@
#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
#define CMD_HDR_DATA_SGL_LEN_OFF 16
#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
+/* dw7 */
+#define CMD_HDR_ADDR_MODE_SEL_OFF 15
+#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
+#define CMD_HDR_ABORT_IPTT_OFF 16
+#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
/* Completion header */
/* dw0 */
@@ -927,6 +936,34 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ int device_id, int abort_flag, int tag_to_abort)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *dev = task->dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct hisi_sas_port *port = slot->port;
+
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
+ (port->id << CMD_HDR_PORT_OFF) |
+ ((dev_is_sata(dev) ? 1:0)
+ << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
+ (abort_flag
+ << CMD_HDR_ABORT_FLAG_OFF));
+
+ /* dw1 */
+ hdr->dw1 = cpu_to_le32(device_id
+ << CMD_HDR_DEV_ID_OFF);
+
+ /* dw7 */
+ hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1526,6 +1563,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
.prep_stp = prep_ata_v3_hw,
+ .prep_abort = prep_abort_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 18/22] scsi: hisi_sas: add v3 code to send internal abort command
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to prepare internal abort command.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index cbc2640..9d5047e 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -165,6 +165,10 @@
/* HW dma structures */
/* Delivery queue header */
/* dw0 */
+#define CMD_HDR_ABORT_FLAG_OFF 0
+#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
+#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
+#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
#define CMD_HDR_RESP_REPORT_OFF 5
#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
#define CMD_HDR_TLR_CTRL_OFF 6
@@ -204,6 +208,11 @@
#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
#define CMD_HDR_DATA_SGL_LEN_OFF 16
#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
+/* dw7 */
+#define CMD_HDR_ADDR_MODE_SEL_OFF 15
+#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
+#define CMD_HDR_ABORT_IPTT_OFF 16
+#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
/* Completion header */
/* dw0 */
@@ -927,6 +936,34 @@ static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
return 0;
}
+static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
+ struct hisi_sas_slot *slot,
+ int device_id, int abort_flag, int tag_to_abort)
+{
+ struct sas_task *task = slot->task;
+ struct domain_device *dev = task->dev;
+ struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
+ struct hisi_sas_port *port = slot->port;
+
+ /* dw0 */
+ hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
+ (port->id << CMD_HDR_PORT_OFF) |
+ ((dev_is_sata(dev) ? 1:0)
+ << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
+ (abort_flag
+ << CMD_HDR_ABORT_FLAG_OFF));
+
+ /* dw1 */
+ hdr->dw1 = cpu_to_le32(device_id
+ << CMD_HDR_DEV_ID_OFF);
+
+ /* dw7 */
+ hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
+ hdr->transfer_tags = cpu_to_le32(slot->idx);
+
+ return 0;
+}
+
static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
{
int i, res = 0;
@@ -1526,6 +1563,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.prep_ssp = prep_ssp_v3_hw,
.prep_smp = prep_smp_v3_hw,
.prep_stp = prep_ata_v3_hw,
+ .prep_abort = prep_abort_v3_hw,
.get_free_slot = get_free_slot_v3_hw,
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 19/22] scsi: hisi_sas: add get_wideport_bitmap_v3_hw()
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code for interface get_wide_port_bitmap_v3_hw().
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 9d5047e..fa686e5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -614,6 +614,18 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
+{
+ int i, bitmap = 0;
+ u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+
+ for (i = 0; i < hisi_hba->n_phy; i++)
+ if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
+ bitmap |= 1 << i;
+
+ return bitmap;
+}
+
/**
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
@@ -1558,6 +1570,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.setup_itct = setup_itct_v3_hw,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
+ .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.free_device = free_device_v3_hw,
.prep_ssp = prep_ssp_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 19/22] scsi: hisi_sas: add get_wideport_bitmap_v3_hw()
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code for interface get_wide_port_bitmap_v3_hw().
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 9d5047e..fa686e5 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -614,6 +614,18 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
}
+static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
+{
+ int i, bitmap = 0;
+ u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
+
+ for (i = 0; i < hisi_hba->n_phy; i++)
+ if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
+ bitmap |= 1 << i;
+
+ return bitmap;
+}
+
/**
* The callpath to this function and upto writing the write
* queue pointer should be safe from interruption.
@@ -1558,6 +1570,7 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.setup_itct = setup_itct_v3_hw,
.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
.sl_notify = sl_notify_v3_hw,
+ .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
.free_device = free_device_v3_hw,
.prep_ssp = prep_ssp_v3_hw,
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
For ECC 1bit error, logic can recover it, so we only print a warning.
For ECC multi-bit and AXI bus fatal error, we panic.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 401 ++++++++++++++++++++++++++++++++-
1 file changed, 399 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index fa686e5..195276b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -51,7 +51,39 @@
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_1US_TIMER_TRSH 0xcc
+#define HGC_LM_DFX_STATUS2 0x128
+#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
+#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff <<\
+ HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
+#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
+#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff <<\
+ HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
+#define HGC_CQE_ECC_ADDR 0x13c
+#define HGC_CQE_ECC_1B_ADDR_OFF 0
+#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
+#define HGC_CQE_ECC_MB_ADDR_OFF 8
+#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
+#define HGC_IOST_ECC_ADDR 0x140
+#define HGC_IOST_ECC_1B_ADDR_OFF 0
+#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
+#define HGC_IOST_ECC_MB_ADDR_OFF 16
+#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
+#define HGC_DQE_ECC_ADDR 0x144
+#define HGC_DQE_ECC_1B_ADDR_OFF 0
+#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
+#define HGC_DQE_ECC_MB_ADDR_OFF 16
+#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
#define CHNL_INT_STATUS 0x148
+#define HGC_ITCT_ECC_ADDR 0x150
+#define HGC_ITCT_ECC_1B_ADDR_OFF 0
+#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << HGC_ITCT_ECC_1B_ADDR_OFF)
+#define HGC_ITCT_ECC_MB_ADDR_OFF 16
+#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << HGC_ITCT_ECC_MB_ADDR_OFF)
+#define HGC_AXI_FIFO_ERR_INFO 0x154
+#define AXI_ERR_INFO_OFF 0
+#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
+#define FIFO_ERR_INFO_OFF 8
+#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
#define INT_COAL_EN 0x19c
#define OQ_INT_COAL_TIME 0x1a0
#define OQ_INT_COAL_CNT 0x1a4
@@ -85,6 +117,26 @@
#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR 0x1e8
#define SAS_ECC_INTR_MSK 0x1ec
+#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
+#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
+#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
+#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
+#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
+#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
+#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
+#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
+#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 8
+#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 9
+#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
+#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
#define HGC_ERR_STAT_EN 0x238
#define DLVRY_Q_0_BASE_ADDR_LO 0x260
#define DLVRY_Q_0_BASE_ADDR_HI 0x264
@@ -98,6 +150,20 @@
#define COMPL_Q_0_DEPTH 0x4e8
#define COMPL_Q_0_WR_PTR 0x4ec
#define COMPL_Q_0_RD_PTR 0x4f0
+#define HGC_RXM_DFX_STATUS14 0xae8
+#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
+#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM0_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
+#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM1_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
+#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM2_OFF)
+#define HGC_RXM_DFX_STATUS15 0xaec
+#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
+#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS15_MEM3_OFF)
#define AWQOS_AWCACHE_CFG 0xc84
#define ARQOS_ARCACHE_CFG 0xc88
@@ -260,6 +326,7 @@
#define ITCT_HDR_RTOLT_OFF 48
#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
+#define HISI_SAS_FATAL_INT_NR 2
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
@@ -1169,8 +1236,9 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
irq_value1) {
if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
CHL_INT1_DMAC_TX_ECC_ERR_MSK))
- panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
- dev_name(dev), irq_value1);
+ panic("%s: DMAC RX/TX ecc bad error!"
+ " (0x%x)",
+ dev_name(dev), irq_value1);
hisi_sas_phy_write32(hisi_hba, phy_no,
CHL_INT1, irq_value1);
@@ -1197,6 +1265,320 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
return IRQ_HANDLED;
}
+static void one_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
+ u32 irq_value)
+{
+ struct device *dev = hisi_hba->dev;
+ u32 reg_val;
+
+ if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
+ dev_info(dev, "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_DQE_ECC_1B_ADDR_MSK)
+ >> HGC_DQE_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
+ dev_info(dev, "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_IOST_ECC_1B_ADDR_MSK)
+ >> HGC_IOST_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
+ dev_info(dev, "hgc_itct_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK)
+ >> HGC_ITCT_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ dev_info(dev, "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ dev_info(dev, "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
+ dev_info(dev, "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_CQE_ECC_1B_ADDR_MSK)
+ >> HGC_CQE_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM0_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM1_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM2_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
+ dev_info(dev, "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK)
+ >> HGC_RXM_DFX_STATUS15_MEM3_OFF);
+ }
+
+}
+
+static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
+ u32 irq_value)
+{
+ u32 reg_val;
+ struct device *dev = hisi_hba->dev;
+
+ if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
+ panic("%s: hgc_dqe_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_DQE_ECC_MB_ADDR_MSK)
+ >> HGC_DQE_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
+ panic("%s: hgc_iost_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_IOST_ECC_MB_ADDR_MSK)
+ >> HGC_IOST_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
+ panic("%s: hgc_itct_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK)
+ >> HGC_ITCT_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ panic("%s: hgc_iostl_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ panic("%s: hgc_itctl_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
+ panic("%s: hgc_cqe_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_CQE_ECC_MB_ADDR_MSK)
+ >> HGC_CQE_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem0_accbad_intr (0x%x) found:"
+ "memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM0_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem1_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM1_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem2_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM2_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
+ panic("%s: rxm_mem3_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK)
+ >> HGC_RXM_DFX_STATUS15_MEM3_OFF);
+ }
+
+}
+
+static irqreturn_t fatal_ecc_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba)
+{
+ u32 irq_value, irq_msk;
+
+ irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
+
+ irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+ if (irq_value) {
+ multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
+ one_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
+ }
+
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
+
+ return IRQ_HANDLED;
+}
+
+#define AXI_ERR_NR 8
+static const char axi_err_info[AXI_ERR_NR][32] = {
+ "IOST_AXI_W_ERR",
+ "IOST_AXI_R_ERR",
+ "ITCT_AXI_W_ERR",
+ "ITCT_AXI_R_ERR",
+ "SATA_AXI_W_ERR",
+ "SATA_AXI_R_ERR",
+ "DQE_AXI_R_ERR",
+ "CQE_AXI_W_ERR"
+};
+
+#define FIFO_ERR_NR 5
+static const char fifo_err_info[FIFO_ERR_NR][32] = {
+ "CQE_WINFO_FIFO",
+ "CQE_MSG_FIFIO",
+ "GETDQE_FIFO",
+ "CMDP_FIFO",
+ "AWTCTRL_FIFO"
+};
+
+static irqreturn_t fatal_axi_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba)
+{
+ u32 irq_value, irq_msk, err_value;
+ struct device *dev = hisi_hba->dev;
+
+ irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
+
+ irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ if (irq_value) {
+ if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_WP_DEPTH_OFF);
+ panic("%s: write pointer and depth error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
+ panic("%s: iptt no match slot error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF))
+ panic("%s: read pointer and depth error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+
+ if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
+ int i;
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_AXI_OFF);
+ err_value = hisi_sas_read32(hisi_hba,
+ HGC_AXI_FIFO_ERR_INFO);
+
+ for (i = 0; i < AXI_ERR_NR; i++) {
+ if (err_value & BIT(i))
+ panic("%s: %s (0x%x) found!\n",
+ dev_name(dev),
+ axi_err_info[i], irq_value);
+ }
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
+ int i;
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_FIFO_OFF);
+ err_value = hisi_sas_read32(hisi_hba,
+ HGC_AXI_FIFO_ERR_INFO);
+
+ for (i = 0; i < FIFO_ERR_NR; i++) {
+ if (err_value & BIT(AXI_ERR_NR + i))
+ panic("%s: %s (0x%x) found!\n",
+ dev_name(dev),
+ fifo_err_info[i], irq_value);
+ }
+
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_LM_OFF);
+ panic("%s: LM add/fetch list error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_ABT_OFF);
+ panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+ }
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fatal_interrupt_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ u32 irq_value1, irq_value2;
+
+ irq_value1 = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ irq_value2 = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+
+ if (irq_value1)
+ return fatal_axi_int_v3_hw(irq_no, hisi_hba);
+
+ if (irq_value2)
+ return fatal_ecc_int_v3_hw(irq_no, hisi_hba);
+
+ return IRQ_NONE;
+}
+
static void slot_err_v3_hw(struct hisi_hba *hisi_hba,
struct sas_task *task,
struct hisi_sas_slot *slot)
@@ -1523,6 +1905,21 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
}
}
+ irq = msi_vectors[11];
+ if (!irq) {
+ dev_err(dev, "irq init: fail map fatal interrupt 11\n");
+ return -ENOENT;
+ }
+
+ rc = devm_request_irq(dev, irq, fatal_interrupt_v3_hw, 0,
+ DRV_NAME " fatal", hisi_hba);
+ if (rc) {
+ dev_err(dev,
+ "irq init: could not request fatal interrupt 11, rc=%d\n",
+ rc);
+ return -ENOENT;
+ }
+
for (i = 0; i < hisi_hba->queue_count; i++) {
int idx = i + 16; /* First cq interrupt is irq16 */
struct hisi_sas_cq *cq = &hisi_hba->cq[i];
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
For ECC 1bit error, logic can recover it, so we only print a warning.
For ECC multi-bit and AXI bus fatal error, we panic.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 401 ++++++++++++++++++++++++++++++++-
1 file changed, 399 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index fa686e5..195276b 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -51,7 +51,39 @@
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
#define CFG_1US_TIMER_TRSH 0xcc
+#define HGC_LM_DFX_STATUS2 0x128
+#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
+#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff <<\
+ HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
+#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
+#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff <<\
+ HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
+#define HGC_CQE_ECC_ADDR 0x13c
+#define HGC_CQE_ECC_1B_ADDR_OFF 0
+#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
+#define HGC_CQE_ECC_MB_ADDR_OFF 8
+#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
+#define HGC_IOST_ECC_ADDR 0x140
+#define HGC_IOST_ECC_1B_ADDR_OFF 0
+#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
+#define HGC_IOST_ECC_MB_ADDR_OFF 16
+#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
+#define HGC_DQE_ECC_ADDR 0x144
+#define HGC_DQE_ECC_1B_ADDR_OFF 0
+#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
+#define HGC_DQE_ECC_MB_ADDR_OFF 16
+#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
#define CHNL_INT_STATUS 0x148
+#define HGC_ITCT_ECC_ADDR 0x150
+#define HGC_ITCT_ECC_1B_ADDR_OFF 0
+#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << HGC_ITCT_ECC_1B_ADDR_OFF)
+#define HGC_ITCT_ECC_MB_ADDR_OFF 16
+#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << HGC_ITCT_ECC_MB_ADDR_OFF)
+#define HGC_AXI_FIFO_ERR_INFO 0x154
+#define AXI_ERR_INFO_OFF 0
+#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
+#define FIFO_ERR_INFO_OFF 8
+#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
#define INT_COAL_EN 0x19c
#define OQ_INT_COAL_TIME 0x1a0
#define OQ_INT_COAL_CNT 0x1a4
@@ -85,6 +117,26 @@
#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR 0x1e8
#define SAS_ECC_INTR_MSK 0x1ec
+#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
+#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
+#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
+#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
+#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
+#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
+#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
+#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
+#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 8
+#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 9
+#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
+#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
+#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
+#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
+#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
+#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
#define HGC_ERR_STAT_EN 0x238
#define DLVRY_Q_0_BASE_ADDR_LO 0x260
#define DLVRY_Q_0_BASE_ADDR_HI 0x264
@@ -98,6 +150,20 @@
#define COMPL_Q_0_DEPTH 0x4e8
#define COMPL_Q_0_WR_PTR 0x4ec
#define COMPL_Q_0_RD_PTR 0x4f0
+#define HGC_RXM_DFX_STATUS14 0xae8
+#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
+#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM0_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
+#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM1_OFF)
+#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
+#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS14_MEM2_OFF)
+#define HGC_RXM_DFX_STATUS15 0xaec
+#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
+#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff <<\
+ HGC_RXM_DFX_STATUS15_MEM3_OFF)
#define AWQOS_AWCACHE_CFG 0xc84
#define ARQOS_ARCACHE_CFG 0xc88
@@ -260,6 +326,7 @@
#define ITCT_HDR_RTOLT_OFF 48
#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
+#define HISI_SAS_FATAL_INT_NR 2
struct hisi_sas_complete_v3_hdr {
__le32 dw0;
@@ -1169,8 +1236,9 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
irq_value1) {
if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
CHL_INT1_DMAC_TX_ECC_ERR_MSK))
- panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
- dev_name(dev), irq_value1);
+ panic("%s: DMAC RX/TX ecc bad error!"
+ " (0x%x)",
+ dev_name(dev), irq_value1);
hisi_sas_phy_write32(hisi_hba, phy_no,
CHL_INT1, irq_value1);
@@ -1197,6 +1265,320 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
return IRQ_HANDLED;
}
+static void one_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
+ u32 irq_value)
+{
+ struct device *dev = hisi_hba->dev;
+ u32 reg_val;
+
+ if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
+ dev_info(dev, "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_DQE_ECC_1B_ADDR_MSK)
+ >> HGC_DQE_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
+ dev_info(dev, "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_IOST_ECC_1B_ADDR_MSK)
+ >> HGC_IOST_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
+ dev_info(dev, "hgc_itct_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK)
+ >> HGC_ITCT_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ dev_info(dev, "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ dev_info(dev, "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
+ dev_info(dev, "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
+ (reg_val & HGC_CQE_ECC_1B_ADDR_MSK)
+ >> HGC_CQE_ECC_1B_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM0_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM1_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ dev_info(dev, "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM2_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
+ dev_info(dev, "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
+ (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK)
+ >> HGC_RXM_DFX_STATUS15_MEM3_OFF);
+ }
+
+}
+
+static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
+ u32 irq_value)
+{
+ u32 reg_val;
+ struct device *dev = hisi_hba->dev;
+
+ if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR);
+ panic("%s: hgc_dqe_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_DQE_ECC_MB_ADDR_MSK)
+ >> HGC_DQE_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR);
+ panic("%s: hgc_iost_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_IOST_ECC_MB_ADDR_MSK)
+ >> HGC_IOST_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR);
+ panic("%s: hgc_itct_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK)
+ >> HGC_ITCT_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ panic("%s: hgc_iostl_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_IOSTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2);
+ panic("%s: hgc_itctl_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK)
+ >> HGC_LM_DFX_STATUS2_ITCTLIST_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR);
+ panic("%s: hgc_cqe_accbad_intr (0x%x) found:"
+ " Ram address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_CQE_ECC_MB_ADDR_MSK)
+ >> HGC_CQE_ECC_MB_ADDR_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem0_accbad_intr (0x%x) found:"
+ "memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM0_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem1_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM1_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14);
+ panic("%s: rxm_mem2_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK)
+ >> HGC_RXM_DFX_STATUS14_MEM2_OFF);
+ }
+
+ if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) {
+ reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15);
+ panic("%s: rxm_mem3_accbad_intr (0x%x) found:"
+ " memory address is 0x%08X\n",
+ dev_name(dev), irq_value,
+ (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK)
+ >> HGC_RXM_DFX_STATUS15_MEM3_OFF);
+ }
+
+}
+
+static irqreturn_t fatal_ecc_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba)
+{
+ u32 irq_value, irq_msk;
+
+ irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
+
+ irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+ if (irq_value) {
+ multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
+ one_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
+ }
+
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
+ hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
+
+ return IRQ_HANDLED;
+}
+
+#define AXI_ERR_NR 8
+static const char axi_err_info[AXI_ERR_NR][32] = {
+ "IOST_AXI_W_ERR",
+ "IOST_AXI_R_ERR",
+ "ITCT_AXI_W_ERR",
+ "ITCT_AXI_R_ERR",
+ "SATA_AXI_W_ERR",
+ "SATA_AXI_R_ERR",
+ "DQE_AXI_R_ERR",
+ "CQE_AXI_W_ERR"
+};
+
+#define FIFO_ERR_NR 5
+static const char fifo_err_info[FIFO_ERR_NR][32] = {
+ "CQE_WINFO_FIFO",
+ "CQE_MSG_FIFIO",
+ "GETDQE_FIFO",
+ "CMDP_FIFO",
+ "AWTCTRL_FIFO"
+};
+
+static irqreturn_t fatal_axi_int_v3_hw(int irq_no, struct hisi_hba *hisi_hba)
+{
+ u32 irq_value, irq_msk, err_value;
+ struct device *dev = hisi_hba->dev;
+
+ irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
+
+ irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ if (irq_value) {
+ if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_WP_DEPTH_OFF);
+ panic("%s: write pointer and depth error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF);
+ panic("%s: iptt no match slot error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF))
+ panic("%s: read pointer and depth error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+
+ if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) {
+ int i;
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_AXI_OFF);
+ err_value = hisi_sas_read32(hisi_hba,
+ HGC_AXI_FIFO_ERR_INFO);
+
+ for (i = 0; i < AXI_ERR_NR; i++) {
+ if (err_value & BIT(i))
+ panic("%s: %s (0x%x) found!\n",
+ dev_name(dev),
+ axi_err_info[i], irq_value);
+ }
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) {
+ int i;
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_FIFO_OFF);
+ err_value = hisi_sas_read32(hisi_hba,
+ HGC_AXI_FIFO_ERR_INFO);
+
+ for (i = 0; i < FIFO_ERR_NR; i++) {
+ if (err_value & BIT(AXI_ERR_NR + i))
+ panic("%s: %s (0x%x) found!\n",
+ dev_name(dev),
+ fifo_err_info[i], irq_value);
+ }
+
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_LM_OFF);
+ panic("%s: LM add/fetch list error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+
+ if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) {
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
+ 1 << ENT_INT_SRC3_ABT_OFF);
+ panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n",
+ dev_name(dev), irq_value);
+ }
+ }
+
+ hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fatal_interrupt_v3_hw(int irq_no, void *p)
+{
+ struct hisi_hba *hisi_hba = p;
+ u32 irq_value1, irq_value2;
+
+ irq_value1 = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
+ irq_value2 = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+
+ if (irq_value1)
+ return fatal_axi_int_v3_hw(irq_no, hisi_hba);
+
+ if (irq_value2)
+ return fatal_ecc_int_v3_hw(irq_no, hisi_hba);
+
+ return IRQ_NONE;
+}
+
static void slot_err_v3_hw(struct hisi_hba *hisi_hba,
struct sas_task *task,
struct hisi_sas_slot *slot)
@@ -1523,6 +1905,21 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
}
}
+ irq = msi_vectors[11];
+ if (!irq) {
+ dev_err(dev, "irq init: fail map fatal interrupt 11\n");
+ return -ENOENT;
+ }
+
+ rc = devm_request_irq(dev, irq, fatal_interrupt_v3_hw, 0,
+ DRV_NAME " fatal", hisi_hba);
+ if (rc) {
+ dev_err(dev,
+ "irq init: could not request fatal interrupt 11, rc=%d\n",
+ rc);
+ return -ENOENT;
+ }
+
for (i = 0; i < hisi_hba->queue_count; i++) {
int idx = i + 16; /* First cq interrupt is irq16 */
struct hisi_sas_cq *cq = &hisi_hba->cq[i];
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
2017-05-17 10:49 ` John Garry
(?)
@ 2017-05-17 12:27 ` Arnd Bergmann
2017-05-17 12:38 ` John Garry
-1 siblings, 1 reply; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 12:27 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
> From: Xiang Chen <chenxiang66@hisilicon.com>
>
> For ECC 1bit error, logic can recover it, so we only print a warning.
> For ECC multi-bit and AXI bus fatal error, we panic.
>
> Signed-off-by: John Garry <john.garry@huawei.com>
> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
This one is tricky as there are conflicting requirements:
- For debugging purposes, you want to continue running the system
to figure out what exactly went wrong. Often enough, having the
kernel panic means you don't get to see the panic message because
console access is unavailable and you cannot log in any more
- For data consistency purposes you want to stop the system as
soon as there is any uncorrectable data error
I see that most scsi drivers don't ever call panic or BUG(), though
you already do so for v1 and v2 hw.
Maybe the SCSI maintainers can provide some more guidance here.
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
2017-05-17 12:27 ` Arnd Bergmann
@ 2017-05-17 12:38 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 12:38 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:27, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > From: Xiang Chen <chenxiang66@hisilicon.com>
>> >
>> > For ECC 1bit error, logic can recover it, so we only print a warning.
>> > For ECC multi-bit and AXI bus fatal error, we panic.
>> >
>> > Signed-off-by: John Garry <john.garry@huawei.com>
>> > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
> This one is tricky as there are conflicting requirements:
>
> - For debugging purposes, you want to continue running the system
> to figure out what exactly went wrong. Often enough, having the
> kernel panic means you don't get to see the panic message because
> console access is unavailable and you cannot log in any more
>
> - For data consistency purposes you want to stop the system as
> soon as there is any uncorrectable data error
>
> I see that most scsi drivers don't ever call panic or BUG(), though
> you already do so for v1 and v2 hw.
>
> Maybe the SCSI maintainers can provide some more guidance here.
>
> Arnd
>
> .
>
Hi Arnd,
Actually latest code for v2 has been updated to do a controller reset,
and not panic, for unrecoverable error:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926
We never got around to implementing controller reset for v1 as this
platform (hip05) is not used much anymore.
As for v3, we will change to to do same once controller reset is
implemented. I should have added this to the commit log.
Thanks,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
@ 2017-05-17 12:38 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 12:38 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:27, Arnd Bergmann wrote:
> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
>> > From: Xiang Chen <chenxiang66@hisilicon.com>
>> >
>> > For ECC 1bit error, logic can recover it, so we only print a warning.
>> > For ECC multi-bit and AXI bus fatal error, we panic.
>> >
>> > Signed-off-by: John Garry <john.garry@huawei.com>
>> > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
> This one is tricky as there are conflicting requirements:
>
> - For debugging purposes, you want to continue running the system
> to figure out what exactly went wrong. Often enough, having the
> kernel panic means you don't get to see the panic message because
> console access is unavailable and you cannot log in any more
>
> - For data consistency purposes you want to stop the system as
> soon as there is any uncorrectable data error
>
> I see that most scsi drivers don't ever call panic or BUG(), though
> you already do so for v1 and v2 hw.
>
> Maybe the SCSI maintainers can provide some more guidance here.
>
> Arnd
>
> .
>
Hi Arnd,
Actually latest code for v2 has been updated to do a controller reset,
and not panic, for unrecoverable error:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926
We never got around to implementing controller reset for v1 as this
platform (hip05) is not used much anymore.
As for v3, we will change to to do same once controller reset is
implemented. I should have added this to the commit log.
Thanks,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
2017-05-17 12:38 ` John Garry
@ 2017-06-13 14:05 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-06-13 14:05 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:38, John Garry wrote:
> On 17/05/2017 13:27, Arnd Bergmann wrote:
>> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com>
>> wrote:
>>> > From: Xiang Chen <chenxiang66@hisilicon.com>
>>> >
>>> > For ECC 1bit error, logic can recover it, so we only print a warning.
>>> > For ECC multi-bit and AXI bus fatal error, we panic.
>>> >
>>> > Signed-off-by: John Garry <john.garry@huawei.com>
>>> > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
>> This one is tricky as there are conflicting requirements:
>>
>> - For debugging purposes, you want to continue running the system
>> to figure out what exactly went wrong. Often enough, having the
>> kernel panic means you don't get to see the panic message because
>> console access is unavailable and you cannot log in any more
>>
>> - For data consistency purposes you want to stop the system as
>> soon as there is any uncorrectable data error
>>
>> I see that most scsi drivers don't ever call panic or BUG(), though
>> you already do so for v1 and v2 hw.
>>
>> Maybe the SCSI maintainers can provide some more guidance here.
>>
>> Arnd
>>
>> .
>>
>
> Hi Arnd,
>
> Actually latest code for v2 has been updated to do a controller reset,
> and not panic, for unrecoverable error:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926
>
>
> We never got around to implementing controller reset for v1 as this
> platform (hip05) is not used much anymore.
>
> As for v3, we will change to to do same once controller reset is
> implemented. I should have added this to the commit log.
>
> Thanks,
> John
It has come to light that hip08 RAS architecture requires handling
certain errors with firmware first model. I am not sure on the flow of
controller reset for fatal errors - I'm currently checking the details.
But it is not worth adding this non-critical patch and reverting it
later, so I'll omit this patch when sending the v6 patchset which
includes the fix for sloppy spinlock usage.
Thanks,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 20/22] scsi: hisi_sas: Add v3 code to support ECC and AXI bus fatal error
@ 2017-06-13 14:05 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-06-13 14:05 UTC (permalink / raw)
To: Arnd Bergmann
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List, Xiang Chen
On 17/05/2017 13:38, John Garry wrote:
> On 17/05/2017 13:27, Arnd Bergmann wrote:
>> On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com>
>> wrote:
>>> > From: Xiang Chen <chenxiang66@hisilicon.com>
>>> >
>>> > For ECC 1bit error, logic can recover it, so we only print a warning.
>>> > For ECC multi-bit and AXI bus fatal error, we panic.
>>> >
>>> > Signed-off-by: John Garry <john.garry@huawei.com>
>>> > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
>> This one is tricky as there are conflicting requirements:
>>
>> - For debugging purposes, you want to continue running the system
>> to figure out what exactly went wrong. Often enough, having the
>> kernel panic means you don't get to see the panic message because
>> console access is unavailable and you cannot log in any more
>>
>> - For data consistency purposes you want to stop the system as
>> soon as there is any uncorrectable data error
>>
>> I see that most scsi drivers don't ever call panic or BUG(), though
>> you already do so for v1 and v2 hw.
>>
>> Maybe the SCSI maintainers can provide some more guidance here.
>>
>> Arnd
>>
>> .
>>
>
> Hi Arnd,
>
> Actually latest code for v2 has been updated to do a controller reset,
> and not panic, for unrecoverable error:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c?h=v4.12-rc1#n2926
>
>
> We never got around to implementing controller reset for v1 as this
> platform (hip05) is not used much anymore.
>
> As for v3, we will change to to do same once controller reset is
> implemented. I should have added this to the commit log.
>
> Thanks,
> John
It has come to light that hip08 RAS architecture requires handling
certain errors with firmware first model. I am not sure on the flow of
controller reset for fatal errors - I'm currently checking the details.
But it is not worth adding this non-critical patch and reverting it
later, so I'll omit this patch when sending the v6 patchset which
includes the fix for sloppy spinlock usage.
Thanks,
John
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 21/22] scsi: hisi_sas: add v3 code to fill some more hw function pointers
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 195276b..766455a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -195,6 +195,8 @@
#define TXID_AUTO (PORT_BASE + 0xb8)
#define CT3_OFF 1
#define CT3_MSK (0x1 << CT3_OFF)
+#define TX_HARDRST_OFF 2
+#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
@@ -648,6 +650,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
+static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
config_id_frame_v3_hw(hisi_hba, phy_no);
@@ -655,6 +665,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
enable_phy_v3_hw(hisi_hba, phy_no);
}
+static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ disable_phy_v3_hw(hisi_hba, phy_no);
+}
+
static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -663,6 +678,22 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
start_phy_v3_hw(hisi_hba, i);
}
+static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ u32 txid_auto;
+
+ stop_phy_v3_hw(hisi_hba, phy_no);
+ if (phy->identify.device_type == SAS_END_DEVICE) {
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | TX_HARDRST_MSK);
+ }
+ msleep(100);
+ start_phy_v3_hw(hisi_hba, phy_no);
+}
+
+
static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
{
start_phys_v3_hw(hisi_hba);
@@ -1961,6 +1992,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
return 0;
}
+enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
+{
+ return SAS_LINK_RATE_12_0_GBPS;
+}
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
@@ -1978,6 +2013,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
+ .phy_enable = enable_phy_v3_hw,
+ .phy_disable = disable_phy_v3_hw,
+ .phy_hard_reset = phy_hard_reset_v3_hw,
+ .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 21/22] scsi: hisi_sas: add v3 code to fill some more hw function pointers
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 195276b..766455a 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -195,6 +195,8 @@
#define TXID_AUTO (PORT_BASE + 0xb8)
#define CT3_OFF 1
#define CT3_MSK (0x1 << CT3_OFF)
+#define TX_HARDRST_OFF 2
+#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
@@ -648,6 +650,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
}
+static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
+
+ cfg &= ~PHY_CFG_ENA_MSK;
+ hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
+}
+
static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
{
config_id_frame_v3_hw(hisi_hba, phy_no);
@@ -655,6 +665,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
enable_phy_v3_hw(hisi_hba, phy_no);
}
+static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ disable_phy_v3_hw(hisi_hba, phy_no);
+}
+
static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
{
int i;
@@ -663,6 +678,22 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
start_phy_v3_hw(hisi_hba, i);
}
+static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
+ u32 txid_auto;
+
+ stop_phy_v3_hw(hisi_hba, phy_no);
+ if (phy->identify.device_type == SAS_END_DEVICE) {
+ txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
+ hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
+ txid_auto | TX_HARDRST_MSK);
+ }
+ msleep(100);
+ start_phy_v3_hw(hisi_hba, phy_no);
+}
+
+
static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
{
start_phys_v3_hw(hisi_hba);
@@ -1961,6 +1992,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
return 0;
}
+enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
+{
+ return SAS_LINK_RATE_12_0_GBPS;
+}
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
@@ -1978,6 +2013,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
.start_delivery = start_delivery_v3_hw,
.slot_complete = slot_complete_v3_hw,
.phys_init = phys_init_v3_hw,
+ .phy_enable = enable_phy_v3_hw,
+ .phy_disable = disable_phy_v3_hw,
+ .phy_hard_reset = phy_hard_reset_v3_hw,
+ .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH 22/22] scsi: hisi_sas: modify internal abort dev flow for v3 hw
2017-05-17 10:49 ` John Garry
@ 2017-05-17 10:49 ` John Garry
-1 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
There is a change for abort dev for v3 hw: add registers to configure
unaborted iptt for a device, and then inform this to logic.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 28 ++++++++++++++++++++++++++++
3 files changed, 45 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index c7d1144..757a134 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -181,6 +181,8 @@ struct hisi_sas_hw {
void (*free_device)(struct hisi_hba *hisi_hba,
struct hisi_sas_device *dev);
int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
+ void (*dereg_device)(struct hisi_hba *hisi_hba,
+ struct domain_device *device);
int (*soft_reset)(struct hisi_hba *hisi_hba);
int max_command_entries;
int complete_hdr_size;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 156b66b..80ffba4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -760,6 +760,13 @@ static void hisi_sas_release_tasks(struct hisi_hba *hisi_hba)
}
}
+static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ if (hisi_hba->hw->dereg_device)
+ hisi_hba->hw->dereg_device(hisi_hba, device);
+}
+
static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -773,6 +780,8 @@ static void hisi_sas_dev_gone(struct domain_device *device)
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
hisi_hba->hw->free_device(hisi_hba, sas_dev);
device->lldd_dev = NULL;
memset(sas_dev, 0, sizeof(*sas_dev));
@@ -1104,6 +1113,7 @@ static int hisi_sas_abort_task(struct sas_task *task)
if (task->dev->dev_type == SAS_SATA_DEV) {
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
rc = hisi_sas_softreset_ata_disk(device);
}
} else if (task->task_proto & SAS_PROTOCOL_SMP) {
@@ -1170,6 +1180,10 @@ static int hisi_sas_I_T_nexus_reset(struct domain_device *device)
return TMF_RESP_FUNC_FAILED;
sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+ hisi_sas_internal_task_abort(hisi_hba, device,
+ HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
rc = hisi_sas_debug_I_T_nexus_reset(device);
if (rc == TMF_RESP_FUNC_COMPLETE) {
@@ -1197,6 +1211,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
HISI_SAS_INT_ABT_DEV, 0);
if (rc == TMF_RESP_FUNC_FAILED)
goto out;
+ hisi_sas_dereg_device(hisi_hba, device);
phy = sas_get_local_phy(device);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 766455a..54546cf 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -50,6 +50,10 @@
#define CFG_ABT_SET_QUERY_IPTT 0xd4
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
+#define CFG_SET_ABORTED_EN_OFF 12
+#define CFG_ABT_SET_IPTT_DONE 0xd8
+#define CFG_ABT_SET_IPTT_DONE_OFF 0
+#define HGC_IOMB_PROC1_STATUS 0x104
#define CFG_1US_TIMER_TRSH 0xcc
#define HGC_LM_DFX_STATUS2 0x128
#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
@@ -1997,6 +2001,29 @@ enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
return SAS_LINK_RATE_12_0_GBPS;
}
+static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ struct hisi_sas_slot *slot, *slot2;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ u32 cfg_abt_set_query_iptt;
+
+ cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
+ CFG_ABT_SET_QUERY_IPTT);
+ list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
+ cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
+ cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
+ (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
+ cfg_abt_set_query_iptt);
+ }
+ cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
+ cfg_abt_set_query_iptt);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
+ 1 << CFG_ABT_SET_IPTT_DONE_OFF);
+}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.setup_itct = setup_itct_v3_hw,
@@ -2017,6 +2044,7 @@ enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
.phy_disable = disable_phy_v3_hw,
.phy_hard_reset = phy_hard_reset_v3_hw,
.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
+ .dereg_device = dereg_device_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 22/22] scsi: hisi_sas: modify internal abort dev flow for v3 hw
@ 2017-05-17 10:49 ` John Garry
0 siblings, 0 replies; 64+ messages in thread
From: John Garry @ 2017-05-17 10:49 UTC (permalink / raw)
To: jejb, martin.petersen
Cc: john.garry2, linuxarm, linux-scsi, linux-kernel, arnd,
Xiang Chen, John Garry
From: Xiang Chen <chenxiang66@hisilicon.com>
There is a change for abort dev for v3 hw: add registers to configure
unaborted iptt for a device, and then inform this to logic.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: John Garry <john.garry@huawei.com>
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c | 15 +++++++++++++++
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 28 ++++++++++++++++++++++++++++
3 files changed, 45 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h
index c7d1144..757a134 100644
--- a/drivers/scsi/hisi_sas/hisi_sas.h
+++ b/drivers/scsi/hisi_sas/hisi_sas.h
@@ -181,6 +181,8 @@ struct hisi_sas_hw {
void (*free_device)(struct hisi_hba *hisi_hba,
struct hisi_sas_device *dev);
int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
+ void (*dereg_device)(struct hisi_hba *hisi_hba,
+ struct domain_device *device);
int (*soft_reset)(struct hisi_hba *hisi_hba);
int max_command_entries;
int complete_hdr_size;
diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c
index 156b66b..80ffba4 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_main.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_main.c
@@ -760,6 +760,13 @@ static void hisi_sas_release_tasks(struct hisi_hba *hisi_hba)
}
}
+static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ if (hisi_hba->hw->dereg_device)
+ hisi_hba->hw->dereg_device(hisi_hba, device);
+}
+
static void hisi_sas_dev_gone(struct domain_device *device)
{
struct hisi_sas_device *sas_dev = device->lldd_dev;
@@ -773,6 +780,8 @@ static void hisi_sas_dev_gone(struct domain_device *device)
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
hisi_hba->hw->free_device(hisi_hba, sas_dev);
device->lldd_dev = NULL;
memset(sas_dev, 0, sizeof(*sas_dev));
@@ -1104,6 +1113,7 @@ static int hisi_sas_abort_task(struct sas_task *task)
if (task->dev->dev_type == SAS_SATA_DEV) {
hisi_sas_internal_task_abort(hisi_hba, device,
HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
rc = hisi_sas_softreset_ata_disk(device);
}
} else if (task->task_proto & SAS_PROTOCOL_SMP) {
@@ -1170,6 +1180,10 @@ static int hisi_sas_I_T_nexus_reset(struct domain_device *device)
return TMF_RESP_FUNC_FAILED;
sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
+ hisi_sas_internal_task_abort(hisi_hba, device,
+ HISI_SAS_INT_ABT_DEV, 0);
+ hisi_sas_dereg_device(hisi_hba, device);
+
rc = hisi_sas_debug_I_T_nexus_reset(device);
if (rc == TMF_RESP_FUNC_COMPLETE) {
@@ -1197,6 +1211,7 @@ static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
HISI_SAS_INT_ABT_DEV, 0);
if (rc == TMF_RESP_FUNC_FAILED)
goto out;
+ hisi_sas_dereg_device(hisi_hba, device);
phy = sas_get_local_phy(device);
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 766455a..54546cf 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -50,6 +50,10 @@
#define CFG_ABT_SET_QUERY_IPTT 0xd4
#define CFG_SET_ABORTED_IPTT_OFF 0
#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
+#define CFG_SET_ABORTED_EN_OFF 12
+#define CFG_ABT_SET_IPTT_DONE 0xd8
+#define CFG_ABT_SET_IPTT_DONE_OFF 0
+#define HGC_IOMB_PROC1_STATUS 0x104
#define CFG_1US_TIMER_TRSH 0xcc
#define HGC_LM_DFX_STATUS2 0x128
#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
@@ -1997,6 +2001,29 @@ enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
return SAS_LINK_RATE_12_0_GBPS;
}
+static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
+ struct domain_device *device)
+{
+ struct hisi_sas_slot *slot, *slot2;
+ struct hisi_sas_device *sas_dev = device->lldd_dev;
+ u32 cfg_abt_set_query_iptt;
+
+ cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
+ CFG_ABT_SET_QUERY_IPTT);
+ list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
+ cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
+ cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
+ (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
+ cfg_abt_set_query_iptt);
+ }
+ cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
+ cfg_abt_set_query_iptt);
+ hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
+ 1 << CFG_ABT_SET_IPTT_DONE_OFF);
+}
+
static const struct hisi_sas_hw hisi_sas_v3_hw = {
.hw_init = hisi_sas_v3_init,
.setup_itct = setup_itct_v3_hw,
@@ -2017,6 +2044,7 @@ enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
.phy_disable = disable_phy_v3_hw,
.phy_hard_reset = phy_hard_reset_v3_hw,
.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
+ .dereg_device = dereg_device_v3_hw,
};
enum {
--
1.9.1
^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH 00/22] hisi_sas: hip08 support
2017-05-17 10:49 ` John Garry
` (22 preceding siblings ...)
(?)
@ 2017-05-17 12:38 ` Arnd Bergmann
-1 siblings, 0 replies; 64+ messages in thread
From: Arnd Bergmann @ 2017-05-17 12:38 UTC (permalink / raw)
To: John Garry
Cc: James E.J. Bottomley, Martin K. Petersen, John Garry, linuxarm,
linux-scsi, Linux Kernel Mailing List
On Wed, May 17, 2017 at 12:49 PM, John Garry <john.garry@huawei.com> wrote:
> This patchset adds support for the HiSilicon SAS controller
> in the hip08 chipset.
>
> The key difference compared to earlier chipsets is that the
> controller is an integrated PCI endpoint in hip08.
> As such, the controller is a pci device (not a platform device,
> like v2 hw in hip07).
>
> The driver is refactored so it can support both platform and
> pci device-based controllers.
>
> File hisi_sas_pci_init.c is introduced for pci device probing
> and initialization. Common functionality is still in
> hisi_sas_main.c, along with platform device probing and
> initialization.
>
> New hw layer file hisi_sas_v3_hw.c is added for hip08
> controller support. HW revisions v2 and v3 are very similar,
> but it was decided to keep support in separate files for now.
>
> As for the patches, (ignoring #1 and #2) the first few
> reorganise some functions from v2 hw.c into main.c, as they
> are required for v3 hw. Then support is added for pci
> device-based controller in subsequent patches.
> And then hip08 support is added in the final patches.
Looks good overall, but I have some high-level comments
on a couple of patches. I'm sure we can resolve them all
easily.
Arnd
^ permalink raw reply [flat|nested] 64+ messages in thread