[PATCH 0/4] fix some issues for Rockchip usb2-phy and add rk322x SoCs' support

[PATCH 0/4] fix some issues for Rockchip usb2-phy and add rk322x SoCs' support

[Frank Wang]

These series of patches fix some issues for rockchip usb2-phy and amend
usb2-phy framework to support one phy which comprises with two host-ports.

In addition, this change also add rk322x usb2-phy support.

Frank Wang (1):
  phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

William Wu (3):
  phy: rockchip-inno-usb2: add a delay after phy resume
  phy: rockchip-inno-usb2: increase otg sm work first schedule time
  phy: rockchip-inno-usb2: add one phy comprises with two host-ports    
    support

 .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
 drivers/phy/phy-rockchip-inno-usb2.c               | 74 ++++++++++++++++++++--
 2 files changed, 71 insertions(+), 4 deletions(-)

-- 
2.0.0

[PATCH 0/4] fix some issues for Rockchip usb2-phy and add rk322x SoCs' support

[Frank Wang]

These series of patches fix some issues for rockchip usb2-phy and amend
usb2-phy framework to support one phy which comprises with two host-ports.

In addition, this change also add rk322x usb2-phy support.

Frank Wang (1):
  phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

William Wu (3):
  phy: rockchip-inno-usb2: add a delay after phy resume
  phy: rockchip-inno-usb2: increase otg sm work first schedule time
  phy: rockchip-inno-usb2: add one phy comprises with two host-ports    
    support

 .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
 drivers/phy/phy-rockchip-inno-usb2.c               | 74 ++++++++++++++++++++--
 2 files changed, 71 insertions(+), 4 deletions(-)

-- 
2.0.0

[PATCH 1/4] phy: rockchip-inno-usb2: add a delay after phy resume

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

When resume phy, it need about 1.5 ~ 2ms to wait for
utmi_clk which used for USB controller to become stable.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index 8efe78a..f12dc8d 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -463,6 +463,9 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
 	if (ret)
 		return ret;
 
+	/* waiting for the utmi_clk to become stable */
+	usleep_range(1500, 2000);
+
 	rport->suspended = false;
 	return 0;
 }
-- 
2.0.0

[PATCH 1/4] phy: rockchip-inno-usb2: add a delay after phy resume

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

When resume phy, it need about 1.5 ~ 2ms to wait for
utmi_clk which used for USB controller to become stable.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index 8efe78a..f12dc8d 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -463,6 +463,9 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
 	if (ret)
 		return ret;
 
+	/* waiting for the utmi_clk to become stable */
+	usleep_range(1500, 2000);
+
 	rport->suspended = false;
 	return 0;
 }
-- 
2.0.0

[PATCH 2/4] phy: rockchip-inno-usb2: increase otg sm work first schedule time

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

In rockchip-inno-usb2 phy driver, we use otg_sm_work to
dynamically manage power consumption for phy otg-port.
If the otg-port works as peripheral mode and does not
communicate with usb host, we will suspend phy.

But once suspend phy, the phy no longer has any internal
clock running, include the utmi_clk which supplied for
usb controller. So if we suspend phy before usb controller
init, it will cause usb controller fail to initialize.

Specifically, without this patch, the observed order is:
 1. unplug usb cable
 2. start system, do dwc2 controller probe
 3. dwc2_lowlevel_hw_enable()
    - phy_init()
     - rockchip_usb2phy_init()
      - schedule otg_sm_work after 2s
        put phy in suspend, and close utmi_clk
 4. dwc2_hsotg_udc_start() - fail to initialize the usb core

Generally, dwc2_hsotg_udc_start() can be called within 5s
after start system on Rockchip platform, so we increase the
the first schedule delay time to 6s for otg_sm_work afer usb
controller calls phy_init(), this can make sure that the usb
controller completes initialization before phy enter suspend.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index f12dc8d..d6e459d 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -421,7 +421,7 @@ static int rockchip_usb2phy_init(struct phy *phy)
 				goto out;
 
 			schedule_delayed_work(&rport->otg_sm_work,
-					      OTG_SCHEDULE_DELAY);
+					      OTG_SCHEDULE_DELAY * 3);
 		} else {
 			/* If OTG works in host only mode, do nothing. */
 			dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
-- 
2.0.0

[PATCH 2/4] phy: rockchip-inno-usb2: increase otg sm work first schedule time

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

In rockchip-inno-usb2 phy driver, we use otg_sm_work to
dynamically manage power consumption for phy otg-port.
If the otg-port works as peripheral mode and does not
communicate with usb host, we will suspend phy.

But once suspend phy, the phy no longer has any internal
clock running, include the utmi_clk which supplied for
usb controller. So if we suspend phy before usb controller
init, it will cause usb controller fail to initialize.

Specifically, without this patch, the observed order is:
 1. unplug usb cable
 2. start system, do dwc2 controller probe
 3. dwc2_lowlevel_hw_enable()
    - phy_init()
     - rockchip_usb2phy_init()
      - schedule otg_sm_work after 2s
        put phy in suspend, and close utmi_clk
 4. dwc2_hsotg_udc_start() - fail to initialize the usb core

Generally, dwc2_hsotg_udc_start() can be called within 5s
after start system on Rockchip platform, so we increase the
the first schedule delay time to 6s for otg_sm_work afer usb
controller calls phy_init(), this can make sure that the usb
controller completes initialization before phy enter suspend.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index f12dc8d..d6e459d 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -421,7 +421,7 @@ static int rockchip_usb2phy_init(struct phy *phy)
 				goto out;
 
 			schedule_delayed_work(&rport->otg_sm_work,
-					      OTG_SCHEDULE_DELAY);
+					      OTG_SCHEDULE_DELAY * 3);
 		} else {
 			/* If OTG works in host only mode, do nothing. */
 			dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
-- 
2.0.0

[PATCH 3/4] phy: rockchip-inno-usb2: add one phy comprises with two host-ports support

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

At the current rockchip-inno-usb2 phy driver framework, it can
only support usb2-phy which comprises with one otg-port and one
host-port.

However, some Rockchip SoCs' (e.g RK3228, RK3229) usb2-phy comprises
with two host-ports, so we use index of otg id for one host-port
configuration, and make it work the same as otg-port host mode.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index d6e459d..d026b4cf 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -406,7 +406,8 @@ static int rockchip_usb2phy_init(struct phy *phy)
 	mutex_lock(&rport->mutex);
 
 	if (rport->port_id == USB2PHY_PORT_OTG) {
-		if (rport->mode != USB_DR_MODE_HOST) {
+		if (rport->mode != USB_DR_MODE_HOST &&
+		    rport->mode != USB_DR_MODE_UNKNOWN) {
 			/* clear bvalid status and enable bvalid detect irq */
 			ret = property_enable(rphy,
 					      &rport->port_cfg->bvalid_det_clr,
@@ -496,7 +497,8 @@ static int rockchip_usb2phy_exit(struct phy *phy)
 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 
 	if (rport->port_id == USB2PHY_PORT_OTG &&
-	    rport->mode != USB_DR_MODE_HOST) {
+	    rport->mode != USB_DR_MODE_HOST &&
+	    rport->mode != USB_DR_MODE_UNKNOWN) {
 		cancel_delayed_work_sync(&rport->otg_sm_work);
 		cancel_delayed_work_sync(&rport->chg_work);
 	} else if (rport->port_id == USB2PHY_PORT_HOST)
@@ -973,7 +975,8 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 	mutex_init(&rport->mutex);
 
 	rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
-	if (rport->mode == USB_DR_MODE_HOST) {
+	if (rport->mode == USB_DR_MODE_HOST ||
+	    rport->mode == USB_DR_MODE_UNKNOWN) {
 		ret = 0;
 		goto out;
 	}
-- 
2.0.0

[PATCH 3/4] phy: rockchip-inno-usb2: add one phy comprises with two host-ports support

[Frank Wang]

From: William Wu <william.wu@rock-chips.com>

At the current rockchip-inno-usb2 phy driver framework, it can
only support usb2-phy which comprises with one otg-port and one
host-port.

However, some Rockchip SoCs' (e.g RK3228, RK3229) usb2-phy comprises
with two host-ports, so we use index of otg id for one host-port
configuration, and make it work the same as otg-port host mode.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 drivers/phy/phy-rockchip-inno-usb2.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index d6e459d..d026b4cf 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -406,7 +406,8 @@ static int rockchip_usb2phy_init(struct phy *phy)
 	mutex_lock(&rport->mutex);
 
 	if (rport->port_id == USB2PHY_PORT_OTG) {
-		if (rport->mode != USB_DR_MODE_HOST) {
+		if (rport->mode != USB_DR_MODE_HOST &&
+		    rport->mode != USB_DR_MODE_UNKNOWN) {
 			/* clear bvalid status and enable bvalid detect irq */
 			ret = property_enable(rphy,
 					      &rport->port_cfg->bvalid_det_clr,
@@ -496,7 +497,8 @@ static int rockchip_usb2phy_exit(struct phy *phy)
 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 
 	if (rport->port_id == USB2PHY_PORT_OTG &&
-	    rport->mode != USB_DR_MODE_HOST) {
+	    rport->mode != USB_DR_MODE_HOST &&
+	    rport->mode != USB_DR_MODE_UNKNOWN) {
 		cancel_delayed_work_sync(&rport->otg_sm_work);
 		cancel_delayed_work_sync(&rport->chg_work);
 	} else if (rport->port_id == USB2PHY_PORT_HOST)
@@ -973,7 +975,8 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 	mutex_init(&rport->mutex);
 
 	rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
-	if (rport->mode == USB_DR_MODE_HOST) {
+	if (rport->mode == USB_DR_MODE_HOST ||
+	    rport->mode == USB_DR_MODE_UNKNOWN) {
 		ret = 0;
 		goto out;
 	}
-- 
2.0.0

[PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Frank Wang]

This adds support usb2-phy for rk322x SoCs and amend phy Documentation.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
 drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
 2 files changed, 61 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
index e71a8d2..b4ce12e 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
@@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
 
 Required properties (phy (parent) node):
  - compatible : should be one of the listed compatibles:
+	* "rockchip,rk322x-usb2phy"
 	* "rockchip,rk3328-usb2phy"
 	* "rockchip,rk3366-usb2phy"
 	* "rockchip,rk3399-usb2phy"
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index d026b4cf..b9d4e23 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
+	{
+		.reg = 0x760,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
+				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
+				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
+				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
+				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
+				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
+				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
+			}
+		},
+		.chg_det = {
+			.opmode		= { 0x0760, 3, 0, 5, 1 },
+			.cp_det		= { 0x0884, 4, 4, 0, 1 },
+			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
+			.dp_det		= { 0x0884, 5, 5, 0, 1 },
+			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
+		},
+	},
+	{
+		.reg = 0x800,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
+				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
+				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
 	{
 		.reg = 0x100,
@@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
 };
 
 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
+	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
-- 
2.0.0

[PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Frank Wang]

This adds support usb2-phy for rk322x SoCs and amend phy Documentation.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
---
 .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
 drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
 2 files changed, 61 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
index e71a8d2..b4ce12e 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
@@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
 
 Required properties (phy (parent) node):
  - compatible : should be one of the listed compatibles:
+	* "rockchip,rk322x-usb2phy"
 	* "rockchip,rk3328-usb2phy"
 	* "rockchip,rk3366-usb2phy"
 	* "rockchip,rk3399-usb2phy"
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index d026b4cf..b9d4e23 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
 	return ret;
 }
 
+static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
+	{
+		.reg = 0x760,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
+				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
+				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
+				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
+				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
+				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
+				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
+				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
+				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
+			}
+		},
+		.chg_det = {
+			.opmode		= { 0x0760, 3, 0, 5, 1 },
+			.cp_det		= { 0x0884, 4, 4, 0, 1 },
+			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
+			.dp_det		= { 0x0884, 5, 5, 0, 1 },
+			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
+		},
+	},
+	{
+		.reg = 0x800,
+		.num_ports	= 2,
+		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
+				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
+				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
+				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
 	{
 		.reg = 0x100,
@@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
 };
 
 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
+	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
-- 
2.0.0

Re: [PATCH 0/4] fix some issues for Rockchip usb2-phy and add rk322x SoCs' support

[Frank Wang]

Hi Heiko and Kishon,

Friendly ping... :-)


On 2017/5/18 11:42, Frank Wang wrote:
> These series of patches fix some issues for rockchip usb2-phy and amend
> usb2-phy framework to support one phy which comprises with two host-ports.
>
> In addition, this change also add rk322x usb2-phy support.
>
> Frank Wang (1):
>    phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs
>
> William Wu (3):
>    phy: rockchip-inno-usb2: add a delay after phy resume
>    phy: rockchip-inno-usb2: increase otg sm work first schedule time
>    phy: rockchip-inno-usb2: add one phy comprises with two host-ports
>      support
>
>   .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>   drivers/phy/phy-rockchip-inno-usb2.c               | 74 ++++++++++++++++++++--
>   2 files changed, 71 insertions(+), 4 deletions(-)
>

BR.
Frank

[PATCH 0/4] fix some issues for Rockchip usb2-phy and add rk322x SoCs' support

[Frank Wang]

Hi Heiko and Kishon,

Friendly ping... :-)


On 2017/5/18 11:42, Frank Wang wrote:
> These series of patches fix some issues for rockchip usb2-phy and amend
> usb2-phy framework to support one phy which comprises with two host-ports.
>
> In addition, this change also add rk322x usb2-phy support.
>
> Frank Wang (1):
>    phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs
>
> William Wu (3):
>    phy: rockchip-inno-usb2: add a delay after phy resume
>    phy: rockchip-inno-usb2: increase otg sm work first schedule time
>    phy: rockchip-inno-usb2: add one phy comprises with two host-ports
>      support
>
>   .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>   drivers/phy/phy-rockchip-inno-usb2.c               | 74 ++++++++++++++++++++--
>   2 files changed, 71 insertions(+), 4 deletions(-)
>

BR.
Frank

Re: [PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Heiko Stuebner]

Hi Frank,

Am Donnerstag, 18. Mai 2017, 11:43:02 CEST schrieb Frank Wang:
> This adds support usb2-phy for rk322x SoCs and amend phy Documentation.
> 
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

this adds a devicetree binding, so you should include devicetree people in
the recipient list:

Rob Herring <robh+dt@kernel.org>
Mark Rutland <mark.rutland@arm.com>
devicetree@vger.kernel.org

as they should Ack such binding additions.


> ---
>  .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>  drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> index e71a8d2..b4ce12e 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> @@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
>  
>  Required properties (phy (parent) node):
>   - compatible : should be one of the listed compatibles:
> +	* "rockchip,rk322x-usb2phy"

devicetree compatibles should not contain wildcards, so please name that
"rockchip,rk3228-usb2phy"

here and in the driver as well.


Heiko


>  	* "rockchip,rk3328-usb2phy"
>  	* "rockchip,rk3366-usb2phy"
>  	* "rockchip,rk3399-usb2phy"
> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
> index d026b4cf..b9d4e23 100644
> --- a/drivers/phy/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
> @@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>  	return ret;
>  }
>  
> +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
> +	{
> +		.reg = 0x760,
> +		.num_ports	= 2,
> +		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
> +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
> +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
> +				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
> +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
> +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
> +				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
> +				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
> +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
> +			}
> +		},
> +		.chg_det = {
> +			.opmode		= { 0x0760, 3, 0, 5, 1 },
> +			.cp_det		= { 0x0884, 4, 4, 0, 1 },
> +			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
> +			.dp_det		= { 0x0884, 5, 5, 0, 1 },
> +			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
> +			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
> +			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
> +			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
> +			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
> +			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
> +		},
> +	},
> +	{
> +		.reg = 0x800,
> +		.num_ports	= 2,
> +		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
> +				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
> +				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
> +				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
> +				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
> +			}
> +		},
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
>  	{
>  		.reg = 0x100,
> @@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>  };
>  
>  static const struct of_device_id rockchip_usb2phy_dt_match[] = {
> +	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
>  	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
>  	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
>  	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
> 

[PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Heiko Stuebner]

Hi Frank,

Am Donnerstag, 18. Mai 2017, 11:43:02 CEST schrieb Frank Wang:
> This adds support usb2-phy for rk322x SoCs and amend phy Documentation.
> 
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

this adds a devicetree binding, so you should include devicetree people in
the recipient list:

Rob Herring <robh+dt@kernel.org>
Mark Rutland <mark.rutland@arm.com>
devicetree at vger.kernel.org

as they should Ack such binding additions.


> ---
>  .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>  drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> index e71a8d2..b4ce12e 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
> @@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
>  
>  Required properties (phy (parent) node):
>   - compatible : should be one of the listed compatibles:
> +	* "rockchip,rk322x-usb2phy"

devicetree compatibles should not contain wildcards, so please name that
"rockchip,rk3228-usb2phy"

here and in the driver as well.


Heiko


>  	* "rockchip,rk3328-usb2phy"
>  	* "rockchip,rk3366-usb2phy"
>  	* "rockchip,rk3399-usb2phy"
> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
> index d026b4cf..b9d4e23 100644
> --- a/drivers/phy/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
> @@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>  	return ret;
>  }
>  
> +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
> +	{
> +		.reg = 0x760,
> +		.num_ports	= 2,
> +		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
> +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
> +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
> +				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
> +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
> +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
> +				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
> +				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
> +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
> +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
> +			}
> +		},
> +		.chg_det = {
> +			.opmode		= { 0x0760, 3, 0, 5, 1 },
> +			.cp_det		= { 0x0884, 4, 4, 0, 1 },
> +			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
> +			.dp_det		= { 0x0884, 5, 5, 0, 1 },
> +			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
> +			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
> +			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
> +			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
> +			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
> +			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
> +		},
> +	},
> +	{
> +		.reg = 0x800,
> +		.num_ports	= 2,
> +		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
> +		.port_cfgs	= {
> +			[USB2PHY_PORT_OTG] = {
> +				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
> +				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
> +				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
> +			},
> +			[USB2PHY_PORT_HOST] = {
> +				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
> +				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
> +				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
> +				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
> +			}
> +		},
> +	},
> +	{ /* sentinel */ }
> +};
> +
>  static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
>  	{
>  		.reg = 0x100,
> @@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>  };
>  
>  static const struct of_device_id rockchip_usb2phy_dt_match[] = {
> +	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
>  	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
>  	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
>  	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
> 

Re: [PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Frank Wang]

Hi Heiko,

On 2017/6/2 4:18, Heiko Stuebner wrote:
> Hi Frank,
>
> Am Donnerstag, 18. Mai 2017, 11:43:02 CEST schrieb Frank Wang:
>> This adds support usb2-phy for rk322x SoCs and amend phy Documentation.
>>
>> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> this adds a devicetree binding, so you should include devicetree people in
> the recipient list:
>
> Rob Herring <robh+dt@kernel.org>
> Mark Rutland <mark.rutland@arm.com>
> devicetree@vger.kernel.org
>
> as they should Ack such binding additions.

Noted and thanks for reminding.

>
>> ---
>>   .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>>   drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
>>   2 files changed, 61 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> index e71a8d2..b4ce12e 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> @@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
>>   
>>   Required properties (phy (parent) node):
>>    - compatible : should be one of the listed compatibles:
>> +	* "rockchip,rk322x-usb2phy"
> devicetree compatibles should not contain wildcards, so please name that
> "rockchip,rk3228-usb2phy"
>
> here and in the driver as well.

Will fix.


BR.
Frank

>
> Heiko
>
>
>>   	* "rockchip,rk3328-usb2phy"
>>   	* "rockchip,rk3366-usb2phy"
>>   	* "rockchip,rk3399-usb2phy"
>> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
>> index d026b4cf..b9d4e23 100644
>> --- a/drivers/phy/phy-rockchip-inno-usb2.c
>> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
>> @@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>>   	return ret;
>>   }
>>   
>> +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
>> +	{
>> +		.reg = 0x760,
>> +		.num_ports	= 2,
>> +		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
>> +		.port_cfgs	= {
>> +			[USB2PHY_PORT_OTG] = {
>> +				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
>> +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
>> +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
>> +				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
>> +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
>> +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
>> +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
>> +				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
>> +				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
>> +			},
>> +			[USB2PHY_PORT_HOST] = {
>> +				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
>> +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
>> +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
>> +			}
>> +		},
>> +		.chg_det = {
>> +			.opmode		= { 0x0760, 3, 0, 5, 1 },
>> +			.cp_det		= { 0x0884, 4, 4, 0, 1 },
>> +			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
>> +			.dp_det		= { 0x0884, 5, 5, 0, 1 },
>> +			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
>> +			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
>> +			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
>> +			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
>> +			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
>> +			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
>> +		},
>> +	},
>> +	{
>> +		.reg = 0x800,
>> +		.num_ports	= 2,
>> +		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
>> +		.port_cfgs	= {
>> +			[USB2PHY_PORT_OTG] = {
>> +				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
>> +				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
>> +				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
>> +			},
>> +			[USB2PHY_PORT_HOST] = {
>> +				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
>> +				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
>> +				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
>> +			}
>> +		},
>> +	},
>> +	{ /* sentinel */ }
>> +};
>> +
>>   static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
>>   	{
>>   		.reg = 0x100,
>> @@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>>   };
>>   
>>   static const struct of_device_id rockchip_usb2phy_dt_match[] = {
>> +	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
>>

[PATCH 4/4] phy: rockchip-inno-usb2: add support of usb2-phy for rk322x SoCs

[Frank Wang]

Hi Heiko,

On 2017/6/2 4:18, Heiko Stuebner wrote:
> Hi Frank,
>
> Am Donnerstag, 18. Mai 2017, 11:43:02 CEST schrieb Frank Wang:
>> This adds support usb2-phy for rk322x SoCs and amend phy Documentation.
>>
>> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
> this adds a devicetree binding, so you should include devicetree people in
> the recipient list:
>
> Rob Herring <robh+dt@kernel.org>
> Mark Rutland <mark.rutland@arm.com>
> devicetree at vger.kernel.org
>
> as they should Ack such binding additions.

Noted and thanks for reminding.

>
>> ---
>>   .../bindings/phy/phy-rockchip-inno-usb2.txt        |  1 +
>>   drivers/phy/phy-rockchip-inno-usb2.c               | 60 ++++++++++++++++++++++
>>   2 files changed, 61 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> index e71a8d2..b4ce12e 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
>> @@ -2,6 +2,7 @@ ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
>>   
>>   Required properties (phy (parent) node):
>>    - compatible : should be one of the listed compatibles:
>> +	* "rockchip,rk322x-usb2phy"
> devicetree compatibles should not contain wildcards, so please name that
> "rockchip,rk3228-usb2phy"
>
> here and in the driver as well.

Will fix.


BR.
Frank

>
> Heiko
>
>
>>   	* "rockchip,rk3328-usb2phy"
>>   	* "rockchip,rk3366-usb2phy"
>>   	* "rockchip,rk3399-usb2phy"
>> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
>> index d026b4cf..b9d4e23 100644
>> --- a/drivers/phy/phy-rockchip-inno-usb2.c
>> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
>> @@ -1144,6 +1144,65 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
>>   	return ret;
>>   }
>>   
>> +static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
>> +	{
>> +		.reg = 0x760,
>> +		.num_ports	= 2,
>> +		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
>> +		.port_cfgs	= {
>> +			[USB2PHY_PORT_OTG] = {
>> +				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
>> +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
>> +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
>> +				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
>> +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
>> +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
>> +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
>> +				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
>> +				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
>> +			},
>> +			[USB2PHY_PORT_HOST] = {
>> +				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
>> +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
>> +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
>> +			}
>> +		},
>> +		.chg_det = {
>> +			.opmode		= { 0x0760, 3, 0, 5, 1 },
>> +			.cp_det		= { 0x0884, 4, 4, 0, 1 },
>> +			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
>> +			.dp_det		= { 0x0884, 5, 5, 0, 1 },
>> +			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
>> +			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
>> +			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
>> +			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
>> +			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
>> +			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
>> +		},
>> +	},
>> +	{
>> +		.reg = 0x800,
>> +		.num_ports	= 2,
>> +		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
>> +		.port_cfgs	= {
>> +			[USB2PHY_PORT_OTG] = {
>> +				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
>> +				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
>> +				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
>> +			},
>> +			[USB2PHY_PORT_HOST] = {
>> +				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
>> +				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
>> +				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
>> +				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
>> +			}
>> +		},
>> +	},
>> +	{ /* sentinel */ }
>> +};
>> +
>>   static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
>>   	{
>>   		.reg = 0x100,
>> @@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
>>   };
>>   
>>   static const struct of_device_id rockchip_usb2phy_dt_match[] = {
>> +	{ .compatible = "rockchip,rk322x-usb2phy", .data = &rk322x_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
>>   	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
>>