* [PATCH] examples/performance-thread: add arm64 support
@ 2017-05-17 18:19 Ashwin Sekhar T K
2017-05-17 18:44 ` Jerin Jacob
` (4 more replies)
0 siblings, 5 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-17 18:19 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
Updated Makefile to allow compilation for arm64 architecture.
Moved the code for setting the initial stack to architecture specific
directory.
Added implementation of context-switch for arm64 architecture.
Fixed minor compilation errors for arm64 compilation.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 99 ++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 95 ++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 111 +++++++++++++++++++++
.../performance-thread/common/arch/x86/stack.h | 65 ++++++++++++
examples/performance-thread/common/common.mk | 10 +-
examples/performance-thread/common/lthread.c | 11 +-
examples/performance-thread/l3fwd-thread/main.c | 2 +-
8 files changed, 383 insertions(+), 14 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
diff --git a/examples/performance-thread/Makefile b/examples/performance-thread/Makefile
index d19f8489e..0c5edfdb9 100644
--- a/examples/performance-thread/Makefile
+++ b/examples/performance-thread/Makefile
@@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
-ifneq ($(CONFIG_RTE_ARCH),"x86_64")
-$(error This application is only supported for x86_64 targets)
+ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
+$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread
diff --git a/examples/performance-thread/common/arch/arm64/ctx.c b/examples/performance-thread/common/arch/arm64/ctx.c
new file mode 100644
index 000000000..7073cfd75
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.c
@@ -0,0 +1,99 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <rte_common.h>
+#include <ctx.h>
+
+void
+ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
+{
+ /* SAVE CURRENT CONTEXT */
+ asm volatile (
+ /* Save SP */
+ "mov x3, sp\n"
+ "str x3, [x1, #0]\n"
+
+ /* Save FP and LR */
+ "stp x29, x30, [x1, #8]\n"
+
+ /* Save Callee Saved Regs x19 - x28 */
+ "stp x19, x20, [x1, #24]\n"
+ "stp x21, x22, [x1, #40]\n"
+ "stp x23, x24, [x1, #56]\n"
+ "stp x25, x26, [x1, #72]\n"
+ "stp x27, x28, [x1, #88]\n"
+ );
+
+ /* RESTORE NEW CONTEXT */
+ asm volatile (
+ /* Restore SP */
+ "ldr x3, [x0, #0]\n"
+ "mov sp, x3\n"
+
+ /* Restore FP and LR */
+ "ldp x29, x30, [x0, #8]\n"
+
+ /* Restore Callee Saved Regs x19 - x28 */
+ "ldp x19, x20, [x0, #24]\n"
+ "ldp x21, x22, [x0, #40]\n"
+ "ldp x23, x24, [x0, #56]\n"
+ "ldp x25, x26, [x0, #72]\n"
+ "ldp x27, x28, [x0, #88]\n"
+ );
+}
diff --git a/examples/performance-thread/common/arch/arm64/ctx.h b/examples/performance-thread/common/arch/arm64/ctx.h
new file mode 100644
index 000000000..27a124d1b
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.h
@@ -0,0 +1,95 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef CTX_H
+#define CTX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CPU context registers
+ */
+struct ctx {
+ void *sp; /* 0 */
+ void *fp; /* 8 */
+ void *lr; /* 16 */
+ void *r19; /* 24 */
+ void *r20; /* 32 */
+ void *r21; /* 40 */
+ void *r22; /* 48 */
+ void *r23; /* 56 */
+ void *r24; /* 64 */
+ void *r25; /* 72 */
+ void *r26; /* 80 */
+ void *r27; /* 88 */
+ void *r28; /* 96 */
+};
+
+
+void
+ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CTX_H_ */
diff --git a/examples/performance-thread/common/arch/arm64/stack.h b/examples/performance-thread/common/arch/arm64/stack.h
new file mode 100644
index 000000000..1e7c6444c
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/stack.h
@@ -0,0 +1,111 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
+
+ /*
+ * Align stack_top to 16 bytes. Arm64 has the constraint that the
+ * stack pointer must always be quad-word aligned.
+ */
+ stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
+
+ /*
+ * First Stack Frame
+ */
+ stack_top[0] = NULL;
+ stack_top[-1] = NULL;
+
+ /*
+ * Initialize the context
+ */
+ lt->ctx.fp = &stack_top[-1];
+ lt->ctx.sp = &stack_top[-2];
+
+ /*
+ * Here only the address of _lthread_exec is saved as the link
+ * register value. The argument to _lthread_exec i.e the address of
+ * the lthread struct is not saved. This is because the first
+ * argument to ctx_switch is the address of the new context,
+ * which also happens to be the address of required lthread struct.
+ * So while returning from ctx_switch into _thread_exec, parameter
+ * register x0 will always contain the required value.
+ */
+ lt->ctx.lr = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/arch/x86/stack.h b/examples/performance-thread/common/arch/x86/stack.h
new file mode 100644
index 000000000..fe18cf40e
--- /dev/null
+++ b/examples/performance-thread/common/arch/x86/stack.h
@@ -0,0 +1,65 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ char *stack_top = (char *)(lt->stack) + lt->stack_size;
+ void **s = (void **)stack_top;
+
+ /* set initial context */
+ s[-3] = NULL;
+ s[-2] = (void *)lt;
+ lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
+ lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
+ lt->ctx.rip = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index f6cab7718..f1f05fdde 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -37,8 +37,14 @@
MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-VPATH := $(MKFILE_PATH) $(MKFILE_PATH)/arch/x86
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/x86
+else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/arm64
+endif
+
+VPATH := $(MKFILE_PATH) $(ARCH_PATH)
SRCS-y += lthread.c lthread_sched.c lthread_cond.c lthread_tls.c lthread_mutex.c lthread_diag.c ctx.c
-INCLUDES += -I$(MKFILE_PATH) -I$(MKFILE_PATH)/arch/x86/
+INCLUDES += -I$(MKFILE_PATH) -I$(ARCH_PATH)
diff --git a/examples/performance-thread/common/lthread.c b/examples/performance-thread/common/lthread.c
index 062275a43..7d76c8c46 100644
--- a/examples/performance-thread/common/lthread.c
+++ b/examples/performance-thread/common/lthread.c
@@ -76,6 +76,7 @@
#include <rte_log.h>
#include <ctx.h>
+#include <stack.h>
#include "lthread_api.h"
#include "lthread.h"
@@ -190,19 +191,11 @@ _lthread_init(struct lthread *lt,
*/
void _lthread_set_stack(struct lthread *lt, void *stack, size_t stack_size)
{
- char *stack_top = (char *)stack + stack_size;
- void **s = (void **)stack_top;
-
/* set stack */
lt->stack = stack;
lt->stack_size = stack_size;
- /* set initial context */
- s[-3] = NULL;
- s[-2] = (void *)lt;
- lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
- lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
- lt->ctx.rip = (void *)_lthread_exec;
+ arch_set_stack(lt, _lthread_exec);
}
/*
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index 2d98473eb..3d9739e91 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -225,7 +225,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
-static __m128i val_eth[RTE_MAX_ETHPORTS];
+static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH] examples/performance-thread: add arm64 support
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
@ 2017-05-17 18:44 ` Jerin Jacob
2017-05-18 6:35 ` Jianbo Liu
2017-05-18 7:34 ` [PATCH v2 0/2] " Ashwin Sekhar T K
` (3 subsequent siblings)
4 siblings, 1 reply; 23+ messages in thread
From: Jerin Jacob @ 2017-05-17 18:44 UTC (permalink / raw)
To: Ashwin Sekhar T K; +Cc: john.mcnamara, jianbo.liu, dev
-----Original Message-----
> Date: Wed, 17 May 2017 11:19:49 -0700
> From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
> jianbo.liu@linaro.org
> Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> Subject: [dpdk-dev] [PATCH] examples/performance-thread: add arm64 support
> X-Mailer: git-send-email 2.12.2
>
> Updated Makefile to allow compilation for arm64 architecture.
>
> Moved the code for setting the initial stack to architecture specific
> directory.
Please split the patch to two
- "arch_set_stack" abstraction and associated x86 change
- arm64 support
Thanks Ashwin.
I think, This may be the last feature to make arm64 at par with x86 features
supported in DPDK.
/Jerin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH] examples/performance-thread: add arm64 support
2017-05-17 18:44 ` Jerin Jacob
@ 2017-05-18 6:35 ` Jianbo Liu
2017-05-18 7:38 ` Sekhar, Ashwin
0 siblings, 1 reply; 23+ messages in thread
From: Jianbo Liu @ 2017-05-18 6:35 UTC (permalink / raw)
To: Jerin Jacob; +Cc: Ashwin Sekhar T K, john.mcnamara, dev
On 18 May 2017 at 02:44, Jerin Jacob <jerin.jacob@caviumnetworks.com> wrote:
> -----Original Message-----
>> Date: Wed, 17 May 2017 11:19:49 -0700
>> From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
>> To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
>> jianbo.liu@linaro.org
>> Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
>> Subject: [dpdk-dev] [PATCH] examples/performance-thread: add arm64 support
>> X-Mailer: git-send-email 2.12.2
>>
>> Updated Makefile to allow compilation for arm64 architecture.
>>
>> Moved the code for setting the initial stack to architecture specific
>> directory.
>
> Please split the patch to two
> - "arch_set_stack" abstraction and associated x86 change
> - arm64 support
There are so many redundant code in l3fwd and l3fwd-thread, I think
it's possible to merge them.
>
> Thanks Ashwin.
>
> I think, This may be the last feature to make arm64 at par with x86 features
> supported in DPDK.
>
> /Jerin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 0/2] examples/performance-thread: add arm64 support
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-17 18:44 ` Jerin Jacob
@ 2017-05-18 7:34 ` Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 0/2] " Ashwin Sekhar T K
` (2 subsequent siblings)
4 siblings, 2 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 7:34 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
This series of patches adds the arm64 support for performance-thread
app.
Patch 1 moves some x86 specific code to architecture dependent directory
Patch 2 adds the necessary arm64 support for lthread.
v2:
* Split the patch into separate patches, one for code reorg and another
for adding arm64 support.
Ashwin Sekhar T K (2):
examples/performance-thread: reorganise arch dependent code
examples/performance-thread: add arm64 support
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 99 ++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 95 ++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 111 +++++++++++++++++++++
.../performance-thread/common/arch/x86/stack.h | 66 ++++++++++++
examples/performance-thread/common/common.mk | 10 +-
examples/performance-thread/common/lthread.c | 11 +-
examples/performance-thread/l3fwd-thread/main.c | 2 +-
8 files changed, 384 insertions(+), 14 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
--
2.12.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] examples/performance-thread: reorganise arch dependent code
2017-05-18 7:34 ` [PATCH v2 0/2] " Ashwin Sekhar T K
@ 2017-05-18 7:34 ` Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
1 sibling, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 7:34 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
Moved the architecture dependent stack set code to architecture
specific directory.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
.../performance-thread/common/arch/x86/stack.h | 66 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 8 ++-
examples/performance-thread/common/lthread.c | 11 +---
3 files changed, 74 insertions(+), 11 deletions(-)
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
diff --git a/examples/performance-thread/common/arch/x86/stack.h b/examples/performance-thread/common/arch/x86/stack.h
new file mode 100644
index 000000000..80c06bf1c
--- /dev/null
+++ b/examples/performance-thread/common/arch/x86/stack.h
@@ -0,0 +1,66 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * Copyright(c) Cavium networks Ltd. 2017.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ char *stack_top = (char *)(lt->stack) + lt->stack_size;
+ void **s = (void **)stack_top;
+
+ /* set initial context */
+ s[-3] = NULL;
+ s[-2] = (void *)lt;
+ lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
+ lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
+ lt->ctx.rip = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index f6cab7718..532dbf61d 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -37,8 +37,12 @@
MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-VPATH := $(MKFILE_PATH) $(MKFILE_PATH)/arch/x86
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/x86
+endif
+
+VPATH := $(MKFILE_PATH) $(ARCH_PATH)
SRCS-y += lthread.c lthread_sched.c lthread_cond.c lthread_tls.c lthread_mutex.c lthread_diag.c ctx.c
-INCLUDES += -I$(MKFILE_PATH) -I$(MKFILE_PATH)/arch/x86/
+INCLUDES += -I$(MKFILE_PATH) -I$(ARCH_PATH)
diff --git a/examples/performance-thread/common/lthread.c b/examples/performance-thread/common/lthread.c
index 062275a43..7d76c8c46 100644
--- a/examples/performance-thread/common/lthread.c
+++ b/examples/performance-thread/common/lthread.c
@@ -76,6 +76,7 @@
#include <rte_log.h>
#include <ctx.h>
+#include <stack.h>
#include "lthread_api.h"
#include "lthread.h"
@@ -190,19 +191,11 @@ _lthread_init(struct lthread *lt,
*/
void _lthread_set_stack(struct lthread *lt, void *stack, size_t stack_size)
{
- char *stack_top = (char *)stack + stack_size;
- void **s = (void **)stack_top;
-
/* set stack */
lt->stack = stack;
lt->stack_size = stack_size;
- /* set initial context */
- s[-3] = NULL;
- s[-2] = (void *)lt;
- lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
- lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
- lt->ctx.rip = (void *)_lthread_exec;
+ arch_set_stack(lt, _lthread_exec);
}
/*
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] examples/performance-thread: add arm64 support
2017-05-18 7:34 ` [PATCH v2 0/2] " Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
@ 2017-05-18 7:34 ` Ashwin Sekhar T K
2017-05-18 8:55 ` Jerin Jacob
1 sibling, 1 reply; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 7:34 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
Updated Makefile to allow compilation for arm64 architecture.
Added necessary arm64 support for lthread.
Fixed minor compilation errors for arm64 compilation.
Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
and x86_64.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 99 ++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 95 ++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 111 +++++++++++++++++++++
examples/performance-thread/common/common.mk | 2 +
examples/performance-thread/l3fwd-thread/main.c | 2 +-
6 files changed, 310 insertions(+), 3 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
diff --git a/examples/performance-thread/Makefile b/examples/performance-thread/Makefile
index d19f8489e..0c5edfdb9 100644
--- a/examples/performance-thread/Makefile
+++ b/examples/performance-thread/Makefile
@@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
-ifneq ($(CONFIG_RTE_ARCH),"x86_64")
-$(error This application is only supported for x86_64 targets)
+ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
+$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread
diff --git a/examples/performance-thread/common/arch/arm64/ctx.c b/examples/performance-thread/common/arch/arm64/ctx.c
new file mode 100644
index 000000000..7073cfd75
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.c
@@ -0,0 +1,99 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <rte_common.h>
+#include <ctx.h>
+
+void
+ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
+{
+ /* SAVE CURRENT CONTEXT */
+ asm volatile (
+ /* Save SP */
+ "mov x3, sp\n"
+ "str x3, [x1, #0]\n"
+
+ /* Save FP and LR */
+ "stp x29, x30, [x1, #8]\n"
+
+ /* Save Callee Saved Regs x19 - x28 */
+ "stp x19, x20, [x1, #24]\n"
+ "stp x21, x22, [x1, #40]\n"
+ "stp x23, x24, [x1, #56]\n"
+ "stp x25, x26, [x1, #72]\n"
+ "stp x27, x28, [x1, #88]\n"
+ );
+
+ /* RESTORE NEW CONTEXT */
+ asm volatile (
+ /* Restore SP */
+ "ldr x3, [x0, #0]\n"
+ "mov sp, x3\n"
+
+ /* Restore FP and LR */
+ "ldp x29, x30, [x0, #8]\n"
+
+ /* Restore Callee Saved Regs x19 - x28 */
+ "ldp x19, x20, [x0, #24]\n"
+ "ldp x21, x22, [x0, #40]\n"
+ "ldp x23, x24, [x0, #56]\n"
+ "ldp x25, x26, [x0, #72]\n"
+ "ldp x27, x28, [x0, #88]\n"
+ );
+}
diff --git a/examples/performance-thread/common/arch/arm64/ctx.h b/examples/performance-thread/common/arch/arm64/ctx.h
new file mode 100644
index 000000000..27a124d1b
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.h
@@ -0,0 +1,95 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef CTX_H
+#define CTX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CPU context registers
+ */
+struct ctx {
+ void *sp; /* 0 */
+ void *fp; /* 8 */
+ void *lr; /* 16 */
+ void *r19; /* 24 */
+ void *r20; /* 32 */
+ void *r21; /* 40 */
+ void *r22; /* 48 */
+ void *r23; /* 56 */
+ void *r24; /* 64 */
+ void *r25; /* 72 */
+ void *r26; /* 80 */
+ void *r27; /* 88 */
+ void *r28; /* 96 */
+};
+
+
+void
+ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CTX_H_ */
diff --git a/examples/performance-thread/common/arch/arm64/stack.h b/examples/performance-thread/common/arch/arm64/stack.h
new file mode 100644
index 000000000..1e7c6444c
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/stack.h
@@ -0,0 +1,111 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
+
+ /*
+ * Align stack_top to 16 bytes. Arm64 has the constraint that the
+ * stack pointer must always be quad-word aligned.
+ */
+ stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
+
+ /*
+ * First Stack Frame
+ */
+ stack_top[0] = NULL;
+ stack_top[-1] = NULL;
+
+ /*
+ * Initialize the context
+ */
+ lt->ctx.fp = &stack_top[-1];
+ lt->ctx.sp = &stack_top[-2];
+
+ /*
+ * Here only the address of _lthread_exec is saved as the link
+ * register value. The argument to _lthread_exec i.e the address of
+ * the lthread struct is not saved. This is because the first
+ * argument to ctx_switch is the address of the new context,
+ * which also happens to be the address of required lthread struct.
+ * So while returning from ctx_switch into _thread_exec, parameter
+ * register x0 will always contain the required value.
+ */
+ lt->ctx.lr = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index 532dbf61d..f1f05fdde 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -39,6 +39,8 @@ MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/x86
+else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/arm64
endif
VPATH := $(MKFILE_PATH) $(ARCH_PATH)
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index 2d98473eb..3d9739e91 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -225,7 +225,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
-static __m128i val_eth[RTE_MAX_ETHPORTS];
+static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH] examples/performance-thread: add arm64 support
2017-05-18 6:35 ` Jianbo Liu
@ 2017-05-18 7:38 ` Sekhar, Ashwin
0 siblings, 0 replies; 23+ messages in thread
From: Sekhar, Ashwin @ 2017-05-18 7:38 UTC (permalink / raw)
To: Jacob, Jerin, jianbo.liu; +Cc: john.mcnamara, dev
On Thu, 2017-05-18 at 14:35 +0800, Jianbo Liu wrote:
> On 18 May 2017 at 02:44, Jerin Jacob <jerin.jacob@caviumnetworks.com>
> wrote:
> >
> > -----Original Message-----
> > >
> > > Date: Wed, 17 May 2017 11:19:49 -0700
> > > From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> > > To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
> > > jianbo.liu@linaro.org
> > > Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks
> > > .com>
> > > Subject: [dpdk-dev] [PATCH] examples/performance-thread: add
> > > arm64 support
> > > X-Mailer: git-send-email 2.12.2
> > >
> > > Updated Makefile to allow compilation for arm64 architecture.
> > >
> > > Moved the code for setting the initial stack to architecture
> > > specific
> > > directory.
> > Please split the patch to two
> > - "arch_set_stack" abstraction and associated x86 change
> > - arm64 support
> There are so many redundant code in l3fwd and l3fwd-thread, I think
> it's possible to merge them.
>
Yes. But I think its better to do them as a completely separate patch
set.
> >
> >
> > Thanks Ashwin.
> >
> > I think, This may be the last feature to make arm64 at par with x86
> > features
> > supported in DPDK.
> >
> > /Jerin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] examples/performance-thread: add arm64 support
2017-05-18 7:34 ` [PATCH v2 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
@ 2017-05-18 8:55 ` Jerin Jacob
2017-05-18 9:00 ` Sekhar, Ashwin
0 siblings, 1 reply; 23+ messages in thread
From: Jerin Jacob @ 2017-05-18 8:55 UTC (permalink / raw)
To: Ashwin Sekhar T K; +Cc: john.mcnamara, jianbo.liu, dev, halayli
-----Original Message-----
> Date: Thu, 18 May 2017 00:34:26 -0700
> From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
> jianbo.liu@linaro.org
> Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> Subject: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add arm64
> support
> X-Mailer: git-send-email 2.12.2
>
> Updated Makefile to allow compilation for arm64 architecture.
>
> Added necessary arm64 support for lthread.
>
> Fixed minor compilation errors for arm64 compilation.
>
> Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
> and x86_64.
>
> +void
> +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
> +{
> + /* SAVE CURRENT CONTEXT */
> + asm volatile (
> + /* Save SP */
> + "mov x3, sp\n"
> + "str x3, [x1, #0]\n"
> +
> + /* Save FP and LR */
> + "stp x29, x30, [x1, #8]\n"
> +
> + /* Save Callee Saved Regs x19 - x28 */
> + "stp x19, x20, [x1, #24]\n"
> + "stp x21, x22, [x1, #40]\n"
> + "stp x23, x24, [x1, #56]\n"
> + "stp x25, x26, [x1, #72]\n"
> + "stp x27, x28, [x1, #88]\n"
> + );
IMO, We need to save SIMD registers in the context as well.
x86 code also not doing that, looks like it is an obvious bug in x86 code as
well.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 2/2] examples/performance-thread: add arm64 support
2017-05-18 8:55 ` Jerin Jacob
@ 2017-05-18 9:00 ` Sekhar, Ashwin
0 siblings, 0 replies; 23+ messages in thread
From: Sekhar, Ashwin @ 2017-05-18 9:00 UTC (permalink / raw)
To: Jacob, Jerin; +Cc: john.mcnamara, halayli, jianbo.liu, dev
On Thu, 2017-05-18 at 14:25 +0530, Jerin Jacob wrote:
> -----Original Message-----
> >
> > Date: Thu, 18 May 2017 00:34:26 -0700
> > From: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
> > To: jerin.jacob@caviumnetworks.com, john.mcnamara@intel.com,
> > jianbo.liu@linaro.org
> > Cc: dev@dpdk.org, Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.c
> > om>
> > Subject: [dpdk-dev] [PATCH v2 2/2] examples/performance-thread: add
> > arm64
> > support
> > X-Mailer: git-send-email 2.12.2
> >
> > Updated Makefile to allow compilation for arm64 architecture.
> >
> > Added necessary arm64 support for lthread.
> >
> > Fixed minor compilation errors for arm64 compilation.
> >
> > Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
> > and x86_64.
> >
> > +void
> > +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx
> > __rte_unused)
> > +{
> > + /* SAVE CURRENT CONTEXT */
> > + asm volatile (
> > + /* Save SP */
> > + "mov x3, sp\n"
> > + "str x3, [x1, #0]\n"
> > +
> > + /* Save FP and LR */
> > + "stp x29, x30, [x1, #8]\n"
> > +
> > + /* Save Callee Saved Regs x19 - x28 */
> > + "stp x19, x20, [x1, #24]\n"
> > + "stp x21, x22, [x1, #40]\n"
> > + "stp x23, x24, [x1, #56]\n"
> > + "stp x25, x26, [x1, #72]\n"
> > + "stp x27, x28, [x1, #88]\n"
> > + );
> IMO, We need to save SIMD registers in the context as well.
> x86 code also not doing that, looks like it is an obvious bug in x86
> code as
> well.
>
Yes. You are correct. Need to save the bottom 64-bits of called saved
ASIMD regs v8-v15. Will update the patch.
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 0/2] examples/performance-thread: add arm64 support
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-17 18:44 ` Jerin Jacob
2017-05-18 7:34 ` [PATCH v2 0/2] " Ashwin Sekhar T K
@ 2017-05-18 10:21 ` Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 0/2] " Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
4 siblings, 2 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 10:21 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
This series of patches adds the arm64 support for performance-thread
app.
Patch 1 moves some x86 specific code to architecture dependent directory
Patch 2 adds the necessary arm64 support for lthread.
v3:
* Added save/restore of callee saved ASIMD registers in ctx_switch
v2:
* Split the patch into separate patches, one for code reorg and another
for adding arm64 support.
Ashwin Sekhar T K (2):
examples/performance-thread: reorganise arch dependent code
examples/performance-thread: add arm64 support
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 117 +++++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 110 +++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 111 +++++++++++++++++++
.../performance-thread/common/arch/x86/stack.h | 66 ++++++++++++
examples/performance-thread/common/common.mk | 10 +-
examples/performance-thread/common/lthread.c | 11 +-
examples/performance-thread/l3fwd-thread/main.c | 2 +-
8 files changed, 417 insertions(+), 14 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
--
2.12.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 1/2] examples/performance-thread: reorganise arch dependent code
2017-05-18 10:21 ` [PATCH v3 0/2] " Ashwin Sekhar T K
@ 2017-05-18 10:21 ` Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
1 sibling, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 10:21 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
Moved the architecture dependent stack set code to architecture
specific directory.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
.../performance-thread/common/arch/x86/stack.h | 66 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 8 ++-
examples/performance-thread/common/lthread.c | 11 +---
3 files changed, 74 insertions(+), 11 deletions(-)
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
diff --git a/examples/performance-thread/common/arch/x86/stack.h b/examples/performance-thread/common/arch/x86/stack.h
new file mode 100644
index 000000000..80c06bf1c
--- /dev/null
+++ b/examples/performance-thread/common/arch/x86/stack.h
@@ -0,0 +1,66 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * Copyright(c) Cavium networks Ltd. 2017.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ char *stack_top = (char *)(lt->stack) + lt->stack_size;
+ void **s = (void **)stack_top;
+
+ /* set initial context */
+ s[-3] = NULL;
+ s[-2] = (void *)lt;
+ lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
+ lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
+ lt->ctx.rip = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index f6cab7718..532dbf61d 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -37,8 +37,12 @@
MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-VPATH := $(MKFILE_PATH) $(MKFILE_PATH)/arch/x86
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/x86
+endif
+
+VPATH := $(MKFILE_PATH) $(ARCH_PATH)
SRCS-y += lthread.c lthread_sched.c lthread_cond.c lthread_tls.c lthread_mutex.c lthread_diag.c ctx.c
-INCLUDES += -I$(MKFILE_PATH) -I$(MKFILE_PATH)/arch/x86/
+INCLUDES += -I$(MKFILE_PATH) -I$(ARCH_PATH)
diff --git a/examples/performance-thread/common/lthread.c b/examples/performance-thread/common/lthread.c
index 062275a43..7d76c8c46 100644
--- a/examples/performance-thread/common/lthread.c
+++ b/examples/performance-thread/common/lthread.c
@@ -76,6 +76,7 @@
#include <rte_log.h>
#include <ctx.h>
+#include <stack.h>
#include "lthread_api.h"
#include "lthread.h"
@@ -190,19 +191,11 @@ _lthread_init(struct lthread *lt,
*/
void _lthread_set_stack(struct lthread *lt, void *stack, size_t stack_size)
{
- char *stack_top = (char *)stack + stack_size;
- void **s = (void **)stack_top;
-
/* set stack */
lt->stack = stack;
lt->stack_size = stack_size;
- /* set initial context */
- s[-3] = NULL;
- s[-2] = (void *)lt;
- lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
- lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
- lt->ctx.rip = (void *)_lthread_exec;
+ arch_set_stack(lt, _lthread_exec);
}
/*
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 2/2] examples/performance-thread: add arm64 support
2017-05-18 10:21 ` [PATCH v3 0/2] " Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
@ 2017-05-18 10:21 ` Ashwin Sekhar T K
2017-07-03 20:57 ` Thomas Monjalon
1 sibling, 1 reply; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-05-18 10:21 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu; +Cc: dev, Ashwin Sekhar T K
Updated Makefile to allow compilation for arm64 architecture.
Added necessary arm64 support for lthread.
Fixed minor compilation errors for arm64 compilation.
Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
and x86_64.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 117 +++++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 110 +++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 111 +++++++++++++++++++
examples/performance-thread/common/common.mk | 2 +
examples/performance-thread/l3fwd-thread/main.c | 2 +-
6 files changed, 343 insertions(+), 3 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
diff --git a/examples/performance-thread/Makefile b/examples/performance-thread/Makefile
index d19f8489e..0c5edfdb9 100644
--- a/examples/performance-thread/Makefile
+++ b/examples/performance-thread/Makefile
@@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
-ifneq ($(CONFIG_RTE_ARCH),"x86_64")
-$(error This application is only supported for x86_64 targets)
+ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
+$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread
diff --git a/examples/performance-thread/common/arch/arm64/ctx.c b/examples/performance-thread/common/arch/arm64/ctx.c
new file mode 100644
index 000000000..95ce16095
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.c
@@ -0,0 +1,117 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <rte_common.h>
+#include <ctx.h>
+
+void
+ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
+{
+ /* SAVE CURRENT CONTEXT */
+ asm volatile (
+ /* Save SP */
+ "mov x3, sp\n"
+ "str x3, [x1, #0]\n"
+
+ /* Save FP and LR */
+ "stp x29, x30, [x1, #8]\n"
+
+ /* Save Callee Saved Regs x19 - x28 */
+ "stp x19, x20, [x1, #24]\n"
+ "stp x21, x22, [x1, #40]\n"
+ "stp x23, x24, [x1, #56]\n"
+ "stp x25, x26, [x1, #72]\n"
+ "stp x27, x28, [x1, #88]\n"
+
+ /*
+ * Save bottom 64-bits of Callee Saved
+ * SIMD Regs v8 - v15
+ */
+ "stp d8, d9, [x1, #104]\n"
+ "stp d10, d11, [x1, #120]\n"
+ "stp d12, d13, [x1, #136]\n"
+ "stp d14, d15, [x1, #152]\n"
+ );
+
+ /* RESTORE NEW CONTEXT */
+ asm volatile (
+ /* Restore SP */
+ "ldr x3, [x0, #0]\n"
+ "mov sp, x3\n"
+
+ /* Restore FP and LR */
+ "ldp x29, x30, [x0, #8]\n"
+
+ /* Restore Callee Saved Regs x19 - x28 */
+ "ldp x19, x20, [x0, #24]\n"
+ "ldp x21, x22, [x0, #40]\n"
+ "ldp x23, x24, [x0, #56]\n"
+ "ldp x25, x26, [x0, #72]\n"
+ "ldp x27, x28, [x0, #88]\n"
+
+ /*
+ * Restore bottom 64-bits of Callee Saved
+ * SIMD Regs v8 - v15
+ */
+ "ldp d8, d9, [x0, #104]\n"
+ "ldp d10, d11, [x0, #120]\n"
+ "ldp d12, d13, [x0, #136]\n"
+ "ldp d14, d15, [x0, #152]\n"
+ );
+}
diff --git a/examples/performance-thread/common/arch/arm64/ctx.h b/examples/performance-thread/common/arch/arm64/ctx.h
new file mode 100644
index 000000000..2905990b2
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.h
@@ -0,0 +1,110 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef CTX_H
+#define CTX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CPU context registers
+ */
+struct ctx {
+ void *sp; /* 0 */
+ void *fp; /* 8 */
+ void *lr; /* 16 */
+
+ /* Callee Saved Generic Registers */
+ void *r19; /* 24 */
+ void *r20; /* 32 */
+ void *r21; /* 40 */
+ void *r22; /* 48 */
+ void *r23; /* 56 */
+ void *r24; /* 64 */
+ void *r25; /* 72 */
+ void *r26; /* 80 */
+ void *r27; /* 88 */
+ void *r28; /* 96 */
+
+ /*
+ * Callee Saved SIMD Registers. Only the bottom 64-bits
+ * of these registers needs to be saved.
+ */
+ void *v8; /* 104 */
+ void *v9; /* 112 */
+ void *v10; /* 120 */
+ void *v11; /* 128 */
+ void *v12; /* 136 */
+ void *v13; /* 144 */
+ void *v14; /* 152 */
+ void *v15; /* 160 */
+};
+
+
+void
+ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CTX_H_ */
diff --git a/examples/performance-thread/common/arch/arm64/stack.h b/examples/performance-thread/common/arch/arm64/stack.h
new file mode 100644
index 000000000..1e7c6444c
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/stack.h
@@ -0,0 +1,111 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * https://github.com/halayli/lthread which carries the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
+
+ /*
+ * Align stack_top to 16 bytes. Arm64 has the constraint that the
+ * stack pointer must always be quad-word aligned.
+ */
+ stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
+
+ /*
+ * First Stack Frame
+ */
+ stack_top[0] = NULL;
+ stack_top[-1] = NULL;
+
+ /*
+ * Initialize the context
+ */
+ lt->ctx.fp = &stack_top[-1];
+ lt->ctx.sp = &stack_top[-2];
+
+ /*
+ * Here only the address of _lthread_exec is saved as the link
+ * register value. The argument to _lthread_exec i.e the address of
+ * the lthread struct is not saved. This is because the first
+ * argument to ctx_switch is the address of the new context,
+ * which also happens to be the address of required lthread struct.
+ * So while returning from ctx_switch into _thread_exec, parameter
+ * register x0 will always contain the required value.
+ */
+ lt->ctx.lr = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index 532dbf61d..f1f05fdde 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -39,6 +39,8 @@ MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/x86
+else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/arm64
endif
VPATH := $(MKFILE_PATH) $(ARCH_PATH)
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index 2d98473eb..3d9739e91 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -225,7 +225,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
-static __m128i val_eth[RTE_MAX_ETHPORTS];
+static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] examples/performance-thread: add arm64 support
2017-05-18 10:21 ` [PATCH v3 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
@ 2017-07-03 20:57 ` Thomas Monjalon
2017-07-03 21:21 ` O'Driscoll, Tim
0 siblings, 1 reply; 23+ messages in thread
From: Thomas Monjalon @ 2017-07-03 20:57 UTC (permalink / raw)
To: Ashwin Sekhar T K
Cc: dev, jerin.jacob, john.mcnamara, jianbo.liu, techboard, govboard
There can be a licensing issue here.
We may need advice from the Governing Board and the Technical Board.
18/05/2017 12:21, Ashwin Sekhar T K:
> +/*
> + * https://github.com/halayli/lthread which carries the following license.
> + *
> + * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] examples/performance-thread: add arm64 support
2017-07-03 20:57 ` Thomas Monjalon
@ 2017-07-03 21:21 ` O'Driscoll, Tim
2017-07-04 7:37 ` Sekhar, Ashwin
0 siblings, 1 reply; 23+ messages in thread
From: O'Driscoll, Tim @ 2017-07-03 21:21 UTC (permalink / raw)
To: Thomas Monjalon, Ashwin Sekhar T K
Cc: dev, jerin.jacob, Mcnamara, John, jianbo.liu, techboard, govboard
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Thomas Monjalon
>
> There can be a licensing issue here.
> We may need advice from the Governing Board and the Technical Board.
That's correct. This uses a 2-clause BSD license, but the Intellectual Property Policy section in the Project Charter (http://dpdk.org/about/charter#ip) specifies 3-clause BSD. If you really need to use a new license, then you'll need to make a request to the Governing Board as specified in clause 6.c in the charter.
>
> 18/05/2017 12:21, Ashwin Sekhar T K:
> > +/*
> > + * https://github.com/halayli/lthread which carries the following
> license.
> > + *
> > + * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + * 1. Redistributions of source code must retain the above copyright
> > + * notice, this list of conditions and the following disclaimer.
> > + * 2. Redistributions in binary form must reproduce the above
> copyright
> > + * notice, this list of conditions and the following disclaimer in
> the
> > + * documentation and/or other materials provided with the
> distribution.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> > + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
> THE
> > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
> PURPOSE
> > + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE
> LIABLE
> > + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> CONSEQUENTIAL
> > + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
> GOODS
> > + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> INTERRUPTION)
> > + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> CONTRACT, STRICT
> > + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
> ANY WAY
> > + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> POSSIBILITY OF
> > + * SUCH DAMAGE.
> > + */
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] examples/performance-thread: add arm64 support
2017-07-03 21:21 ` O'Driscoll, Tim
@ 2017-07-04 7:37 ` Sekhar, Ashwin
2017-07-04 14:02 ` O'Driscoll, Tim
0 siblings, 1 reply; 23+ messages in thread
From: Sekhar, Ashwin @ 2017-07-04 7:37 UTC (permalink / raw)
To: thomas, tim.odriscoll
Cc: john.mcnamara, govboard, Jacob, Jerin, techboard, dev, jianbo.liu
This license is already there in many files in examples/performance-
thread directory.
There are two cases in my patch.
1.
I moved some code from examples/performance-thread/common/lthread.c to
examples/performance-thread/common/arch/x86/stack.h.
lthread.c already has the below kind of license. So I think there is no
issue retaining the same in stack.h also.
2.
I added the following files.
examples/performance-thread/common/arch/arm64/ctx.c
examples/performance-thread/common/arch/arm64/ctx.h
examples/performance-thread/common/arch/arm64/stack.h
These are actually written by me and not taken from the github link.
By mistake I copied the license entirely :)
For these files, I shall remove it and re-post a v3.
Thanks
Ashwin
On Mon, 2017-07-03 at 21:21 +0000, O'Driscoll, Tim wrote:
> >
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Thomas
> > Monjalon
> >
> > There can be a licensing issue here.
> > We may need advice from the Governing Board and the Technical
> > Board.
> That's correct. This uses a 2-clause BSD license, but the
> Intellectual Property Policy section in the Project Charter (http://d
> pdk.org/about/charter#ip) specifies 3-clause BSD. If you really need
> to use a new license, then you'll need to make a request to the
> Governing Board as specified in clause 6.c in the charter.
>
> >
> >
> > 18/05/2017 12:21, Ashwin Sekhar T K:
> > >
> > > +/*
> > > + * https://github.com/halayli/lthread which carries the
> > > following
> > license.
> > >
> > > + *
> > > + * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
> > > + *
> > > + * Redistribution and use in source and binary forms, with or
> > > without
> > > + * modification, are permitted provided that the following
> > > conditions
> > > + * are met:
> > > + * 1. Redistributions of source code must retain the above
> > > copyright
> > > + * notice, this list of conditions and the following
> > > disclaimer.
> > > + * 2. Redistributions in binary form must reproduce the above
> > copyright
> > >
> > > + * notice, this list of conditions and the following
> > > disclaimer in
> > the
> > >
> > > + * documentation and/or other materials provided with the
> > distribution.
> > >
> > > + *
> > > + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS
> > > IS'' AND
> > > + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> > > TO,
> > THE
> > >
> > > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> > > PARTICULAR
> > PURPOSE
> > >
> > > + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE
> > LIABLE
> > >
> > > + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> > CONSEQUENTIAL
> > >
> > > + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> > > SUBSTITUTE
> > GOODS
> > >
> > > + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> > INTERRUPTION)
> > >
> > > + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> > CONTRACT, STRICT
> > >
> > > + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> > > ARISING IN
> > ANY WAY
> > >
> > > + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> > POSSIBILITY OF
> > >
> > > + * SUCH DAMAGE.
> > > + */
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 0/2] examples/performance-thread: add arm64 support
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
` (2 preceding siblings ...)
2017-05-18 10:21 ` [PATCH v3 0/2] " Ashwin Sekhar T K
@ 2017-07-04 8:05 ` Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
4 siblings, 2 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:05 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll, techboard,
govboard
Cc: dev, Ashwin Sekhar T K
This series of patches adds the arm64 support for performance-thread
app.
Patch 1 moves some x86 specific code to architecture dependent directory
Patch 2 adds the necessary arm64 support for lthread.
v4:
* Added the 2-clause license to examples/performance-thread/common/arch/x86/stack.h
as this file contains the code moved from examples/performance-thread/common/lthread.c
which already has this license.
* Removed the 2-clause license from newly added aarch64 files as these code are
not taken from the github link mentioned in the 2-clause license.
v3:
* Added save/restore of callee saved ASIMD registers in ctx_switch
v2:
* Split the patch into separate patches, one for code reorg and another
for adding arm64 support.
Ashwin Sekhar T K (2):
examples/performance-thread: reorganise arch dependent code
examples/performance-thread: add arm64 support
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 72 +++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 68 ++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 84 +++++++++++++++++++
.../performance-thread/common/arch/x86/stack.h | 94 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 10 ++-
examples/performance-thread/common/lthread.c | 11 +--
examples/performance-thread/l3fwd-thread/main.c | 2 +-
8 files changed, 331 insertions(+), 14 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
--
2.12.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 1/2] examples/performance-thread: reorganise arch dependent code
2017-07-04 8:05 ` [PATCH v4 0/2] " Ashwin Sekhar T K
@ 2017-07-04 8:05 ` Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
1 sibling, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:05 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll, techboard,
govboard
Cc: dev, Ashwin Sekhar T K
Moved the architecture dependent stack set code to architecture
specific directory.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
.../performance-thread/common/arch/x86/stack.h | 94 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 8 +-
examples/performance-thread/common/lthread.c | 11 +--
3 files changed, 102 insertions(+), 11 deletions(-)
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
diff --git a/examples/performance-thread/common/arch/x86/stack.h b/examples/performance-thread/common/arch/x86/stack.h
new file mode 100644
index 000000000..adb8e4fc2
--- /dev/null
+++ b/examples/performance-thread/common/arch/x86/stack.h
@@ -0,0 +1,94 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * Copyright(c) Cavium networks Ltd. 2017.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Some portions of this software is derived from the
+ * https://github.com/halayli/lthread which carrys the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ char *stack_top = (char *)(lt->stack) + lt->stack_size;
+ void **s = (void **)stack_top;
+
+ /* set initial context */
+ s[-3] = NULL;
+ s[-2] = (void *)lt;
+ lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
+ lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
+ lt->ctx.rip = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index f6cab7718..532dbf61d 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -37,8 +37,12 @@
MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-VPATH := $(MKFILE_PATH) $(MKFILE_PATH)/arch/x86
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/x86
+endif
+
+VPATH := $(MKFILE_PATH) $(ARCH_PATH)
SRCS-y += lthread.c lthread_sched.c lthread_cond.c lthread_tls.c lthread_mutex.c lthread_diag.c ctx.c
-INCLUDES += -I$(MKFILE_PATH) -I$(MKFILE_PATH)/arch/x86/
+INCLUDES += -I$(MKFILE_PATH) -I$(ARCH_PATH)
diff --git a/examples/performance-thread/common/lthread.c b/examples/performance-thread/common/lthread.c
index 062275a43..7d76c8c46 100644
--- a/examples/performance-thread/common/lthread.c
+++ b/examples/performance-thread/common/lthread.c
@@ -76,6 +76,7 @@
#include <rte_log.h>
#include <ctx.h>
+#include <stack.h>
#include "lthread_api.h"
#include "lthread.h"
@@ -190,19 +191,11 @@ _lthread_init(struct lthread *lt,
*/
void _lthread_set_stack(struct lthread *lt, void *stack, size_t stack_size)
{
- char *stack_top = (char *)stack + stack_size;
- void **s = (void **)stack_top;
-
/* set stack */
lt->stack = stack;
lt->stack_size = stack_size;
- /* set initial context */
- s[-3] = NULL;
- s[-2] = (void *)lt;
- lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
- lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
- lt->ctx.rip = (void *)_lthread_exec;
+ arch_set_stack(lt, _lthread_exec);
}
/*
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 2/2] examples/performance-thread: add arm64 support
2017-07-04 8:05 ` [PATCH v4 0/2] " Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
@ 2017-07-04 8:05 ` Ashwin Sekhar T K
1 sibling, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:05 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll, techboard,
govboard
Cc: dev, Ashwin Sekhar T K
Updated Makefile to allow compilation for arm64 architecture.
Added necessary arm64 support for lthread.
Fixed minor compilation errors for arm64 compilation.
Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
and x86_64.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 72 +++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 68 ++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 84 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 2 +
examples/performance-thread/l3fwd-thread/main.c | 2 +-
6 files changed, 229 insertions(+), 3 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
diff --git a/examples/performance-thread/Makefile b/examples/performance-thread/Makefile
index d19f8489e..0c5edfdb9 100644
--- a/examples/performance-thread/Makefile
+++ b/examples/performance-thread/Makefile
@@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
-ifneq ($(CONFIG_RTE_ARCH),"x86_64")
-$(error This application is only supported for x86_64 targets)
+ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
+$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread
diff --git a/examples/performance-thread/common/arch/arm64/ctx.c b/examples/performance-thread/common/arch/arm64/ctx.c
new file mode 100644
index 000000000..1c0424eba
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.c
@@ -0,0 +1,72 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rte_common.h>
+#include <ctx.h>
+
+void
+ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
+{
+ /* SAVE CURRENT CONTEXT */
+ asm volatile (
+ /* Save SP */
+ "mov x3, sp\n"
+ "str x3, [x1, #0]\n"
+
+ /* Save FP and LR */
+ "stp x29, x30, [x1, #8]\n"
+
+ /* Save Callee Saved Regs x19 - x28 */
+ "stp x19, x20, [x1, #24]\n"
+ "stp x21, x22, [x1, #40]\n"
+ "stp x23, x24, [x1, #56]\n"
+ "stp x25, x26, [x1, #72]\n"
+ "stp x27, x28, [x1, #88]\n"
+ );
+
+ /* RESTORE NEW CONTEXT */
+ asm volatile (
+ /* Restore SP */
+ "ldr x3, [x0, #0]\n"
+ "mov sp, x3\n"
+
+ /* Restore FP and LR */
+ "ldp x29, x30, [x0, #8]\n"
+
+ /* Restore Callee Saved Regs x19 - x28 */
+ "ldp x19, x20, [x0, #24]\n"
+ "ldp x21, x22, [x0, #40]\n"
+ "ldp x23, x24, [x0, #56]\n"
+ "ldp x25, x26, [x0, #72]\n"
+ "ldp x27, x28, [x0, #88]\n"
+ );
+}
diff --git a/examples/performance-thread/common/arch/arm64/ctx.h b/examples/performance-thread/common/arch/arm64/ctx.h
new file mode 100644
index 000000000..a9e0b744e
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.h
@@ -0,0 +1,68 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CTX_H
+#define CTX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CPU context registers
+ */
+struct ctx {
+ void *sp; /* 0 */
+ void *fp; /* 8 */
+ void *lr; /* 16 */
+ void *r19; /* 24 */
+ void *r20; /* 32 */
+ void *r21; /* 40 */
+ void *r22; /* 48 */
+ void *r23; /* 56 */
+ void *r24; /* 64 */
+ void *r25; /* 72 */
+ void *r26; /* 80 */
+ void *r27; /* 88 */
+ void *r28; /* 96 */
+};
+
+
+void
+ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CTX_H_ */
diff --git a/examples/performance-thread/common/arch/arm64/stack.h b/examples/performance-thread/common/arch/arm64/stack.h
new file mode 100644
index 000000000..98bbef888
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/stack.h
@@ -0,0 +1,84 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
+
+ /*
+ * Align stack_top to 16 bytes. Arm64 has the constraint that the
+ * stack pointer must always be quad-word aligned.
+ */
+ stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
+
+ /*
+ * First Stack Frame
+ */
+ stack_top[0] = NULL;
+ stack_top[-1] = NULL;
+
+ /*
+ * Initialize the context
+ */
+ lt->ctx.fp = &stack_top[-1];
+ lt->ctx.sp = &stack_top[-2];
+
+ /*
+ * Here only the address of _lthread_exec is saved as the link
+ * register value. The argument to _lthread_exec i.e the address of
+ * the lthread struct is not saved. This is because the first
+ * argument to ctx_switch is the address of the new context,
+ * which also happens to be the address of required lthread struct.
+ * So while returning from ctx_switch into _thread_exec, parameter
+ * register x0 will always contain the required value.
+ */
+ lt->ctx.lr = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index 532dbf61d..f1f05fdde 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -39,6 +39,8 @@ MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/x86
+else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/arm64
endif
VPATH := $(MKFILE_PATH) $(ARCH_PATH)
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index fb847d13e..69734c24a 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -226,7 +226,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
-static __m128i val_eth[RTE_MAX_ETHPORTS];
+static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 0/2] examples/performance-thread: add arm64 support
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
` (3 preceding siblings ...)
2017-07-04 8:05 ` [PATCH v4 0/2] " Ashwin Sekhar T K
@ 2017-07-04 8:22 ` Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
` (2 more replies)
4 siblings, 3 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:22 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll
Cc: dev, Ashwin Sekhar T K
This series of patches adds the arm64 support for performance-thread
app.
Patch 1 moves some x86 specific code to architecture dependent directory
Patch 2 adds the necessary arm64 support for lthread.
v5:
* Added back the save/restore of callee saved ASIMD registers in ctx_switch.
This was omitted by mistake in v4.
v4:
* Added the 2-clause license to examples/performance-thread/common/arch/x86/stack.h
as this file contains the code moved from examples/performance-thread/common/lthread.c
which already has this license.
* Removed the 2-clause license from newly added aarch64 files as these code are
not taken from the github link mentioned in the 2-clause license.
v3:
* Added save/restore of callee saved ASIMD registers in ctx_switch
v2:
* Split the patch into separate patches, one for code reorg and another
for adding arm64 support.
Ashwin Sekhar T K (2):
examples/performance-thread: reorganise arch dependent code
examples/performance-thread: add arm64 support
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 90 +++++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 83 +++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 84 +++++++++++++++++++
.../performance-thread/common/arch/x86/stack.h | 94 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 10 ++-
examples/performance-thread/common/lthread.c | 11 +--
examples/performance-thread/l3fwd-thread/main.c | 2 +-
8 files changed, 364 insertions(+), 14 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
--
2.12.2
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
@ 2017-07-04 8:22 ` Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 13:20 ` [PATCH v5 0/2] " Thomas Monjalon
2 siblings, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:22 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll
Cc: dev, Ashwin Sekhar T K
Moved the architecture dependent stack set code to architecture
specific directory.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
.../performance-thread/common/arch/x86/stack.h | 94 ++++++++++++++++++++++
examples/performance-thread/common/common.mk | 8 +-
examples/performance-thread/common/lthread.c | 11 +--
3 files changed, 102 insertions(+), 11 deletions(-)
create mode 100644 examples/performance-thread/common/arch/x86/stack.h
diff --git a/examples/performance-thread/common/arch/x86/stack.h b/examples/performance-thread/common/arch/x86/stack.h
new file mode 100644
index 000000000..adb8e4fc2
--- /dev/null
+++ b/examples/performance-thread/common/arch/x86/stack.h
@@ -0,0 +1,94 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * Copyright(c) Cavium networks Ltd. 2017.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Some portions of this software is derived from the
+ * https://github.com/halayli/lthread which carrys the following license.
+ *
+ * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ char *stack_top = (char *)(lt->stack) + lt->stack_size;
+ void **s = (void **)stack_top;
+
+ /* set initial context */
+ s[-3] = NULL;
+ s[-2] = (void *)lt;
+ lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
+ lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
+ lt->ctx.rip = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index f6cab7718..532dbf61d 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -37,8 +37,12 @@
MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
-VPATH := $(MKFILE_PATH) $(MKFILE_PATH)/arch/x86
+ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/x86
+endif
+
+VPATH := $(MKFILE_PATH) $(ARCH_PATH)
SRCS-y += lthread.c lthread_sched.c lthread_cond.c lthread_tls.c lthread_mutex.c lthread_diag.c ctx.c
-INCLUDES += -I$(MKFILE_PATH) -I$(MKFILE_PATH)/arch/x86/
+INCLUDES += -I$(MKFILE_PATH) -I$(ARCH_PATH)
diff --git a/examples/performance-thread/common/lthread.c b/examples/performance-thread/common/lthread.c
index 062275a43..7d76c8c46 100644
--- a/examples/performance-thread/common/lthread.c
+++ b/examples/performance-thread/common/lthread.c
@@ -76,6 +76,7 @@
#include <rte_log.h>
#include <ctx.h>
+#include <stack.h>
#include "lthread_api.h"
#include "lthread.h"
@@ -190,19 +191,11 @@ _lthread_init(struct lthread *lt,
*/
void _lthread_set_stack(struct lthread *lt, void *stack, size_t stack_size)
{
- char *stack_top = (char *)stack + stack_size;
- void **s = (void **)stack_top;
-
/* set stack */
lt->stack = stack;
lt->stack_size = stack_size;
- /* set initial context */
- s[-3] = NULL;
- s[-2] = (void *)lt;
- lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *)));
- lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *)));
- lt->ctx.rip = (void *)_lthread_exec;
+ arch_set_stack(lt, _lthread_exec);
}
/*
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v5 2/2] examples/performance-thread: add arm64 support
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
@ 2017-07-04 8:22 ` Ashwin Sekhar T K
2017-07-04 13:20 ` [PATCH v5 0/2] " Thomas Monjalon
2 siblings, 0 replies; 23+ messages in thread
From: Ashwin Sekhar T K @ 2017-07-04 8:22 UTC (permalink / raw)
To: jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll
Cc: dev, Ashwin Sekhar T K
Updated Makefile to allow compilation for arm64 architecture.
Added necessary arm64 support for lthread.
Fixed minor compilation errors for arm64 compilation.
Tested the apps l3fwd-thread and lthread_pthread_shim on thunderx
and x86_64.
Signed-off-by: Ashwin Sekhar T K <ashwin.sekhar@caviumnetworks.com>
---
examples/performance-thread/Makefile | 4 +-
.../performance-thread/common/arch/arm64/ctx.c | 90 ++++++++++++++++++++++
.../performance-thread/common/arch/arm64/ctx.h | 83 ++++++++++++++++++++
.../performance-thread/common/arch/arm64/stack.h | 84 ++++++++++++++++++++
examples/performance-thread/common/common.mk | 2 +
examples/performance-thread/l3fwd-thread/main.c | 2 +-
6 files changed, 262 insertions(+), 3 deletions(-)
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.c
create mode 100644 examples/performance-thread/common/arch/arm64/ctx.h
create mode 100644 examples/performance-thread/common/arch/arm64/stack.h
diff --git a/examples/performance-thread/Makefile b/examples/performance-thread/Makefile
index d19f8489e..0c5edfdb9 100644
--- a/examples/performance-thread/Makefile
+++ b/examples/performance-thread/Makefile
@@ -38,8 +38,8 @@ RTE_TARGET ?= x86_64-native-linuxapp-gcc
include $(RTE_SDK)/mk/rte.vars.mk
-ifneq ($(CONFIG_RTE_ARCH),"x86_64")
-$(error This application is only supported for x86_64 targets)
+ifeq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) $(CONFIG_RTE_ARCH_ARM64)),)
+$(error This application is only supported for x86_64 and arm64 targets)
endif
DIRS-y += l3fwd-thread
diff --git a/examples/performance-thread/common/arch/arm64/ctx.c b/examples/performance-thread/common/arch/arm64/ctx.c
new file mode 100644
index 000000000..1b38b63f0
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.c
@@ -0,0 +1,90 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rte_common.h>
+#include <ctx.h>
+
+void
+ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused)
+{
+ /* SAVE CURRENT CONTEXT */
+ asm volatile (
+ /* Save SP */
+ "mov x3, sp\n"
+ "str x3, [x1, #0]\n"
+
+ /* Save FP and LR */
+ "stp x29, x30, [x1, #8]\n"
+
+ /* Save Callee Saved Regs x19 - x28 */
+ "stp x19, x20, [x1, #24]\n"
+ "stp x21, x22, [x1, #40]\n"
+ "stp x23, x24, [x1, #56]\n"
+ "stp x25, x26, [x1, #72]\n"
+ "stp x27, x28, [x1, #88]\n"
+
+ /*
+ * Save bottom 64-bits of Callee Saved
+ * SIMD Regs v8 - v15
+ */
+ "stp d8, d9, [x1, #104]\n"
+ "stp d10, d11, [x1, #120]\n"
+ "stp d12, d13, [x1, #136]\n"
+ "stp d14, d15, [x1, #152]\n"
+ );
+
+ /* RESTORE NEW CONTEXT */
+ asm volatile (
+ /* Restore SP */
+ "ldr x3, [x0, #0]\n"
+ "mov sp, x3\n"
+
+ /* Restore FP and LR */
+ "ldp x29, x30, [x0, #8]\n"
+
+ /* Restore Callee Saved Regs x19 - x28 */
+ "ldp x19, x20, [x0, #24]\n"
+ "ldp x21, x22, [x0, #40]\n"
+ "ldp x23, x24, [x0, #56]\n"
+ "ldp x25, x26, [x0, #72]\n"
+ "ldp x27, x28, [x0, #88]\n"
+
+ /*
+ * Restore bottom 64-bits of Callee Saved
+ * SIMD Regs v8 - v15
+ */
+ "ldp d8, d9, [x0, #104]\n"
+ "ldp d10, d11, [x0, #120]\n"
+ "ldp d12, d13, [x0, #136]\n"
+ "ldp d14, d15, [x0, #152]\n"
+ );
+}
diff --git a/examples/performance-thread/common/arch/arm64/ctx.h b/examples/performance-thread/common/arch/arm64/ctx.h
new file mode 100644
index 000000000..996922b58
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/ctx.h
@@ -0,0 +1,83 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CTX_H
+#define CTX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CPU context registers
+ */
+struct ctx {
+ void *sp; /* 0 */
+ void *fp; /* 8 */
+ void *lr; /* 16 */
+
+ /* Callee Saved Generic Registers */
+ void *r19; /* 24 */
+ void *r20; /* 32 */
+ void *r21; /* 40 */
+ void *r22; /* 48 */
+ void *r23; /* 56 */
+ void *r24; /* 64 */
+ void *r25; /* 72 */
+ void *r26; /* 80 */
+ void *r27; /* 88 */
+ void *r28; /* 96 */
+
+ /*
+ * Callee Saved SIMD Registers. Only the bottom 64-bits
+ * of these registers needs to be saved.
+ */
+ void *v8; /* 104 */
+ void *v9; /* 112 */
+ void *v10; /* 120 */
+ void *v11; /* 128 */
+ void *v12; /* 136 */
+ void *v13; /* 144 */
+ void *v14; /* 152 */
+ void *v15; /* 160 */
+};
+
+
+void
+ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CTX_H_ */
diff --git a/examples/performance-thread/common/arch/arm64/stack.h b/examples/performance-thread/common/arch/arm64/stack.h
new file mode 100644
index 000000000..98bbef888
--- /dev/null
+++ b/examples/performance-thread/common/arch/arm64/stack.h
@@ -0,0 +1,84 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright (C) Cavium networks Ltd. 2017.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Cavium networks nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef STACK_H
+#define STACK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lthread_int.h"
+
+/*
+ * Sets up the initial stack for the lthread.
+ */
+static inline void
+arch_set_stack(struct lthread *lt, void *func)
+{
+ void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
+
+ /*
+ * Align stack_top to 16 bytes. Arm64 has the constraint that the
+ * stack pointer must always be quad-word aligned.
+ */
+ stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
+
+ /*
+ * First Stack Frame
+ */
+ stack_top[0] = NULL;
+ stack_top[-1] = NULL;
+
+ /*
+ * Initialize the context
+ */
+ lt->ctx.fp = &stack_top[-1];
+ lt->ctx.sp = &stack_top[-2];
+
+ /*
+ * Here only the address of _lthread_exec is saved as the link
+ * register value. The argument to _lthread_exec i.e the address of
+ * the lthread struct is not saved. This is because the first
+ * argument to ctx_switch is the address of the new context,
+ * which also happens to be the address of required lthread struct.
+ * So while returning from ctx_switch into _thread_exec, parameter
+ * register x0 will always contain the required value.
+ */
+ lt->ctx.lr = func;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STACK_H_ */
diff --git a/examples/performance-thread/common/common.mk b/examples/performance-thread/common/common.mk
index 532dbf61d..f1f05fdde 100644
--- a/examples/performance-thread/common/common.mk
+++ b/examples/performance-thread/common/common.mk
@@ -39,6 +39,8 @@ MKFILE_PATH=$(abspath $(dir $(lastword $(MAKEFILE_LIST))))
ifeq ($(CONFIG_RTE_ARCH_X86_64),y)
ARCH_PATH += $(MKFILE_PATH)/arch/x86
+else ifeq ($(CONFIG_RTE_ARCH_ARM64),y)
+ARCH_PATH += $(MKFILE_PATH)/arch/arm64
endif
VPATH := $(MKFILE_PATH) $(ARCH_PATH)
diff --git a/examples/performance-thread/l3fwd-thread/main.c b/examples/performance-thread/l3fwd-thread/main.c
index fb847d13e..69734c24a 100644
--- a/examples/performance-thread/l3fwd-thread/main.c
+++ b/examples/performance-thread/l3fwd-thread/main.c
@@ -226,7 +226,7 @@ static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
static uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];
static struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
-static __m128i val_eth[RTE_MAX_ETHPORTS];
+static xmm_t val_eth[RTE_MAX_ETHPORTS];
/* replace first 12B of the ethernet header. */
#define MASK_ETH 0x3f
--
2.12.2
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v5 0/2] examples/performance-thread: add arm64 support
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
@ 2017-07-04 13:20 ` Thomas Monjalon
2 siblings, 0 replies; 23+ messages in thread
From: Thomas Monjalon @ 2017-07-04 13:20 UTC (permalink / raw)
To: Ashwin Sekhar T K
Cc: dev, jerin.jacob, john.mcnamara, jianbo.liu, tim.odriscoll
> Ashwin Sekhar T K (2):
> examples/performance-thread: reorganise arch dependent code
> examples/performance-thread: add arm64 support
Applied, thanks
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] examples/performance-thread: add arm64 support
2017-07-04 7:37 ` Sekhar, Ashwin
@ 2017-07-04 14:02 ` O'Driscoll, Tim
0 siblings, 0 replies; 23+ messages in thread
From: O'Driscoll, Tim @ 2017-07-04 14:02 UTC (permalink / raw)
To: Sekhar, Ashwin, thomas
Cc: Mcnamara, John, govboard, Jacob, Jerin, techboard, dev, jianbo.liu
> From: Sekhar, Ashwin [mailto:Ashwin.Sekhar@cavium.com]
>
> This license is already there in many files in examples/performance-
> thread directory.
>
> There are two cases in my patch.
>
> 1.
> I moved some code from examples/performance-thread/common/lthread.c to
> examples/performance-thread/common/arch/x86/stack.h.
> lthread.c already has the below kind of license. So I think there is no
> issue retaining the same in stack.h also.
That sounds reasonable to me. IANAL, but I don't understand the license in the performance-thread example. It uses BSD 3-clause but references some code that was originally released under BSD 2-clause. It doesn't state that it's dual-licensed, and as far as I know, wasn't re-licensed by the original copyright holder. Anyway, that's an existing problem and not something created by your changes. We'll need to look into it and probably update the IP section of the Project Charter to reflect this.
>
> 2.
> I added the following files.
> examples/performance-thread/common/arch/arm64/ctx.c
> examples/performance-thread/common/arch/arm64/ctx.h
> examples/performance-thread/common/arch/arm64/stack.h
>
> These are actually written by me and not taken from the github link.
> By mistake I copied the license entirely :)
>
> For these files, I shall remove it and re-post a v3.
>
> Thanks
> Ashwin
>
>
> On Mon, 2017-07-03 at 21:21 +0000, O'Driscoll, Tim wrote:
> > >
> > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Thomas
> > > Monjalon
> > >
> > > There can be a licensing issue here.
> > > We may need advice from the Governing Board and the Technical
> > > Board.
> > That's correct. This uses a 2-clause BSD license, but the
> > Intellectual Property Policy section in the Project Charter (http://d
> > pdk.org/about/charter#ip) specifies 3-clause BSD. If you really need
> > to use a new license, then you'll need to make a request to the
> > Governing Board as specified in clause 6.c in the charter.
> >
> > >
> > >
> > > 18/05/2017 12:21, Ashwin Sekhar T K:
> > > >
> > > > +/*
> > > > + * https://github.com/halayli/lthread which carries the
> > > > following
> > > license.
> > > >
> > > > + *
> > > > + * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com>
> > > > + *
> > > > + * Redistribution and use in source and binary forms, with or
> > > > without
> > > > + * modification, are permitted provided that the following
> > > > conditions
> > > > + * are met:
> > > > + * 1. Redistributions of source code must retain the above
> > > > copyright
> > > > + * notice, this list of conditions and the following
> > > > disclaimer.
> > > > + * 2. Redistributions in binary form must reproduce the above
> > > copyright
> > > >
> > > > + * notice, this list of conditions and the following
> > > > disclaimer in
> > > the
> > > >
> > > > + * documentation and/or other materials provided with the
> > > distribution.
> > > >
> > > > + *
> > > > + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS
> > > > IS'' AND
> > > > + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> > > > TO,
> > > THE
> > > >
> > > > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> > > > PARTICULAR
> > > PURPOSE
> > > >
> > > > + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE
> > > LIABLE
> > > >
> > > > + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> > > CONSEQUENTIAL
> > > >
> > > > + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> > > > SUBSTITUTE
> > > GOODS
> > > >
> > > > + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> > > INTERRUPTION)
> > > >
> > > > + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> > > CONTRACT, STRICT
> > > >
> > > > + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> > > > ARISING IN
> > > ANY WAY
> > > >
> > > > + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
> > > POSSIBILITY OF
> > > >
> > > > + * SUCH DAMAGE.
> > > > + */
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2017-07-04 14:02 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-17 18:19 [PATCH] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-17 18:44 ` Jerin Jacob
2017-05-18 6:35 ` Jianbo Liu
2017-05-18 7:38 ` Sekhar, Ashwin
2017-05-18 7:34 ` [PATCH v2 0/2] " Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 7:34 ` [PATCH v2 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-05-18 8:55 ` Jerin Jacob
2017-05-18 9:00 ` Sekhar, Ashwin
2017-05-18 10:21 ` [PATCH v3 0/2] " Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-05-18 10:21 ` [PATCH v3 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-03 20:57 ` Thomas Monjalon
2017-07-03 21:21 ` O'Driscoll, Tim
2017-07-04 7:37 ` Sekhar, Ashwin
2017-07-04 14:02 ` O'Driscoll, Tim
2017-07-04 8:05 ` [PATCH v4 0/2] " Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:05 ` [PATCH v4 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 0/2] " Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 1/2] examples/performance-thread: reorganise arch dependent code Ashwin Sekhar T K
2017-07-04 8:22 ` [PATCH v5 2/2] examples/performance-thread: add arm64 support Ashwin Sekhar T K
2017-07-04 13:20 ` [PATCH v5 0/2] " Thomas Monjalon
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