[PATCH v2 00/11] ARC plat-eznps upstream cont.

[PATCH v2 00/11] ARC plat-eznps upstream cont.

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Change Log
-----------
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.


With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.

it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.

This was based on for-curr branch as the mos updated one I found
at this point of time. 

Liav Rehana (2):
  ARC: typo fix in mm/fault.c
  ARC: typos fix in kernel/entry-compact.S

Noam Camus (9):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: [plat-eznps] typo fix at Kconfig
  ARC: [plat-eznps] Fix TLB Errata
  ARC: [plat-eznps] disabled stall counter due to a HW bug
  ARC: [plat-eznps] spinlock aware for MTM
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle
    task
  ARC: enable platform specific mem_service implementation
  ARC: [plat-eznps] Handle memory error as an exception

 arch/arc/include/asm/cacheflush.h       |    3 ++-
 arch/arc/include/asm/spinlock.h         |    6 ++++++
 arch/arc/kernel/entry-compact.S         |   25 +++++++++++++------------
 arch/arc/kernel/process.c               |    7 +++++++
 arch/arc/kernel/setup.c                 |    6 +++---
 arch/arc/kernel/smp.c                   |    4 ++--
 arch/arc/mm/cache.c                     |   14 +++++++++++---
 arch/arc/mm/fault.c                     |    2 +-
 arch/arc/mm/tlb.c                       |    4 ++--
 arch/arc/mm/tlbex.S                     |    9 +++++++++
 arch/arc/plat-eznps/Kconfig             |   15 +++++++++++++--
 arch/arc/plat-eznps/entry.S             |   14 ++++++++++++++
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 arch/arc/plat-eznps/mtm.c               |    2 --
 14 files changed, 84 insertions(+), 28 deletions(-)

[PATCH v2 00/11] ARC plat-eznps upstream cont.

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Change Log
-----------
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.


With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.

it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.

This was based on for-curr branch as the mos updated one I found
at this point of time. 

Liav Rehana (2):
  ARC: typo fix in mm/fault.c
  ARC: typos fix in kernel/entry-compact.S

Noam Camus (9):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: [plat-eznps] typo fix at Kconfig
  ARC: [plat-eznps] Fix TLB Errata
  ARC: [plat-eznps] disabled stall counter due to a HW bug
  ARC: [plat-eznps] spinlock aware for MTM
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle
    task
  ARC: enable platform specific mem_service implementation
  ARC: [plat-eznps] Handle memory error as an exception

 arch/arc/include/asm/cacheflush.h       |    3 ++-
 arch/arc/include/asm/spinlock.h         |    6 ++++++
 arch/arc/kernel/entry-compact.S         |   25 +++++++++++++------------
 arch/arc/kernel/process.c               |    7 +++++++
 arch/arc/kernel/setup.c                 |    6 +++---
 arch/arc/kernel/smp.c                   |    4 ++--
 arch/arc/mm/cache.c                     |   14 +++++++++++---
 arch/arc/mm/fault.c                     |    2 +-
 arch/arc/mm/tlb.c                       |    4 ++--
 arch/arc/mm/tlbex.S                     |    9 +++++++++
 arch/arc/plat-eznps/Kconfig             |   15 +++++++++++++--
 arch/arc/plat-eznps/entry.S             |   14 ++++++++++++++
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 arch/arc/plat-eznps/mtm.c               |    2 --
 14 files changed, 84 insertions(+), 28 deletions(-)

[PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/setup.c |    6 +++---
 arch/arc/kernel/smp.c   |    4 ++--
 arch/arc/mm/cache.c     |    2 +-
 arch/arc/mm/tlb.c       |    2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
 	read_arc_build_cfg_regs();
 	arc_init_IRQ();
 
-	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
 	arc_mmu_init();
 	arc_cache_init();
 
-	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-	printk(arc_platform_smp_cpuinfo());
+	pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_platform_smp_cpuinfo());
 
 	arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
 	secondary_idle_tsk = idle;
 
-	pr_info("Idle Task [%d] %p", cpu, idle);
-	pr_info("Trying to bring up CPU%u ...\n", cpu);
+	pr_debug("Idle Task [%d] %p", cpu, idle);
+	pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
 	if (plat_smp_ops.cpu_kick)
 		plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..7d3e79b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
 	unsigned int __maybe_unused cpu = smp_processor_id();
 	char str[256];
 
-	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
 	char str[256];
 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
 
-	printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1

[PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/kernel/setup.c |    6 +++---
 arch/arc/kernel/smp.c   |    4 ++--
 arch/arc/mm/cache.c     |    2 +-
 arch/arc/mm/tlb.c       |    2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
 	read_arc_build_cfg_regs();
 	arc_init_IRQ();
 
-	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
 	arc_mmu_init();
 	arc_cache_init();
 
-	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-	printk(arc_platform_smp_cpuinfo());
+	pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_platform_smp_cpuinfo());
 
 	arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
 	secondary_idle_tsk = idle;
 
-	pr_info("Idle Task [%d] %p", cpu, idle);
-	pr_info("Trying to bring up CPU%u ...\n", cpu);
+	pr_debug("Idle Task [%d] %p", cpu, idle);
+	pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
 	if (plat_smp_ops.cpu_kick)
 		plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..7d3e79b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
 	unsigned int __maybe_unused cpu = smp_processor_id();
 	char str[256];
 
-	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
 	char str[256];
 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
 
-	printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1

[PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/include/asm/cacheflush.h |    3 ++-
 arch/arc/mm/cache.c               |   12 ++++++++++--
 arch/arc/mm/tlb.c                 |    2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7d3e79b..e1ea57f 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr)
 {
-	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+	struct ic_inv_args ic_inv = {
+		.paddr	= paddr,
+		.vaddr	= vaddr,
+		.sz	= PAGE_SIZE
+	};
+
+	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 
 			/* invalidate any existing icache lines (U-mapping) */
 			if (vma->vm_flags & VM_EXEC)
-				__inv_icache_page(paddr, vaddr);
+				__inv_icache_page(vma, paddr, vaddr);
 		}
 	}
 }
-- 
1.7.1

[PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noamca at mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>
---
 arch/arc/include/asm/cacheflush.h |    3 ++-
 arch/arc/mm/cache.c               |   12 ++++++++++--
 arch/arc/mm/tlb.c                 |    2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7d3e79b..e1ea57f 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr)
 {
-	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+	struct ic_inv_args ic_inv = {
+		.paddr	= paddr,
+		.vaddr	= vaddr,
+		.sz	= PAGE_SIZE
+	};
+
+	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 
 			/* invalidate any existing icache lines (U-mapping) */
 			if (vma->vm_flags & VM_EXEC)
-				__inv_icache_page(paddr, vaddr);
+				__inv_icache_page(vma, paddr, vaddr);
 		}
 	}
 }
-- 
1.7.1

Re: [PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

[Vineet Gupta]

On 05/27/2017 11:51 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This patch is derived due to performance issue.
> The use case is a page fault that resides on more than the local cpu.
> Trying to broadcast all CPUs results on performance degradation.
> So we try to avoid this by sending only to the relevant CPUs.
> 
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>

This indeed looks like a nice optimization - do you have any performance numbers 
when say running hackbench or other multi-threaded workloads !

-Vineet

> ---
>   arch/arc/include/asm/cacheflush.h |    3 ++-
>   arch/arc/mm/cache.c               |   12 ++++++++++--
>   arch/arc/mm/tlb.c                 |    2 +-
>   3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
> index fc662f4..716dba1 100644
> --- a/arch/arc/include/asm/cacheflush.h
> +++ b/arch/arc/include/asm/cacheflush.h
> @@ -33,7 +33,8 @@
>   
>   void flush_icache_range(unsigned long kstart, unsigned long kend);
>   void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr);
>   void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
>   
>   #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
> index 7d3e79b..e1ea57f 100644
> --- a/arch/arc/mm/cache.c
> +++ b/arch/arc/mm/cache.c
> @@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
>   }
>   
>   /* wrapper to compile time eliminate alignment checks in flush loop */
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr)
>   {
> -	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
> +	struct ic_inv_args ic_inv = {
> +		.paddr	= paddr,
> +		.vaddr	= vaddr,
> +		.sz	= PAGE_SIZE
> +	};
> +
> +	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
> +			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
>   }
>   
>   /*
> diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
> index c5e70d8..a095608 100644
> --- a/arch/arc/mm/tlb.c
> +++ b/arch/arc/mm/tlb.c
> @@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
>   
>   			/* invalidate any existing icache lines (U-mapping) */
>   			if (vma->vm_flags & VM_EXEC)
> -				__inv_icache_page(paddr, vaddr);
> +				__inv_icache_page(vma, paddr, vaddr);
>   		}
>   	}
>   }
> 

[PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

[Vineet Gupta]

On 05/27/2017 11:51 PM, Noam Camus wrote:
> From: Noam Camus <noamca at mellanox.com>
> 
> This patch is derived due to performance issue.
> The use case is a page fault that resides on more than the local cpu.
> Trying to broadcast all CPUs results on performance degradation.
> So we try to avoid this by sending only to the relevant CPUs.
> 
> Signed-off-by: Noam Camus <noamca at mellanox.com>
> Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>

This indeed looks like a nice optimization - do you have any performance numbers 
when say running hackbench or other multi-threaded workloads !

-Vineet

> ---
>   arch/arc/include/asm/cacheflush.h |    3 ++-
>   arch/arc/mm/cache.c               |   12 ++++++++++--
>   arch/arc/mm/tlb.c                 |    2 +-
>   3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
> index fc662f4..716dba1 100644
> --- a/arch/arc/include/asm/cacheflush.h
> +++ b/arch/arc/include/asm/cacheflush.h
> @@ -33,7 +33,8 @@
>   
>   void flush_icache_range(unsigned long kstart, unsigned long kend);
>   void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr);
>   void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
>   
>   #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
> index 7d3e79b..e1ea57f 100644
> --- a/arch/arc/mm/cache.c
> +++ b/arch/arc/mm/cache.c
> @@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
>   }
>   
>   /* wrapper to compile time eliminate alignment checks in flush loop */
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr)
>   {
> -	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
> +	struct ic_inv_args ic_inv = {
> +		.paddr	= paddr,
> +		.vaddr	= vaddr,
> +		.sz	= PAGE_SIZE
> +	};
> +
> +	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
> +			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
>   }
>   
>   /*
> diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
> index c5e70d8..a095608 100644
> --- a/arch/arc/mm/tlb.c
> +++ b/arch/arc/mm/tlb.c
> @@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
>   
>   			/* invalidate any existing icache lines (U-mapping) */
>   			if (vma->vm_flags & VM_EXEC)
> -				__inv_icache_page(paddr, vaddr);
> +				__inv_icache_page(vma, paddr, vaddr);
>   		}
>   	}
>   }
> 

[PATCH v2 03/11] ARC: typo fix in mm/fault.c

[Noam Camus]

From: Liav Rehana <liavr@mellanox.com>

Signed-off-by: Liav Rehana <liavr@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/mm/fault.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -207,7 +207,7 @@ void do_page_fault(unsigned long address, struct pt_regs *regs)
 	/* Are we prepared to handle this kernel fault?
 	 *
 	 * (The kernel has valid exception-points in the source
-	 *  when it acesses user-memory. When it fails in one
+	 *  when it accesses user-memory. When it fails in one
 	 *  of those points, we find it in a table and do a jump
 	 *  to some fixup code that loads an appropriate error
 	 *  code)
-- 
1.7.1

[PATCH v2 03/11] ARC: typo fix in mm/fault.c

[Noam Camus]

From: Liav Rehana <liavr@mellanox.com>

Signed-off-by: Liav Rehana <liavr at mellanox.com>
Signed-off-by: Noam Camus <noamca at mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>
---
 arch/arc/mm/fault.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -207,7 +207,7 @@ void do_page_fault(unsigned long address, struct pt_regs *regs)
 	/* Are we prepared to handle this kernel fault?
 	 *
 	 * (The kernel has valid exception-points in the source
-	 *  when it acesses user-memory. When it fails in one
+	 *  when it accesses user-memory. When it fails in one
 	 *  of those points, we find it in a table and do a jump
 	 *  to some fixup code that loads an appropriate error
 	 *  code)
-- 
1.7.1

[PATCH v2 04/11] ARC: typos fix in kernel/entry-compact.S

[Noam Camus]

From: Liav Rehana <liavr@mellanox.com>

Signed-off-by: Liav Rehana <liavr@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/kernel/entry-compact.S |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include <linux/errno.h>
-#include <linux/linkage.h>	/* {EXTRY,EXIT} */
+#include <linux/linkage.h>	/* {ENTRY,EXIT} */
 #include <asm/entry.h>
 #include <asm/irqflags.h>
 
@@ -80,8 +80,8 @@
 	.align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ; ******************** Exceptions **********************
 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI             ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
 				 ;         or Misaligned Access
 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
-VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension            ; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved                ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; ---------------------------------------------
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
 	;------ (5) Type of Protection Violation? ----------
 	;
 	; ProtV Hardware Exception is triggered for Access Faults of 2 types
-	;   -Access Violaton	: 00_23_(00|01|02|03)_00
+	;   -Access Violation	: 00_23_(00|01|02|03)_00
 	;			         x  r  w  r+w
 	;   -Unaligned Access	: 00_23_04_00
 	;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-	# Interrpts are actually disabled from this point on, but will get
+	# Interrupts are actually disabled from this point on, but will get
 	# reenabled after we return from interrupt/exception.
 	# But irq tracer needs to be told now...
 	TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
 	lr	r10, [status32]
 
 	; Restore REG File. In case multiple Events outstanding,
-	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+	; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
 	; Note that we use realtime STATUS32 (not pt_regs->status32) to
 	; decide that.
 
-- 
1.7.1

[PATCH v2 04/11] ARC: typos fix in kernel/entry-compact.S

[Noam Camus]

From: Liav Rehana <liavr@mellanox.com>

Signed-off-by: Liav Rehana <liavr at mellanox.com>
Signed-off-by: Noam Camus <noamca at mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>
---
 arch/arc/kernel/entry-compact.S |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include <linux/errno.h>
-#include <linux/linkage.h>	/* {EXTRY,EXIT} */
+#include <linux/linkage.h>	/* {ENTRY,EXIT} */
 #include <asm/entry.h>
 #include <asm/irqflags.h>
 
@@ -80,8 +80,8 @@
 	.align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ; ******************** Exceptions **********************
 VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI             ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
 VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
 				 ;         or Misaligned Access
 VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
-VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension            ; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved                ; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; ---------------------------------------------
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
 	;------ (5) Type of Protection Violation? ----------
 	;
 	; ProtV Hardware Exception is triggered for Access Faults of 2 types
-	;   -Access Violaton	: 00_23_(00|01|02|03)_00
+	;   -Access Violation	: 00_23_(00|01|02|03)_00
 	;			         x  r  w  r+w
 	;   -Unaligned Access	: 00_23_04_00
 	;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-	# Interrpts are actually disabled from this point on, but will get
+	# Interrupts are actually disabled from this point on, but will get
 	# reenabled after we return from interrupt/exception.
 	# But irq tracer needs to be told now...
 	TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
 	lr	r10, [status32]
 
 	; Restore REG File. In case multiple Events outstanding,
-	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+	; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
 	; Note that we use realtime STATUS32 (not pt_regs->status32) to
 	; decide that.
 
-- 
1.7.1

[PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/plat-eznps/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
 	help
 	  Support for EZchip development platforms,
 	  based on ARC700 cores.
-	  We handle few flavours:
-	    - Hardware Emulator AKA HE which is FPGA based chasis
+	  We handle few flavors:
+	    - Hardware Emulator AKA HE which is FPGA based chassis
 	    - Simulator based on MetaWare nSIM
 	    - NPS400 chip based on ASIC
 
-- 
1.7.1

[PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Signed-off-by: Noam Camus <noamca at mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>
---
 arch/arc/plat-eznps/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
 	help
 	  Support for EZchip development platforms,
 	  based on ARC700 cores.
-	  We handle few flavours:
-	    - Hardware Emulator AKA HE which is FPGA based chasis
+	  We handle few flavors:
+	    - Hardware Emulator AKA HE which is FPGA based chassis
 	    - Simulator based on MetaWare nSIM
 	    - NPS400 chip based on ASIC
 
-- 
1.7.1

[PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/mm/tlbex.S |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..0e1e47a 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+	/* verify if entry for this vaddr+ASID already exists */
+	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
+	lr    r0, [ARC_REG_TLBINDEX]
+	bbit0 r0, 31, 88f
+#endif
+
 	/* Get free TLB slot: Set = computed from vaddr, way = random */
 	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,8 @@ ex_saved_reg1:
 #else
 	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+
+88:
 .endm
 
 
-- 
1.7.1

[PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/mm/tlbex.S |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..0e1e47a 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+	/* verify if entry for this vaddr+ASID already exists */
+	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
+	lr    r0, [ARC_REG_TLBINDEX]
+	bbit0 r0, 31, 88f
+#endif
+
 	/* Get free TLB slot: Set = computed from vaddr, way = random */
 	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,8 @@ ex_saved_reg1:
 #else
 	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+
+88:
 .endm
 
 
-- 
1.7.1

[PATCH v2 07/11] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.

Remove those couple of lines and resort to HW reset value i.e.
this feature is disabled (.sten field equals 0).

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/plat-eznps/mtm.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index aaaaffd..e0cb36b 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
 	mt_ctrl.value = 0;
 	mt_ctrl.hsen = 1;
 	mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
-	mt_ctrl.sten = 1;
-	mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
 	mt_ctrl.mten = 1;
 	write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
-- 
1.7.1

[PATCH v2 07/11] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
When this feature is enabled low values of this counter cause
downgrade in performance and in the worst case even a livelock.

Remove those couple of lines and resort to HW reset value i.e.
this feature is disabled (.sten field equals 0).

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/plat-eznps/mtm.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index aaaaffd..e0cb36b 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
 	mt_ctrl.value = 0;
 	mt_ctrl.hsen = 1;
 	mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
-	mt_ctrl.sten = 1;
-	mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
 	mt_ctrl.mten = 1;
 	write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
-- 
1.7.1

Re: [PATCH v2 07/11] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Alexey Brodkin]

Hi Noam,

On Sun, 2017-05-28 at 09:52 +0300, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This counter represents threshold for consecutive stall that which
> trigger HW threads scheduling.
> When this feature is enabled low values of this counter cause
> downgrade in performance and in the worst case even a livelock.
> 
> Remove those couple of lines and resort to HW reset value i.e.
> this feature is disabled (.sten field equals 0).

Looks like you made a change I was asking for here.
But there's no mention of the change so it's easy to not note
that change. Not critical but please add a changelog next time 
even if it's only a comment message that was modified since
the previous revision.

Otherwise...

Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>

> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>  arch/arc/plat-eznps/mtm.c |    2 --
>  1 files changed, 0 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
> index aaaaffd..e0cb36b 100644
> --- a/arch/arc/plat-eznps/mtm.c
> +++ b/arch/arc/plat-eznps/mtm.c
> @@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
>  	mt_ctrl.value = 0;
>  	mt_ctrl.hsen = 1;
>  	mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
> -	mt_ctrl.sten = 1;
> -	mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
>  	mt_ctrl.mten = 1;
>  	write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
>  

[PATCH v2 07/11] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Alexey Brodkin]

Hi Noam,

On Sun, 2017-05-28@09:52 +0300, Noam Camus wrote:
> From: Noam Camus <noamca at mellanox.com>
> 
> This counter represents threshold for consecutive stall that which
> trigger HW threads scheduling.
> When this feature is enabled low values of this counter cause
> downgrade in performance and in the worst case even a livelock.
> 
> Remove those couple of lines and resort to HW reset value i.e.
> this feature is disabled (.sten field equals 0).

Looks like you made a change I was asking for here.
But there's no mention of the change so it's easy to not note
that change. Not critical but please add a changelog next time?
even if it's only a comment message that was modified since
the previous revision.

Otherwise...

Reviewed-by: Alexey Brodkin <abrodkin at synopsys.com>

> Signed-off-by: Noam Camus <noamca at mellanox.com>
> ---
> ?arch/arc/plat-eznps/mtm.c |????2 --
> ?1 files changed, 0 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
> index aaaaffd..e0cb36b 100644
> --- a/arch/arc/plat-eznps/mtm.c
> +++ b/arch/arc/plat-eznps/mtm.c
> @@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
> ?	mt_ctrl.value = 0;
> ?	mt_ctrl.hsen = 1;
> ?	mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
> -	mt_ctrl.sten = 1;
> -	mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
> ?	mt_ctrl.mten = 1;
> ?	write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
> ?

[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.

We noticed about 10% improvement of execution time with hackbench test.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/include/asm/spinlock.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 233d5ff..0a54ce7 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 	__asm__ __volatile__(
 	"1:	ex  %0, [%1]		\n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+	"	.word %3		\n"
+#endif
 	"	breq  %0, %2, 1b	\n"
 	: "+&r" (val)
 	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+	, "i"(CTOP_INST_SCHD_RW)
+#endif
 	: "memory");
 
 	/*
-- 
1.7.1

[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.

We noticed about 10% improvement of execution time with hackbench test.

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/include/asm/spinlock.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 233d5ff..0a54ce7 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 	__asm__ __volatile__(
 	"1:	ex  %0, [%1]		\n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+	"	.word %3		\n"
+#endif
 	"	breq  %0, %2, 1b	\n"
 	: "+&r" (val)
 	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+	, "i"(CTOP_INST_SCHD_RW)
+#endif
 	: "memory");
 
 	/*
-- 
1.7.1

Re: [PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This way when we execute "ex" during trying to hold lock we can switch to
> other HW thread and utilize the core intead of just spinning on a lock.
> 
> We noticed about 10% improvement of execution time with hackbench test.
> 
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>   arch/arc/include/asm/spinlock.h |    6 ++++++
>   1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
> index 233d5ff..0a54ce7 100644
> --- a/arch/arc/include/asm/spinlock.h
> +++ b/arch/arc/include/asm/spinlock.h
> @@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
>   
>   	__asm__ __volatile__(
>   	"1:	ex  %0, [%1]		\n"
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +	"	.word %3		\n"
> +#endif
>   	"	breq  %0, %2, 1b	\n"
>   	: "+&r" (val)
>   	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +	, "i"(CTOP_INST_SCHD_RW)
> +#endif
>   	: "memory");
>   
>   	/*
> 

This is ugly - I will fix it up here to create an NPS version of arch_spin_lock !

-Vineet

[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca at mellanox.com>
> 
> This way when we execute "ex" during trying to hold lock we can switch to
> other HW thread and utilize the core intead of just spinning on a lock.
> 
> We noticed about 10% improvement of execution time with hackbench test.
> 
> Signed-off-by: Noam Camus <noamca at mellanox.com>
> ---
>   arch/arc/include/asm/spinlock.h |    6 ++++++
>   1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
> index 233d5ff..0a54ce7 100644
> --- a/arch/arc/include/asm/spinlock.h
> +++ b/arch/arc/include/asm/spinlock.h
> @@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
>   
>   	__asm__ __volatile__(
>   	"1:	ex  %0, [%1]		\n"
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +	"	.word %3		\n"
> +#endif
>   	"	breq  %0, %2, 1b	\n"
>   	: "+&r" (val)
>   	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
> +#ifdef CONFIG_EZNPS_MTM_EXT
> +	, "i"(CTOP_INST_SCHD_RW)
> +#endif
>   	: "memory");
>   
>   	/*
> 

This is ugly - I will fix it up here to create an NPS version of arch_spin_lock !

-Vineet

RE: [PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

> From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
> Sent: Friday, June 2, 2017 21:36 PM
...

>>   arch/arc/include/asm/spinlock.h |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>> 
>> diff --git a/arch/arc/include/asm/spinlock.h 
>> b/arch/arc/include/asm/spinlock.h index 233d5ff..0a54ce7 100644
>> --- a/arch/arc/include/asm/spinlock.h
>> +++ b/arch/arc/include/asm/spinlock.h
>> @@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t 
>> *lock)
>>   
>>   	__asm__ __volatile__(
>>   	"1:	ex  %0, [%1]		\n"
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +	"	.word %3		\n"
>> +#endif
>>   	"	breq  %0, %2, 1b	\n"
>>   	: "+&r" (val)
>>   	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +	, "i"(CTOP_INST_SCHD_RW)
>> +#endif
>>   	: "memory");
>>   
>>   	/*
>> 

>This is ugly - I will fix it up here to create an NPS version of arch_spin_lock !
TNX

-Noam

[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

> From: Vineet Gupta [mailto:Vineet.Gupta1 at synopsys.com] 
> Sent: Friday, June 2, 2017 21:36 PM
...

>>   arch/arc/include/asm/spinlock.h |    6 ++++++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>> 
>> diff --git a/arch/arc/include/asm/spinlock.h 
>> b/arch/arc/include/asm/spinlock.h index 233d5ff..0a54ce7 100644
>> --- a/arch/arc/include/asm/spinlock.h
>> +++ b/arch/arc/include/asm/spinlock.h
>> @@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t 
>> *lock)
>>   
>>   	__asm__ __volatile__(
>>   	"1:	ex  %0, [%1]		\n"
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +	"	.word %3		\n"
>> +#endif
>>   	"	breq  %0, %2, 1b	\n"
>>   	: "+&r" (val)
>>   	: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +	, "i"(CTOP_INST_SCHD_RW)
>> +#endif
>>   	: "memory");
>>   
>>   	/*
>> 

>This is ugly - I will fix it up here to create an NPS version of arch_spin_lock !
TNX

-Noam

[PATCH v2 09/11] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can execute instructions.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/process.c               |    7 +++++++
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 2a018de..d3c39e4 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -82,10 +82,17 @@
 void arch_cpu_idle(void)
 {
 	/* sleep, but enable all interrupts before committing */
+#if !defined(CONFIG_EZNPS_MTM_EXT)
 	__asm__ __volatile__(
 		"sleep %0	\n"
 		:
 		:"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const */
+#else
+	__asm__ __volatile__(
+		".word %0	\n"
+		:
+		:"i"(CTOP_INST_HWSCHD_WFT_IE12));
+#endif
 }
 
 asmlinkage void ret_from_fork(void);
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index ee2e32d..7729d3d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,6 +46,7 @@
 #define CTOP_AUX_UDMC				(CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
+#define CTOP_INST_HWSCHD_WFT_IE12		0x3E6F7344
 #define CTOP_INST_HWSCHD_OFF_R4			0x3C6F00BF
 #define CTOP_INST_HWSCHD_RESTORE_R4		0x3E6F7103
 #define CTOP_INST_SCHD_RW			0x3E6F7004
-- 
1.7.1

[PATCH v2 09/11] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can execute instructions.

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/kernel/process.c               |    7 +++++++
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 2a018de..d3c39e4 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -82,10 +82,17 @@
 void arch_cpu_idle(void)
 {
 	/* sleep, but enable all interrupts before committing */
+#if !defined(CONFIG_EZNPS_MTM_EXT)
 	__asm__ __volatile__(
 		"sleep %0	\n"
 		:
 		:"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const */
+#else
+	__asm__ __volatile__(
+		".word %0	\n"
+		:
+		:"i"(CTOP_INST_HWSCHD_WFT_IE12));
+#endif
 }
 
 asmlinkage void ret_from_fork(void);
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index ee2e32d..7729d3d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,6 +46,7 @@
 #define CTOP_AUX_UDMC				(CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
+#define CTOP_INST_HWSCHD_WFT_IE12		0x3E6F7344
 #define CTOP_INST_HWSCHD_OFF_R4			0x3C6F00BF
 #define CTOP_INST_HWSCHD_RESTORE_R4		0x3E6F7103
 #define CTOP_INST_SCHD_RW			0x3E6F7004
-- 
1.7.1

[PATCH v2 10/11] ARC: enable platform specific mem_service implementation

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/entry-compact.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index f285dbb..c5736d6 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -200,8 +200,9 @@ END(handle_interrupt_level2)
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
 ; (Kernel mode memory errors handled via separate exception vectors)
+; Platforms can override this weak version if needed
 ; ---------------------------------------------
-ENTRY(mem_service)
+WEAK(mem_service)
 
 	INTERRUPT_PROLOGUE 2
 
-- 
1.7.1

[PATCH v2 10/11] ARC: enable platform specific mem_service implementation

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

For User Mode Memory Bus Error some platforms do not creat interrupt
level 2 e.g. nps400 creates machine check exception.
Turning mem_service into weak symbol allows each platform to override
mem_service with its own implementation.

Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/kernel/entry-compact.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index f285dbb..c5736d6 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -200,8 +200,9 @@ END(handle_interrupt_level2)
 ; ---------------------------------------------
 ; User Mode Memory Bus Error Interrupt Handler
 ; (Kernel mode memory errors handled via separate exception vectors)
+; Platforms can override this weak version if needed
 ; ---------------------------------------------
-ENTRY(mem_service)
+WEAK(mem_service)
 
 	INTERRUPT_PROLOGUE 2
 
-- 
1.7.1

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override weak symbole of mem_service to achieve that.

Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++++++++++
 arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..c5f946c 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
 	  any of them seem like CPU from Linux point of view.
 	  All threads within same core share the execution unit of the
 	  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+       bool "ARC-EZchip Memory error as an exception"
+       depends on ARC_PLAT_EZNPS
+       default n
+       help
+         On the real chip of the NPS, user memory errors are handled
+         as a machine check exception, whereas on simulator platform
+         for NPS, it handled as an interrupt level 2 (like legacy arc
+         real chip architecture).This configuration will cause the kernel
+         to handle memory error as a machine check exception.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..03e2892 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -68,3 +68,17 @@ ENTRY(res_service)
 
 	j	stext
 END(res_service)
+
+#if defined(CONFIG_EZNPS_MEM_ERROR)
+ENTRY(mem_service)
+	; SW workaround to cover up on a difference between
+	; NPS real chip and simulator behaviors.
+	; NPS real chip will activate a machine check exception
+	; in case of memory error, while the simulator will
+	; trigger a level 2 interrupt. Therefor this code section
+	; should be reached only in simulation mode.
+	; DEAD END: display Regs and HALT
+
+	j EV_MachineCheck
+END(mem_service)
+#endif
-- 
1.7.1

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

From: Noam Camus <noamca@mellanox.com>

This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override weak symbole of mem_service to achieve that.

Signed-off-by: Elad Kanfi <eladkan at mellanox.com>
Signed-off-by: Noam Camus <noamca at mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++++++++++
 arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..c5f946c 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
 	  any of them seem like CPU from Linux point of view.
 	  All threads within same core share the execution unit of the
 	  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+       bool "ARC-EZchip Memory error as an exception"
+       depends on ARC_PLAT_EZNPS
+       default n
+       help
+         On the real chip of the NPS, user memory errors are handled
+         as a machine check exception, whereas on simulator platform
+         for NPS, it handled as an interrupt level 2 (like legacy arc
+         real chip architecture).This configuration will cause the kernel
+         to handle memory error as a machine check exception.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..03e2892 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -68,3 +68,17 @@ ENTRY(res_service)
 
 	j	stext
 END(res_service)
+
+#if defined(CONFIG_EZNPS_MEM_ERROR)
+ENTRY(mem_service)
+	; SW workaround to cover up on a difference between
+	; NPS real chip and simulator behaviors.
+	; NPS real chip will activate a machine check exception
+	; in case of memory error, while the simulator will
+	; trigger a level 2 interrupt. Therefor this code section
+	; should be reached only in simulation mode.
+	; DEAD END: display Regs and HALT
+
+	j EV_MachineCheck
+END(mem_service)
+#endif
-- 
1.7.1

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n
> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.

Do you really need a Kconfig option here. AFAIKR you guys had some magic in 
platform code to determine whether running on sim or hw - can that be not used ?

> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif


Just squash the weak symbol patch in here - not worth a separate patch !

-Vineet

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca at mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan at mellanox.com>
> Signed-off-by: Noam Camus <noamca at mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n
> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.

Do you really need a Kconfig option here. AFAIKR you guys had some magic in 
platform code to determine whether running on sim or hw - can that be not used ?

> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif


Just squash the weak symbol patch in here - not worth a separate patch !

-Vineet

RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
> Sent: Friday, June 2, 2017 22:04 PM

>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig 
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>>   	  any of them seem like CPU from Linux point of view.
>>   	  All threads within same core share the execution unit of the
>>   	  core and HW scheduler round robin between them.
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n
>> +       help
>> +         On the real chip of the NPS, user memory errors are handled
>> +         as a machine check exception, whereas on simulator platform
>> +         for NPS, it handled as an interrupt level 2 (like legacy arc
>> +         real chip architecture).This configuration will cause the kernel
>> +         to handle memory error as a machine check exception.

>Do you really need a Kconfig option here. AFAIKR you guys had some magic in platform code to determine whether running on sim or hw - can that be not used ?
We do not have this anymore, needed to create dedicated one here.

...

>> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S 
>> index 328261c..03e2892 100644
>> --- a/arch/arc/plat-eznps/entry.S
>> +++ b/arch/arc/plat-eznps/entry.S
>> @@ -68,3 +68,17 @@ ENTRY(res_service)
>>   
>>   	j	stext
>>   END(res_service)
>> +
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +ENTRY(mem_service)
>> +	; SW workaround to cover up on a difference between
>> +	; NPS real chip and simulator behaviors.
>> +	; NPS real chip will activate a machine check exception
>> +	; in case of memory error, while the simulator will
>> +	; trigger a level 2 interrupt. Therefor this code section
>> +	; should be reached only in simulation mode.
>> +	; DEAD END: display Regs and HALT
>> +
>> +	j EV_MachineCheck
>> +END(mem_service)
>> +#endif


>Just squash the weak symbol patch in here - not worth a separate patch !
Ok , no problem.

-Noam

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Vineet Gupta [mailto:Vineet.Gupta1 at synopsys.com] 
> Sent: Friday, June 2, 2017 22:04 PM

>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig 
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>>   	  any of them seem like CPU from Linux point of view.
>>   	  All threads within same core share the execution unit of the
>>   	  core and HW scheduler round robin between them.
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n
>> +       help
>> +         On the real chip of the NPS, user memory errors are handled
>> +         as a machine check exception, whereas on simulator platform
>> +         for NPS, it handled as an interrupt level 2 (like legacy arc
>> +         real chip architecture).This configuration will cause the kernel
>> +         to handle memory error as a machine check exception.

>Do you really need a Kconfig option here. AFAIKR you guys had some magic in platform code to determine whether running on sim or hw - can that be not used ?
We do not have this anymore, needed to create dedicated one here.

...

>> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S 
>> index 328261c..03e2892 100644
>> --- a/arch/arc/plat-eznps/entry.S
>> +++ b/arch/arc/plat-eznps/entry.S
>> @@ -68,3 +68,17 @@ ENTRY(res_service)
>>   
>>   	j	stext
>>   END(res_service)
>> +
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +ENTRY(mem_service)
>> +	; SW workaround to cover up on a difference between
>> +	; NPS real chip and simulator behaviors.
>> +	; NPS real chip will activate a machine check exception
>> +	; in case of memory error, while the simulator will
>> +	; trigger a level 2 interrupt. Therefor this code section
>> +	; should be reached only in simulation mode.
>> +	; DEAD END: display Regs and HALT
>> +
>> +	j EV_MachineCheck
>> +END(mem_service)
>> +#endif


>Just squash the weak symbol patch in here - not worth a separate patch !
Ok , no problem.

-Noam

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n

So you set default to "n" - thus by default it works for the simulator not silicon ?


> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.
> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif
> 

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca at mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan at mellanox.com>
> Signed-off-by: Noam Camus <noamca at mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n

So you set default to "n" - thus by default it works for the simulator not silicon ?


> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.
> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif
> 

RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

>From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n

>So you set default to "n" - thus by default it works for the simulator not silicon ?
Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

-Noam

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

>From: Vineet Gupta [mailto:Vineet.Gupta1 at synopsys.com] 
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n

>So you set default to "n" - thus by default it works for the simulator not silicon ?
Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

-Noam

RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Noam Camus 
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' <Vineet.Gupta1@synopsys.com>; linux-snps-arc@lists.infradead.org
>Cc: linux-kernel@vger.kernel.org; Elad Kanfi <eladkan@mellanox.com>
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

>>From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
>>Sent: Wednesday, June 7, 2017 1:11 AM
>...
>>> +
>>> +config EZNPS_MEM_ERROR
>>> +       bool "ARC-EZchip Memory error as an exception"
>>> +       depends on ARC_PLAT_EZNPS
>>> +       default n

>>So you set default to "n" - thus by default it works for the simulator not silicon ?
>Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

Sorry, but It is not correct.
Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
Please re-update this CONFIG help section.

Thanks
-Noam

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Noam Camus 
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' <Vineet.Gupta1 at synopsys.com>; linux-snps-arc at lists.infradead.org
>Cc: linux-kernel at vger.kernel.org; Elad Kanfi <eladkan at mellanox.com>
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

>>From: Vineet Gupta [mailto:Vineet.Gupta1 at synopsys.com] 
>>Sent: Wednesday, June 7, 2017 1:11 AM
>...
>>> +
>>> +config EZNPS_MEM_ERROR
>>> +       bool "ARC-EZchip Memory error as an exception"
>>> +       depends on ARC_PLAT_EZNPS
>>> +       default n

>>So you set default to "n" - thus by default it works for the simulator not silicon ?
>Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

Sorry, but It is not correct.
Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
Please re-update this CONFIG help section.

Thanks
-Noam

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/07/2017 04:14 AM, Noam Camus wrote:
>>>> +config EZNPS_MEM_ERROR
>>>> +       bool "ARC-EZchip Memory error as an exception"
>>>> +       depends on ARC_PLAT_EZNPS
>>>> +       default n
>>> So you set default to "n" - thus by default it works for the simulator not silicon ?
>> Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.
> Sorry, but It is not correct.
> Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
> Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
> Please re-update this CONFIG help section.



So NPS *hardware* generates exception, jumps to vector mem_service(), which you 
redirect to the machine check handler - which simply panics.
But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to "n". So 
how is the default working for hardware ? Doesn't it need to be "y"

BTW it seems your patch is wrong otherwise too. So the userspace bus error will go 
to machine check handler which currently just panic's. You really want to kill the 
user space process and continue, thus need to call do_memory_error()

-Vineet

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/07/2017 04:14 AM, Noam Camus wrote:
>>>> +config EZNPS_MEM_ERROR
>>>> +       bool "ARC-EZchip Memory error as an exception"
>>>> +       depends on ARC_PLAT_EZNPS
>>>> +       default n
>>> So you set default to "n" - thus by default it works for the simulator not silicon ?
>> Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.
> Sorry, but It is not correct.
> Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
> Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
> Please re-update this CONFIG help section.



So NPS *hardware* generates exception, jumps to vector mem_service(), which you 
redirect to the machine check handler - which simply panics.
But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to "n". So 
how is the default working for hardware ? Doesn't it need to be "y"

BTW it seems your patch is wrong otherwise too. So the userspace bus error will go 
to machine check handler which currently just panic's. You really want to kill the 
user space process and continue, thus need to call do_memory_error()

-Vineet

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/07/2017 08:29 PM, Noam Camus wrote:
> *From:* Noam Camus
> *Sent:* Wednesday, June 7, 2017 8:06:17 PM
> *To:* Vineet Gupta; linux-snps-arc@lists.infradead.org
> *Cc:* linux-kernel@vger.kernel.org; Elad Kanfi
> *Subject:* Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an 
> exception
>
> *> From:*Vineet Gupta <Vineet.Gupta1@synopsys.com>
>
> *> Sent:* Wednesday, June 7, 2017 7:15 PM...
>
> > So NPS *hardware* generates exception, jumps to vector mem_service(), which you
> > redirect to the machine check handler - which simply panics.
> > But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to 
> "n". So
> > how is the default working for hardware ? Doesn't it need to be "y"
>
> The NPS400 architects changed userspace bus error behavior to be machine check 
> instead of Interrupt level 2.
> The reason was that since we are dealing with imprecise exception.
> So memory request result will be back to core long time after bad instruction 
> was executed.
> In the meantime core be able to do HW schedule between threads and result may 
> hit another thread.
> The core do not keep information on each such bus transaction so it just 
> interfere current thread without knowing if it was the initiator of this bus 
> transaction.
> In such case we prefer to create machine check and end with PANIC.

Ok this make sense !

>
> With simulator we just turn this configuration on, so we redirect the Legacy 
> Synopsys L2 ISR from nSIM into machine check.
> This way we end up just like with silicon 😊

This doesn't make sense :-)
In simulation (where L2 interrupt is asserted), you need to handle it as such - 
say reading out the banked regs for L2 interrupt. What you are doing here is 
handling it like an exception which won't work . I really don't see the point of 
this "alignment" - hardware and simulation are different. simulation semantics are 
already supported by generic ARC code. And for silicon case, the existing vector 
woudl MachineCheck would work for both K and U. So I'm not sure what we are trying 
to achieve here !


>
>
> >BTW it seems your patch is wrong otherwise too. So the userspace bus error will go
> >to machine check handler which currently just panic's. You really want to kill the
> >user space process and continue, thus need to call do_memory_error()
> So I believe that we do correct thing here, when we deal with multi thread cores.

Sure, the imprecise handling of bus error is an issue - but we should atleat try 
to recover. By just panic'ing unconditionally, you are enabling a one liner user 
program to panic the system (granted in simulation only)

-Vineet

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/07/2017 08:29 PM, Noam Camus wrote:
> *From:* Noam Camus
> *Sent:* Wednesday, June 7, 2017 8:06:17 PM
> *To:* Vineet Gupta; linux-snps-arc at lists.infradead.org
> *Cc:* linux-kernel at vger.kernel.org; Elad Kanfi
> *Subject:* Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an 
> exception
>
> *> From:*Vineet Gupta <Vineet.Gupta1 at synopsys.com>
>
> *> Sent:* Wednesday, June 7, 2017 7:15 PM...
>
> > So NPS *hardware* generates exception, jumps to vector mem_service(), which you
> > redirect to the machine check handler - which simply panics.
> > But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to 
> "n". So
> > how is the default working for hardware ? Doesn't it need to be "y"
>
> The NPS400 architects changed userspace bus error behavior to be machine check 
> instead of Interrupt level 2.
> The reason was that since we are dealing with imprecise exception.
> So memory request result will be back to core long time after bad instruction 
> was executed.
> In the meantime core be able to do HW schedule between threads and result may 
> hit another thread.
> The core do not keep information on each such bus transaction so it just 
> interfere current thread without knowing if it was the initiator of this bus 
> transaction.
> In such case we prefer to create machine check and end with PANIC.

Ok this make sense !

>
> With simulator we just turn this configuration on, so we redirect the Legacy 
> Synopsys L2 ISR from nSIM into machine check.
> This way we end up just like with silicon ?

This doesn't make sense :-)
In simulation (where L2 interrupt is asserted), you need to handle it as such - 
say reading out the banked regs for L2 interrupt. What you are doing here is 
handling it like an exception which won't work . I really don't see the point of 
this "alignment" - hardware and simulation are different. simulation semantics are 
already supported by generic ARC code. And for silicon case, the existing vector 
woudl MachineCheck would work for both K and U. So I'm not sure what we are trying 
to achieve here !


>
>
> >BTW it seems your patch is wrong otherwise too. So the userspace bus error will go
> >to machine check handler which currently just panic's. You really want to kill the
> >user space process and continue, thus need to call do_memory_error()
> So I believe that we do correct thing here, when we deal with multi thread cores.

Sure, the imprecise handling of bus error is an issue - but we should atleat try 
to recover. By just panic'ing unconditionally, you are enabling a one liner user 
program to panic the system (granted in simulation only)

-Vineet

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/08/2017 11:23 AM, Noam Camus wrote:
>
>
> *> From:* Vineet Gupta <Vineet.Gupta1@synopsys.com>
> *> Sent:* Thursday, June 8, 2017 7:38 PM
>
> >>
> >> With simulator we just turn this configuration on, so we redirect the Legacy
> >> Synopsys L2 ISR from nSIM into machine check.
> >> This way we end up just like with silicon 😊
>
> >This doesn't make sense :-)
> >In simulation (where L2 interrupt is asserted), you need to handle it as such -
> >say reading out the banked regs for L2 interrupt. What you are doing here is
> >handling it like an exception which won't work . I really don't see the point of
> >this "alignment" - hardware and simulation are different. simulation semantics are
> >already supported by generic ARC code. And for silicon case, the existing vector
> >woudl MachineCheck would work for both K and U. So I'm not sure what we are trying
> >to achieve here !
> With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we 
> strive to have similar echo system for both silicon and its simulator.

Right, but if you are using nSIM which generates L2 interrupt for user mode error 
- then it is already different from silicon and needs to handled as such.

> If we could, we would alter nSIM to behave just like our silicon.
> So in current situation where we lack doing so we suffice in single pretty small 
> adjustment in OS (platform specific code).

You are saying contradicting things here. Above u want EZSim to simulate CTOP 
(i.e. generate machinechk for U errors) but here you claim u use nSIM which will 
generates L2 intr.

So I'm still grossly confused.

What does EZSim (based on nSIM) do when bus error is triggered from User mode - 
does it raise (A) L2 interrupt or (B) MachineCheck ?

If it is (A) the the existing common code in ARC will work - mem_service() -> 
do_memory_error() -> panic()
if it is (B), again the common machinecheck handler will be called and will panic.

I don't see the need to mix both (A) and (B) i.e. use mem_service() which is a L2 
interrupt, but then handle it in MachieChekc which is for exceptions ? How is that 
supposed to work !

-Vineet

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/08/2017 11:23 AM, Noam Camus wrote:
>
>
> *> From:* Vineet Gupta <Vineet.Gupta1 at synopsys.com>
> *> Sent:* Thursday, June 8, 2017 7:38 PM
>
> >>
> >> With simulator we just turn this configuration on, so we redirect the Legacy
> >> Synopsys L2 ISR from nSIM into machine check.
> >> This way we end up just like with silicon ?
>
> >This doesn't make sense :-)
> >In simulation (where L2 interrupt is asserted), you need to handle it as such -
> >say reading out the banked regs for L2 interrupt. What you are doing here is
> >handling it like an exception which won't work . I really don't see the point of
> >this "alignment" - hardware and simulation are different. simulation semantics are
> >already supported by generic ARC code. And for silicon case, the existing vector
> >woudl MachineCheck would work for both K and U. So I'm not sure what we are trying
> >to achieve here !
> With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we 
> strive to have similar echo system for both silicon and its simulator.

Right, but if you are using nSIM which generates L2 interrupt for user mode error 
- then it is already different from silicon and needs to handled as such.

> If we could, we would alter nSIM to behave just like our silicon.
> So in current situation where we lack doing so we suffice in single pretty small 
> adjustment in OS (platform specific code).

You are saying contradicting things here. Above u want EZSim to simulate CTOP 
(i.e. generate machinechk for U errors) but here you claim u use nSIM which will 
generates L2 intr.

So I'm still grossly confused.

What does EZSim (based on nSIM) do when bus error is triggered from User mode - 
does it raise (A) L2 interrupt or (B) MachineCheck ?

If it is (A) the the existing common code in ARC will work - mem_service() -> 
do_memory_error() -> panic()
if it is (B), again the common machinecheck handler will be called and will panic.

I don't see the need to mix both (A) and (B) i.e. use mem_service() which is a L2 
interrupt, but then handle it in MachieChekc which is for exceptions ? How is that 
supposed to work !

-Vineet

Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/08/2017 08:17 PM, Noam Camus wrote:
>
> *> From:*Vineet Gupta <Vineet.Gupta1@synopsys.com>
>
> *> Sent:* Thursday, June 8, 2017 10:00 PM
>
>
> >> With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we
> >> strive to have similar echo system for both silicon and its simulator.
>
> >Right, but if you are using nSIM which generates L2 interrupt for user mode error
> >- then it is already different from silicon and needs to handled as such.
> Why so, this is something I wish to minimize and not just live with.
> So I handle difference by redirecting back to the track I want to.
>
> >> If we could, we would alter nSIM to behave just like our silicon.
> >> So in current situation where we lack doing so we suffice in single pretty small
> >> adjustment in OS (platform specific code).
>
> >You are saying contradicting things here. Above u want EZSim to simulate CTOP
> >(i.e. generate machinechk for U errors) but here you claim u use nSIM which will
> >generates L2 intr.
>
> >So I'm still grossly confused.
> Sorry, for confusion.
> I am using nSIM which creates L2 interrupt and not machine check because I got 
> no alternative.
> At the first chance I get the opportunity, I put execution back to my desired 
> direction.
> Since the direction as our silicon dictate is ending with die() it is a clear 
> path without a risk.

OK I understand now - you want the die semantics not try and continue... but the 
patch is simply wrong. From L2 interrupt you jump to machine check vector which 
reads ECR. In this case it would be bogus - with some old stale value. What you 
really want is an NPS version of do_memory_error - since platforms can have their 
way of dealing with such errors - but the low level machine handling is just not 
in their control.

I'd propose the patch below and then you can define your own version of 
do_memory_error() and handle as appropriate !

---->
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index ff83e78d0cfb..5a8042784ee9 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -80,11 +80,26 @@ int name(unsigned long address, struct pt_regs *regs) \
  DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
  DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
  DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
  DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
  DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)

  /*
+ * Entry point for bus errors
+ * opencoded DO_ERROR_INFO() but __weak to allow possible plarform override
+ */
+int __weak do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+       siginfo_t info = {
+               .si_signo = SIGBUS,
+               .si_errno = 0,
+               .si_code  = BUS_ADRERR,
+               .si_addr = (void __user *)address,
+       };
+
+       return unhandled_exception("Invalid Mem Access", regs, &info);
+}
+
+/*

[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Vineet Gupta]

On 06/08/2017 08:17 PM, Noam Camus wrote:
>
> *> From:*Vineet Gupta <Vineet.Gupta1 at synopsys.com>
>
> *> Sent:* Thursday, June 8, 2017 10:00 PM
>
>
> >> With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we
> >> strive to have similar echo system for both silicon and its simulator.
>
> >Right, but if you are using nSIM which generates L2 interrupt for user mode error
> >- then it is already different from silicon and needs to handled as such.
> Why so, this is something I wish to minimize and not just live with.
> So I handle difference by redirecting back to the track I want to.
>
> >> If we could, we would alter nSIM to behave just like our silicon.
> >> So in current situation where we lack doing so we suffice in single pretty small
> >> adjustment in OS (platform specific code).
>
> >You are saying contradicting things here. Above u want EZSim to simulate CTOP
> >(i.e. generate machinechk for U errors) but here you claim u use nSIM which will
> >generates L2 intr.
>
> >So I'm still grossly confused.
> Sorry, for confusion.
> I am using nSIM which creates L2 interrupt and not machine check because I got 
> no alternative.
> At the first chance I get the opportunity, I put execution back to my desired 
> direction.
> Since the direction as our silicon dictate is ending with die() it is a clear 
> path without a risk.

OK I understand now - you want the die semantics not try and continue... but the 
patch is simply wrong. From L2 interrupt you jump to machine check vector which 
reads ECR. In this case it would be bogus - with some old stale value. What you 
really want is an NPS version of do_memory_error - since platforms can have their 
way of dealing with such errors - but the low level machine handling is just not 
in their control.

I'd propose the patch below and then you can define your own version of 
do_memory_error() and handle as appropriate !

---->
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index ff83e78d0cfb..5a8042784ee9 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -80,11 +80,26 @@ int name(unsigned long address, struct pt_regs *regs) \
  DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
  DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
  DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
  DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
  DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)

  /*
+ * Entry point for bus errors
+ * opencoded DO_ERROR_INFO() but __weak to allow possible plarform override
+ */
+int __weak do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+       siginfo_t info = {
+               .si_signo = SIGBUS,
+               .si_errno = 0,
+               .si_code  = BUS_ADRERR,
+               .si_addr = (void __user *)address,
+       };
+
+       return unhandled_exception("Invalid Mem Access", regs, &info);
+}
+
+/*