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From: "Lankhorst, Maarten" <maarten.lankhorst@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Kumar, Mahesh1" <mahesh1.kumar@intel.com>,
	"maarten.lankhorst@linux.intel.com"
	<maarten.lankhorst@linux.intel.com>
Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 1/3] drm/i915/skl+: Don't trust cached ddb values
Date: Tue, 30 May 2017 14:35:06 +0000	[thread overview]
Message-ID: <1496154904.3120.1.camel@intel.com> (raw)
In-Reply-To: <059c2f57-6899-ffc0-7564-ff56b6cbdb17@intel.com>


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Mahesh Kumar schreef op di 30-05-2017 om 18:26 [+0530]:
> Hi Maarten,
> 
> Thanks for review :)
> 
> 
> On Tuesday 30 May 2017 03:30 PM, Maarten Lankhorst wrote:
> > Op 26-05-17 om 17:15 schreef Mahesh Kumar:
> > > Don't trust cached DDB values. Recalculate the ddb value if
> > > cached value
> > > is zero.
> > > 
> > > If i915 is build as a module, there may be a race condition when
> > > cursor_disable call comes even before intel_fbdev_initial_config.
> > > Which may lead to cached value being 0. And further commit will
> > > fail
> > > until a modeset.
> > > 
> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > > ---
> > >   drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
> > >   1 file changed, 10 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 936eef1634c7..b67be1355e39 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3721,6 +3721,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> > > drm_device *dev,
> > >   	struct drm_i915_private *dev_priv = to_i915(dev);
> > >   	struct drm_crtc *for_crtc = cstate->base.crtc;
> > >   	unsigned int pipe_size, ddb_size;
> > > +	unsigned int active_crtcs;
> > >   	int nth_active_pipe;
> > >   
> > >   	if (WARN_ON(!state) || !cstate->base.active) {
> > > @@ -3731,10 +3732,11 @@ skl_ddb_get_pipe_allocation_limits(struct
> > > drm_device *dev,
> > >   	}
> > >   
> > >   	if (intel_state->active_pipe_changes)
> > > -		*num_active = hweight32(intel_state-
> > > >active_crtcs);
> > > +		active_crtcs = intel_state->active_crtcs;
> > >   	else
> > > -		*num_active = hweight32(dev_priv->active_crtcs);
> > > +		active_crtcs = dev_priv->active_crtcs;
> > >   
> > > +	*num_active = hweight32(active_crtcs);
> > >   	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> > >   	WARN_ON(ddb_size == 0);
> > >   
> > > @@ -3754,12 +3756,15 @@ skl_ddb_get_pipe_allocation_limits(struct
> > > drm_device *dev,
> > >   		 * copy from old state to be sure
> > >   		 */
> > >   		*alloc = to_intel_crtc_state(for_crtc->state)-
> > > >wm.skl.ddb;
> > > -		return;
> > > +		if (!skl_ddb_entry_size(alloc))
> > > +			DRM_DEBUG_KMS("Cached pipe DDB is 0
> > > recalculate\n");
> > > +		else
> > > +			return;
> > >   	}
> > >   
> > > -	nth_active_pipe = hweight32(intel_state->active_crtcs &
> > > +	nth_active_pipe = hweight32(active_crtcs &
> > >   				    (drm_crtc_mask(for_crtc) -
> > > 1));
> > > -	pipe_size = ddb_size / hweight32(intel_state-
> > > >active_crtcs);
> > > +	pipe_size = ddb_size / hweight32(active_crtcs);
> > >   	alloc->start = nth_active_pipe * ddb_size /
> > > *num_active;
> > >   	alloc->end = alloc->start + pipe_size;
> > >   }
> > 
> > I'd love it if you also add a warning somewhere for active pipe
> > with no ddb allocation to prevent this from reoccuring in the
> > future. :)
> > But with the root cause being a invalid ddb allocation at boot,
> > won't the below one liner should fix it too, but better?
> 
> Above DEBUG message is actually warning. That will hit only if pipe
> is 
> active & DDB allocated for that pipe is "0" (we do return from caller
> if 
> !cstate->active).
> I can reword the msg to be WARN & make it something like "Pipe is
> active 
> with No DDB allocated, recompute ddb now". This will fix the issue
> as 
> well as add warning msg.
> 
> > 
> > I'l ltest it when f3-kbl becomes available again.
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index a488e068c3d6..63a47909f618 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5051,7 +5051,7 @@ skl_compute_wm(struct drm_atomic_state
> > *state)
> >   	 */
> >   	for_each_new_crtc_in_state(state, crtc, cstate, i)
> >   		changed = true;
> > -	if (!changed)
> > +	if (!changed && !to_i915(state->dev)->wm.distrust_bios_wm)
> >   		return 0;
> >   
> 
> This change should also solve the issue during boot.

Yeah I did some testing and this fixes it.
Looks like a bug in the original implementation of skl_compute_wm that
the KBL just happened to hit.

So I guess if others are hitting it too, then this needs
Fixes: 98d39494d375 ("drm/i915/gen9: Compute DDB allocation at atomic
check time (v4)")
Cc: <stable@vger.kernel.org> # v4.8+

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_______________________________________________
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Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2017-05-30 14:35 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-26 15:15 [PATCH 0/3] Remaining patches for WM cleanup series Mahesh Kumar
2017-05-26 15:15 ` [PATCH 1/3] drm/i915/skl+: Don't trust cached ddb values Mahesh Kumar
2017-05-26 21:23   ` Rodrigo Vivi
2017-05-29  5:56     ` Mahesh Kumar
2017-05-30 10:00   ` Maarten Lankhorst
2017-05-30 12:56     ` Mahesh Kumar
2017-05-30 14:35       ` Lankhorst, Maarten [this message]
2017-05-31  7:56   ` [PATCH] drm/i915: Always recompute watermarks when distrust_bios_wm is set Maarten Lankhorst
2017-05-31  7:56     ` Maarten Lankhorst
2017-05-31 10:42     ` Mahesh Kumar
2017-05-31 10:59       ` Maarten Lankhorst
2017-05-31 15:42     ` [PATCH] drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2 Maarten Lankhorst
2017-05-31 17:43       ` Mahesh Kumar
2017-05-31 17:43         ` Mahesh Kumar
2017-05-31 22:08       ` Matt Roper
2017-05-26 15:15 ` [PATCH 2/3] drm/i915/skl: New ddb allocation algorithm Mahesh Kumar
2017-05-31 22:16   ` Matt Roper
2017-06-01  5:59     ` Mahesh Kumar
2017-05-26 15:15 ` [PATCH 3/3] drm/i915/skl+: consider max supported plane pixel rate while scaling Mahesh Kumar
2017-06-01  8:24   ` Maarten Lankhorst
2017-05-26 15:43 ` ✗ Fi.CI.BAT: warning for Remaining patches for WM cleanup series (rev3) Patchwork

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