[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt, uart.

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
    Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt       |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile              |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts        |  39 +++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi          | 166 +++++++++++++++++++++
 6 files changed, 212 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt, uart.

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
    Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt       |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile              |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts        |  39 +++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi          | 166 +++++++++++++++++++++
 6 files changed, 212 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

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[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt, uart.

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
    Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt       |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile              |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts        |  39 +++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi          | 166 +++++++++++++++++++++
 6 files changed, 212 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v2 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
    "mediatek,mt2701"
+   "mediatek,mt2712"
    "mediatek,mt6580"
    "mediatek,mt6589"
    "mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
     Required root node properties:
       - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+    Required root node properties:
+      - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
     Required root node properties:
       - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
 	"mediatek,mt6580-sysirq"
 	"mediatek,mt6577-sysirq"
 	"mediatek,mt2701-sysirq"
+	"mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v2 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
    "mediatek,mt2701"
+   "mediatek,mt2712"
    "mediatek,mt6580"
    "mediatek,mt6589"
    "mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
     Required root node properties:
       - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+    Required root node properties:
+      - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
     Required root node properties:
       - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
 	"mediatek,mt6580-sysirq"
 	"mediatek,mt6577-sysirq"
 	"mediatek,mt2701-sysirq"
+	"mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v2 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.shen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
    "mediatek,mt2701"
+   "mediatek,mt2712"
    "mediatek,mt6580"
    "mediatek,mt6589"
    "mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
     Required root node properties:
       - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+    Required root node properties:
+      - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
     Required root node properties:
       - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
 	"mediatek,mt6580-sysirq"
 	"mediatek,mt6577-sysirq"
 	"mediatek,mt2701-sysirq"
+	"mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 0000000..e526c0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+	model = "MediaTek MT2712 evaluation board";
+	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+		linux,initrd-start = <0x45000000>;
+		linux,initrd-end   = <0x4a000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 0000000..6df0da9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt2712";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x000>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x001>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x200>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	uart_clk: dummy26m {
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart5: serial@1000f000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x1000f000 0 0x400>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		sysirq: interrupt-controller@10220a80 {
+			compatible = "mediatek,mt2712-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10220a80 0 0x40>;
+		};
+
+		gic: interrupt-controller@10510000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10510000 0 0x1000>,
+			      <0 0x10520000 0 0x1000>,
+			      <0 0x10540000 0 0x2000>,
+			      <0 0x10560000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart4: serial@11019000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11019000 0 0x400>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+	};
+};
+
-- 
1.9.1

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 0000000..e526c0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+	model = "MediaTek MT2712 evaluation board";
+	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+		linux,initrd-start = <0x45000000>;
+		linux,initrd-end   = <0x4a000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 0000000..6df0da9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt2712";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x000>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x001>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x200>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	uart_clk: dummy26m {
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart5: serial@1000f000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x1000f000 0 0x400>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		sysirq: interrupt-controller@10220a80 {
+			compatible = "mediatek,mt2712-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10220a80 0 0x40>;
+		};
+
+		gic: interrupt-controller@10510000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10510000 0 0x1000>,
+			      <0 0x10520000 0 0x1000>,
+			      <0 0x10540000 0 0x2000>,
+			      <0 0x10560000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		uart0: serial@11002000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart1: serial@11003000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart2: serial@11004000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart3: serial@11005000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart4: serial@11019000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11019000 0 0x400>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+	};
+};
+
-- 
1.9.1

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile       |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 0000000..e526c0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+	model = "MediaTek MT2712 evaluation board";
+	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x80000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+		linux,initrd-start = <0x45000000>;
+		linux,initrd-end   = <0x4a000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 0000000..6df0da9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.shen@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt2712";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+			};
+		};
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x000>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x001>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x200>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	uart_clk: dummy26m {
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart5: serial at 1000f000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x1000f000 0 0x400>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		sysirq: interrupt-controller at 10220a80 {
+			compatible = "mediatek,mt2712-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10220a80 0 0x40>;
+		};
+
+		gic: interrupt-controller at 10510000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10510000 0 0x1000>,
+			      <0 0x10520000 0 0x1000>,
+			      <0 0x10540000 0 0x2000>,
+			      <0 0x10560000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		uart0: serial at 11002000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11002000 0 0x400>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart1: serial at 11003000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11003000 0 0x400>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart2: serial at 11004000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11004000 0 0x400>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart3: serial at 11005000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x400>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart4: serial at 11019000 {
+			compatible = "mediatek,mt2712-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11019000 0 0x400>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+	};
+};
+
-- 
1.9.1

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 31/05/17 12:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>  3 files changed, 206 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

Why 6? I only count 3 cores...

> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial@1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller@10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller@10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,

If that's truly a GIC400, then the above is wrong (the CPU interface is
spread over 8kB).

I also suspect that the first 4kB are aliased over
0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
true SBSA tradition). If that's the case, then the size is actually 128kB.

> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;

Please check GICV as well, which probably behaves the same way.

> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;

Same thing here with 6 CPUs.

> +		};
> +
> +		uart0: serial@11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 

No PMU wired on this system?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 31/05/17 12:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>  3 files changed, 206 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

Why 6? I only count 3 cores...

> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial@1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller@10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller@10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,

If that's truly a GIC400, then the above is wrong (the CPU interface is
spread over 8kB).

I also suspect that the first 4kB are aliased over
0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
true SBSA tradition). If that's the case, then the size is actually 128kB.

> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;

Please check GICV as well, which probably behaves the same way.

> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;

Same thing here with 6 CPUs.

> +		};
> +
> +		uart0: serial@11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 

No PMU wired on this system?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 31/05/17 12:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>  3 files changed, 206 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};
> +
> +	memory at 40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu at 200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

Why 6? I only count 3 cores...

> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial at 1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller at 10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller at 10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,

If that's truly a GIC400, then the above is wrong (the CPU interface is
spread over 8kB).

I also suspect that the first 4kB are aliased over
0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
true SBSA tradition). If that's the case, then the size is actually 128kB.

> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;

Please check GICV as well, which probably behaves the same way.

> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;

Same thing here with 6 CPUs.

> +		};
> +
> +		uart0: serial at 11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial at 11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial at 11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial at 11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial at 11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 

No PMU wired on this system?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Matthias Brugger]

On 31/05/17 13:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>   3 files changed, 206 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};

Just declare serial0 here, as you don't use the others.

> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;

initrd-start and end should be dynamically set by the bootloader and not 
via a chosen node. Is your bootloader not able to do that?

> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

do you mean cortex-a53?

> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

same here.

Regards,
Matthias

> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial@1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller@10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller@10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,
> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;
> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +
> +		uart0: serial@11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Matthias Brugger]

On 31/05/17 13:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>   3 files changed, 206 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};

Just declare serial0 here, as you don't use the others.

> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;

initrd-start and end should be dynamically set by the bootloader and not 
via a chosen node. Is your bootloader not able to do that?

> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

do you mean cortex-a53?

> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

same here.

Regards,
Matthias

> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial@1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller@10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller@10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,
> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;
> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +
> +		uart0: serial@11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 
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[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Matthias Brugger]

On 31/05/17 13:39, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>   3 files changed, 206 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..e526c0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> +	model = "MediaTek MT2712 evaluation board";
> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +	};

Just declare serial0 here, as you don't use the others.

> +
> +	memory at 40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +		linux,initrd-start = <0x45000000>;
> +		linux,initrd-end   = <0x4a000000>;

initrd-start and end should be dynamically set by the bootloader and not 
via a chosen node. Is your bootloader not able to do that?

> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..6df0da9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <yt.shen@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt2712";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

do you mean cortex-a53?

> +			reg = <0x000>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";

same here.

Regards,
Matthias

> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu at 200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x200>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		clock-frequency = <26000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		uart5: serial at 1000f000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x1000f000 0 0x400>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		sysirq: interrupt-controller at 10220a80 {
> +			compatible = "mediatek,mt2712-sysirq",
> +				     "mediatek,mt6577-sysirq";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			reg = <0 0x10220a80 0 0x40>;
> +		};
> +
> +		gic: interrupt-controller at 10510000 {
> +			compatible = "arm,gic-400";
> +			#interrupt-cells = <3>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			reg = <0 0x10510000 0 0x1000>,
> +			      <0 0x10520000 0 0x1000>,
> +			      <0 0x10540000 0 0x2000>,
> +			      <0 0x10560000 0 0x2000>;
> +			interrupts = <GIC_PPI 9
> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +
> +		uart0: serial at 11002000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11002000 0 0x400>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial at 11003000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11003000 0 0x400>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial at 11004000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11004000 0 0x400>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial at 11005000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11005000 0 0x400>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial at 11019000 {
> +			compatible = "mediatek,mt2712-uart",
> +				     "mediatek,mt6577-uart";
> +			reg = <0 0x11019000 0 0x400>;
> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> +			clocks = <&uart_clk>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> 

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >  3 files changed, 206 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> > +
> > +	memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu@200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> 
> Why 6? I only count 3 cores...
OK, will change to GIC_CPU_MASK_RAW(0x13)

Sorry for the late reply.
> 
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial@1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller@10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller@10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> 
> If that's truly a GIC400, then the above is wrong (the CPU interface is
> spread over 8kB).
> 
> I also suspect that the first 4kB are aliased over
> 0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
> true SBSA tradition). If that's the case, then the size is actually 128kB.
The chip information at hand is not enough for me to answer this
question, if I have further document will check this part.

> 
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> 
> Please check GICV as well, which probably behaves the same way.
The reg entry I changed to 
  reg = <0 0x10510000 0 0x1000>,
        <0 0x10520000 0 0x20000>,
        <0 0x10540000 0 0x20000>,
        <0 0x10560000 0 0x20000>;
  is that correct?

The platform boot to shell successfully.  The boot message shows
additional different two lines:
...
[    0.000000] GIC: Adjusting CPU interface base to 0x000000001052f000
[    0.000000] GIC: Using split EOI/Deactivate mode
...

> 
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> 
> Same thing here with 6 CPUs.
Will change to GIC_CPU_MASK_RAW(0x13)

> 
> > +		};
> > +
> > +		uart0: serial@11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial@11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 
> 
> No PMU wired on this system?
After checking, there is a PMU on the system, but not verified yet.
And the plan for this patch series does not include PMU, is it
necessary?

Thanks for the review.

yt.shen

> 
> Thanks,
> 
> 	M.

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >  3 files changed, 206 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> > +
> > +	memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu@200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> 
> Why 6? I only count 3 cores...
OK, will change to GIC_CPU_MASK_RAW(0x13)

Sorry for the late reply.
> 
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial@1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller@10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller@10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> 
> If that's truly a GIC400, then the above is wrong (the CPU interface is
> spread over 8kB).
> 
> I also suspect that the first 4kB are aliased over
> 0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
> true SBSA tradition). If that's the case, then the size is actually 128kB.
The chip information at hand is not enough for me to answer this
question, if I have further document will check this part.

> 
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> 
> Please check GICV as well, which probably behaves the same way.
The reg entry I changed to 
  reg = <0 0x10510000 0 0x1000>,
        <0 0x10520000 0 0x20000>,
        <0 0x10540000 0 0x20000>,
        <0 0x10560000 0 0x20000>;
  is that correct?

The platform boot to shell successfully.  The boot message shows
additional different two lines:
...
[    0.000000] GIC: Adjusting CPU interface base to 0x000000001052f000
[    0.000000] GIC: Using split EOI/Deactivate mode
...

> 
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> 
> Same thing here with 6 CPUs.
Will change to GIC_CPU_MASK_RAW(0x13)

> 
> > +		};
> > +
> > +		uart0: serial@11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial@11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 
> 
> No PMU wired on this system?
After checking, there is a PMU on the system, but not verified yet.
And the plan for this patch series does not include PMU, is it
necessary?

Thanks for the review.

yt.shen

> 
> Thanks,
> 
> 	M.


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[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >  3 files changed, 206 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> > +
> > +	memory at 40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu at 0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu at 1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu at 200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> 
> Why 6? I only count 3 cores...
OK, will change to GIC_CPU_MASK_RAW(0x13)

Sorry for the late reply.
> 
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial at 1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller at 10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller at 10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> 
> If that's truly a GIC400, then the above is wrong (the CPU interface is
> spread over 8kB).
> 
> I also suspect that the first 4kB are aliased over
> 0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
> true SBSA tradition). If that's the case, then the size is actually 128kB.
The chip information at hand is not enough for me to answer this
question, if I have further document will check this part.

> 
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> 
> Please check GICV as well, which probably behaves the same way.
The reg entry I changed to 
  reg = <0 0x10510000 0 0x1000>,
        <0 0x10520000 0 0x20000>,
        <0 0x10540000 0 0x20000>,
        <0 0x10560000 0 0x20000>;
  is that correct?

The platform boot to shell successfully.  The boot message shows
additional different two lines:
...
[    0.000000] GIC: Adjusting CPU interface base to 0x000000001052f000
[    0.000000] GIC: Using split EOI/Deactivate mode
...

> 
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> 
> Same thing here with 6 CPUs.
Will change to GIC_CPU_MASK_RAW(0x13)

> 
> > +		};
> > +
> > +		uart0: serial at 11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial at 11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial at 11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial at 11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial at 11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 
> 
> No PMU wired on this system?
After checking, there is a PMU on the system, but not verified yet.
And the plan for this patch series does not include PMU, is it
necessary?

Thanks for the review.

yt.shen

> 
> Thanks,
> 
> 	M.

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 09/06/17 14:41, YT Shen wrote:
> On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
>> On 31/05/17 12:39, YT Shen wrote:
>>> This adds basic chip support for Mediatek 2712
>>>
>>> Signed-off-by: YT Shen <yt.shen@mediatek.com>
>>> ---
>>>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>>>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>>>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>>>  3 files changed, 206 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
>>> index 9fbfd32..fcc0604 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -1,3 +1,4 @@
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>> new file mode 100644
>>> index 0000000..e526c0f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * Copyright (c) 2017 MediaTek Inc.
>>> + * Author: YT Shen <yt.shen@mediatek.com>
>>> + *
>>> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "mt2712e.dtsi"
>>> +
>>> +/ {
>>> +	model = "MediaTek MT2712 evaluation board";
>>> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
>>> +
>>> +	aliases {
>>> +		serial0 = &uart0;
>>> +		serial1 = &uart1;
>>> +		serial2 = &uart2;
>>> +		serial3 = &uart3;
>>> +		serial4 = &uart4;
>>> +		serial5 = &uart5;
>>> +	};
>>> +
>>> +	memory@40000000 {
>>> +		device_type = "memory";
>>> +		reg = <0 0x40000000 0 0x80000000>;
>>> +	};
>>> +
>>> +	chosen {
>>> +		stdout-path = "serial0:921600n8";
>>> +		linux,initrd-start = <0x45000000>;
>>> +		linux,initrd-end   = <0x4a000000>;
>>> +	};
>>> +};
>>> +
>>> +&uart0 {
>>> +	status = "okay";
>>> +};
>>> +
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>> new file mode 100644
>>> index 0000000..6df0da9
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>> @@ -0,0 +1,166 @@
>>> +/*
>>> + * Copyright (c) 2017 MediaTek Inc.
>>> + * Author: YT Shen <yt.shen@mediatek.com>
>>> + *
>>> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +	compatible = "mediatek,mt2712";
>>> +	interrupt-parent = <&sysirq>;
>>> +	#address-cells = <2>;
>>> +	#size-cells = <2>;
>>> +
>>> +	cpus {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +
>>> +		cpu-map {
>>> +			cluster0 {
>>> +				core0 {
>>> +					cpu = <&cpu0>;
>>> +				};
>>> +				core1 {
>>> +					cpu = <&cpu1>;
>>> +				};
>>> +			};
>>> +
>>> +			cluster1 {
>>> +				core0 {
>>> +					cpu = <&cpu2>;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		cpu0: cpu@0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			reg = <0x000>;
>>> +		};
>>> +
>>> +		cpu1: cpu@1 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			reg = <0x001>;
>>> +			enable-method = "psci";
>>> +		};
>>> +
>>> +		cpu2: cpu@200 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a72";
>>> +			reg = <0x200>;
>>> +			enable-method = "psci";
>>> +		};
>>> +	};
>>> +
>>> +	psci {
>>> +		compatible = "arm,psci-0.2";
>>> +		method = "smc";
>>> +	};
>>> +
>>> +	uart_clk: dummy26m {
>>> +		compatible = "fixed-clock";
>>> +		clock-frequency = <26000000>;
>>> +		#clock-cells = <0>;
>>> +	};
>>> +
>>> +	timer {
>>> +		compatible = "arm,armv8-timer";
>>> +		interrupt-parent = <&gic>;
>>> +		interrupts = <GIC_PPI 13
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>
>> Why 6? I only count 3 cores...
> OK, will change to GIC_CPU_MASK_RAW(0x13)
> 
> Sorry for the late reply.
>>
>>> +			     <GIC_PPI 14
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 11
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 10
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
>>> +	};
>>> +
>>> +	soc {
>>> +		#address-cells = <2>;
>>> +		#size-cells = <2>;
>>> +		compatible = "simple-bus";
>>> +		ranges;
>>> +
>>> +		uart5: serial@1000f000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x1000f000 0 0x400>;
>>> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		sysirq: interrupt-controller@10220a80 {
>>> +			compatible = "mediatek,mt2712-sysirq",
>>> +				     "mediatek,mt6577-sysirq";
>>> +			interrupt-controller;
>>> +			#interrupt-cells = <3>;
>>> +			interrupt-parent = <&gic>;
>>> +			reg = <0 0x10220a80 0 0x40>;
>>> +		};
>>> +
>>> +		gic: interrupt-controller@10510000 {
>>> +			compatible = "arm,gic-400";
>>> +			#interrupt-cells = <3>;
>>> +			interrupt-parent = <&gic>;
>>> +			interrupt-controller;
>>> +			reg = <0 0x10510000 0 0x1000>,
>>> +			      <0 0x10520000 0 0x1000>,
>>
>> If that's truly a GIC400, then the above is wrong (the CPU interface is
>> spread over 8kB).
>>
>> I also suspect that the first 4kB are aliased over
>> 0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
>> true SBSA tradition). If that's the case, then the size is actually 128kB.
> The chip information at hand is not enough for me to answer this
> question, if I have further document will check this part.
> 
>>
>>> +			      <0 0x10540000 0 0x2000>,
>>> +			      <0 0x10560000 0 0x2000>;
>>
>> Please check GICV as well, which probably behaves the same way.
> The reg entry I changed to 
>   reg = <0 0x10510000 0 0x1000>,
>         <0 0x10520000 0 0x20000>,
>         <0 0x10540000 0 0x20000>,
>         <0 0x10560000 0 0x20000>;
>   is that correct?

Only you (or whoever integrated GIC400 on the platform) can know that.
I'd say that it is likely to be correct based on what's below, but
that's only an educated guess.

> 
> The platform boot to shell successfully.  The boot message shows
> additional different two lines:
> ...
> [    0.000000] GIC: Adjusting CPU interface base to 0x000000001052f000
> [    0.000000] GIC: Using split EOI/Deactivate mode
> ...

Seems OK to me.

>>
>>> +			interrupts = <GIC_PPI 9
>>> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>>
>> Same thing here with 6 CPUs.
> Will change to GIC_CPU_MASK_RAW(0x13)
> 
>>
>>> +		};
>>> +
>>> +		uart0: serial@11002000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11002000 0 0x400>;
>>> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart1: serial@11003000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11003000 0 0x400>;
>>> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart2: serial@11004000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11004000 0 0x400>;
>>> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart3: serial@11005000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11005000 0 0x400>;
>>> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart4: serial@11019000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11019000 0 0x400>;
>>> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +	};
>>> +};
>>> +
>>>
>>
>> No PMU wired on this system?
> After checking, there is a PMU on the system, but not verified yet.
> And the plan for this patch series does not include PMU, is it
> necessary?

Well, it is an important part of the system, and given that it comes
directly with the CPU cores, it'd be good to have it. But as always,
that's up to you.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 09/06/17 14:41, YT Shen wrote:
> On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
>> On 31/05/17 12:39, YT Shen wrote:
>>> This adds basic chip support for Mediatek 2712
>>>
>>> Signed-off-by: YT Shen <yt.shen@mediatek.com>
>>> ---
>>>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>>>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
>>>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
>>>  3 files changed, 206 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
>>> index 9fbfd32..fcc0604 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -1,3 +1,4 @@
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
>>>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>> new file mode 100644
>>> index 0000000..e526c0f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>>> @@ -0,0 +1,39 @@
>>> +/*
>>> + * Copyright (c) 2017 MediaTek Inc.
>>> + * Author: YT Shen <yt.shen@mediatek.com>
>>> + *
>>> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "mt2712e.dtsi"
>>> +
>>> +/ {
>>> +	model = "MediaTek MT2712 evaluation board";
>>> +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
>>> +
>>> +	aliases {
>>> +		serial0 = &uart0;
>>> +		serial1 = &uart1;
>>> +		serial2 = &uart2;
>>> +		serial3 = &uart3;
>>> +		serial4 = &uart4;
>>> +		serial5 = &uart5;
>>> +	};
>>> +
>>> +	memory at 40000000 {
>>> +		device_type = "memory";
>>> +		reg = <0 0x40000000 0 0x80000000>;
>>> +	};
>>> +
>>> +	chosen {
>>> +		stdout-path = "serial0:921600n8";
>>> +		linux,initrd-start = <0x45000000>;
>>> +		linux,initrd-end   = <0x4a000000>;
>>> +	};
>>> +};
>>> +
>>> +&uart0 {
>>> +	status = "okay";
>>> +};
>>> +
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>> new file mode 100644
>>> index 0000000..6df0da9
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>>> @@ -0,0 +1,166 @@
>>> +/*
>>> + * Copyright (c) 2017 MediaTek Inc.
>>> + * Author: YT Shen <yt.shen@mediatek.com>
>>> + *
>>> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +	compatible = "mediatek,mt2712";
>>> +	interrupt-parent = <&sysirq>;
>>> +	#address-cells = <2>;
>>> +	#size-cells = <2>;
>>> +
>>> +	cpus {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +
>>> +		cpu-map {
>>> +			cluster0 {
>>> +				core0 {
>>> +					cpu = <&cpu0>;
>>> +				};
>>> +				core1 {
>>> +					cpu = <&cpu1>;
>>> +				};
>>> +			};
>>> +
>>> +			cluster1 {
>>> +				core0 {
>>> +					cpu = <&cpu2>;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		cpu0: cpu at 0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			reg = <0x000>;
>>> +		};
>>> +
>>> +		cpu1: cpu at 1 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>> +			reg = <0x001>;
>>> +			enable-method = "psci";
>>> +		};
>>> +
>>> +		cpu2: cpu at 200 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a72";
>>> +			reg = <0x200>;
>>> +			enable-method = "psci";
>>> +		};
>>> +	};
>>> +
>>> +	psci {
>>> +		compatible = "arm,psci-0.2";
>>> +		method = "smc";
>>> +	};
>>> +
>>> +	uart_clk: dummy26m {
>>> +		compatible = "fixed-clock";
>>> +		clock-frequency = <26000000>;
>>> +		#clock-cells = <0>;
>>> +	};
>>> +
>>> +	timer {
>>> +		compatible = "arm,armv8-timer";
>>> +		interrupt-parent = <&gic>;
>>> +		interrupts = <GIC_PPI 13
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>
>> Why 6? I only count 3 cores...
> OK, will change to GIC_CPU_MASK_RAW(0x13)
> 
> Sorry for the late reply.
>>
>>> +			     <GIC_PPI 14
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 11
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
>>> +			     <GIC_PPI 10
>>> +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
>>> +	};
>>> +
>>> +	soc {
>>> +		#address-cells = <2>;
>>> +		#size-cells = <2>;
>>> +		compatible = "simple-bus";
>>> +		ranges;
>>> +
>>> +		uart5: serial at 1000f000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x1000f000 0 0x400>;
>>> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		sysirq: interrupt-controller at 10220a80 {
>>> +			compatible = "mediatek,mt2712-sysirq",
>>> +				     "mediatek,mt6577-sysirq";
>>> +			interrupt-controller;
>>> +			#interrupt-cells = <3>;
>>> +			interrupt-parent = <&gic>;
>>> +			reg = <0 0x10220a80 0 0x40>;
>>> +		};
>>> +
>>> +		gic: interrupt-controller at 10510000 {
>>> +			compatible = "arm,gic-400";
>>> +			#interrupt-cells = <3>;
>>> +			interrupt-parent = <&gic>;
>>> +			interrupt-controller;
>>> +			reg = <0 0x10510000 0 0x1000>,
>>> +			      <0 0x10520000 0 0x1000>,
>>
>> If that's truly a GIC400, then the above is wrong (the CPU interface is
>> spread over 8kB).
>>
>> I also suspect that the first 4kB are aliased over
>> 0x10520000:0x1052f000, and the second over 0x10530000:0x1053f000 (in the
>> true SBSA tradition). If that's the case, then the size is actually 128kB.
> The chip information at hand is not enough for me to answer this
> question, if I have further document will check this part.
> 
>>
>>> +			      <0 0x10540000 0 0x2000>,
>>> +			      <0 0x10560000 0 0x2000>;
>>
>> Please check GICV as well, which probably behaves the same way.
> The reg entry I changed to 
>   reg = <0 0x10510000 0 0x1000>,
>         <0 0x10520000 0 0x20000>,
>         <0 0x10540000 0 0x20000>,
>         <0 0x10560000 0 0x20000>;
>   is that correct?

Only you (or whoever integrated GIC400 on the platform) can know that.
I'd say that it is likely to be correct based on what's below, but
that's only an educated guess.

> 
> The platform boot to shell successfully.  The boot message shows
> additional different two lines:
> ...
> [    0.000000] GIC: Adjusting CPU interface base to 0x000000001052f000
> [    0.000000] GIC: Using split EOI/Deactivate mode
> ...

Seems OK to me.

>>
>>> +			interrupts = <GIC_PPI 9
>>> +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>>
>> Same thing here with 6 CPUs.
> Will change to GIC_CPU_MASK_RAW(0x13)
> 
>>
>>> +		};
>>> +
>>> +		uart0: serial at 11002000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11002000 0 0x400>;
>>> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart1: serial at 11003000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11003000 0 0x400>;
>>> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart2: serial at 11004000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11004000 0 0x400>;
>>> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart3: serial at 11005000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11005000 0 0x400>;
>>> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		uart4: serial at 11019000 {
>>> +			compatible = "mediatek,mt2712-uart",
>>> +				     "mediatek,mt6577-uart";
>>> +			reg = <0 0x11019000 0 0x400>;
>>> +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
>>> +			clocks = <&uart_clk>;
>>> +			status = "disabled";
>>> +		};
>>> +	};
>>> +};
>>> +
>>>
>>
>> No PMU wired on this system?
> After checking, there is a PMU on the system, but not verified yet.
> And the plan for this patch series does not include PMU, is it
> necessary?

Well, it is an important part of the system, and given that it comes
directly with the CPU cores, it'd be good to have it. But as always,
that's up to you.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 13:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >   3 files changed, 206 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> 
> Just declare serial0 here, as you don't use the others.
Ok, will remove the others.

Sorry for the late reply.

> > +
> > +	memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> 
> initrd-start and end should be dynamically set by the bootloader and not 
> via a chosen node. Is your bootloader not able to do that?
OK, will remove initrd start and end later.
Yes, current bootloader I used is new development and it does not send
any parameters now

> 
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> do you mean cortex-a53?
No, the cpu is cortex-a35.
Although I cannot find other cortex-a35 description in mainline kernel.

Thanks for the review.

yt.shen

> 
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> same here.
> 
> Regards,
> Matthias
> 
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu@200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial@1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller@10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller@10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> > +		};
> > +
> > +		uart0: serial@11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial@11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 13:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >   3 files changed, 206 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> 
> Just declare serial0 here, as you don't use the others.
Ok, will remove the others.

Sorry for the late reply.

> > +
> > +	memory@40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> 
> initrd-start and end should be dynamically set by the bootloader and not 
> via a chosen node. Is your bootloader not able to do that?
OK, will remove initrd start and end later.
Yes, current bootloader I used is new development and it does not send
any parameters now

> 
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> do you mean cortex-a53?
No, the cpu is cortex-a35.
Although I cannot find other cortex-a35 description in mainline kernel.

Thanks for the review.

yt.shen

> 
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> same here.
> 
> Regards,
> Matthias
> 
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu@200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial@1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller@10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller@10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> > +		};
> > +
> > +		uart0: serial@11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial@11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial@11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial@11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial@11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 13:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile       |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++++++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 ++++++++++++++++++++++++++++
> >   3 files changed, 206 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +	model = "MediaTek MT2712 evaluation board";
> > +	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +	};
> 
> Just declare serial0 here, as you don't use the others.
Ok, will remove the others.

Sorry for the late reply.

> > +
> > +	memory at 40000000 {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000 0 0x80000000>;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:921600n8";
> > +		linux,initrd-start = <0x45000000>;
> > +		linux,initrd-end   = <0x4a000000>;
> 
> initrd-start and end should be dynamically set by the bootloader and not 
> via a chosen node. Is your bootloader not able to do that?
OK, will remove initrd start and end later.
Yes, current bootloader I used is new development and it does not send
any parameters now

> 
> > +	};
> > +};
> > +
> > +&uart0 {
> > +	status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.shen@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt2712";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu-map {
> > +			cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +			cluster1 {
> > +				core0 {
> > +					cpu = <&cpu2>;
> > +				};
> > +			};
> > +		};
> > +
> > +		cpu0: cpu at 0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> do you mean cortex-a53?
No, the cpu is cortex-a35.
Although I cannot find other cortex-a35 description in mainline kernel.

Thanks for the review.

yt.shen

> 
> > +			reg = <0x000>;
> > +		};
> > +
> > +		cpu1: cpu at 1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> 
> same here.
> 
> Regards,
> Matthias
> 
> > +			reg = <0x001>;
> > +			enable-method = "psci";
> > +		};
> > +
> > +		cpu2: cpu at 200 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x200>;
> > +			enable-method = "psci";
> > +		};
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-0.2";
> > +		method = "smc";
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <26000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 11
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 10
> > +			      (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		uart5: serial at 1000f000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x1000f000 0 0x400>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		sysirq: interrupt-controller at 10220a80 {
> > +			compatible = "mediatek,mt2712-sysirq",
> > +				     "mediatek,mt6577-sysirq";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			reg = <0 0x10220a80 0 0x40>;
> > +		};
> > +
> > +		gic: interrupt-controller at 10510000 {
> > +			compatible = "arm,gic-400";
> > +			#interrupt-cells = <3>;
> > +			interrupt-parent = <&gic>;
> > +			interrupt-controller;
> > +			reg = <0 0x10510000 0 0x1000>,
> > +			      <0 0x10520000 0 0x1000>,
> > +			      <0 0x10540000 0 0x2000>,
> > +			      <0 0x10560000 0 0x2000>;
> > +			interrupts = <GIC_PPI 9
> > +				(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> > +		};
> > +
> > +		uart0: serial at 11002000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11002000 0 0x400>;
> > +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart1: serial at 11003000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11003000 0 0x400>;
> > +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart2: serial at 11004000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11004000 0 0x400>;
> > +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart3: serial at 11005000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11005000 0 0x400>;
> > +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +
> > +		uart4: serial at 11019000 {
> > +			compatible = "mediatek,mt2712-uart",
> > +				     "mediatek,mt6577-uart";
> > +			reg = <0 0x11019000 0 0x400>;
> > +			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
> > +			clocks = <&uart_clk>;
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > +
> > 

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 09/06/17 14:56, YT Shen wrote:
> On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:

[...]

>>> +		cpu0: cpu@0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>
>> do you mean cortex-a53?
> No, the cpu is cortex-a35.
> Although I cannot find other cortex-a35 description in mainline kernel.

We usually don't keep track of individual cores if we don't need to
(errata workarounds, for example). And for the record, here's some blurb
about Cortex-A35:

https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 09/06/17 14:56, YT Shen wrote:
> On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:

[...]

>>> +		cpu0: cpu@0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>
>> do you mean cortex-a53?
> No, the cpu is cortex-a35.
> Although I cannot find other cortex-a35 description in mainline kernel.

We usually don't keep track of individual cores if we don't need to
(errata workarounds, for example). And for the record, here's some blurb
about Cortex-A35:

https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[Marc Zyngier]

On 09/06/17 14:56, YT Shen wrote:
> On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:

[...]

>>> +		cpu0: cpu at 0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a35";
>>
>> do you mean cortex-a53?
> No, the cpu is cortex-a35.
> Although I cannot find other cortex-a35 description in mainline kernel.

We usually don't keep track of individual cores if we don't need to
(errata workarounds, for example). And for the record, here's some blurb
about Cortex-A35:

https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...