[PATCH 01/13] drm/i915/cnp: Introduce Cannonpoint PCH.

[PATCH 01/13] drm/i915/cnp: Introduce Cannonpoint PCH.

[Rodrigo Vivi]

Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:

- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.

All of these changes follow more the BXT style.

v2: Update definition to use dev_priv isntead of dev (Tvrtko).

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2fdfaf1..9e4c13e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -216,6 +216,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 				DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 					!IS_KABYLAKE(dev_priv));
+			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_CNP;
+				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bde554e..0b82604 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1151,6 +1151,7 @@ enum intel_pch {
 	PCH_LPT,	/* Lynxpoint PCH */
 	PCH_SPT,        /* Sunrisepoint PCH */
 	PCH_KBP,        /* Kabypoint PCH */
+	PCH_CNP,        /* Cannonpoint PCH */
 	PCH_NOP,
 };
 
@@ -2966,11 +2967,13 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
+#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7b7f55a..4cd9ee1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2548,7 +2548,8 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
 			I915_WRITE(SDEIIR, iir);
 			ret = IRQ_HANDLED;
 
-			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+			if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+			    HAS_PCH_CNP(dev_priv))
 				spt_irq_handler(dev_priv, iir);
 			else
 				cpt_irq_handler(dev_priv, iir);
@@ -4289,7 +4290,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->disable_vblank = gen8_disable_vblank;
 		if (IS_GEN9_LP(dev_priv))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
+		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
+			 HAS_PCH_CNP(dev_priv))
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 		else
 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
-- 
1.9.1

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[PATCH 02/13] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

[Rodrigo Vivi]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended mask for SPT and
CNP while not touching the code for any of the other platforms.

v2: (Rodrigo) Make platform agnostic and fix commit message.

Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 8 +++++++-
 drivers/gpu/drm/i915/i915_drv.h | 4 ++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e4c13e..90b646c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -170,6 +170,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
+			unsigned short id_ext = pch->device &
+				INTEL_PCH_DEVICE_ID_MASK_EXT;
+
 			dev_priv->pch_id = id;
 
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
@@ -206,7 +209,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
 					!IS_KABYLAKE(dev_priv));
-			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
+			} else if (id_ext == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 				WARN_ON(!IS_SKYLAKE(dev_priv) &&
@@ -219,6 +222,9 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_CNP;
+				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b82604..c31c0cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2959,6 +2959,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
+#define INTEL_PCH_DEVICE_ID_MASK_EXT		0xff80
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
@@ -2968,12 +2969,15 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
 #define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
 #define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
+#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+#define HAS_PCH_CNP_LP(dev_priv) \
+	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
-- 
1.9.1

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[PATCH 03/13] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

[Rodrigo Vivi]

RAWCLK_FREQ register has changed for platforms with CNP+.

[29:26] This field provides the denominator for the fractional
	part of the microsecond counter divider.  The numerator
	is fixed at 1. Program this field to the denominator of
	the fractional portion of reference frequency minus one.
	If the fraction is 0, program to 0.
	0100b = Fraction .2 MHz = Fraction 1/5.
	0000b = Fraction .0 MHz.

[25:16] This field provides the integer part of the microsecond
	counter divider. Program this field to the integer portion
	of the reference frequenct minus one.

Also this register tells us that proper raw clock should be read
from SFUSE_STRAP and programmed to this register. Up to this point
on other platforms we are reading instead of programming it so
probably relying on whatever BIOS had configured here.

Now on let's follow the spec and also program this register
fetching the right value from SFUSE_STRAP as Spec tells us to do.

v2: Read from SFUSE_STRAP and Program RAWCLK_FREQ instead of
    reading the value relying someone else will program that
    for us.
v3: Add missing else. (Jani)
v4: Addressing all Ville's catches:
    Use macro for shift bits instead of defining shift.
    Remove shift from the cleaning bits with mask that already
    has it.
    Add missing I915_WRITE to actually write the reg.
    Stop using useless DIV_ROUND_* on divider that is exact
    dividion and use DIV_ROUND_CLOSEST for the fraction part.
v5: Remove useless Read-Modify-Write on raclk_freq reg. (Ville).
v6: Change is per PCH instead of per platform.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |  5 +++++
 drivers/gpu/drm/i915/intel_cdclk.c | 29 ++++++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 231ee86..cb83fb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6838,6 +6838,10 @@ enum {
 #define  FDL_TP2_TIMER_SHIFT    10
 #define  FDL_TP2_TIMER_MASK     (3<<10)
 #define  RAWCLK_FREQ_MASK       0x3ff
+#define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
+#define  CNP_RAWCLK_DIV(div)	((div) << 16)
+#define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
+#define  CNP_RAWCLK_FRAC(frac)	((frac) << 26)
 
 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
 
@@ -8141,6 +8145,7 @@ enum {
 /* SFUSE_STRAP */
 #define SFUSE_STRAP			_MMIO(0xc2014)
 #define  SFUSE_STRAP_FUSE_LOCK		(1<<13)
+#define  SFUSE_STRAP_RAW_FREQUENCY	(1<<8)
 #define  SFUSE_STRAP_DISPLAY_DISABLED	(1<<7)
 #define  SFUSE_STRAP_CRT_DISABLED	(1<<6)
 #define  SFUSE_STRAP_DDIB_DETECTED	(1<<2)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 2979297..634c89f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1780,6 +1780,30 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 			   DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
 }
 
+static int cnp_rawclk(struct drm_i915_private *dev_priv)
+{
+	u32 rawclk;
+	int divider, fraction;
+
+	if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
+		/* 24 MHz */
+		divider = 24000;
+		fraction = 0;
+	} else {
+		/* 19.2 MHz */
+		divider = 19000;
+		fraction = 200;
+	}
+
+	rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
+	if (fraction)
+		rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
+							    fraction) - 1);
+
+	I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
+	return divider + fraction;
+}
+
 static int pch_rawclk(struct drm_i915_private *dev_priv)
 {
 	return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
@@ -1827,7 +1851,10 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
+
+	if (HAS_PCH_CNP(dev_priv))
+		dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
+	else if (HAS_PCH_SPLIT(dev_priv))
 		dev_priv->rawclk_freq = pch_rawclk(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
-- 
1.9.1

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[PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

[Rodrigo Vivi]

Split out BXT and CNP's setup_backlight(),enable_backlight(),
disable_backlight() and hz_to_pwm() into
two separate functions instead of reusing BXT function.

Reuse set_backlight() and get_backlight() since they have
no reference to the utility pin.

v2: Reuse BXT functions with controller 0 instead of
    redefining it. (Jani).
    Use dev_priv->rawclk_freq instead of getting the value
    from SFUSE_STRAP.
v3: Avoid setup backligh controller along with hooks and
    fully reuse hooks setup as suggested by Jani.
v4: Clean up commit message.
v5: Implement per PCH instead per platform.

v6: Introduce a new function for CNP.(Jani and Ville)

v7: Squash the all CNP Backlight support patches into a
single patch. (Jani)

v8: Correct indentation, remove unneeded blank lines and
correct mail address (Jani).

v9: Remove unused enum pipe. (by CI)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_panel.c | 93 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c8103f8..7e34a1b 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
 	}
 }
 
+static void cnp_disable_backlight(struct intel_connector *connector)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+	struct intel_panel *panel = &connector->panel;
+	u32 tmp;
+
+	intel_panel_actually_set_backlight(connector, 0);
+
+	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+		   tmp & ~BXT_BLC_PWM_ENABLE);
+}
+
 static void pwm_disable_backlight(struct intel_connector *connector)
 {
 	struct intel_panel *panel = &connector->panel;
@@ -1086,6 +1099,35 @@ static void bxt_enable_backlight(struct intel_connector *connector)
 			pwm_ctl | BXT_BLC_PWM_ENABLE);
 }
 
+static void cnp_enable_backlight(struct intel_connector *connector)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+	struct intel_panel *panel = &connector->panel;
+	u32 pwm_ctl;
+
+	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
+		DRM_DEBUG_KMS("backlight already enabled\n");
+		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
+		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+			   pwm_ctl);
+	}
+
+	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+		   panel->backlight.max);
+
+	intel_panel_actually_set_backlight(connector, panel->backlight.level);
+
+	pwm_ctl = 0;
+	if (panel->backlight.active_low_pwm)
+		pwm_ctl |= BXT_BLC_PWM_POLARITY;
+
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+		   pwm_ctl | BXT_BLC_PWM_ENABLE);
+}
+
 static void pwm_enable_backlight(struct intel_connector *connector)
 {
 	struct intel_panel *panel = &connector->panel;
@@ -1250,6 +1292,18 @@ void intel_backlight_device_unregister(struct intel_connector *connector)
 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
 
 /*
+ * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
+ *      Value is found in SFUSE_STRAP.
+ *      PWM increment = 1
+ */
+static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+
+	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
+}
+
+/*
  * BXT: PWM clock frequency = 19.2 MHz.
  */
 static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
@@ -1644,6 +1698,37 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
 	return 0;
 }
 
+static int
+cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
+{
+	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+	struct intel_panel *panel = &connector->panel;
+	u32 pwm_ctl, val;
+
+	panel->backlight.controller = dev_priv->vbt.backlight.controller;
+
+	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+	panel->backlight.max =
+		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
+
+	if (!panel->backlight.max)
+		panel->backlight.max = get_backlight_max_vbt(connector);
+
+	if (!panel->backlight.max)
+		return -ENODEV;
+
+	val = bxt_get_backlight(connector);
+	val = intel_panel_compute_brightness(connector, val);
+	panel->backlight.level = clamp(val, panel->backlight.min,
+				       panel->backlight.max);
+
+	panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
+
+	return 0;
+}
+
 static int pwm_setup_backlight(struct intel_connector *connector,
 			       enum pipe pipe)
 {
@@ -1760,6 +1845,14 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
 		panel->backlight.set = bxt_set_backlight;
 		panel->backlight.get = bxt_get_backlight;
 		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
+	} else if (HAS_PCH_CNP(dev_priv)) {
+		panel->backlight.setup = cnp_setup_backlight;
+		panel->backlight.enable = cnp_enable_backlight;
+		panel->backlight.disable = cnp_disable_backlight;
+		panel->backlight.set = bxt_set_backlight;
+		panel->backlight.get = bxt_get_backlight;
+		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
 	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
 		   HAS_PCH_KBP(dev_priv)) {
 		panel->backlight.setup = lpt_setup_backlight;
-- 
1.9.1

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Re: [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

[Pandiyan, Dhinakaran]

On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> Split out BXT and CNP's setup_backlight(),enable_backlight(),
> disable_backlight() and hz_to_pwm() into
> two separate functions instead of reusing BXT function.
> 
> Reuse set_backlight() and get_backlight() since they have
> no reference to the utility pin.
> 
> v2: Reuse BXT functions with controller 0 instead of
>     redefining it. (Jani).
>     Use dev_priv->rawclk_freq instead of getting the value
>     from SFUSE_STRAP.
> v3: Avoid setup backligh controller along with hooks and
>     fully reuse hooks setup as suggested by Jani.
> v4: Clean up commit message.
> v5: Implement per PCH instead per platform.
> 
> v6: Introduce a new function for CNP.(Jani and Ville)
> 
> v7: Squash the all CNP Backlight support patches into a
> single patch. (Jani)
> 
> v8: Correct indentation, remove unneeded blank lines and
> correct mail address (Jani).
> 
> v9: Remove unused enum pipe. (by CI)
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_panel.c | 93 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index c8103f8..7e34a1b 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
>  	}
>  }
>  
> +static void cnp_disable_backlight(struct intel_connector *connector)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +	struct intel_panel *panel = &connector->panel;
> +	u32 tmp;
> +
> +	intel_panel_actually_set_backlight(connector, 0);
> +
> +	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +		   tmp & ~BXT_BLC_PWM_ENABLE);
> +}
> +
>  static void pwm_disable_backlight(struct intel_connector *connector)
>  {
>  	struct intel_panel *panel = &connector->panel;
> @@ -1086,6 +1099,35 @@ static void bxt_enable_backlight(struct intel_connector *connector)
>  			pwm_ctl | BXT_BLC_PWM_ENABLE);
>  }
>  
> +static void cnp_enable_backlight(struct intel_connector *connector)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +	struct intel_panel *panel = &connector->panel;
> +	u32 pwm_ctl;
> +
> +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));

Shouldn't this be BLC_PWM_PCH_CTL1?

I think reusing CPU register definitions for PCH is confusing. Even more
so, when we already have separate definitions for PCH.

BSpec specifically refers to these registers as SBLC_PWM_CTL1,
SBLC_PWM_FREQ and SBLC_PWM_DUTY.




> +	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> +		DRM_DEBUG_KMS("backlight already enabled\n");
> +		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> +		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +			   pwm_ctl);
> +	}
> +
> +	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> +		   panel->backlight.max);
> +
> +	intel_panel_actually_set_backlight(connector, panel->backlight.level);
> +
> +	pwm_ctl = 0;
> +	if (panel->backlight.active_low_pwm)
> +		pwm_ctl |= BXT_BLC_PWM_POLARITY;
> +
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> +	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +		   pwm_ctl | BXT_BLC_PWM_ENABLE);
> +}
> +
>  static void pwm_enable_backlight(struct intel_connector *connector)
>  {
>  	struct intel_panel *panel = &connector->panel;
> @@ -1250,6 +1292,18 @@ void intel_backlight_device_unregister(struct intel_connector *connector)
>  #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
>  
>  /*
> + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
> + *      Value is found in SFUSE_STRAP.
> + *      PWM increment = 1
> + */
> +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +
> +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
> +}
> +
> +/*
>   * BXT: PWM clock frequency = 19.2 MHz.
>   */
>  static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> @@ -1644,6 +1698,37 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
>  	return 0;
>  }
>  
> +static int
> +cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> +	struct intel_panel *panel = &connector->panel;
> +	u32 pwm_ctl, val;
> +
> +	panel->backlight.controller = dev_priv->vbt.backlight.controller;

Are there are two controllers in CNP? I did not find any references in
BSpec, can you please confirm?


> +
> +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> +	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> +	panel->backlight.max =
> +		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
> +
> +	if (!panel->backlight.max)
> +		panel->backlight.max = get_backlight_max_vbt(connector);
> +
> +	if (!panel->backlight.max)
> +		return -ENODEV;
> +
> +	val = bxt_get_backlight(connector);
> +	val = intel_panel_compute_brightness(connector, val);
> +	panel->backlight.level = clamp(val, panel->backlight.min,
> +				       panel->backlight.max);
> +
> +	panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
> +
> +	return 0;
> +}
> +
>  static int pwm_setup_backlight(struct intel_connector *connector,
>  			       enum pipe pipe)
>  {
> @@ -1760,6 +1845,14 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
>  		panel->backlight.set = bxt_set_backlight;
>  		panel->backlight.get = bxt_get_backlight;
>  		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> +		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
^Spurious line.

> +	} else if (HAS_PCH_CNP(dev_priv)) {
> +		panel->backlight.setup = cnp_setup_backlight;
> +		panel->backlight.enable = cnp_enable_backlight;
> +		panel->backlight.disable = cnp_disable_backlight;
> +		panel->backlight.set = bxt_set_backlight;
> +		panel->backlight.get = bxt_get_backlight;
> +		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>  		   HAS_PCH_KBP(dev_priv)) {
>  		panel->backlight.setup = lpt_setup_backlight;

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Re: [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

[Vivi, Rodrigo]

On Thu, 2017-06-01 at 02:15 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> > Split out BXT and CNP's setup_backlight(),enable_backlight(),
> > disable_backlight() and hz_to_pwm() into
> > two separate functions instead of reusing BXT function.
> > 
> > Reuse set_backlight() and get_backlight() since they have
> > no reference to the utility pin.
> > 
> > v2: Reuse BXT functions with controller 0 instead of
> >     redefining it. (Jani).
> >     Use dev_priv->rawclk_freq instead of getting the value
> >     from SFUSE_STRAP.
> > v3: Avoid setup backligh controller along with hooks and
> >     fully reuse hooks setup as suggested by Jani.
> > v4: Clean up commit message.
> > v5: Implement per PCH instead per platform.
> > 
> > v6: Introduce a new function for CNP.(Jani and Ville)
> > 
> > v7: Squash the all CNP Backlight support patches into a
> > single patch. (Jani)
> > 
> > v8: Correct indentation, remove unneeded blank lines and
> > correct mail address (Jani).
> > 
> > v9: Remove unused enum pipe. (by CI)
> > 
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Suggested-by: Jani Nikula <jani.nikula@intel.com>
> > Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_panel.c | 93 ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 93 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> > index c8103f8..7e34a1b 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> >  	}
> >  }
> >  
> > +static void cnp_disable_backlight(struct intel_connector *connector)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 tmp;
> > +
> > +	intel_panel_actually_set_backlight(connector, 0);
> > +
> > +	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +		   tmp & ~BXT_BLC_PWM_ENABLE);
> > +}
> > +
> >  static void pwm_disable_backlight(struct intel_connector *connector)
> >  {
> >  	struct intel_panel *panel = &connector->panel;
> > @@ -1086,6 +1099,35 @@ static void bxt_enable_backlight(struct intel_connector *connector)
> >  			pwm_ctl | BXT_BLC_PWM_ENABLE);
> >  }
> >  
> > +static void cnp_enable_backlight(struct intel_connector *connector)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 pwm_ctl;
> > +
> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> 
> Shouldn't this be BLC_PWM_PCH_CTL1?

Not sure. Are we going to
1) redefine everything? including all registers and bit definitions that
are identical?
2) reuse part of CPU and part of old PCH?

> 
> I think reusing CPU register definitions for PCH is confusing. Even more
> so, when we already have separate definitions for PCH.

Actually the BXT backlight implementation was used on CNP. So all of
this was moved from CPU to PCH.

> BSpec specifically refers to these registers as SBLC_PWM_CTL1,
> SBLC_PWM_FREQ and SBLC_PWM_DUTY.

I believe we traditionally try to reuse registers definitions that are
there already instead of redefine everytime that spec changes the name.

For me all of this implementation is more like BXT so we should proceed
with this from this point and on and reusing as much as we can.

However during the review it was decided to not reuse directly the bxt
functions... So now I'm not sure in which point we should stop
duplicating code anymore... 

> 
> 
> 
> 
> > +	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> > +		DRM_DEBUG_KMS("backlight already enabled\n");
> > +		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> > +		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +			   pwm_ctl);
> > +	}
> > +
> > +	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> > +		   panel->backlight.max);
> > +
> > +	intel_panel_actually_set_backlight(connector, panel->backlight.level);
> > +
> > +	pwm_ctl = 0;
> > +	if (panel->backlight.active_low_pwm)
> > +		pwm_ctl |= BXT_BLC_PWM_POLARITY;
> > +
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> > +	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +		   pwm_ctl | BXT_BLC_PWM_ENABLE);
> > +}
> > +
> >  static void pwm_enable_backlight(struct intel_connector *connector)
> >  {
> >  	struct intel_panel *panel = &connector->panel;
> > @@ -1250,6 +1292,18 @@ void intel_backlight_device_unregister(struct intel_connector *connector)
> >  #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
> >  
> >  /*
> > + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
> > + *      Value is found in SFUSE_STRAP.
> > + *      PWM increment = 1
> > + */
> > +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +
> > +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
> > +}
> > +
> > +/*
> >   * BXT: PWM clock frequency = 19.2 MHz.
> >   */
> >  static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> > @@ -1644,6 +1698,37 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
> >  	return 0;
> >  }
> >  
> > +static int
> > +cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 pwm_ctl, val;
> > +
> > +	panel->backlight.controller = dev_priv->vbt.backlight.controller;
> 
> Are there are two controllers in CNP? I did not find any references in
> BSpec, can you please confirm?

We only have one controller on CNP. We might have more coming soon, but
for the current CNP platforms there is only one controller and I do
believe we could just ignore VBT for now. But question now is:

1. Leave as is.

2. set this panel->backlight.controller = 0; and move on.

3. Use BLC_PWM_PCH_CTL1 directly and  BXT_BLC_PWM_FREQ(0) and _DUTY(0)

4. Use BLC_PWM_PCH_CTL1 directly and reimplement SBLC_PWM_FREQ and
SBLC_PWM_DUTY.

5. Reimplement SBLC_PWM_CTL1, SBLC_PWM_FREQ and SBLC_PWM_DUTY.

Although 4 or 5 seems to be the right way to go now I'd like to
highlight that maybe next PCH can be more like BXT than like CNP. So we
would need to reimplement everything again.

I honestly don't mind which option we go. My position was to fully reuse
BXT as I had initially done. But that was nacked. So please just let me
know the direction that I provide the patch ;)

Thanks,
Rodrigo.

> 
> 
> > +
> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +
> > +	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> > +	panel->backlight.max =
> > +		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
> > +
> > +	if (!panel->backlight.max)
> > +		panel->backlight.max = get_backlight_max_vbt(connector);
> > +
> > +	if (!panel->backlight.max)
> > +		return -ENODEV;
> > +
> > +	val = bxt_get_backlight(connector);
> > +	val = intel_panel_compute_brightness(connector, val);
> > +	panel->backlight.level = clamp(val, panel->backlight.min,
> > +				       panel->backlight.max);
> > +
> > +	panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
> > +
> > +	return 0;
> > +}
> > +
> >  static int pwm_setup_backlight(struct intel_connector *connector,
> >  			       enum pipe pipe)
> >  {
> > @@ -1760,6 +1845,14 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
> >  		panel->backlight.set = bxt_set_backlight;
> >  		panel->backlight.get = bxt_get_backlight;
> >  		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> > +		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> ^Spurious line.
> 
> > +	} else if (HAS_PCH_CNP(dev_priv)) {
> > +		panel->backlight.setup = cnp_setup_backlight;
> > +		panel->backlight.enable = cnp_enable_backlight;
> > +		panel->backlight.disable = cnp_disable_backlight;
> > +		panel->backlight.set = bxt_set_backlight;
> > +		panel->backlight.get = bxt_get_backlight;
> > +		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
> >  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
> >  		   HAS_PCH_KBP(dev_priv)) {
> >  		panel->backlight.setup = lpt_setup_backlight;
> 

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Re: [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

[Pandiyan, Dhinakaran]

Based on your clarification the second option feels like the right choice, with a relevant comment in code. Like you said, we get to retain BXT register definitions and clarify that the register is on a PCH for CNP. 

-DK

-----Original Message-----
From: Vivi, Rodrigo 
Sent: Thursday, June 1, 2017 9:29 AM
To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

On Thu, 2017-06-01 at 02:15 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> > Split out BXT and CNP's setup_backlight(),enable_backlight(),
> > disable_backlight() and hz_to_pwm() into two separate functions 
> > instead of reusing BXT function.
> > 
> > Reuse set_backlight() and get_backlight() since they have no 
> > reference to the utility pin.
> > 
> > v2: Reuse BXT functions with controller 0 instead of
> >     redefining it. (Jani).
> >     Use dev_priv->rawclk_freq instead of getting the value
> >     from SFUSE_STRAP.
> > v3: Avoid setup backligh controller along with hooks and
> >     fully reuse hooks setup as suggested by Jani.
> > v4: Clean up commit message.
> > v5: Implement per PCH instead per platform.
> > 
> > v6: Introduce a new function for CNP.(Jani and Ville)
> > 
> > v7: Squash the all CNP Backlight support patches into a single 
> > patch. (Jani)
> > 
> > v8: Correct indentation, remove unneeded blank lines and correct 
> > mail address (Jani).
> > 
> > v9: Remove unused enum pipe. (by CI)
> > 
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Suggested-by: Jani Nikula <jani.nikula@intel.com>
> > Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_panel.c | 93 
> > ++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 93 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> > b/drivers/gpu/drm/i915/intel_panel.c
> > index c8103f8..7e34a1b 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
> >  	}
> >  }
> >  
> > +static void cnp_disable_backlight(struct intel_connector 
> > +*connector) {
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 tmp;
> > +
> > +	intel_panel_actually_set_backlight(connector, 0);
> > +
> > +	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +		   tmp & ~BXT_BLC_PWM_ENABLE);
> > +}
> > +
> >  static void pwm_disable_backlight(struct intel_connector 
> > *connector)  {
> >  	struct intel_panel *panel = &connector->panel; @@ -1086,6 +1099,35 
> > @@ static void bxt_enable_backlight(struct intel_connector *connector)
> >  			pwm_ctl | BXT_BLC_PWM_ENABLE);
> >  }
> >  
> > +static void cnp_enable_backlight(struct intel_connector *connector) 
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 pwm_ctl;
> > +
> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> 
> Shouldn't this be BLC_PWM_PCH_CTL1?

Not sure. Are we going to
1) redefine everything? including all registers and bit definitions that are identical?
2) reuse part of CPU and part of old PCH?

> 
> I think reusing CPU register definitions for PCH is confusing. Even 
> more so, when we already have separate definitions for PCH.

Actually the BXT backlight implementation was used on CNP. So all of this was moved from CPU to PCH.

> BSpec specifically refers to these registers as SBLC_PWM_CTL1, 
> SBLC_PWM_FREQ and SBLC_PWM_DUTY.

I believe we traditionally try to reuse registers definitions that are there already instead of redefine everytime that spec changes the name.

For me all of this implementation is more like BXT so we should proceed with this from this point and on and reusing as much as we can.

However during the review it was decided to not reuse directly the bxt functions... So now I'm not sure in which point we should stop duplicating code anymore... 

> 
> 
> 
> 
> > +	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
> > +		DRM_DEBUG_KMS("backlight already enabled\n");
> > +		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> > +		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +			   pwm_ctl);
> > +	}
> > +
> > +	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> > +		   panel->backlight.max);
> > +
> > +	intel_panel_actually_set_backlight(connector, 
> > +panel->backlight.level);
> > +
> > +	pwm_ctl = 0;
> > +	if (panel->backlight.active_low_pwm)
> > +		pwm_ctl |= BXT_BLC_PWM_POLARITY;
> > +
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> > +	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> > +		   pwm_ctl | BXT_BLC_PWM_ENABLE); }
> > +
> >  static void pwm_enable_backlight(struct intel_connector *connector)  
> > {
> >  	struct intel_panel *panel = &connector->panel; @@ -1250,6 +1292,18 
> > @@ void intel_backlight_device_unregister(struct intel_connector 
> > *connector)  #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
> >  
> >  /*
> > + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
> > + *      Value is found in SFUSE_STRAP.
> > + *      PWM increment = 1
> > + */
> > +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 
> > +pwm_freq_hz) {
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +
> > +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz); 
> > +}
> > +
> > +/*
> >   * BXT: PWM clock frequency = 19.2 MHz.
> >   */
> >  static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 
> > pwm_freq_hz) @@ -1644,6 +1698,37 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
> >  	return 0;
> >  }
> >  
> > +static int
> > +cnp_setup_backlight(struct intel_connector *connector, enum pipe 
> > +unused) {
> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > +	struct intel_panel *panel = &connector->panel;
> > +	u32 pwm_ctl, val;
> > +
> > +	panel->backlight.controller = dev_priv->vbt.backlight.controller;
> 
> Are there are two controllers in CNP? I did not find any references in 
> BSpec, can you please confirm?

We only have one controller on CNP. We might have more coming soon, but for the current CNP platforms there is only one controller and I do believe we could just ignore VBT for now. But question now is:

1. Leave as is.

2. set this panel->backlight.controller = 0; and move on.

3. Use BLC_PWM_PCH_CTL1 directly and  BXT_BLC_PWM_FREQ(0) and _DUTY(0)

4. Use BLC_PWM_PCH_CTL1 directly and reimplement SBLC_PWM_FREQ and SBLC_PWM_DUTY.

5. Reimplement SBLC_PWM_CTL1, SBLC_PWM_FREQ and SBLC_PWM_DUTY.

Although 4 or 5 seems to be the right way to go now I'd like to highlight that maybe next PCH can be more like BXT than like CNP. So we would need to reimplement everything again.

I honestly don't mind which option we go. My position was to fully reuse BXT as I had initially done. But that was nacked. So please just let me know the direction that I provide the patch ;)

Thanks,
Rodrigo.

> 
> 
> > +
> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> > +
> > +	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> > +	panel->backlight.max =
> > +		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
> > +
> > +	if (!panel->backlight.max)
> > +		panel->backlight.max = get_backlight_max_vbt(connector);
> > +
> > +	if (!panel->backlight.max)
> > +		return -ENODEV;
> > +
> > +	val = bxt_get_backlight(connector);
> > +	val = intel_panel_compute_brightness(connector, val);
> > +	panel->backlight.level = clamp(val, panel->backlight.min,
> > +				       panel->backlight.max);
> > +
> > +	panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
> > +
> > +	return 0;
> > +}
> > +
> >  static int pwm_setup_backlight(struct intel_connector *connector,
> >  			       enum pipe pipe)
> >  {
> > @@ -1760,6 +1845,14 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
> >  		panel->backlight.set = bxt_set_backlight;
> >  		panel->backlight.get = bxt_get_backlight;
> >  		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> > +		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> ^Spurious line.
> 
> > +	} else if (HAS_PCH_CNP(dev_priv)) {
> > +		panel->backlight.setup = cnp_setup_backlight;
> > +		panel->backlight.enable = cnp_enable_backlight;
> > +		panel->backlight.disable = cnp_disable_backlight;
> > +		panel->backlight.set = bxt_set_backlight;
> > +		panel->backlight.get = bxt_get_backlight;
> > +		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
> >  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
> >  		   HAS_PCH_KBP(dev_priv)) {
> >  		panel->backlight.setup = lpt_setup_backlight;
> 

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Re: [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.

[Jani Nikula]

On Thu, 01 Jun 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote:
> Based on your clarification the second option feels like the right
> choice, with a relevant comment in code. Like you said, we get to
> retain BXT register definitions and clarify that the register is on a
> PCH for CNP.

Ack. We can also clarify/unify the definitions later on as needed.

BR,
Jani.

>
> -DK
>
> -----Original Message-----
> From: Vivi, Rodrigo 
> Sent: Thursday, June 1, 2017 9:29 AM
> To: Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 04/13] drm/i915/cnp: Backlight support for CNP.
>
> On Thu, 2017-06-01 at 02:15 +0000, Pandiyan, Dhinakaran wrote:
>> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
>> > Split out BXT and CNP's setup_backlight(),enable_backlight(),
>> > disable_backlight() and hz_to_pwm() into two separate functions 
>> > instead of reusing BXT function.
>> > 
>> > Reuse set_backlight() and get_backlight() since they have no 
>> > reference to the utility pin.
>> > 
>> > v2: Reuse BXT functions with controller 0 instead of
>> >     redefining it. (Jani).
>> >     Use dev_priv->rawclk_freq instead of getting the value
>> >     from SFUSE_STRAP.
>> > v3: Avoid setup backligh controller along with hooks and
>> >     fully reuse hooks setup as suggested by Jani.
>> > v4: Clean up commit message.
>> > v5: Implement per PCH instead per platform.
>> > 
>> > v6: Introduce a new function for CNP.(Jani and Ville)
>> > 
>> > v7: Squash the all CNP Backlight support patches into a single 
>> > patch. (Jani)
>> > 
>> > v8: Correct indentation, remove unneeded blank lines and correct 
>> > mail address (Jani).
>> > 
>> > v9: Remove unused enum pipe. (by CI)
>> > 
>> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> > Suggested-by: Jani Nikula <jani.nikula@intel.com>
>> > Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
>> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> > Cc: Jani Nikula <jani.nikula@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/intel_panel.c | 93 
>> > ++++++++++++++++++++++++++++++++++++++
>> >  1 file changed, 93 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/intel_panel.c 
>> > b/drivers/gpu/drm/i915/intel_panel.c
>> > index c8103f8..7e34a1b 100644
>> > --- a/drivers/gpu/drm/i915/intel_panel.c
>> > +++ b/drivers/gpu/drm/i915/intel_panel.c
>> > @@ -796,6 +796,19 @@ static void bxt_disable_backlight(struct intel_connector *connector)
>> >  	}
>> >  }
>> >  
>> > +static void cnp_disable_backlight(struct intel_connector 
>> > +*connector) {
>> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> > +	struct intel_panel *panel = &connector->panel;
>> > +	u32 tmp;
>> > +
>> > +	intel_panel_actually_set_backlight(connector, 0);
>> > +
>> > +	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> > +		   tmp & ~BXT_BLC_PWM_ENABLE);
>> > +}
>> > +
>> >  static void pwm_disable_backlight(struct intel_connector 
>> > *connector)  {
>> >  	struct intel_panel *panel = &connector->panel; @@ -1086,6 +1099,35 
>> > @@ static void bxt_enable_backlight(struct intel_connector *connector)
>> >  			pwm_ctl | BXT_BLC_PWM_ENABLE);
>> >  }
>> >  
>> > +static void cnp_enable_backlight(struct intel_connector *connector) 
>> > +{
>> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> > +	struct intel_panel *panel = &connector->panel;
>> > +	u32 pwm_ctl;
>> > +
>> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> 
>> Shouldn't this be BLC_PWM_PCH_CTL1?
>
> Not sure. Are we going to
> 1) redefine everything? including all registers and bit definitions that are identical?
> 2) reuse part of CPU and part of old PCH?
>
>> 
>> I think reusing CPU register definitions for PCH is confusing. Even 
>> more so, when we already have separate definitions for PCH.
>
> Actually the BXT backlight implementation was used on CNP. So all of this was moved from CPU to PCH.
>
>> BSpec specifically refers to these registers as SBLC_PWM_CTL1, 
>> SBLC_PWM_FREQ and SBLC_PWM_DUTY.
>
> I believe we traditionally try to reuse registers definitions that are there already instead of redefine everytime that spec changes the name.
>
> For me all of this implementation is more like BXT so we should proceed with this from this point and on and reusing as much as we can.
>
> However during the review it was decided to not reuse directly the bxt functions... So now I'm not sure in which point we should stop duplicating code anymore... 
>
>> 
>> 
>> 
>> 
>> > +	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
>> > +		DRM_DEBUG_KMS("backlight already enabled\n");
>> > +		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
>> > +		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> > +			   pwm_ctl);
>> > +	}
>> > +
>> > +	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
>> > +		   panel->backlight.max);
>> > +
>> > +	intel_panel_actually_set_backlight(connector, 
>> > +panel->backlight.level);
>> > +
>> > +	pwm_ctl = 0;
>> > +	if (panel->backlight.active_low_pwm)
>> > +		pwm_ctl |= BXT_BLC_PWM_POLARITY;
>> > +
>> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
>> > +	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> > +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
>> > +		   pwm_ctl | BXT_BLC_PWM_ENABLE); }
>> > +
>> >  static void pwm_enable_backlight(struct intel_connector *connector)  
>> > {
>> >  	struct intel_panel *panel = &connector->panel; @@ -1250,6 +1292,18 
>> > @@ void intel_backlight_device_unregister(struct intel_connector 
>> > *connector)  #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
>> >  
>> >  /*
>> > + * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
>> > + *      Value is found in SFUSE_STRAP.
>> > + *      PWM increment = 1
>> > + */
>> > +static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 
>> > +pwm_freq_hz) {
>> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> > +
>> > +	return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz); 
>> > +}
>> > +
>> > +/*
>> >   * BXT: PWM clock frequency = 19.2 MHz.
>> >   */
>> >  static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 
>> > pwm_freq_hz) @@ -1644,6 +1698,37 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe
>> >  	return 0;
>> >  }
>> >  
>> > +static int
>> > +cnp_setup_backlight(struct intel_connector *connector, enum pipe 
>> > +unused) {
>> > +	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> > +	struct intel_panel *panel = &connector->panel;
>> > +	u32 pwm_ctl, val;
>> > +
>> > +	panel->backlight.controller = dev_priv->vbt.backlight.controller;
>> 
>> Are there are two controllers in CNP? I did not find any references in 
>> BSpec, can you please confirm?
>
> We only have one controller on CNP. We might have more coming soon, but for the current CNP platforms there is only one controller and I do believe we could just ignore VBT for now. But question now is:
>
> 1. Leave as is.
>
> 2. set this panel->backlight.controller = 0; and move on.
>
> 3. Use BLC_PWM_PCH_CTL1 directly and  BXT_BLC_PWM_FREQ(0) and _DUTY(0)
>
> 4. Use BLC_PWM_PCH_CTL1 directly and reimplement SBLC_PWM_FREQ and SBLC_PWM_DUTY.
>
> 5. Reimplement SBLC_PWM_CTL1, SBLC_PWM_FREQ and SBLC_PWM_DUTY.
>
> Although 4 or 5 seems to be the right way to go now I'd like to highlight that maybe next PCH can be more like BXT than like CNP. So we would need to reimplement everything again.
>
> I honestly don't mind which option we go. My position was to fully reuse BXT as I had initially done. But that was nacked. So please just let me know the direction that I provide the patch ;)
>
> Thanks,
> Rodrigo.
>
>> 
>> 
>> > +
>> > +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>> > +
>> > +	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
>> > +	panel->backlight.max =
>> > +		I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
>> > +
>> > +	if (!panel->backlight.max)
>> > +		panel->backlight.max = get_backlight_max_vbt(connector);
>> > +
>> > +	if (!panel->backlight.max)
>> > +		return -ENODEV;
>> > +
>> > +	val = bxt_get_backlight(connector);
>> > +	val = intel_panel_compute_brightness(connector, val);
>> > +	panel->backlight.level = clamp(val, panel->backlight.min,
>> > +				       panel->backlight.max);
>> > +
>> > +	panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
>> > +
>> > +	return 0;
>> > +}
>> > +
>> >  static int pwm_setup_backlight(struct intel_connector *connector,
>> >  			       enum pipe pipe)
>> >  {
>> > @@ -1760,6 +1845,14 @@ void intel_panel_destroy_backlight(struct drm_connector *connector)
>> >  		panel->backlight.set = bxt_set_backlight;
>> >  		panel->backlight.get = bxt_get_backlight;
>> >  		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> > +		panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
>> ^Spurious line.
>> 
>> > +	} else if (HAS_PCH_CNP(dev_priv)) {
>> > +		panel->backlight.setup = cnp_setup_backlight;
>> > +		panel->backlight.enable = cnp_enable_backlight;
>> > +		panel->backlight.disable = cnp_disable_backlight;
>> > +		panel->backlight.set = bxt_set_backlight;
>> > +		panel->backlight.get = bxt_get_backlight;
>> > +		panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
>> >  	} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
>> >  		   HAS_PCH_KBP(dev_priv)) {
>> >  		panel->backlight.setup = lpt_setup_backlight;
>> 
>

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH 05/13] drm/i915/cnp: add CNP gmbus support

[Rodrigo Vivi]

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
    supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
    starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
    Re-add pin 4 for port D. Lost during some rebase.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
 drivers/gpu/drm/i915/intel_i2c.c  | 20 ++++++++++++++++++--
 3 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb83fb7..1329420 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2626,9 +2626,10 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
 #define   GMBUS_PIN_DPD		6 /* HDMID */
 #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
-#define   GMBUS_PIN_1_BXT	1
+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
+#define   GMBUS_PIN_4_CNP	4
 #define   GMBUS_NUM_PINS	7 /* including 0 */
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 41267ff..ec0779a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1802,19 +1802,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_B:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_1_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPB;
 		break;
 	case PORT_C:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_2_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPC;
 		break;
 	case PORT_D:
-		if (IS_CHERRYVIEW(dev_priv))
+		if (HAS_PCH_CNP(dev_priv))
+			ddc_pin = GMBUS_PIN_4_CNP;
+		else if (IS_CHERRYVIEW(dev_priv))
 			ddc_pin = GMBUS_PIN_DPD_CHV;
 		else
 			ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8..3eb4a91 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,25 @@ struct gmbus_pin {
 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 };
 
+/*
+ * FIXME: Spec maps 3-misc-0xc541c and 4-portd-0xc5420.
+ * However, current available pre-prod VBT maps:
+ * portD to pin 3 using 0xc5420.
+ */
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "misc", GPIOE },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOD },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		return &gmbus_pins_cnp[pin];
+	else if (IS_GEN9_LP(dev_priv))
 		return &gmbus_pins_bxt[pin];
 	else if (IS_GEN9_BC(dev_priv))
 		return &gmbus_pins_skl[pin];
@@ -87,7 +101,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_cnp);
+	else if (IS_GEN9_LP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
 	else if (IS_GEN9_BC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/cnp: add CNP gmbus support

[Rodrigo Vivi]

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
    supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
    starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
    Re-add pin 4 for port D. Lost during some rebase.
v5: Use table as spec. If VBT is wrong it should be ignored.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
 drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
 drivers/gpu/drm/i915/intel_i2c.c  | 15 +++++++++++++--
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6826547..efbbeb8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
 #define   GMBUS_PIN_DPB		5 /* SDVO, HDMIB */
 #define   GMBUS_PIN_DPD		6 /* HDMID */
 #define   GMBUS_PIN_RESERVED	7 /* 7 reserved */
-#define   GMBUS_PIN_1_BXT	1
+#define   GMBUS_PIN_1_BXT	1 /* BXT+ (atom) and CNP+ (big core) */
 #define   GMBUS_PIN_2_BXT	2
 #define   GMBUS_PIN_3_BXT	3
+#define   GMBUS_PIN_4_CNP	4
 #define   GMBUS_NUM_PINS	7 /* including 0 */
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6efc3cb..f8c40ae 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
 
 	switch (port) {
 	case PORT_B:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_1_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPB;
 		break;
 	case PORT_C:
-		if (IS_GEN9_LP(dev_priv))
+		if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 			ddc_pin = GMBUS_PIN_2_BXT;
 		else
 			ddc_pin = GMBUS_PIN_DPC;
 		break;
 	case PORT_D:
-		if (IS_CHERRYVIEW(dev_priv))
+		if (HAS_PCH_CNP(dev_priv))
+			ddc_pin = GMBUS_PIN_4_CNP;
+		else if (IS_CHERRYVIEW(dev_priv))
 			ddc_pin = GMBUS_PIN_DPD_CHV;
 		else
 			ddc_pin = GMBUS_PIN_DPD;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index b6401e8..3c9e00d 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -68,11 +68,20 @@ struct gmbus_pin {
 	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 };
 
+static const struct gmbus_pin gmbus_pins_cnp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		return &gmbus_pins_cnp[pin];
+	else if (IS_GEN9_LP(dev_priv))
 		return &gmbus_pins_bxt[pin];
 	else if (IS_GEN9_BC(dev_priv))
 		return &gmbus_pins_skl[pin];
@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (IS_GEN9_LP(dev_priv))
+	if (HAS_PCH_CNP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_cnp);
+	else if (IS_GEN9_LP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_bxt);
 	else if (IS_GEN9_BC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_skl);
-- 
1.9.1

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Re: [PATCH] drm/i915/cnp: add CNP gmbus support

[Rodrigo Vivi]

Anusha, when going to merge I noticed that we had the wrong version here.

The incorrect version would break hdmi on CFL. The right workaround is
not to respect the CNL bios for the pin number.

So, I hope I can keep your rv-b on this one, but I'd like you to confirm please.

Thanks,
Rodrigo.

On Wed, May 31, 2017 at 11:26 AM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On CNP PCH based platforms the gmbus is on the south display that
> is on PCH. The existing implementation for previous platforms
> already covers the need for CNP expect for the pin pair configuration
> that follows similar definitions that we had on BXT.
>
> v2: Don't drop "_BXT" as the indicator of the first platform
>     supporting this pin numbers. Suggested by Daniel.
> v3: Add missing else and fix register table since CNP GPIO_CTL
>     starts on 0xC5014.
> v4: Fix pin number and map according to the current available VBT.
>     Re-add pin 4 for port D. Lost during some rebase.
> v5: Use table as spec. If VBT is wrong it should be ignored.
>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
>  drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
>  drivers/gpu/drm/i915/intel_i2c.c  | 15 +++++++++++++--
>  3 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6826547..efbbeb8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
>  #define   GMBUS_PIN_DPB                5 /* SDVO, HDMIB */
>  #define   GMBUS_PIN_DPD                6 /* HDMID */
>  #define   GMBUS_PIN_RESERVED   7 /* 7 reserved */
> -#define   GMBUS_PIN_1_BXT      1
> +#define   GMBUS_PIN_1_BXT      1 /* BXT+ (atom) and CNP+ (big core) */
>  #define   GMBUS_PIN_2_BXT      2
>  #define   GMBUS_PIN_3_BXT      3
> +#define   GMBUS_PIN_4_CNP      4
>  #define   GMBUS_NUM_PINS       7 /* including 0 */
>  #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
>  #define   GMBUS_SW_CLR_INT     (1<<31)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6efc3cb..f8c40ae 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>
>         switch (port) {
>         case PORT_B:
> -               if (IS_GEN9_LP(dev_priv))
> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>                         ddc_pin = GMBUS_PIN_1_BXT;
>                 else
>                         ddc_pin = GMBUS_PIN_DPB;
>                 break;
>         case PORT_C:
> -               if (IS_GEN9_LP(dev_priv))
> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>                         ddc_pin = GMBUS_PIN_2_BXT;
>                 else
>                         ddc_pin = GMBUS_PIN_DPC;
>                 break;
>         case PORT_D:
> -               if (IS_CHERRYVIEW(dev_priv))
> +               if (HAS_PCH_CNP(dev_priv))
> +                       ddc_pin = GMBUS_PIN_4_CNP;
> +               else if (IS_CHERRYVIEW(dev_priv))
>                         ddc_pin = GMBUS_PIN_DPD_CHV;
>                 else
>                         ddc_pin = GMBUS_PIN_DPD;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index b6401e8..3c9e00d 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -68,11 +68,20 @@ struct gmbus_pin {
>         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
>  };
>
> +static const struct gmbus_pin gmbus_pins_cnp[] = {
> +       [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
> +       [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
> +       [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
> +       [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +};
> +
>  /* pin is expected to be valid */
>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
>                                              unsigned int pin)
>  {
> -       if (IS_GEN9_LP(dev_priv))
> +       if (HAS_PCH_CNP(dev_priv))
> +               return &gmbus_pins_cnp[pin];
> +       else if (IS_GEN9_LP(dev_priv))
>                 return &gmbus_pins_bxt[pin];
>         else if (IS_GEN9_BC(dev_priv))
>                 return &gmbus_pins_skl[pin];
> @@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>  {
>         unsigned int size;
>
> -       if (IS_GEN9_LP(dev_priv))
> +       if (HAS_PCH_CNP(dev_priv))
> +               size = ARRAY_SIZE(gmbus_pins_cnp);
> +       else if (IS_GEN9_LP(dev_priv))
>                 size = ARRAY_SIZE(gmbus_pins_bxt);
>         else if (IS_GEN9_BC(dev_priv))
>                 size = ARRAY_SIZE(gmbus_pins_skl);
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [PATCH] drm/i915/cnp: add CNP gmbus support

[Srivatsa, Anusha]

>-----Original Message-----
>From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>Sent: Wednesday, May 31, 2017 11:29 AM
>To: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Cc: intel-gfx <intel-gfx@lists.freedesktop.org>; Nikula, Jani
><jani.nikula@intel.com>; Vetter, Daniel <daniel.vetter@intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support
>
>Anusha, when going to merge I noticed that we had the wrong version here.
>
>The incorrect version would break hdmi on CFL. The right workaround is not to
>respect the CNL bios for the pin number.
>
>So, I hope I can keep your rv-b on this one, but I'd like you to confirm please.

Looked into the spec again. You are right, mapping has to be changed.

Anusha 

>Thanks,
>Rodrigo.
>
>On Wed, May 31, 2017 at 11:26 AM, Rodrigo Vivi <rodrigo.vivi@intel.com>
>wrote:
>> On CNP PCH based platforms the gmbus is on the south display that is
>> on PCH. The existing implementation for previous platforms already
>> covers the need for CNP expect for the pin pair configuration that
>> follows similar definitions that we had on BXT.
>>
>> v2: Don't drop "_BXT" as the indicator of the first platform
>>     supporting this pin numbers. Suggested by Daniel.
>> v3: Add missing else and fix register table since CNP GPIO_CTL
>>     starts on 0xC5014.
>> v4: Fix pin number and map according to the current available VBT.
>>     Re-add pin 4 for port D. Lost during some rebase.
>> v5: Use table as spec. If VBT is wrong it should be ignored.
>>
>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h   |  3 ++-
>>  drivers/gpu/drm/i915/intel_hdmi.c |  8 +++++---
>> drivers/gpu/drm/i915/intel_i2c.c  | 15 +++++++++++++--
>>  3 files changed, 20 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 6826547..efbbeb8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2618,9 +2618,10 @@ enum skl_disp_power_wells {
>>  #define   GMBUS_PIN_DPB                5 /* SDVO, HDMIB */
>>  #define   GMBUS_PIN_DPD                6 /* HDMID */
>>  #define   GMBUS_PIN_RESERVED   7 /* 7 reserved */
>> -#define   GMBUS_PIN_1_BXT      1
>> +#define   GMBUS_PIN_1_BXT      1 /* BXT+ (atom) and CNP+ (big core) */
>>  #define   GMBUS_PIN_2_BXT      2
>>  #define   GMBUS_PIN_3_BXT      3
>> +#define   GMBUS_PIN_4_CNP      4
>>  #define   GMBUS_NUM_PINS       7 /* including 0 */
>>  #define GMBUS1                 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /*
>command/status */
>>  #define   GMBUS_SW_CLR_INT     (1<<31)
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>> b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 6efc3cb..f8c40ae 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1892,19 +1892,21 @@ static u8 intel_hdmi_ddc_pin(struct
>> drm_i915_private *dev_priv,
>>
>>         switch (port) {
>>         case PORT_B:
>> -               if (IS_GEN9_LP(dev_priv))
>> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>>                         ddc_pin = GMBUS_PIN_1_BXT;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPB;
>>                 break;
>>         case PORT_C:
>> -               if (IS_GEN9_LP(dev_priv))
>> +               if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>>                         ddc_pin = GMBUS_PIN_2_BXT;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPC;
>>                 break;
>>         case PORT_D:
>> -               if (IS_CHERRYVIEW(dev_priv))
>> +               if (HAS_PCH_CNP(dev_priv))
>> +                       ddc_pin = GMBUS_PIN_4_CNP;
>> +               else if (IS_CHERRYVIEW(dev_priv))
>>                         ddc_pin = GMBUS_PIN_DPD_CHV;
>>                 else
>>                         ddc_pin = GMBUS_PIN_DPD; diff --git
>> a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
>> index b6401e8..3c9e00d 100644
>> --- a/drivers/gpu/drm/i915/intel_i2c.c
>> +++ b/drivers/gpu/drm/i915/intel_i2c.c
>> @@ -68,11 +68,20 @@ struct gmbus_pin {
>>         [GMBUS_PIN_3_BXT] = { "misc", GPIOD },  };
>>
>> +static const struct gmbus_pin gmbus_pins_cnp[] = {
>> +       [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
>> +       [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
>> +       [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
>> +       [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, };
>> +
>>  /* pin is expected to be valid */
>>  static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
>*dev_priv,
>>                                              unsigned int pin)  {
>> -       if (IS_GEN9_LP(dev_priv))
>> +       if (HAS_PCH_CNP(dev_priv))
>> +               return &gmbus_pins_cnp[pin];
>> +       else if (IS_GEN9_LP(dev_priv))
>>                 return &gmbus_pins_bxt[pin];
>>         else if (IS_GEN9_BC(dev_priv))
>>                 return &gmbus_pins_skl[pin]; @@ -87,7 +96,9 @@ bool
>> intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,  {
>>         unsigned int size;
>>
>> -       if (IS_GEN9_LP(dev_priv))
>> +       if (HAS_PCH_CNP(dev_priv))
>> +               size = ARRAY_SIZE(gmbus_pins_cnp);
>> +       else if (IS_GEN9_LP(dev_priv))
>>                 size = ARRAY_SIZE(gmbus_pins_bxt);
>>         else if (IS_GEN9_BC(dev_priv))
>>                 size = ARRAY_SIZE(gmbus_pins_skl);
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
>--
>Rodrigo Vivi
>Blog: http://blog.vivi.eng.br
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Re: [PATCH] drm/i915/cnp: add CNP gmbus support

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 14114 bytes --]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170531]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-add-CNP-gmbus-support/20170601-070244
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201722 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/mod_devicetable.h:11,
                    from include/linux/i2c.h:29,
                    from drivers/gpu//drm/i915/intel_hdmi.c:29:
   drivers/gpu//drm/i915/intel_hdmi.c: In function 'intel_hdmi_ddc_pin':
>> drivers/gpu//drm/i915/intel_hdmi.c:1805:31: error: implicit declaration of function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
      if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
                                  ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu//drm/i915/intel_hdmi.c:1805:3: note: in expansion of macro 'if'
      if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
      ^~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls64
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u64
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 68 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 5 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_get_crtc_for_pipe
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_attached_encoder
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:hdmi_to_dig_port
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_to_dev
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:hsw_infoframe_enabled
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:hdmi_sink_is_deep_color
   Cyclomatic Complexity 12 drivers/gpu//drm/i915/intel_hdmi.c:gcp_default_phase_possible
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:vlv_enable_hdmi
   Cyclomatic Complexity 23 drivers/gpu//drm/i915/intel_hdmi.c:hdmi_12bpc_possible
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_source_max_tmds_clock
   Cyclomatic Complexity 15 drivers/gpu//drm/i915/intel_hdmi.c:hdmi_port_clock_limit
   Cyclomatic Complexity 16 drivers/gpu//drm/i915/intel_hdmi.c:hdmi_port_clock_valid
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:cpt_infoframe_enabled
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_set_gcp_infoframe
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/intel_hdmi.c:assert_hdmi_port_disabled
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:g4x_infoframe_index
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:g4x_infoframe_enable
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_hdmi.c:cpt_write_infoframe
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_drv.h:enc_to_dig_port
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:ibx_infoframe_enabled
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:g4x_infoframe_enabled
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:vlv_infoframe_enabled
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:ibx_write_infoframe
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:hsw_dip_data_reg
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:hsw_infoframe_enable
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:hsw_write_infoframe
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:g4x_write_infoframe
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:vlv_write_infoframe
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_get_modes
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_destroy
   Cyclomatic Complexity 18 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_ddc_pin
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_add_properties
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/intel_hdmi.c:intel_enable_hdmi_audio
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:vlv_hdmi_post_disable
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:chv_hdmi_post_pll_disable
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:chv_hdmi_post_disable
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:pch_disable_hdmi
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_wait_for_vblank
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_drv.h:intel_wait_for_vblank_if_active
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:enc_to_intel_hdmi
   Cyclomatic Complexity 44 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_compute_config
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:intel_write_infoframe
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_set_avi_infoframe
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_set_spd_infoframe
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_set_hdmi_infoframe
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_hdmi.c:cpt_set_infoframes
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:ibx_set_infoframes
   Cyclomatic Complexity 11 drivers/gpu//drm/i915/intel_hdmi.c:g4x_set_infoframes
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:hsw_set_infoframes
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:vlv_set_infoframes
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_attached_hdmi
   Cyclomatic Complexity 23 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_mode_valid
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_unset_edid
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_dp_dual_mode_detect
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_set_edid
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_force
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_detect
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_hdmi.c:g4x_enable_hdmi
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:vlv_hdmi_pre_enable
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:chv_hdmi_pre_enable
   Cyclomatic Complexity 13 drivers/gpu//drm/i915/intel_hdmi.c:ibx_enable_hdmi
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:cpt_enable_hdmi
   Cyclomatic Complexity 22 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_get_config
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_get_hw_state
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_hdmi.c:intel_dp_dual_mode_set_tmds_output
   Cyclomatic Complexity 21 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_prepare
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_pre_enable
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:vlv_hdmi_pre_pll_enable
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:chv_hdmi_pre_pll_enable
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_hdmi.c:intel_disable_hdmi
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_hdmi.c:g4x_disable_hdmi
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_hdmi.c:pch_post_disable_hdmi
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_handle_sink_scrambling
   Cyclomatic Complexity 20 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_init_connector
   Cyclomatic Complexity 21 drivers/gpu//drm/i915/intel_hdmi.c:intel_hdmi_init
   cc1: all warnings being treated as errors
--
   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/mod_devicetable.h:11,
                    from include/linux/i2c.h:29,
                    from drivers/gpu//drm/i915/intel_i2c.c:29:
   drivers/gpu//drm/i915/intel_i2c.c: In function 'get_gmbus_pin':
>> drivers/gpu//drm/i915/intel_i2c.c:82:6: error: implicit declaration of function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
     if (HAS_PCH_CNP(dev_priv))
         ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu//drm/i915/intel_i2c.c:82:2: note: in expansion of macro 'if'
     if (HAS_PCH_CNP(dev_priv))
     ^~
   Cyclomatic Complexity 1 arch/x86/include/asm/current.h:get_current
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_save_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/irqflags.h:arch_irqs_disabled_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:rep_nop
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:cpu_relax
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:preempt_count
   Cyclomatic Complexity 7 arch/x86/include/asm/preempt.h:__preempt_count_add
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:__preempt_count_dec_and_test
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 4 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 arch/x86/include/asm/io.h:readl
   Cyclomatic Complexity 1 arch/x86/include/asm/io.h:writel
   Cyclomatic Complexity 4 include/drm/drmP.h:drm_can_sleep
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_equal
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_valid
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:__raw_i915_read32
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:__raw_i915_write32
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:to_intel_gmbus
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_i2c.c:gmbus_is_index_read
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:gmbus_func
   Cyclomatic Complexity 10 drivers/gpu//drm/i915/intel_i2c.c:get_gmbus_pin
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:intel_gpio_setup
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_i2c.c:intel_i2c_quirk_set
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:get_reserved
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:get_clock
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:get_data
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:set_clock
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:set_data
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:intel_gpio_post_xfer
   Cyclomatic Complexity 1 include/linux/sched/clock.h:local_clock
   Cyclomatic Complexity 21 drivers/gpu//drm/i915/intel_i2c.c:gmbus_wait
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer_read_chunk
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer_read
   Cyclomatic Complexity 9 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer_index_read
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer_write_chunk
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer_write
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_uncore.h:intel_wait_for_register_fw
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:gmbus_wait_idle
   Cyclomatic Complexity 18 drivers/gpu//drm/i915/intel_i2c.c:do_gmbus_xfer
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_i2c.c:gmbus_xfer
   Cyclomatic Complexity 12 drivers/gpu//drm/i915/intel_i2c.c:intel_gmbus_is_valid_pin
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:intel_i2c_reset
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:intel_gpio_pre_xfer
   Cyclomatic Complexity 15 drivers/gpu//drm/i915/intel_i2c.c:intel_setup_gmbus
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:intel_gmbus_get_adapter
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_i2c.c:intel_gmbus_set_speed
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:intel_gmbus_force_bit
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_i2c.c:intel_teardown_gmbus
   cc1: all warnings being treated as errors

vim +/HAS_PCH_CNP +1805 drivers/gpu//drm/i915/intel_hdmi.c

  1799				      info->alternate_ddc_pin, port_name(port));
  1800			return info->alternate_ddc_pin;
  1801		}
  1802	
  1803		switch (port) {
  1804		case PORT_B:
> 1805			if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
  1806				ddc_pin = GMBUS_PIN_1_BXT;
  1807			else
  1808				ddc_pin = GMBUS_PIN_DPB;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 28686 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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[PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Rodrigo Vivi]

As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 58dca87..1a27c72 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
-	if (!IS_GEN9_LP(dev_priv))
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 		regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 
 	pp_on = I915_READ(regs.pp_on);
 	pp_off = I915_READ(regs.pp_off);
-	if (!IS_GEN9_LP(dev_priv)) {
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
 		I915_WRITE(regs.pp_ctrl, pp_ctl);
 		pp_div = I915_READ(regs.pp_div);
 	}
@@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
 		   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
 			BXT_POWER_CYCLE_DELAY_SHIFT;
 		if (tmp > 0)
@@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
 	/* Compute the divisor for the pp clock, simply match the Bspec
 	 * formula. */
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		pp_div = I915_READ(regs.pp_ctrl);
 		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
 		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
 		      I915_READ(regs.pp_on),
 		      I915_READ(regs.pp_off),
-		      IS_GEN9_LP(dev_priv) ?
+		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
 		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
 		      I915_READ(regs.pp_div));
 }
-- 
1.9.1

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Re: [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Clint Taylor]

Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>

-Clint

On 05/30/2017 03:42 PM, Rodrigo Vivi wrote:
> As for BXT, PP_DIVISOR was removed from CNP PCH and power
> cycle delay has been moved to PP_CONTROL.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 58dca87..1a27c72 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>   	regs->pp_stat = PP_STATUS(pps_idx);
>   	regs->pp_on = PP_ON_DELAYS(pps_idx);
>   	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -	if (!IS_GEN9_LP(dev_priv))
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
>   		regs->pp_div = PP_DIVISOR(pps_idx);
>   }
>   
> @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>   
>   	pp_on = I915_READ(regs.pp_on);
>   	pp_off = I915_READ(regs.pp_off);
> -	if (!IS_GEN9_LP(dev_priv)) {
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
>   		I915_WRITE(regs.pp_ctrl, pp_ctl);
>   		pp_div = I915_READ(regs.pp_div);
>   	}
> @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>   	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>   		   PANEL_POWER_DOWN_DELAY_SHIFT;
>   
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>   		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>   			BXT_POWER_CYCLE_DELAY_SHIFT;
>   		if (tmp > 0)
> @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>   		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>   	/* Compute the divisor for the pp clock, simply match the Bspec
>   	 * formula. */
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>   		pp_div = I915_READ(regs.pp_ctrl);
>   		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>   		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>   	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>   		      I915_READ(regs.pp_on),
>   		      I915_READ(regs.pp_off),
> -		      IS_GEN9_LP(dev_priv) ?
> +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
>   		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>   		      I915_READ(regs.pp_div));
>   }

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Re: [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Pandiyan, Dhinakaran]

On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> As for BXT, PP_DIVISOR was removed from CNP PCH and power
> cycle delay has been moved to PP_CONTROL.
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 58dca87..1a27c72 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>  	regs->pp_stat = PP_STATUS(pps_idx);

We get the PPS index for BXT from bxt_power_sequencer_idx(), but I don't
see that in this patch for CNP PCH. Does that mean CNP has just one
power sequencer? 


>  	regs->pp_on = PP_ON_DELAYS(pps_idx);
>  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -	if (!IS_GEN9_LP(dev_priv))
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
>  		regs->pp_div = PP_DIVISOR(pps_idx);
>  }
>  
> @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  
>  	pp_on = I915_READ(regs.pp_on);
>  	pp_off = I915_READ(regs.pp_off);
> -	if (!IS_GEN9_LP(dev_priv)) {
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
>  		I915_WRITE(regs.pp_ctrl, pp_ctl);
>  		pp_div = I915_READ(regs.pp_div);
>  	}
> @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>  		   PANEL_POWER_DOWN_DELAY_SHIFT;
>  
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>  			BXT_POWER_CYCLE_DELAY_SHIFT;
>  		if (tmp > 0)
> @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>  	/* Compute the divisor for the pp clock, simply match the Bspec
>  	 * formula. */
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		pp_div = I915_READ(regs.pp_ctrl);
>  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)


I am not seeing the I915_WRITE for pp_div.


> @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>  		      I915_READ(regs.pp_on),
>  		      I915_READ(regs.pp_off),
> -		      IS_GEN9_LP(dev_priv) ?
> +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
>  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>  		      I915_READ(regs.pp_div));
>  }

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Re: [PATCH 06/13] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Vivi, Rodrigo]

On Wed, 2017-05-31 at 21:08 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > cycle delay has been moved to PP_CONTROL.
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 58dca87..1a27c72 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> >  	regs->pp_stat = PP_STATUS(pps_idx);
> 
> We get the PPS index for BXT from bxt_power_sequencer_idx(), but I don't
> see that in this patch for CNP PCH. Does that mean CNP has just one
> power sequencer? 

exactly, only one power sequencer for CNP.

> 
> 
> >  	regs->pp_on = PP_ON_DELAYS(pps_idx);
> >  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > -	if (!IS_GEN9_LP(dev_priv))
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> >  		regs->pp_div = PP_DIVISOR(pps_idx);
> >  }
> >  
> > @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> >  	pp_on = I915_READ(regs.pp_on);
> >  	pp_off = I915_READ(regs.pp_off);
> > -	if (!IS_GEN9_LP(dev_priv)) {
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> >  		I915_WRITE(regs.pp_ctrl, pp_ctl);
> >  		pp_div = I915_READ(regs.pp_div);
> >  	}
> > @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> >  		   PANEL_POWER_DOWN_DELAY_SHIFT;
> >  
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> >  			BXT_POWER_CYCLE_DELAY_SHIFT;
> >  		if (tmp > 0)
> > @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> >  	/* Compute the divisor for the pp clock, simply match the Bspec
> >  	 * formula. */
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		pp_div = I915_READ(regs.pp_ctrl);
> >  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> >  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> 
> 
> I am not seeing the I915_WRITE for pp_div.

good catch!
so far we have reusing what BIOS had left there...
Sending a new version...

> 
> 
> > @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> >  		      I915_READ(regs.pp_on),
> >  		      I915_READ(regs.pp_off),
> > -		      IS_GEN9_LP(dev_priv) ?
> > +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> >  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> >  		      I915_READ(regs.pp_div));
> >  }
> 

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[PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Rodrigo Vivi]

As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.

v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
    as on Broxton. (Found by DK)

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 58dca87..db51338 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 	regs->pp_stat = PP_STATUS(pps_idx);
 	regs->pp_on = PP_ON_DELAYS(pps_idx);
 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
-	if (!IS_GEN9_LP(dev_priv))
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 		regs->pp_div = PP_DIVISOR(pps_idx);
 }
 
@@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 
 	pp_on = I915_READ(regs.pp_on);
 	pp_off = I915_READ(regs.pp_off);
-	if (!IS_GEN9_LP(dev_priv)) {
+	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
 		I915_WRITE(regs.pp_ctrl, pp_ctl);
 		pp_div = I915_READ(regs.pp_div);
 	}
@@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
 		   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
 			BXT_POWER_CYCLE_DELAY_SHIFT;
 		if (tmp > 0)
@@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
 	/* Compute the divisor for the pp clock, simply match the Bspec
 	 * formula. */
-	if (IS_GEN9_LP(dev_priv)) {
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
 		pp_div = I915_READ(regs.pp_ctrl);
 		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
 		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 
 	I915_WRITE(regs.pp_on, pp_on);
 	I915_WRITE(regs.pp_off, pp_off);
-	if (IS_GEN9_LP(dev_priv))
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
 		I915_WRITE(regs.pp_ctrl, pp_div);
 	else
 		I915_WRITE(regs.pp_div, pp_div);
@@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
 	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
 		      I915_READ(regs.pp_on),
 		      I915_READ(regs.pp_off),
-		      IS_GEN9_LP(dev_priv) ?
+		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
 		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
 		      I915_READ(regs.pp_div));
 }
-- 
1.9.1

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Re: [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Pandiyan, Dhinakaran]

On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> As for BXT, PP_DIVISOR was removed from CNP PCH and power
> cycle delay has been moved to PP_CONTROL.
> 
> v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
>     as on Broxton. (Found by DK)
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I believe I've covered all instances of IS_GEN9_LP in PPS related code
and I've verified changes against BSpec. So,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

I would've preferred if you mentioned somewhere that this is similar to
BXT except for having just one instance of PPS.

-DK

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 58dca87..db51338 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>  	regs->pp_stat = PP_STATUS(pps_idx);
>  	regs->pp_on = PP_ON_DELAYS(pps_idx);
>  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> -	if (!IS_GEN9_LP(dev_priv))
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
>  		regs->pp_div = PP_DIVISOR(pps_idx);
>  }
>  
> @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  
>  	pp_on = I915_READ(regs.pp_on);
>  	pp_off = I915_READ(regs.pp_off);
> -	if (!IS_GEN9_LP(dev_priv)) {
> +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
>  		I915_WRITE(regs.pp_ctrl, pp_ctl);
>  		pp_div = I915_READ(regs.pp_div);
>  	}
> @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>  		   PANEL_POWER_DOWN_DELAY_SHIFT;
>  
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>  			BXT_POWER_CYCLE_DELAY_SHIFT;
>  		if (tmp > 0)
> @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>  	/* Compute the divisor for the pp clock, simply match the Bspec
>  	 * formula. */
> -	if (IS_GEN9_LP(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
>  		pp_div = I915_READ(regs.pp_ctrl);
>  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  
>  	I915_WRITE(regs.pp_on, pp_on);
>  	I915_WRITE(regs.pp_off, pp_off);
> -	if (IS_GEN9_LP(dev_priv))
> +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
>  		I915_WRITE(regs.pp_ctrl, pp_div);
>  	else
>  		I915_WRITE(regs.pp_div, pp_div);
> @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>  		      I915_READ(regs.pp_on),
>  		      I915_READ(regs.pp_off),
> -		      IS_GEN9_LP(dev_priv) ?
> +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
>  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>  		      I915_READ(regs.pp_div));
>  }

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Re: [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Vivi, Rodrigo]

On Wed, 2017-05-31 at 23:07 +0000, Pandiyan, Dhinakaran wrote:
> On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > cycle delay has been moved to PP_CONTROL.
> > 
> > v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> >     as on Broxton. (Found by DK)
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> I believe I've covered all instances of IS_GEN9_LP in PPS related code
> and I've verified changes against BSpec. So,
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Thanks

> 
> I would've preferred if you mentioned somewhere that this is similar to
> BXT except for having just one instance of PPS.

I can improve the commit message with:

Panel Power sequences for CNP is similar to Broxton, but with only one
sequencer.

Main difference from SPT is that PP_DIVISOR was removed and power cycle
delay has been moved to PP_CONTROL.

> 
> -DK
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 58dca87..db51338 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> >  	regs->pp_stat = PP_STATUS(pps_idx);
> >  	regs->pp_on = PP_ON_DELAYS(pps_idx);
> >  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > -	if (!IS_GEN9_LP(dev_priv))
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> >  		regs->pp_div = PP_DIVISOR(pps_idx);
> >  }
> >  
> > @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> >  	pp_on = I915_READ(regs.pp_on);
> >  	pp_off = I915_READ(regs.pp_off);
> > -	if (!IS_GEN9_LP(dev_priv)) {
> > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> >  		I915_WRITE(regs.pp_ctrl, pp_ctl);
> >  		pp_div = I915_READ(regs.pp_div);
> >  	}
> > @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> >  		   PANEL_POWER_DOWN_DELAY_SHIFT;
> >  
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> >  			BXT_POWER_CYCLE_DELAY_SHIFT;
> >  		if (tmp > 0)
> > @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> >  	/* Compute the divisor for the pp clock, simply match the Bspec
> >  	 * formula. */
> > -	if (IS_GEN9_LP(dev_priv)) {
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> >  		pp_div = I915_READ(regs.pp_ctrl);
> >  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> >  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > @@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  
> >  	I915_WRITE(regs.pp_on, pp_on);
> >  	I915_WRITE(regs.pp_off, pp_off);
> > -	if (IS_GEN9_LP(dev_priv))
> > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> >  		I915_WRITE(regs.pp_ctrl, pp_div);
> >  	else
> >  		I915_WRITE(regs.pp_div, pp_div);
> > @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> >  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> >  		      I915_READ(regs.pp_on),
> >  		      I915_READ(regs.pp_off),
> > -		      IS_GEN9_LP(dev_priv) ?
> > +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> >  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> >  		      I915_READ(regs.pp_div));
> >  }
> 

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Re: [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Pandiyan, Dhinakaran]

On Wed, 2017-05-31 at 23:46 +0000, Vivi, Rodrigo wrote:
> On Wed, 2017-05-31 at 23:07 +0000, Pandiyan, Dhinakaran wrote:
> > On Wed, 2017-05-31 at 14:54 -0700, Rodrigo Vivi wrote:
> > > As for BXT, PP_DIVISOR was removed from CNP PCH and power
> > > cycle delay has been moved to PP_CONTROL.
> > > 
> > > v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> > >     as on Broxton. (Found by DK)
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > 
> > I believe I've covered all instances of IS_GEN9_LP in PPS related code
> > and I've verified changes against BSpec. So,
> > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Thanks
> 
> > 
> > I would've preferred if you mentioned somewhere that this is similar to
> > BXT except for having just one instance of PPS.
> 
> I can improve the commit message with:
> 
> Panel Power sequences for CNP is similar to Broxton, but with only one
> sequencer.
> 
> Main difference from SPT is that PP_DIVISOR was removed and power cycle
> delay has been moved to PP_CONTROL.
> 

Sounds good!

> > 
> > -DK
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
> > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 58dca87..db51338 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> > >  	regs->pp_stat = PP_STATUS(pps_idx);
> > >  	regs->pp_on = PP_ON_DELAYS(pps_idx);
> > >  	regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > > -	if (!IS_GEN9_LP(dev_priv))
> > > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> > >  		regs->pp_div = PP_DIVISOR(pps_idx);
> > >  }
> > >  
> > > @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  
> > >  	pp_on = I915_READ(regs.pp_on);
> > >  	pp_off = I915_READ(regs.pp_off);
> > > -	if (!IS_GEN9_LP(dev_priv)) {
> > > +	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> > >  		I915_WRITE(regs.pp_ctrl, pp_ctl);
> > >  		pp_div = I915_READ(regs.pp_div);
> > >  	}
> > > @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > >  		   PANEL_POWER_DOWN_DELAY_SHIFT;
> > >  
> > > -	if (IS_GEN9_LP(dev_priv)) {
> > > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >  		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > >  			BXT_POWER_CYCLE_DELAY_SHIFT;
> > >  		if (tmp > 0)
> > > @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > >  	/* Compute the divisor for the pp clock, simply match the Bspec
> > >  	 * formula. */
> > > -	if (IS_GEN9_LP(dev_priv)) {
> > > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > >  		pp_div = I915_READ(regs.pp_ctrl);
> > >  		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > >  		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > > @@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  
> > >  	I915_WRITE(regs.pp_on, pp_on);
> > >  	I915_WRITE(regs.pp_off, pp_off);
> > > -	if (IS_GEN9_LP(dev_priv))
> > > +	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> > >  		I915_WRITE(regs.pp_ctrl, pp_div);
> > >  	else
> > >  		I915_WRITE(regs.pp_div, pp_div);
> > > @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> > >  	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> > >  		      I915_READ(regs.pp_on),
> > >  		      I915_READ(regs.pp_off),
> > > -		      IS_GEN9_LP(dev_priv) ?
> > > +		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> > >  		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> > >  		      I915_READ(regs.pp_div));
> > >  }
> > 
> 

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Re: [PATCH] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 9725 bytes --]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170531]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnp-Panel-Power-sequence-changes-for-CNP-PCH/20170601-101509
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201722 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All error/warnings (new ones prefixed by >>):

   In file included from include/uapi/linux/stddef.h:1:0,
                    from include/linux/stddef.h:4,
                    from include/uapi/linux/posix_types.h:4,
                    from include/uapi/linux/types.h:13,
                    from include/linux/types.h:5,
                    from include/linux/mod_devicetable.h:11,
                    from include/linux/i2c.h:29,
                    from drivers/gpu//drm/i915/intel_dp.c:28:
   drivers/gpu//drm/i915/intel_dp.c: In function 'intel_pps_get_registers':
>> drivers/gpu//drm/i915/intel_dp.c:801:32: error: implicit declaration of function 'HAS_PCH_CNP' [-Werror=implicit-function-declaration]
     if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
                                   ^
   include/linux/compiler.h:160:30: note: in definition of macro '__trace_if'
     if (__builtin_constant_p(!!(cond)) ? !!(cond) :   \
                                 ^~~~
>> drivers/gpu//drm/i915/intel_dp.c:801:2: note: in expansion of macro 'if'
     if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
     ^~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls64
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u64
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic64_64.h:atomic64_read
   Cyclomatic Complexity 1 include/asm-generic/atomic-long.h:atomic_long_read
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 arch/x86/include/asm/paravirt.h:arch_local_save_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/irqflags.h:arch_irqs_disabled_flags
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:rep_nop
   Cyclomatic Complexity 1 arch/x86/include/asm/processor.h:cpu_relax
   Cyclomatic Complexity 1 include/linux/mutex.h:__mutex_owner
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 arch/x86/include/asm/preempt.h:preempt_count
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 5 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/jiffies.h:_usecs_to_jiffies
   Cyclomatic Complexity 4 include/linux/jiffies.h:usecs_to_jiffies
   Cyclomatic Complexity 1 include/linux/workqueue.h:to_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:__init_work
   Cyclomatic Complexity 68 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 5 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 4 include/drm/drmP.h:drm_can_sleep
   Cyclomatic Complexity 1 include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:yesno
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:onoff
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:msecs_to_jiffies_timeout
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_max_lane_count
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_enhanced_frame_cap
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_tps3_supported
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_is_branch
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_get_crtc_for_pipe
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_attached_encoder
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:dp_to_dig_port
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:dp_to_lspcon
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_crtc_has_type
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:intel_dp_unused_lane_mask
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:is_edp
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_dp_to_dev
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_dp_max_common_rate
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_dp_max_common_lane_count
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:vlv_pipe_has_pp_on
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:vlv_pipe_has_vdd_on
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:vlv_pipe_any
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:skl_get_aux_clock_divider
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/intel_dp.c:skl_get_aux_send_ctl
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_dp.c:gen4_signal_levels
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_dp_autotest_phy_pattern
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:intel_dp_rate_index
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:intel_dp_common_len_rate_limit
   Cyclomatic Complexity 14 drivers/gpu//drm/i915/intel_dp.c:intel_dp_set_clock
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:vlv_active_pipe
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:vlv_initial_pps_pipe
   Cyclomatic Complexity 12 drivers/gpu//drm/i915/intel_dp.c:g4x_get_aux_send_ctl
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:g4x_get_aux_clock_divider
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:ilk_get_aux_clock_divider
   Cyclomatic Complexity 11 drivers/gpu//drm/i915/intel_dp.c:hsw_get_aux_clock_divider
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:intel_dp_unpack_aux
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_pps_dump_state
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_dp.c:gen7_edp_signal_levels
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_dp.c:gen6_edp_signal_levels
   Cyclomatic Complexity 37 drivers/gpu//drm/i915/intel_dp.c:_intel_dp_set_link_train
   Cyclomatic Complexity 2 include/linux/ktime.h:ktime_divns
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_to_ms
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_ms_delta
   Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
   Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_drv.h:enc_to_dig_port
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_drv.h:enc_to_intel_dp
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/intel_dp.c:intel_attached_dp
   Cyclomatic Complexity 16 drivers/gpu//drm/i915/intel_dp.c:vlv_find_free_pps
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_dp.c:ibx_digital_port_connected
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_dp.c:cpt_digital_port_connected
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:gm45_digital_port_connected
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:g4x_digital_port_connected
   Cyclomatic Complexity 5 drivers/gpu//drm/i915/intel_dp.c:intel_dp_num_rates
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/intel_dp.c:intel_dp_set_sink_rates
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_dp.c:intersect_rates
   Cyclomatic Complexity 6 drivers/gpu//drm/i915/intel_dp.c:intel_dp_set_common_rates
   Cyclomatic Complexity 7 drivers/gpu//drm/i915/intel_dp.c:intel_dp_init_connector_port_info
   Cyclomatic Complexity 8 drivers/gpu//drm/i915/intel_dp.c:intel_aux_port
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:skl_aux_ctl_reg
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:ilk_aux_ctl_reg
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:g4x_aux_ctl_reg
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:intel_aux_ctl_reg
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:skl_aux_data_reg
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:ilk_aux_data_reg
   Cyclomatic Complexity 3 drivers/gpu//drm/i915/intel_dp.c:g4x_aux_data_reg
   Cyclomatic Complexity 4 drivers/gpu//drm/i915/intel_dp.c:intel_aux_data_reg

vim +/HAS_PCH_CNP +801 drivers/gpu//drm/i915/intel_dp.c

   795			pps_idx = vlv_power_sequencer_pipe(intel_dp);
   796	
   797		regs->pp_ctrl = PP_CONTROL(pps_idx);
   798		regs->pp_stat = PP_STATUS(pps_idx);
   799		regs->pp_on = PP_ON_DELAYS(pps_idx);
   800		regs->pp_off = PP_OFF_DELAYS(pps_idx);
 > 801		if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
   802			regs->pp_div = PP_DIVISOR(pps_idx);
   803	}
   804	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Rodrigo Vivi]

Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen9 graphics based platform on top of CNP PCH.

Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 3 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c31c0cf..2f20e87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -826,6 +826,7 @@ enum intel_platform {
 	INTEL_BROXTON,
 	INTEL_KABYLAKE,
 	INTEL_GEMINILAKE,
+	INTEL_COFFEELAKE,
 	INTEL_MAX_PLATFORMS
 };
 
@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform == INTEL_COFFEELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf43dc1..31ea988 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -425,6 +425,14 @@
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+static const struct intel_device_info intel_coffeelake_info = {
+	BDW_FEATURES,
+	.is_alpha_support = 1,
+	.platform = INTEL_COFFEELAKE,
+	.gen = 9,
+	.ddb_size = 896,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3718341..acc746f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@
 	PLATFORM_NAME(BROXTON),
 	PLATFORM_NAME(KABYLAKE),
 	PLATFORM_NAME(GEMINILAKE),
+	PLATFORM_NAME(COFFEELAKE),
 };
 #undef PLATFORM_NAME
 
-- 
1.9.1

_______________________________________________
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Re: [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Tuesday, May 30, 2017 3:43 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform
>definition.
>
>Coffee Lake is a Intel® Processor containing Intel® HD Graphics following
>Kabylake.
>
>It is Gen9 graphics based platform on top of CNP PCH.
>
>Let's start by adding the platform definition based on previous platforms but yet
>as preliminary_hw_support.
>
>On following patches we will start adding PCI IDs and the platform specific
>changes.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h          | 2 ++
> drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> 3 files changed, 11 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index c31c0cf..2f20e87 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -826,6 +826,7 @@ enum intel_platform {
> 	INTEL_BROXTON,
> 	INTEL_KABYLAKE,
> 	INTEL_GEMINILAKE,
>+	INTEL_COFFEELAKE,
> 	INTEL_MAX_PLATFORMS
> };
>
>@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg)
> #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
> #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
> #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform ==
>INTEL_GEMINILAKE)
>+#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform ==
>INTEL_COFFEELAKE)
> #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index cf43dc1..31ea988 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -425,6 +425,14 @@
> 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
>BSD2_RING,  };
>
>+static const struct intel_device_info intel_coffeelake_info = {
>+	BDW_FEATURES,
>+	.is_alpha_support = 1,
>+	.platform = INTEL_COFFEELAKE,
>+	.gen = 9,
>+	.ddb_size = 896,
>+};

Rodrigo, what about properties like has_guc, has_csr, color etc? 

BR
Anusha
> /*
>  * Make sure any device matches here are from most specific to most
>  * general.  For example, since the Quanta match is based on the subsystem diff -
>-git a/drivers/gpu/drm/i915/intel_device_info.c
>b/drivers/gpu/drm/i915/intel_device_info.c
>index 3718341..acc746f 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -51,6 +51,7 @@
> 	PLATFORM_NAME(BROXTON),
> 	PLATFORM_NAME(KABYLAKE),
> 	PLATFORM_NAME(GEMINILAKE),
>+	PLATFORM_NAME(COFFEELAKE),
> };
> #undef PLATFORM_NAME
>
>--
>1.9.1
>
>_______________________________________________
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>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Rodrigo Vivi]

On Thu, Jun 1, 2017 at 3:27 PM, Srivatsa, Anusha
<anusha.srivatsa@intel.com> wrote:
>
>
>>-----Original Message-----
>>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>>Rodrigo Vivi
>>Sent: Tuesday, May 30, 2017 3:43 PM
>>To: intel-gfx@lists.freedesktop.org
>>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>>Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform
>>definition.
>>
>>Coffee Lake is a Intel® Processor containing Intel® HD Graphics following
>>Kabylake.
>>
>>It is Gen9 graphics based platform on top of CNP PCH.
>>
>>Let's start by adding the platform definition based on previous platforms but yet
>>as preliminary_hw_support.
>>
>>On following patches we will start adding PCI IDs and the platform specific
>>changes.
>>
>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>---
>> drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>> drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>> 3 files changed, 11 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>index c31c0cf..2f20e87 100644
>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>@@ -826,6 +826,7 @@ enum intel_platform {
>>       INTEL_BROXTON,
>>       INTEL_KABYLAKE,
>>       INTEL_GEMINILAKE,
>>+      INTEL_COFFEELAKE,
>>       INTEL_MAX_PLATFORMS
>> };
>>
>>@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct
>>scatterlist *sg)
>> #define IS_BROXTON(dev_priv)  ((dev_priv)->info.platform == INTEL_BROXTON)
>> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
>> #define IS_GEMINILAKE(dev_priv)       ((dev_priv)->info.platform ==
>>INTEL_GEMINILAKE)
>>+#define IS_COFFEELAKE(dev_priv)       ((dev_priv)->info.platform ==
>>INTEL_COFFEELAKE)
>> #define IS_MOBILE(dev_priv)   ((dev_priv)->info.is_mobile)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>                                   (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>>index cf43dc1..31ea988 100644
>>--- a/drivers/gpu/drm/i915/i915_pci.c
>>+++ b/drivers/gpu/drm/i915/i915_pci.c
>>@@ -425,6 +425,14 @@
>>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
>>BSD2_RING,  };
>>
>>+static const struct intel_device_info intel_coffeelake_info = {
>>+      BDW_FEATURES,
>>+      .is_alpha_support = 1,
>>+      .platform = INTEL_COFFEELAKE,
>>+      .gen = 9,
>>+      .ddb_size = 896,
>>+};
>
> Rodrigo, what about properties like has_guc, has_csr, color etc?

I believe "has_guc" should be part of the GuC patch that you are about
to send ;)

as "has_csr" is part of "[PATCH 13/13] drm/i915/cfl: Coffe Lake reuses
Kabylake DMC."

while "color" one is not needed, as it was not in Kabylake and Skylake.

>
> BR
> Anusha
>> /*
>>  * Make sure any device matches here are from most specific to most
>>  * general.  For example, since the Quanta match is based on the subsystem diff -
>>-git a/drivers/gpu/drm/i915/intel_device_info.c
>>b/drivers/gpu/drm/i915/intel_device_info.c
>>index 3718341..acc746f 100644
>>--- a/drivers/gpu/drm/i915/intel_device_info.c
>>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>>@@ -51,6 +51,7 @@
>>       PLATFORM_NAME(BROXTON),
>>       PLATFORM_NAME(KABYLAKE),
>>       PLATFORM_NAME(GEMINILAKE),
>>+      PLATFORM_NAME(COFFEELAKE),
>> };
>> #undef PLATFORM_NAME
>>
>>--
>>1.9.1
>>
>>_______________________________________________
>>Intel-gfx mailing list
>>Intel-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>Sent: Thursday, June 1, 2017 3:48 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake
>platform definition.
>
>On Thu, Jun 1, 2017 at 3:27 PM, Srivatsa, Anusha <anusha.srivatsa@intel.com>
>wrote:
>>
>>
>>>-----Original Message-----
>>>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
>>>Behalf Of Rodrigo Vivi
>>>Sent: Tuesday, May 30, 2017 3:43 PM
>>>To: intel-gfx@lists.freedesktop.org
>>>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>>>Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake
>>>platform definition.
>>>
>>>Coffee Lake is a Intel® Processor containing Intel® HD Graphics
>>>following Kabylake.
>>>
>>>It is Gen9 graphics based platform on top of CNP PCH.
>>>
>>>Let's start by adding the platform definition based on previous
>>>platforms but yet as preliminary_hw_support.
>>>
>>>On following patches we will start adding PCI IDs and the platform
>>>specific changes.
>>>
>>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>---
>>> drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>>> drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
>>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>>> 3 files changed, 11 insertions(+)
>>>
>>>diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>b/drivers/gpu/drm/i915/i915_drv.h index c31c0cf..2f20e87 100644
>>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>>@@ -826,6 +826,7 @@ enum intel_platform {
>>>       INTEL_BROXTON,
>>>       INTEL_KABYLAKE,
>>>       INTEL_GEMINILAKE,
>>>+      INTEL_COFFEELAKE,
>>>       INTEL_MAX_PLATFORMS
>>> };
>>>
>>>@@ -2768,6 +2769,7 @@ static inline struct scatterlist
>>>*__sg_next(struct scatterlist *sg)  #define IS_BROXTON(dev_priv)
>>>((dev_priv)->info.platform == INTEL_BROXTON)  #define
>>>IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
>>> #define IS_GEMINILAKE(dev_priv)       ((dev_priv)->info.platform ==
>>>INTEL_GEMINILAKE)
>>>+#define IS_COFFEELAKE(dev_priv)       ((dev_priv)->info.platform ==
>>>INTEL_COFFEELAKE)
>>> #define IS_MOBILE(dev_priv)   ((dev_priv)->info.is_mobile)
>>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>>                                   (INTEL_DEVID(dev_priv) & 0xFF00) ==
>>>0x0C00) diff --git a/drivers/gpu/drm/i915/i915_pci.c
>>>b/drivers/gpu/drm/i915/i915_pci.c index cf43dc1..31ea988 100644
>>>--- a/drivers/gpu/drm/i915/i915_pci.c
>>>+++ b/drivers/gpu/drm/i915/i915_pci.c
>>>@@ -425,6 +425,14 @@
>>>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
>>>BSD2_RING,  };
>>>
>>>+static const struct intel_device_info intel_coffeelake_info = {
>>>+      BDW_FEATURES,
>>>+      .is_alpha_support = 1,
>>>+      .platform = INTEL_COFFEELAKE,
>>>+      .gen = 9,
>>>+      .ddb_size = 896,
>>>+};
>>
>> Rodrigo, what about properties like has_guc, has_csr, color etc?
>
>I believe "has_guc" should be part of the GuC patch that you are about to send ;)
>
>as "has_csr" is part of "[PATCH 13/13] drm/i915/cfl: Coffe Lake reuses Kabylake
>DMC."
>
>while "color" one is not needed, as it was not in Kabylake and Skylake.

Oh.... I actually sent GuC patch some weeks back without adding has_guc, Should I change that patch and resend or will adding has_guc in this patch make more sense?

Anusha
>>
>> BR
>> Anusha
>>> /*
>>>  * Make sure any device matches here are from most specific to most
>>>  * general.  For example, since the Quanta match is based on the
>>>subsystem diff - -git a/drivers/gpu/drm/i915/intel_device_info.c
>>>b/drivers/gpu/drm/i915/intel_device_info.c
>>>index 3718341..acc746f 100644
>>>--- a/drivers/gpu/drm/i915/intel_device_info.c
>>>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>>>@@ -51,6 +51,7 @@
>>>       PLATFORM_NAME(BROXTON),
>>>       PLATFORM_NAME(KABYLAKE),
>>>       PLATFORM_NAME(GEMINILAKE),
>>>+      PLATFORM_NAME(COFFEELAKE),
>>> };
>>> #undef PLATFORM_NAME
>>>
>>>--
>>>1.9.1
>>>
>>>_______________________________________________
>>>Intel-gfx mailing list
>>>Intel-gfx@lists.freedesktop.org
>>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
>--
>Rodrigo Vivi
>Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Vivi, Rodrigo]

On Thu, 2017-06-01 at 23:14 +0000, Srivatsa, Anusha wrote:
> 
> >-----Original Message-----
> >From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
> >Sent: Thursday, June 1, 2017 3:48 PM
> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; intel-gfx@lists.freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake
> >platform definition.
> >
> >On Thu, Jun 1, 2017 at 3:27 PM, Srivatsa, Anusha <anusha.srivatsa@intel.com>
> >wrote:
> >>
> >>
> >>>-----Original Message-----
> >>>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
> >>>Behalf Of Rodrigo Vivi
> >>>Sent: Tuesday, May 30, 2017 3:43 PM
> >>>To: intel-gfx@lists.freedesktop.org
> >>>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> >>>Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake
> >>>platform definition.
> >>>
> >>>Coffee Lake is a Intel® Processor containing Intel® HD Graphics
> >>>following Kabylake.
> >>>
> >>>It is Gen9 graphics based platform on top of CNP PCH.
> >>>
> >>>Let's start by adding the platform definition based on previous
> >>>platforms but yet as preliminary_hw_support.
> >>>
> >>>On following patches we will start adding PCI IDs and the platform
> >>>specific changes.
> >>>
> >>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>---
> >>> drivers/gpu/drm/i915/i915_drv.h          | 2 ++
> >>> drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
> >>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>> 3 files changed, 11 insertions(+)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >>>b/drivers/gpu/drm/i915/i915_drv.h index c31c0cf..2f20e87 100644
> >>>--- a/drivers/gpu/drm/i915/i915_drv.h
> >>>+++ b/drivers/gpu/drm/i915/i915_drv.h
> >>>@@ -826,6 +826,7 @@ enum intel_platform {
> >>>       INTEL_BROXTON,
> >>>       INTEL_KABYLAKE,
> >>>       INTEL_GEMINILAKE,
> >>>+      INTEL_COFFEELAKE,
> >>>       INTEL_MAX_PLATFORMS
> >>> };
> >>>
> >>>@@ -2768,6 +2769,7 @@ static inline struct scatterlist
> >>>*__sg_next(struct scatterlist *sg)  #define IS_BROXTON(dev_priv)
> >>>((dev_priv)->info.platform == INTEL_BROXTON)  #define
> >>>IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
> >>> #define IS_GEMINILAKE(dev_priv)       ((dev_priv)->info.platform ==
> >>>INTEL_GEMINILAKE)
> >>>+#define IS_COFFEELAKE(dev_priv)       ((dev_priv)->info.platform ==
> >>>INTEL_COFFEELAKE)
> >>> #define IS_MOBILE(dev_priv)   ((dev_priv)->info.is_mobile)
> >>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> >>>                                   (INTEL_DEVID(dev_priv) & 0xFF00) ==
> >>>0x0C00) diff --git a/drivers/gpu/drm/i915/i915_pci.c
> >>>b/drivers/gpu/drm/i915/i915_pci.c index cf43dc1..31ea988 100644
> >>>--- a/drivers/gpu/drm/i915/i915_pci.c
> >>>+++ b/drivers/gpu/drm/i915/i915_pci.c
> >>>@@ -425,6 +425,14 @@
> >>>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING |
> >>>BSD2_RING,  };
> >>>
> >>>+static const struct intel_device_info intel_coffeelake_info = {
> >>>+      BDW_FEATURES,
> >>>+      .is_alpha_support = 1,
> >>>+      .platform = INTEL_COFFEELAKE,
> >>>+      .gen = 9,
> >>>+      .ddb_size = 896,
> >>>+};
> >>
> >> Rodrigo, what about properties like has_guc, has_csr, color etc?
> >
> >I believe "has_guc" should be part of the GuC patch that you are about to send ;)
> >
> >as "has_csr" is part of "[PATCH 13/13] drm/i915/cfl: Coffe Lake reuses Kabylake
> >DMC."
> >
> >while "color" one is not needed, as it was not in Kabylake and Skylake.
> 
> Oh.... I actually sent GuC patch some weeks back without adding has_guc, Should I change that patch and resend or will adding has_guc in this patch make more sense?

Well, you will have to resend here to this mailing list anyways after
all these CFL patches gets merged. So I believe the right place for that
is change that patch.

and count on me for revieweing that ;)

> 
> Anusha
> >>
> >> BR
> >> Anusha
> >>> /*
> >>>  * Make sure any device matches here are from most specific to most
> >>>  * general.  For example, since the Quanta match is based on the
> >>>subsystem diff - -git a/drivers/gpu/drm/i915/intel_device_info.c
> >>>b/drivers/gpu/drm/i915/intel_device_info.c
> >>>index 3718341..acc746f 100644
> >>>--- a/drivers/gpu/drm/i915/intel_device_info.c
> >>>+++ b/drivers/gpu/drm/i915/intel_device_info.c
> >>>@@ -51,6 +51,7 @@
> >>>       PLATFORM_NAME(BROXTON),
> >>>       PLATFORM_NAME(KABYLAKE),
> >>>       PLATFORM_NAME(GEMINILAKE),
> >>>+      PLATFORM_NAME(COFFEELAKE),
> >>> };
> >>> #undef PLATFORM_NAME
> >>>
> >>>--
> >>>1.9.1
> >>>
> >>>_______________________________________________
> >>>Intel-gfx mailing list
> >>>Intel-gfx@lists.freedesktop.org
> >>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> >--
> >Rodrigo Vivi
> >Blog: http://blog.vivi.eng.br

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Vivi, Rodrigo
>Sent: Thursday, June 1, 2017 4:20 PM
>To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; rodrigo.vivi@gmail.com
>Subject: Re: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee Lake
>platform definition.
>
>On Thu, 2017-06-01 at 23:14 +0000, Srivatsa, Anusha wrote:
>>
>> >-----Original Message-----
>> >From: Rodrigo Vivi [mailto:rodrigo.vivi@gmail.com]
>> >Sent: Thursday, June 1, 2017 3:48 PM
>> >To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
>> >Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>> >intel-gfx@lists.freedesktop.org
>> >Subject: Re: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee
>> >Lake platform definition.
>> >
>> >On Thu, Jun 1, 2017 at 3:27 PM, Srivatsa, Anusha
>> ><anusha.srivatsa@intel.com>
>> >wrote:
>> >>
>> >>
>> >>>-----Original Message-----
>> >>>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
>> >>>Behalf Of Rodrigo Vivi
>> >>>Sent: Tuesday, May 30, 2017 3:43 PM
>> >>>To: intel-gfx@lists.freedesktop.org
>> >>>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> >>>Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cfl: Introduce Coffee
>> >>>Lake platform definition.
>> >>>
>> >>>Coffee Lake is a Intel® Processor containing Intel® HD Graphics
>> >>>following Kabylake.
>> >>>
>> >>>It is Gen9 graphics based platform on top of CNP PCH.
>> >>>
>> >>>Let's start by adding the platform definition based on previous
>> >>>platforms but yet as preliminary_hw_support.
>> >>>
>> >>>On following patches we will start adding PCI IDs and the platform
>> >>>specific changes.
>> >>>
>> >>>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

>> >>> drivers/gpu/drm/i915/i915_drv.h          | 2 ++
>> >>> drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
>> >>> drivers/gpu/drm/i915/intel_device_info.c | 1 +
>> >>> 3 files changed, 11 insertions(+)
>> >>>
>> >>>diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> >>>b/drivers/gpu/drm/i915/i915_drv.h index c31c0cf..2f20e87 100644
>> >>>--- a/drivers/gpu/drm/i915/i915_drv.h
>> >>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>> >>>@@ -826,6 +826,7 @@ enum intel_platform {
>> >>>       INTEL_BROXTON,
>> >>>       INTEL_KABYLAKE,
>> >>>       INTEL_GEMINILAKE,
>> >>>+      INTEL_COFFEELAKE,
>> >>>       INTEL_MAX_PLATFORMS
>> >>> };
>> >>>
>> >>>@@ -2768,6 +2769,7 @@ static inline struct scatterlist
>> >>>*__sg_next(struct scatterlist *sg)  #define IS_BROXTON(dev_priv)
>> >>>((dev_priv)->info.platform == INTEL_BROXTON)  #define
>> >>>IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
>> >>> #define IS_GEMINILAKE(dev_priv)       ((dev_priv)->info.platform ==
>> >>>INTEL_GEMINILAKE)
>> >>>+#define IS_COFFEELAKE(dev_priv)       ((dev_priv)->info.platform ==
>> >>>INTEL_COFFEELAKE)
>> >>> #define IS_MOBILE(dev_priv)   ((dev_priv)->info.is_mobile)
>> >>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> >>>                                   (INTEL_DEVID(dev_priv) & 0xFF00)
>> >>>==
>> >>>0x0C00) diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> >>>b/drivers/gpu/drm/i915/i915_pci.c index cf43dc1..31ea988 100644
>> >>>--- a/drivers/gpu/drm/i915/i915_pci.c
>> >>>+++ b/drivers/gpu/drm/i915/i915_pci.c
>> >>>@@ -425,6 +425,14 @@
>> >>>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING
>> >>>| BSD2_RING,  };
>> >>>
>> >>>+static const struct intel_device_info intel_coffeelake_info = {
>> >>>+      BDW_FEATURES,
>> >>>+      .is_alpha_support = 1,
>> >>>+      .platform = INTEL_COFFEELAKE,
>> >>>+      .gen = 9,
>> >>>+      .ddb_size = 896,
>> >>>+};
>> >>
>> >> Rodrigo, what about properties like has_guc, has_csr, color etc?
>> >
>> >I believe "has_guc" should be part of the GuC patch that you are
>> >about to send ;)
>> >
>> >as "has_csr" is part of "[PATCH 13/13] drm/i915/cfl: Coffe Lake
>> >reuses Kabylake DMC."
>> >
>> >while "color" one is not needed, as it was not in Kabylake and Skylake.
>>
>> Oh.... I actually sent GuC patch some weeks back without adding has_guc,
>Should I change that patch and resend or will adding has_guc in this patch make
>more sense?
>
>Well, you will have to resend here to this mailing list anyways after all these CFL
>patches gets merged. So I believe the right place for that is change that patch.
>
>and count on me for revieweing that ;)

Got it. Thanks :) 

Anusha
>>
>> Anusha
>> >>
>> >> BR
>> >> Anusha
>> >>> /*
>> >>>  * Make sure any device matches here are from most specific to
>> >>>most
>> >>>  * general.  For example, since the Quanta match is based on the
>> >>>subsystem diff - -git a/drivers/gpu/drm/i915/intel_device_info.c
>> >>>b/drivers/gpu/drm/i915/intel_device_info.c
>> >>>index 3718341..acc746f 100644
>> >>>--- a/drivers/gpu/drm/i915/intel_device_info.c
>> >>>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>> >>>@@ -51,6 +51,7 @@
>> >>>       PLATFORM_NAME(BROXTON),
>> >>>       PLATFORM_NAME(KABYLAKE),
>> >>>       PLATFORM_NAME(GEMINILAKE),
>> >>>+      PLATFORM_NAME(COFFEELAKE),
>> >>> };
>> >>> #undef PLATFORM_NAME
>> >>>
>> >>>--
>> >>>1.9.1
>> >>>
>> >>>_______________________________________________
>> >>>Intel-gfx mailing list
>> >>>Intel-gfx@lists.freedesktop.org
>> >>>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> >
>> >
>> >
>> >--
>> >Rodrigo Vivi
>> >Blog: http://blog.vivi.eng.br

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/cfl: Introduce Coffee Lake platform definition.

[Rodrigo Vivi]

Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.

It is Gen9 graphics based platform on top of CNP PCH.

Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.

On following patches we will start adding PCI IDs and the
platform specific changes.

v2: Also add BS2 ring that is present on GT3. As on KBL, according
    spec: "GT3 also has additional media blocks with second instance
    of VEBox and VDBox each", i.e. BSD2 ring in our case. Noticed
    when reviewing PCI ID patches.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c31c0cf..2f20e87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -826,6 +826,7 @@ enum intel_platform {
 	INTEL_BROXTON,
 	INTEL_KABYLAKE,
 	INTEL_GEMINILAKE,
+	INTEL_COFFEELAKE,
 	INTEL_MAX_PLATFORMS
 };
 
@@ -2768,6 +2769,7 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	((dev_priv)->info.platform == INTEL_COFFEELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cf43dc1..a32bc7b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -425,6 +425,22 @@
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
+#define CFL_FEATURES \
+	.is_alpha_support = 1, \
+	BDW_FEATURES, \
+	.platform = INTEL_COFFEELAKE, \
+	.gen = 9, \
+	.ddb_size = 896
+
+static const struct intel_device_info intel_coffeelake_info = {
+	CFL_FEATURES,
+};
+
+static const struct intel_device_info intel_coffeelake_gt3_info = {
+	CFL_FEATURES,
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3718341..acc746f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -51,6 +51,7 @@
 	PLATFORM_NAME(BROXTON),
 	PLATFORM_NAME(KABYLAKE),
 	PLATFORM_NAME(GEMINILAKE),
+	PLATFORM_NAME(COFFEELAKE),
 };
 #undef PLATFORM_NAME
 
-- 
1.9.1

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[PATCH 08/13] drm/i915/cfl: Coffee Lake uses CNP PCH.

[Rodrigo Vivi]

So let's force it on the virtual detection.

Also it is still the only silicon for now on this PCH,
so WARN otherwise.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90b646c..2f618f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 		ret = PCH_SPT;
 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
+	} else if (IS_COFFEELAKE(dev_priv)) {
+		ret = PCH_CNP;
 	}
 
 	return ret;
@@ -222,9 +224,11 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint PCH\n");
+				WARN_ON(!IS_COFFEELAKE(dev_priv));
 			} else if (id_ext == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CNP;
 				DRM_DEBUG_KMS("Found CannonPoint LP PCH\n");
+				WARN_ON(!IS_COFFEELAKE(dev_priv));
 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
-- 
1.9.1

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Re: [PATCH 08/13] drm/i915/cfl: Coffee Lake uses CNP PCH.

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Tuesday, May 30, 2017 3:43 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>Subject: [Intel-gfx] [PATCH 08/13] drm/i915/cfl: Coffee Lake uses CNP PCH.
>
>So let's force it on the virtual detection.
>
>Also it is still the only silicon for now on this PCH, so WARN otherwise.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 90b646c..2f618f7 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -139,6 +139,8 @@ static enum intel_pch intel_virt_detect_pch(struct
>drm_i915_private *dev_priv)
> 	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> 		ret = PCH_SPT;
> 		DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
>+	} else if (IS_COFFEELAKE(dev_priv)) {
>+		ret = PCH_CNP;
> 	}
>
> 	return ret;
>@@ -222,9 +224,11 @@ static void intel_detect_pch(struct drm_i915_private
>*dev_priv)
> 			} else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
> 				dev_priv->pch_type = PCH_CNP;
> 				DRM_DEBUG_KMS("Found CannonPoint
>PCH\n");
>+				WARN_ON(!IS_COFFEELAKE(dev_priv));
> 			} else if (id_ext ==
>INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
> 				dev_priv->pch_type = PCH_CNP;
> 				DRM_DEBUG_KMS("Found CannonPoint LP
>PCH\n");
>+				WARN_ON(!IS_COFFEELAKE(dev_priv));
> 			} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> 				   (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> 				   ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)
>&&
>--
>1.9.1
>
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[PATCH 09/13] drm/i915/cfl: Basic PM plumbing for Coffee Lake.

[Rodrigo Vivi]

All here is pretty much like Kabylake, expect the PCH.

This patch exclude the addition of DMC, GuC and most workardounds since
they might have changes/updates.

v2: Take advantage of IS_GEN9_BC minimizing the needed plumbing.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
 drivers/gpu/drm/i915/intel_pm.c  | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0914ad9..e364814 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
 		}
 	}
 
-	if (IS_KABYLAKE(dev_priv))
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		return kbl_get_buf_trans_dp(dev_priv, n_entries);
 	else
 		return skl_get_buf_trans_dp(dev_priv, n_entries);
@@ -458,7 +458,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 	if (IS_GEN9_LP(dev_priv))
 		return hdmi_level;
 
-	if (IS_GEN9_BC(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 		hdmi_default_entry = 8;
 	} else if (IS_BROADWELL(dev_priv)) {
@@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
 		if (dp_iboost) {
 			iboost = dp_iboost;
 		} else {
-			if (IS_KABYLAKE(dev_priv))
+			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
 									&n_entries);
 			else
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 936eef1..3e762b1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	if (IS_KABYLAKE(dev_priv))
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		return true;
 
 	if (IS_SKYLAKE(dev_priv) &&
@@ -8139,7 +8139,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
 		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
 			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-	/* WaFbcNukeOnHostModify:kbl */
+	/* WaFbcNukeOnHostModify:kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
 }
@@ -8607,7 +8607,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_SKYLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
-	else if (IS_KABYLAKE(dev_priv))
+	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
 	else if (IS_BROXTON(dev_priv))
 		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
-- 
1.9.1

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Re: [PATCH 09/13] drm/i915/cfl: Basic PM plumbing for Coffee Lake.

[Pandiyan, Dhinakaran]

On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> All here is pretty much like Kabylake, expect the PCH.
> 
> This patch exclude the addition of DMC, GuC and most workardounds since
> they might have changes/updates.
> 
> v2: Take advantage of IS_GEN9_BC minimizing the needed plumbing.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
>  drivers/gpu/drm/i915/intel_pm.c  | 6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0914ad9..e364814 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c

DDI changes look like they should be a separate patch.  

> @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
>  		}
>  	}
>  
> -	if (IS_KABYLAKE(dev_priv))
> +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
>  	else
>  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> @@ -458,7 +458,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>  	if (IS_GEN9_LP(dev_priv))
>  		return hdmi_level;
>  
> -	if (IS_GEN9_BC(dev_priv)) {
> +	if (IS_GEN9_BC(dev_priv) || IS_COFFEELAKE(dev_priv)) {

Shouldn't GEN9_BC already include COFFEELAKE?

>  		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
>  		hdmi_default_entry = 8;
>  	} else if (IS_BROADWELL(dev_priv)) {
> @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
>  		if (dp_iboost) {
>  			iboost = dp_iboost;
>  		} else {
> -			if (IS_KABYLAKE(dev_priv))
> +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
>  									&n_entries);
>  			else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 936eef1..3e762b1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
>  static bool
>  intel_has_sagv(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_KABYLAKE(dev_priv))
> +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		return true;
>  
>  	if (IS_SKYLAKE(dev_priv) &&
> @@ -8139,7 +8139,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
>  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>  
> -	/* WaFbcNukeOnHostModify:kbl */
> +	/* WaFbcNukeOnHostModify:kbl,cfl */

I could not verify if this workaround is applicable to CFL.



>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>  }
> @@ -8607,7 +8607,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_SKYLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> -	else if (IS_KABYLAKE(dev_priv))
> +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
>  	else if (IS_BROXTON(dev_priv))
>  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;

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Re: [PATCH 09/13] drm/i915/cfl: Basic PM plumbing for Coffee Lake.

[Pandiyan, Dhinakaran]

On Fri, 2017-06-02 at 21:25 +0000, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> > All here is pretty much like Kabylake, expect the PCH.
> > 
> > This patch exclude the addition of DMC, GuC and most workardounds since
> > they might have changes/updates.
> > 
> > v2: Take advantage of IS_GEN9_BC minimizing the needed plumbing.
> > 
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> >  drivers/gpu/drm/i915/intel_pm.c  | 6 +++---
> >  2 files changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 0914ad9..e364814 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> 
> DDI changes look like they should be a separate patch.  
> 
> > @@ -429,7 +429,7 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
> >  		}
> >  	}
> >  
> > -	if (IS_KABYLAKE(dev_priv))
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		return kbl_get_buf_trans_dp(dev_priv, n_entries);
> >  	else
> >  		return skl_get_buf_trans_dp(dev_priv, n_entries);
> > @@ -458,7 +458,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> >  	if (IS_GEN9_LP(dev_priv))
> >  		return hdmi_level;
> >  
> > -	if (IS_GEN9_BC(dev_priv)) {
> > +	if (IS_GEN9_BC(dev_priv) || IS_COFFEELAKE(dev_priv)) {
> 
> Shouldn't GEN9_BC already include COFFEELAKE?
> 
> >  		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
> >  		hdmi_default_entry = 8;
> >  	} else if (IS_BROADWELL(dev_priv)) {
> > @@ -1478,7 +1478,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
> >  		if (dp_iboost) {
> >  			iboost = dp_iboost;
> >  		} else {
> > -			if (IS_KABYLAKE(dev_priv))
> > +			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
> >  									&n_entries);
> >  			else
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 936eef1..3e762b1 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3549,7 +3549,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
> >  static bool
> >  intel_has_sagv(struct drm_i915_private *dev_priv)
> >  {
> > -	if (IS_KABYLAKE(dev_priv))
> > +	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		return true;
> >  
> >  	if (IS_SKYLAKE(dev_priv) &&
> > @@ -8139,7 +8139,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> >  		I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> >  			   GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >  
> > -	/* WaFbcNukeOnHostModify:kbl */
> > +	/* WaFbcNukeOnHostModify:kbl,cfl */
> 
> I could not verify if this workaround is applicable to CFL.
> 
> 
> 
> >  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> >  		   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> >  }
> > @@ -8607,7 +8607,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> >  {
> >  	if (IS_SKYLAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > -	else if (IS_KABYLAKE(dev_priv))
> > +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> >  		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;

We could perhaps add a distinct hook for CFL here. That way, all the
workarounds can be applied in the following patch, instead of
implementing one wa here and the rest in the next patch. It'd also make
it cleaner to add new wa's for CFL parts. Let me know what you think.



> >  	else if (IS_BROXTON(dev_priv))
> >  		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> 
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[PATCH 10/13] drm/i915/cfl: Add Coffee Lake PCI IDs for H and S Skus.

[Rodrigo Vivi]

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 include/drm/i915_pciids.h       | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 31ea988..0b1c96d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -477,6 +477,7 @@
 	INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
+	INTEL_CFL_IDS(&intel_coffeelake_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 27e0dba..a0e4d12 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -334,4 +334,8 @@
 	INTEL_KBL_GT3_IDS(info), \
 	INTEL_KBL_GT4_IDS(info)
 
+#define INTEL_CFL_IDS(info) \
+	INTEL_VGA_DEVICE(0x3E92, info), /* CFL-S GT2 */ \
+	INTEL_VGA_DEVICE(0x3E9B, info) /* CFL-H GT2 */
+
 #endif /* _I915_PCIIDS_H */
-- 
1.9.1

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[PATCH 11/13] drm/i915/cfl: Add CFL PCI IDs for U SKU

[Rodrigo Vivi]

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

Follow the spec and add the PCI Ids.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 include/drm/i915_pciids.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a0e4d12..35c443f 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -336,6 +336,7 @@
 
 #define INTEL_CFL_IDS(info) \
 	INTEL_VGA_DEVICE(0x3E92, info), /* CFL-S GT2 */ \
-	INTEL_VGA_DEVICE(0x3E9B, info) /* CFL-H GT2 */
+	INTEL_VGA_DEVICE(0x3E9B, info), /* CFL-H GT2 */ \
+	INTEL_VGA_DEVICE(0x3EA5, info) /* CFL-U GT3 */
 
 #endif /* _I915_PCIIDS_H */
-- 
1.9.1

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[PATCH 12/13] drm/i915/cfl: Introduce Coffee Lake workardounds.

[Rodrigo Vivi]

Coffee Lake inherit most of Kabylake production
workardounds.

Only difference identified so far is:
- WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c | 75 +++++++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_pm.c        | 10 ++---
 3 files changed, 61 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0c1008a..f793eeb 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1884,7 +1884,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 699f2d3..3867e80 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -814,24 +814,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	int ret;
 
-	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
+	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 
-	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
+	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 
-	/* WaDisableKillLogic:bxt,skl,kbl */
+	/* WaDisableKillLogic:bxt,skl,kbl,cfl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
 
-	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
-	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
+	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
+	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  FLOW_CONTROL_ENABLE |
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
+	/* Syncing dependencies between camera and graphics:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 
@@ -851,18 +851,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		 */
 	}
 
-	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
-	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
+	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
+	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 			  GEN9_ENABLE_YV12_BUGFIX |
 			  GEN9_ENABLE_GPGPU_PREEMPTION);
 
-	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
-	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
+	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
+	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
-	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
+	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
 
@@ -871,7 +871,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 				  PIXEL_MASK_CAMMING_DISABLE);
 
-	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
+	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
@@ -889,39 +889,40 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	 * a TLB invalidation occurs during a PSD flush.
 	 */
 
-	/* WaForceEnableNonCoherent:skl,bxt,kbl */
+	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_NON_COHERENT);
 
-	/* WaDisableHDCInvalidation:skl,bxt,kbl */
+	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   BDW_DISABLE_HDC_INVALIDATION);
 
-	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
+	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
 	if (IS_SKYLAKE(dev_priv) ||
 	    IS_KABYLAKE(dev_priv) ||
+	    IS_COFFEELAKE(dev_priv)||
 	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
 
-	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
+	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
+	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 
-	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
+	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
 	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 	if (ret)
 		return ret;
 
-	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
+	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
 	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
 	if (ret)
 		return ret;
 
-	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
+	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
 	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
 	if (ret)
 		return ret;
@@ -1140,6 +1141,38 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static int cfl_init_workarounds(struct intel_engine_cs *engine)
+{
+	struct drm_i915_private *dev_priv = engine->i915;
+	int ret;
+
+	ret = gen9_init_workarounds(engine);
+	if (ret)
+		return ret;
+
+	/* WaEnableGapsTsvCreditFix:cfl */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN9_GAPS_TSV_CREDIT_DISABLE));
+
+	/* WaToEnableHwFixForPushConstHWBug:cfl */
+	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
+	/* WaDisableGafsUnitClkGating:cfl */
+	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableSbeCacheDispatchPortSharing:cfl */
+	WA_SET_BIT_MASKED(
+		GEN7_HALF_SLICE_CHICKEN1,
+		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
+	/* WaInPlaceDecompressionHang:cfl */
+	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+	return 0;
+}
+
 int init_workarounds_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
@@ -1162,6 +1195,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
 		err = kbl_init_workarounds(engine);
 	else if (IS_GEMINILAKE(dev_priv))
 		err =  glk_init_workarounds(engine);
+	else if (IS_COFFEELAKE(dev_priv))
+		err = cfl_init_workarounds(engine);
 	else
 		err = 0;
 	if (err)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3e762b1..844b886 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -58,24 +58,24 @@
 
 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
 	I915_WRITE(CHICKEN_PAR1_1,
 		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
 
 	I915_WRITE(GEN8_CONFIG0,
 		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
 
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(GEN8_CHICKEN_DCPR_1,
 		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
 
-	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
-	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
+	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
+	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
 	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 		   DISP_FBC_WM_DIS |
 		   DISP_FBC_MEMORY_WAKE);
 
-	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 		   ILK_DPFC_DISABLE_DUMMY0);
 }
-- 
1.9.1

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[PATCH 13/13] drm/i915/cfl: Coffe Lake reuses Kabylake DMC.

[Rodrigo Vivi]

From the DMC perspective the same firmware is used on
both platforms. We haven't recieved any separated release
specifically for Coffee Lake so let's just re-use what
is already there for Kabylake.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c  | 1 +
 drivers/gpu/drm/i915/intel_csr.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0b1c96d..c1052b8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -430,6 +430,7 @@
 	.is_alpha_support = 1,
 	.platform = INTEL_COFFEELAKE,
 	.gen = 9,
+	.has_csr = 1,
 	.ddb_size = 896,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 1575bde..fb6af0b 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -291,7 +291,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 
 	if (IS_GEMINILAKE(dev_priv)) {
 		required_version = GLK_CSR_VERSION_REQUIRED;
-	} else if (IS_KABYLAKE(dev_priv)) {
+	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 		required_version = KBL_CSR_VERSION_REQUIRED;
 	} else if (IS_SKYLAKE(dev_priv)) {
 		required_version = SKL_CSR_VERSION_REQUIRED;
@@ -440,7 +440,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 
 	if (IS_GEMINILAKE(dev_priv))
 		csr->fw_path = I915_CSR_GLK;
-	else if (IS_KABYLAKE(dev_priv))
+	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 		csr->fw_path = I915_CSR_KBL;
 	else if (IS_SKYLAKE(dev_priv))
 		csr->fw_path = I915_CSR_SKL;
-- 
1.9.1

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Re: [PATCH 13/13] drm/i915/cfl: Coffe Lake reuses Kabylake DMC.

[Pandiyan, Dhinakaran]

On Tue, 2017-05-30 at 15:43 -0700, Rodrigo Vivi wrote:
> From the DMC perspective the same firmware is used on
> both platforms. We haven't recieved any separated release
> specifically for Coffee Lake so let's just re-use what
> is already there for Kabylake.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Typo in title, did you mean cofveve? :)

The patch does what it says. With the title fixed,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c  | 1 +
>  drivers/gpu/drm/i915/intel_csr.c | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0b1c96d..c1052b8 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -430,6 +430,7 @@
>  	.is_alpha_support = 1,
>  	.platform = INTEL_COFFEELAKE,
>  	.gen = 9,
> +	.has_csr = 1,
>  	.ddb_size = 896,
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 1575bde..fb6af0b 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -291,7 +291,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
>  
>  	if (IS_GEMINILAKE(dev_priv)) {
>  		required_version = GLK_CSR_VERSION_REQUIRED;
> -	} else if (IS_KABYLAKE(dev_priv)) {
> +	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
>  		required_version = KBL_CSR_VERSION_REQUIRED;
>  	} else if (IS_SKYLAKE(dev_priv)) {
>  		required_version = SKL_CSR_VERSION_REQUIRED;
> @@ -440,7 +440,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>  
>  	if (IS_GEMINILAKE(dev_priv))
>  		csr->fw_path = I915_CSR_GLK;
> -	else if (IS_KABYLAKE(dev_priv))
> +	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>  		csr->fw_path = I915_CSR_KBL;
>  	else if (IS_SKYLAKE(dev_priv))
>  		csr->fw_path = I915_CSR_SKL;

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✓ Fi.CI.BAT: success for series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH.

[Patchwork]

== Series Details ==

Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH.
URL   : https://patchwork.freedesktop.org/series/25070/
State : success

== Summary ==

Series 25070v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25070/revisions/1/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                pass       -> FAIL       (fi-snb-2600) fdo#100007
Test kms_busy:
        Subgroup basic-flip-default-b:
                dmesg-warn -> PASS       (fi-skl-6700hq) fdo#101144 +2
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-skl-6700hq) fdo#101154 +7

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#101154 https://bugs.freedesktop.org/show_bug.cgi?id=101154

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:442s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:434s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:573s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:511s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:488s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:483s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:431s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:409s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:416s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:487s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:468s
fi-kbl-7500u     total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  time:466s
fi-kbl-7560u     total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  time:568s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:455s
fi-skl-6700hq    total:278  pass:239  dwarn:0   dfail:1   fail:17  skip:21  time:427s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:464s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:499s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:436s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:527s
fi-snb-2600      total:278  pass:247  dwarn:0   dfail:0   fail:2   skip:29  time:400s

0af3152d8e2034d1491ef8738e7dfc6e08852606 drm-tip: 2017y-05m-30d-17h-20m-32s UTC integration manifest
c934512 drm/i915/cfl: Coffe Lake reuses Kabylake DMC.
f7fee3b drm/i915/cfl: Introduce Coffee Lake workardounds.
ee60872 drm/i915/cfl: Add CFL PCI IDs for U SKU
1cf32ae drm/i915/cfl: Add Coffee Lake PCI IDs for H and S Skus.
67c0f0e drm/i915/cfl: Basic PM plumbing for Coffee Lake.
58a30b1 drm/i915/cfl: Coffee Lake uses CNP PCH.
d936662 drm/i915/cfl: Introduce Coffee Lake platform definition.
2fa16bd drm/i915/cnp: Panel Power sequence changes for CNP PCH.
c4215bd drm/i915/cnp: add CNP gmbus support
e994334 drm/i915/cnp: Backlight support for CNP.
b6b0d57 drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
03689d6 drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
ec7d8a0 drm/i915/cnp: Introduce Cannonpoint PCH.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4834/
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✓ Fi.CI.BAT: success for series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)
URL   : https://patchwork.freedesktop.org/series/25070/
State : success

== Summary ==

Series 25070v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25070/revisions/2/mbox/

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-uc:
                pass       -> FAIL       (fi-snb-2600) fdo#100007
Test kms_busy:
        Subgroup basic-flip-default-b:
                pass       -> DMESG-WARN (fi-skl-6700hq) fdo#101144 +2
Test kms_cursor_legacy:
        Subgroup basic-busy-flip-before-cursor-atomic:
                pass       -> FAIL       (fi-skl-6700hq) fdo#101154 +7

fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#101154 https://bugs.freedesktop.org/show_bug.cgi?id=101154

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:443s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:434s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:580s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:506s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:488s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:483s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:432s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:415s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:418s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:502s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:462s
fi-kbl-7500u     total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  time:464s
fi-kbl-7560u     total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  time:570s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:455s
fi-skl-6700hq    total:278  pass:229  dwarn:1   dfail:0   fail:26  skip:22  time:402s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:474s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:509s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:439s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:535s
fi-snb-2600      total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  time:403s

593aae9587d79f8a823a36f4e6cc12e23b547d07 drm-tip: 2017y-05m-31d-14h-36m-16s UTC integration manifest
70f0c4a drm/i915/cfl: Coffe Lake reuses Kabylake DMC.
0674cbd drm/i915/cfl: Introduce Coffee Lake workardounds.
5026cc0 drm/i915/cfl: Add CFL PCI IDs for U SKU
5d82218 drm/i915/cfl: Add Coffee Lake PCI IDs for H and S Skus.
7a0af93 drm/i915/cfl: Basic PM plumbing for Coffee Lake.
a092590 drm/i915/cfl: Coffee Lake uses CNP PCH.
cffd6d9 drm/i915/cfl: Introduce Coffee Lake platform definition.
c027cc9 drm/i915/cnp: Panel Power sequence changes for CNP PCH.
14ffeee drm/i915/cnp: add CNP gmbus support
4910b96 drm/i915/cnp: Backlight support for CNP.
918c713 drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
01dd2f3 drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
84e5d90 drm/i915/cnp: Introduce Cannonpoint PCH.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4846/
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✓ Fi.CI.BAT: success for series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [01/13] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)
URL   : https://patchwork.freedesktop.org/series/25070/
State : success

== Summary ==

Series 25070v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25070/revisions/3/mbox/

fi-bdw-5557u     total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  time:442s
fi-bdw-gvtdvm    total:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  time:430s
fi-bsw-n3050     total:278  pass:242  dwarn:0   dfail:0   fail:0   skip:36  time:573s
fi-bxt-j4205     total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  time:505s
fi-byt-j1900     total:278  pass:254  dwarn:0   dfail:0   fail:0   skip:24  time:495s
fi-byt-n2820     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:481s
fi-hsw-4770      total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:437s
fi-hsw-4770r     total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  time:412s
fi-ilk-650       total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  time:412s
fi-ivb-3520m     total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:495s
fi-ivb-3770      total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  time:462s
fi-kbl-7500u     total:278  pass:255  dwarn:5   dfail:0   fail:0   skip:18  time:464s
fi-kbl-7560u     total:278  pass:263  dwarn:5   dfail:0   fail:0   skip:10  time:587s
fi-skl-6260u     total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:465s
fi-skl-6700hq    total:278  pass:239  dwarn:0   dfail:1   fail:17  skip:21  time:428s
fi-skl-6700k     total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  time:464s
fi-skl-6770hq    total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  time:499s
fi-skl-gvtdvm    total:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  time:438s
fi-snb-2520m     total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  time:549s
fi-snb-2600      total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  time:409s

593aae9587d79f8a823a36f4e6cc12e23b547d07 drm-tip: 2017y-05m-31d-14h-36m-16s UTC integration manifest
44b9c8d drm/i915/cfl: Coffe Lake reuses Kabylake DMC.
c27cae8 drm/i915/cfl: Introduce Coffee Lake workardounds.
cc122a6 drm/i915/cfl: Add CFL PCI IDs for U SKU
d6d7f7a drm/i915/cfl: Add Coffee Lake PCI IDs for H and S Skus.
3c73119 drm/i915/cfl: Basic PM plumbing for Coffee Lake.
7f55a8d drm/i915/cfl: Coffee Lake uses CNP PCH.
ca5cc1d drm/i915/cfl: Introduce Coffee Lake platform definition.
2413280 drm/i915/cnp: Panel Power sequence changes for CNP PCH.
5983e52 drm/i915/cnp: add CNP gmbus support
0a5a491 drm/i915/cnp: Backlight support for CNP.
8254669 drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
78728ef drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
657bcfc drm/i915/cnp: Introduce Cannonpoint PCH.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4850/
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